From c1a770298b60ae2dd80a9e01561ed6e02fe5af14 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Wed, 12 Apr 2023 14:04:45 +0200 Subject: [PATCH] add downscaling option to CTS input modules --- cts/source/cts_pkg.vhd | 2 +- cts/source/cts_trg_input.vhd | 41 +++++++++++++++++++++++++++++------- cts/source/cts_trigger.vhd | 12 +++++------ 3 files changed, 40 insertions(+), 15 deletions(-) diff --git a/cts/source/cts_pkg.vhd b/cts/source/cts_pkg.vhd index 0cf0e36..a3011a0 100755 --- a/cts/source/cts_pkg.vhd +++ b/cts/source/cts_pkg.vhd @@ -249,7 +249,7 @@ package cts_pkg is RST_IN : in std_logic; DATA_IN : in std_logic; DATA_OUT : out std_logic; - CONFIG_IN : in std_logic_vector(15 downto 0) := (others => '0') + CONFIG_IN : in std_logic_vector(19 downto 0) := (others => '0') ); end component; diff --git a/cts/source/cts_trg_input.vhd b/cts/source/cts_trg_input.vhd index 32c2614..bbb1073 100644 --- a/cts/source/cts_trg_input.vhd +++ b/cts/source/cts_trg_input.vhd @@ -5,11 +5,12 @@ -- Bit Description -- -- Input Module Configuration --- 5:0 Delay (0 to 15 cycles) +-- 5:0 Delay (0 to 63 cycles) -- 11:8 Spike Rejection. Number of clock cycles the signal has to be stably asserted until it is interpreted high. -- 12 Invert (0: Bypass, 1: Invert Input) --- 13 Override Enable (0: Bypass, 1: Set Value of 10. Bit) --- 14 Override Value +-- 13 Override Enable (0: Bypass, 1: Set Value of Bit 14) +-- 14 Override Value +-- 19:16 Downscale 2**N -- library ieee; @@ -22,7 +23,7 @@ entity CTS_TRG_INPUT is RST_IN : in std_logic; DATA_IN : in std_logic; DATA_OUT : out std_logic; - CONFIG_IN : in std_logic_vector(15 downto 0) := (others => '0') + CONFIG_IN : in std_logic_vector(19 downto 0) := (others => '0') ); end CTS_TRG_INPUT; @@ -37,12 +38,15 @@ architecture rtl of CTS_TRG_INPUT is signal config_invert_i : std_logic; signal config_over_ena_i : std_logic; signal config_over_val_i : std_logic; + signal config_downscale_i: integer range 15 downto 0; -- connection between stages signal from_inverter_i, from_delay_i, from_spike_i : std_logic; signal delay_line_i : std_logic_vector(MAX_DELAY-1 downto 0); signal spike_rej_counter_i : integer range 0 to MAX_SPIKE_REJ-1; + signal signal_counter_i : unsigned(15 downto 0); + begin -- inverter proc_delay: process(CLK_IN) is @@ -72,12 +76,19 @@ begin proc_spike: process(CLK_IN) is begin if rising_edge(CLK_IN) then - if RST_IN = '1' or from_delay_i = '0' then + if RST_IN = '1' then + signal_counter_i <= 0; + spike_rej_counter_i <= config_spike_i; + from_spike_i <= '0'; + elsif from_delay_i = '0' then spike_rej_counter_i <= config_spike_i; - from_spike_i <= '0'; + from_spike_i <= '0'; else if spike_rej_counter_i = 0 then - from_spike_i <= '1'; + from_spike_i <= '1'; + if from_spike_i = '0' then --count only rising edges for downscaling + signal_counter_i <= signal_counter_i + 1; + end if; else spike_rej_counter_i <= spike_rej_counter_i - 1; from_spike_i <= '0'; @@ -88,14 +99,27 @@ begin -- override proc_override: process(CLK_IN) is + variable t : std_logic; begin if rising_edge(CLK_IN) then if RST_IN = '1' then DATA_OUT <= '0'; elsif config_over_ena_i = '1' then DATA_OUT <= config_over_val_i; - else + elsif config_downscale_i = 0 then DATA_OUT <= from_spike_i; + else + t := '0'; + for j in 1 to 15 loop + if signal_counter_i(j-1 downto 0) = 0 and config_downscale_i = j then + t := '1'; + end if; + end loop; + if t = '1' then + DATA_OUT <= from_spike_i; + else + DATA_OUT <= '0'; + end if; end if; end if; end process; @@ -106,4 +130,5 @@ begin config_invert_i <= CONFIG_IN(12); config_over_ena_i <= CONFIG_IN(13); config_over_val_i <= CONFIG_IN(14); + config_downscale_i<= to_integer(unsigned(CONFIG_IN(19 downto 16))); end architecture; diff --git a/cts/source/cts_trigger.vhd b/cts/source/cts_trigger.vhd index 7bba9b6..7cf62ed 100755 --- a/cts/source/cts_trigger.vhd +++ b/cts/source/cts_trigger.vhd @@ -114,8 +114,8 @@ architecture RTL of CTS_TRIGGER is -- Trigger Inputs (Spike Rejection, Negation, Override ...) signal triggers_i : std_logic_vector(EFFECTIVE_INPUT_COUNT - 1 downto 0); - type trigger_input_configs_t is array(EFFECTIVE_INPUT_COUNT - 1 downto 0) of std_logic_vector(15 downto 0); - signal trigger_input_configs_i : trigger_input_configs_t; + type trigger_input_configs_t is array(EFFECTIVE_INPUT_COUNT - 1 downto 0) of std_logic_vector(19 downto 0); + signal trigger_input_configs_i : trigger_input_configs_t := (others => (others => '0')); type trigger_input_counters_t is array(EFFECTIVE_INPUT_COUNT - 1 downto 0) of unsigned(31 downto 0); signal trigger_input_counters_i : trigger_input_counters_t; @@ -127,7 +127,7 @@ architecture RTL of CTS_TRIGGER is -- TRIGGER_PULSER_COUNT type pulser_interval_t is array(MAX(0, TRIGGER_PULSER_COUNT - 1) downto 0) of std_logic_vector(31 downto 0); - signal pulser_interval_i : pulser_interval_t; + signal pulser_interval_i : pulser_interval_t := (others => x"0001869f"); signal pulser_counter_i : pulser_interval_t := (others => (others => '0')); -- Random Pulser @@ -428,7 +428,7 @@ begin channel_mask_i <= (others => '0'); channel_edge_select_i <= (others => '1'); - trigger_input_configs_i <= (others => (others => '0')); +-- trigger_input_configs_i <= (others => (others => '0')); coin_config_i <= (others => X"000F0000"); -- pulser_interval_i <= (others => (others => '1')); @@ -514,10 +514,10 @@ begin REGIO_DATAREADY_OUT <= REGIO_READ_ENABLE_IN; REGIO_WRITE_ACK_OUT <= REGIO_WRITE_ENABLE_IN; - REGIO_DATA_OUT(15 downto 0) <= trigger_input_configs_i(i); + REGIO_DATA_OUT(19 downto 0) <= trigger_input_configs_i(i); if REGIO_WRITE_ENABLE_IN = '1' then - trigger_input_configs_i(i) <= REGIO_DATA_IN(15 downto 0); + trigger_input_configs_i(i) <= REGIO_DATA_IN(19 downto 0); end if; end if; ref_addr := ref_addr + 1; -- 2.43.0