From c1bd80ed23ca4d486f421c7618c6fd25ed6371e5 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Mon, 23 Jan 2017 16:50:48 +0100 Subject: [PATCH] Update Trb3sc template design --- pinout/trb3sc_basic.lpf | 86 +++++++++++++++++++-------------------- template/config.vhd | 4 +- template/trb3sc_basic.lpf | 7 ++++ template/trb3sc_basic.prj | 1 + template/trb3sc_basic.vhd | 28 ++++++++++++- 5 files changed, 80 insertions(+), 46 deletions(-) diff --git a/pinout/trb3sc_basic.lpf b/pinout/trb3sc_basic.lpf index 6d458be..8ac283b 100644 --- a/pinout/trb3sc_basic.lpf +++ b/pinout/trb3sc_basic.lpf @@ -303,48 +303,48 @@ IOBUF GROUP "HDR_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN ; # # LOCATE COMP "KEL38_N" SITE "AB27"; # # LOCATE COMP "KEL39_N" SITE "M33"; # # LOCATE COMP "KEL40_N" SITE "M28"; -# LOCATE COMP "KEL_1" SITE "AP5"; -# LOCATE COMP "KEL_2" SITE "AP2"; -# LOCATE COMP "KEL_3" SITE "AN1"; -# LOCATE COMP "KEL_4" SITE "AN3"; -# LOCATE COMP "KEL_5" SITE "AL5"; -# LOCATE COMP "KEL_6" SITE "AM6"; -# LOCATE COMP "KEL_7" SITE "AL4"; -# LOCATE COMP "KEL_8" SITE "AJ5"; -# LOCATE COMP "KEL_9" SITE "AJ2"; -# LOCATE COMP "KEL_10" SITE "AL3"; -# LOCATE COMP "KEL_11" SITE "AD9"; -# LOCATE COMP "KEL_12" SITE "AJ4"; -# LOCATE COMP "KEL_13" SITE "V4"; -# LOCATE COMP "KEL_14" SITE "V5"; -# LOCATE COMP "KEL_15" SITE "T9"; -# LOCATE COMP "KEL_16" SITE "T2"; -# LOCATE COMP "KEL_17" SITE "P7"; -# LOCATE COMP "KEL_18" SITE "R8"; -# LOCATE COMP "KEL_19" SITE "R2"; -# LOCATE COMP "KEL_20" SITE "P9"; -# LOCATE COMP "KEL_21" SITE "AP29"; -# LOCATE COMP "KEL_22" SITE "AP33"; -# LOCATE COMP "KEL_23" SITE "AN34"; -# LOCATE COMP "KEL_24" SITE "AP31"; -# LOCATE COMP "KEL_25" SITE "AN32"; -# LOCATE COMP "KEL_26" SITE "AM29"; -# LOCATE COMP "KEL_27" SITE "AL31"; -# LOCATE COMP "KEL_28" SITE "AL30"; -# LOCATE COMP "KEL_29" SITE "AL34"; -# LOCATE COMP "KEL_30" SITE "AJ31"; -# LOCATE COMP "KEL_31" SITE "AH33"; -# LOCATE COMP "KEL_32" SITE "AL32"; -# LOCATE COMP "KEL_33" SITE "AF32"; -# LOCATE COMP "KEL_34" SITE "AE32"; -# LOCATE COMP "KEL_35" SITE "AE30"; -# LOCATE COMP "KEL_36" SITE "AD26"; -# LOCATE COMP "KEL_37" SITE "M29"; -# LOCATE COMP "KEL_38" SITE "AC28"; -# LOCATE COMP "KEL_39" SITE "M34"; -# LOCATE COMP "KEL_40" SITE "L28"; -# DEFINE PORT GROUP "KEL_group" "KEL*" ; -# IOBUF GROUP "KEL_group" IO_TYPE=LVDS25 ; +LOCATE COMP "KEL_1" SITE "AP5"; +LOCATE COMP "KEL_2" SITE "AP2"; +LOCATE COMP "KEL_3" SITE "AN1"; +LOCATE COMP "KEL_4" SITE "AN3"; +LOCATE COMP "KEL_5" SITE "AL5"; +LOCATE COMP "KEL_6" SITE "AM6"; +LOCATE COMP "KEL_7" SITE "AL4"; +LOCATE COMP "KEL_8" SITE "AJ5"; +LOCATE COMP "KEL_9" SITE "AJ2"; +LOCATE COMP "KEL_10" SITE "AL3"; +LOCATE COMP "KEL_11" SITE "AD9"; +LOCATE COMP "KEL_12" SITE "AJ4"; +LOCATE COMP "KEL_13" SITE "V4"; +LOCATE COMP "KEL_14" SITE "V5"; +LOCATE COMP "KEL_15" SITE "T9"; +LOCATE COMP "KEL_16" SITE "T2"; +LOCATE COMP "KEL_17" SITE "P7"; +LOCATE COMP "KEL_18" SITE "R8"; +LOCATE COMP "KEL_19" SITE "R2"; +LOCATE COMP "KEL_20" SITE "P9"; +LOCATE COMP "KEL_21" SITE "AP29"; +LOCATE COMP "KEL_22" SITE "AP33"; +LOCATE COMP "KEL_23" SITE "AN34"; +LOCATE COMP "KEL_24" SITE "AP31"; +LOCATE COMP "KEL_25" SITE "AN32"; +LOCATE COMP "KEL_26" SITE "AM29"; +LOCATE COMP "KEL_27" SITE "AL31"; +LOCATE COMP "KEL_28" SITE "AL30"; +LOCATE COMP "KEL_29" SITE "AL34"; +LOCATE COMP "KEL_30" SITE "AJ31"; +LOCATE COMP "KEL_31" SITE "AH33"; +LOCATE COMP "KEL_32" SITE "AL32"; +LOCATE COMP "KEL_33" SITE "AF32"; +LOCATE COMP "KEL_34" SITE "AE32"; +LOCATE COMP "KEL_35" SITE "AE30"; +LOCATE COMP "KEL_36" SITE "AD26"; +LOCATE COMP "KEL_37" SITE "M29"; +LOCATE COMP "KEL_38" SITE "AC28"; +LOCATE COMP "KEL_39" SITE "M34"; +LOCATE COMP "KEL_40" SITE "L28"; +DEFINE PORT GROUP "KEL_group" "KEL*" ; +IOBUF GROUP "KEL_group" IO_TYPE=LVDS25 ; ################################################################# # Many LED @@ -508,4 +508,4 @@ LOCATE COMP "TEST_LINE_13" SITE "D20"; LOCATE COMP "TEST_LINE_14" SITE "F21"; LOCATE COMP "TEST_LINE_15" SITE "F22"; DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ; -IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=8; \ No newline at end of file +IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=8; diff --git a/template/config.vhd b/template/config.vhd index 1859932..9bb53f5 100644 --- a/template/config.vhd +++ b/template/config.vhd @@ -23,7 +23,7 @@ package config is constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"60"; --set to 0 for backplane serdes, set to 3 for front SFP serdes - constant SERDES_NUM : integer := 0; + constant SERDES_NUM : integer := 3; constant INCLUDE_UART : integer := c_YES; constant INCLUDE_SPI : integer := c_YES; @@ -102,4 +102,4 @@ function generateIncludedFeatures return std_logic_vector is constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures; -end package body; \ No newline at end of file +end package body; diff --git a/template/trb3sc_basic.lpf b/template/trb3sc_basic.lpf index e69de29..82eb127 100644 --- a/template/trb3sc_basic.lpf +++ b/template/trb3sc_basic.lpf @@ -0,0 +1,7 @@ + +MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" CLKNET clk_sys TO CLKNET clk_sys 5x; +MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" CLKNET clk_sys TO CELL "THE_TDC/*Channe*/Channel200/RingBuffer*FIFO/*" 5x; + +MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" TO CLKNET clk_full_osc 2x; +MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" TO CLKNET clk_full 2x; + diff --git a/template/trb3sc_basic.prj b/template/trb3sc_basic.prj index fa52f08..c24b807 100644 --- a/template/trb3sc_basic.prj +++ b/template/trb3sc_basic.prj @@ -92,6 +92,7 @@ add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x8k_oreg.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_9x2k_oreg.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" diff --git a/template/trb3sc_basic.vhd b/template/trb3sc_basic.vhd index 4590ca3..e57c6e2 100644 --- a/template/trb3sc_basic.vhd +++ b/template/trb3sc_basic.vhd @@ -40,7 +40,7 @@ entity trb3sc_basic is --to be added --KEL Connector --- KEL : inout std_logic_vector(40 downto 1); + KEL : inout std_logic_vector(40 downto 1); --Additional IO HDR_IO : inout std_logic_vector(10 downto 1); @@ -145,6 +145,11 @@ architecture trb3sc_arch of trb3sc_basic is signal lcd_data : std_logic_vector(511 downto 0); signal sfp_los_i, sfp_txdis_i, sfp_prsnt_i : std_logic; + + type a_t is array(1 to 16) of std_logic_vector(6000 downto 0); + signal c : a_t; + attribute syn_keep of c : signal is true; + attribute syn_preserve of c : signal is true; attribute syn_keep of GSR_N : signal is true; attribute syn_preserve of GSR_N : signal is true; @@ -415,6 +420,27 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record -- TEST_LINE <= med_stat_debug(15 downto 0); + +readout_tx(0).data_finished <= '1'; +readout_tx(0).data_write <= '0'; +readout_tx(0).busy_release <= '1'; + + +-- gen_chains : for i in 1 to 16 generate +-- process begin +-- wait until rising_edge(clk_full); +-- c(i)(5000 downto 1) <= c(i)(4999 downto 0); +-- c(i)(0) <= not c(i)(0) or KEL(i); +-- BACK_GPIO(i-1) <= c(i)(5000); +-- if reset_i = '1' then +-- c(i)(5000 downto 0) <= (others => '0'); +-- end if; +-- end process; +-- +-- end generate; + + + end architecture; -- 2.43.0