From c1cf13d334cb9d4093347f488316bcd80a90d0ef Mon Sep 17 00:00:00 2001 From: Tobias Weber Date: Wed, 3 Jan 2018 15:36:55 +0100 Subject: [PATCH] Testbench for sensor board slow control and minor bugfixes to corresponding source files. --- mupix/Mupix8/sources/MupixBoardDAC.vhd | 21 +-- mupix/Mupix8/sources/TestpulseGenerator.vhd | 4 +- mupix/Mupix8/tb/MupixBoardDACTest.vhd | 161 ++++++++++++++++++++ 3 files changed, 175 insertions(+), 11 deletions(-) create mode 100644 mupix/Mupix8/tb/MupixBoardDACTest.vhd diff --git a/mupix/Mupix8/sources/MupixBoardDAC.vhd b/mupix/Mupix8/sources/MupixBoardDAC.vhd index ba48fff..103df86 100644 --- a/mupix/Mupix8/sources/MupixBoardDAC.vhd +++ b/mupix/Mupix8/sources/MupixBoardDAC.vhd @@ -8,6 +8,9 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity MupixBoardDAC is + generic( + fpga_clock_speed : integer := 1e8; + spi_clock_speed : integer := 5e4); port( clk : in std_logic; --clock reset : in std_logic; --reset @@ -55,8 +58,8 @@ architecture RTL of MupixBoardDAC is component ADS1018SPI generic( - fpga_clock_speed : integer := 1e8; - spi_clock_speed : integer := 1e4 + fpga_clock_speed : integer; + spi_clock_speed : integer ); port( clk : in std_logic; @@ -113,8 +116,8 @@ begin threshold_injection_dac : entity work.LTC1658SPI generic map( data_length => c_bits_threshold_dacs, - fpga_clock_speed => 1e8, --100 MHz - spi_clock_speed => 5e4 --50 kHz + fpga_clock_speed => fpga_clock_speed, --100 MHz + spi_clock_speed => spi_clock_speed --50 kHz ) port map( clk => clk, @@ -131,8 +134,8 @@ begin temperature_dac : entity work.LTC1658SPI generic map( data_length => c_bits_temperature_dac, - fpga_clock_speed => 1e8, --100 MHz - spi_clock_speed => 5e4 --50 kHz + fpga_clock_speed => fpga_clock_speed, --100 MHz + spi_clock_speed => spi_clock_speed --50 kHz ) port map( clk => clk, @@ -149,8 +152,8 @@ begin temperature_adc : component ADS1018SPI generic map( - fpga_clock_speed => 1e8, - spi_clock_speed => 5e4 + fpga_clock_speed => fpga_clock_speed, + spi_clock_speed => spi_clock_speed ) port map( clk => clk, @@ -245,7 +248,7 @@ begin start_write_temperature <= '1'; SLV_ACK_OUT <= '1'; when x"0096" => - start_write_threshold <= '1'; + start_write_threshold <= SLV_DATA_IN(0); SLV_ACK_OUT <= '1'; when x"0097" => config_adc <= SLV_DATA_IN(15 downto 0); diff --git a/mupix/Mupix8/sources/TestpulseGenerator.vhd b/mupix/Mupix8/sources/TestpulseGenerator.vhd index 2a7c288..fb9f473 100644 --- a/mupix/Mupix8/sources/TestpulseGenerator.vhd +++ b/mupix/Mupix8/sources/TestpulseGenerator.vhd @@ -48,7 +48,7 @@ begin when gen => pulse_o <= '1'; length_counter <= length_counter + 1; - if length_counter = unsigned(pulse_length) then + if length_counter = unsigned(pulse_length) - 1 then injection_generator_fsm <= pause; pause_counter <= (others => '0'); else @@ -57,7 +57,7 @@ begin when pause => pulse_o <= '0'; if pulse_pause /= x"0000" then - if std_logic_vector(pause_counter) = pulse_pause then + if pause_counter = unsigned(pulse_pause) - 1 then injection_generator_fsm <= gen; length_counter <= (others => '0'); else diff --git a/mupix/Mupix8/tb/MupixBoardDACTest.vhd b/mupix/Mupix8/tb/MupixBoardDACTest.vhd new file mode 100644 index 0000000..3ed4f34 --- /dev/null +++ b/mupix/Mupix8/tb/MupixBoardDACTest.vhd @@ -0,0 +1,161 @@ +----------------------------------------------------------------------------------- +-- Test of Mupix 8 board slow control excluding control of Mupix 8 itself +-- Tobias Weber +-- Ruhr Unversitaet Bochum +------------------------------------------------------------------------------------ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.TRBSimulationPkg.all; + +entity MupixBoardDACTest is +end entity MupixBoardDACTest; + +architecture sim of MupixBoardDACTest is + + component MupixBoardDAC + generic( + fpga_clock_speed : integer := 1e8; + spi_clock_speed : integer := 5e4); + port( + clk : in std_logic; + reset : in std_logic; + spi_dout_dac : in std_logic; + dac4_dout : in std_logic; + spi_dout_adc : in std_logic; + spi_clk : out std_logic; + spi_din : out std_logic; + spi_ld_tmp_dac : out std_logic; + spi_ld_thres : out std_logic; + spi_cs_adc : out std_logic; + injection_pulse : out std_logic; + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ADDR_IN : in std_logic_vector(15 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic + ); + end component MupixBoardDAC; + + constant c_clk_period : time := 10 ns; + + signal clk : std_logic; + signal spi_clk : std_logic; + signal spi_din : std_logic; + signal reset : std_logic := '0'; + signal spi_dout_dac : std_logic := '0'; + signal dac4_dout : std_logic := '0'; + signal spi_dout_adc : std_logic := '0'; + signal spi_ld_tmp_dac : std_logic; + signal spi_ld_thres : std_logic; + signal spi_cs_adc : std_logic; + signal injection_pulse : std_logic; + signal SLV_READ_IN : std_logic := '0'; + signal SLV_WRITE_IN : std_logic := '0'; + signal SLV_DATA_OUT : std_logic_vector(31 downto 0); + signal SLV_DATA_IN : std_logic_vector(31 downto 0) := (others => '0'); + signal SLV_ADDR_IN : std_logic_vector(15 downto 0) := (others => '0'); + signal SLV_ACK_OUT : std_logic; + signal SLV_NO_MORE_DATA_OUT : std_logic; + signal SLV_UNKNOWN_ADDR_OUT : std_logic; + + signal temp_dac : std_logic_vector(15 downto 0) := (others => '0'); + signal threshold_dacs : std_logic_vector(63 downto 0) := (others => '0'); + + +begin + + MupixBoardDAC_1:entity work.MupixBoardDAC + generic map( + fpga_clock_speed => 1e8, + spi_clock_speed => 5e6 + ) + port map( + clk => clk, + reset => reset, + spi_dout_dac => spi_dout_dac, + dac4_dout => dac4_dout, + spi_dout_adc => spi_dout_adc, + spi_clk => spi_clk, + spi_din => spi_din, + spi_ld_tmp_dac => spi_ld_tmp_dac, + spi_ld_thres => spi_ld_thres, + spi_cs_adc => spi_cs_adc, + injection_pulse => injection_pulse, + SLV_READ_IN => SLV_READ_IN, + SLV_WRITE_IN => SLV_WRITE_IN, + SLV_DATA_OUT => SLV_DATA_OUT, + SLV_DATA_IN => SLV_DATA_IN, + SLV_ADDR_IN => SLV_ADDR_IN, + SLV_ACK_OUT => SLV_ACK_OUT, + SLV_NO_MORE_DATA_OUT => SLV_NO_MORE_DATA_OUT, + SLV_UNKNOWN_ADDR_OUT => SLV_UNKNOWN_ADDR_OUT + ); + + dac_proc : process(spi_clk) is + begin + if spi_clk'event and spi_clk = '1' then + temp_dac <= temp_dac(temp_dac'length - 2 downto 0) & spi_din; + threshold_dacs <= threshold_dacs(threshold_dacs'length - 2 downto 0) & spi_din; + end if; + end process dac_proc; + + dac4_dout <= threshold_dacs(threshold_dacs'length - 1) after 150 ns; + spi_dout_dac <= temp_dac(temp_dac'length - 1) after 150 ns; + + clk_gen : process is + begin + clk <= '0'; + wait for c_clk_period/2; + clk <= '1'; + wait for c_clk_period/2; + end process clk_gen; + + stimulus : process is + begin + wait for 100 ns; + --test injection pulse + --single pulse, no pause + TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"00500000", x"0099", c_clk_period); + wait for 100*c_clk_period; + --several pulse, 20 clk periods pause + TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"000A0014", x"0099", c_clk_period); + wait for 400*c_clk_period; + TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"00000000", x"0099", c_clk_period); + --write to threshold DACs (2x to test readback) + TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"AAAABBBB", x"0090", c_clk_period); + TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"CCCCDDDD", x"0091", c_clk_period); + TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"00000001", x"0096", c_clk_period); + TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"00000000", x"0096", c_clk_period); + if spi_ld_thres = '0' then + wait until spi_ld_thres = '1'; + wait for 40*c_clk_period; + end if; + TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"DDDDBBBB", x"0090", c_clk_period); + TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"CCCCAAAA", x"0091", c_clk_period); + TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"00000001", x"0096", c_clk_period); + TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"00000000", x"0096", c_clk_period); + if spi_ld_thres = '0' then + wait until spi_ld_thres = '1'; + wait for 40*c_clk_period; + end if; + --write to temperature DAC + TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"0000ABCD", x"0094", c_clk_period); + if spi_ld_tmp_dac = '0' then + wait until spi_ld_tmp_dac = '1'; + wait for 40*c_clk_period; + end if; + TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"0000ABCD", x"0094", c_clk_period); + if spi_ld_tmp_dac = '0' then + wait until spi_ld_tmp_dac = '1'; + wait for 40*c_clk_period; + end if; + wait; + end process stimulus; + + +end architecture; \ No newline at end of file -- 2.43.0