From c3176170219f2bb97c32125f74b28a0d0b7af904 Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Wed, 27 Apr 2022 14:21:34 +0200 Subject: [PATCH] phaserbox added --- special/clockbox.vhd | 12 ++- special/ddmtd.vhd | 23 +++-- special/phaserbox.vhd | 195 +++++++++++++++++++++++++++++++++++++++++ special/statistics.vhd | 6 +- 4 files changed, 223 insertions(+), 13 deletions(-) create mode 100644 special/phaserbox.vhd diff --git a/special/clockbox.vhd b/special/clockbox.vhd index 596f1e4..326c630 100644 --- a/special/clockbox.vhd +++ b/special/clockbox.vhd @@ -19,6 +19,14 @@ end entity clockbox; architecture clockbox_arch of clockbox is -- Components + component clockpoint is + port( + SAMPLE_CLK : in std_logic; + DATA_IN : in std_logic; + CLK_DATA : in std_logic; + DATA_OUT : out std_logic + ); + end component clockpoint; -- state machine signals @@ -35,7 +43,7 @@ architecture clockbox_arch of clockbox is begin - THE_PING_POINT: entity clockpoint + THE_PING_POINT: clockpoint port map( SAMPLE_CLK => SAMPLE_CLK, DATA_IN => PING_IN, @@ -43,7 +51,7 @@ begin DATA_OUT => PING_OUT ); - THE_PONG_POINT: entity clockpoint + THE_PONG_POINT: clockpoint port map( SAMPLE_CLK => SAMPLE_CLK, DATA_IN => PONG_IN, diff --git a/special/ddmtd.vhd b/special/ddmtd.vhd index 39dc808..325e465 100644 --- a/special/ddmtd.vhd +++ b/special/ddmtd.vhd @@ -47,9 +47,12 @@ architecture ddmtd_arch of ddmtd is signal delay_ce_x : std_logic; signal delay_rst : std_logic; signal delay_ctr : unsigned(10 downto 0); + signal delay_store_x : std_logic; signal delay_store : std_logic; signal delay_valid : std_logic; signal delay_data : std_logic_vector(9 downto 0); + signal clr_done_i : std_logic; + signal clr_done_q : std_logic; attribute HGROUP : string; -- attribute BBOX : string; @@ -62,12 +65,14 @@ architecture ddmtd_arch of ddmtd is begin -THE_SAMPLER_PROC: process( AUXCLK ) +THE_SYNC_PROC: process( AUXCLK ) begin - if( rising_edge(AUXCLK) ) then - delay_valid <= delay_store; + if( rising_edge(AUXCLK) ) then + delay_store <= delay_store_x; + delay_valid <= delay_store; + clr_done_q <= clr_done_i; end if; -end process THE_SAMPLER_PROC; +end process THE_SYNC_PROC; -- PING deglitcher THE_PING_DEGLITCH: deglitch @@ -101,9 +106,11 @@ begin end if; end process THE_DELAY_CTR_PROC; -delay_rst <= start_pong_i when FSM_ACTIVE_IN = '0' else FSM_RST_IN; -delay_store <= start_pong_i when FSM_ACTIVE_IN = '0' else '1'; -delay_ce_x <= delay_ce when FSM_ACTIVE_IN = '0' else FSM_CE_IN; +delay_rst <= start_ping_i when FSM_ACTIVE_IN = '0' else FSM_RST_IN; +delay_store_x <= start_pong_i when FSM_ACTIVE_IN = '0' else '1'; +delay_ce_x <= delay_ce when FSM_ACTIVE_IN = '0' else FSM_CE_IN; + +clr_done_i <= '1' when (delay_ctr = b"11_1111_1110") else '0'; THE_DELAY_CE_PROC: process( AUXCLK, RESET ) begin @@ -146,6 +153,6 @@ START_PONG_OUT <= start_pong_i; DELAY_VALUE_OUT <= delay_data; DELAY_VALID_OUT <= delay_valid; TOGGLE_OUT <= toggle_q; -FSM_CLR_DONE_OUT <= std_logic(delay_ctr(10)); +FSM_CLR_DONE_OUT <= clr_done_q; end architecture; diff --git a/special/phaserbox.vhd b/special/phaserbox.vhd new file mode 100644 index 0000000..80a4a76 --- /dev/null +++ b/special/phaserbox.vhd @@ -0,0 +1,195 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; + +entity phaserbox is +port( + SAMPLE_CLK : in std_logic; -- auxiliary clock for sampling + RESET : in std_logic; + -- input signals + TX_SYNC_IN : in std_logic; -- outgoing sync signal + TX_CLK_IN : in std_logic; -- TX clock + RX_SYNC_IN : in std_logic; -- incoming sync signal + RX_CLK_IN : in std_logic; -- RX clock + START_DELAY_IN : in std_logic; -- outgoing DLM komma + STOP_DELAY_IN : in std_logic; -- incoming DLM komma + -- histogram + HISTO_CLK : in std_logic; + HISTO_START_IN : in std_logic; + HISTO_DONE_OUT : out std_logic; + HISTO_ADDR_IN : in std_logic_vector(9 downto 0); + HISTO_DATA_OUT : out std_logic_vector(17 downto 0); + -- + COARSE_DELAY_OUT : out std_logic_vector(31 downto 0); + -- + DEBUG_OUT : out std_logic_vector(15 downto 0) +); +end entity phaserbox; + +architecture phaserbox_arch of phaserbox is + + -- Components + component clockbox is + port( + SAMPLE_CLK : in std_logic; + PING_IN : in std_logic; + CLK_PING : in std_logic; + PONG_IN : in std_logic; + CLK_PONG : in std_logic; + PING_OUT : out std_logic; + PONG_OUT : out std_logic + ); + end component clockbox; + + component ddmtd is + port( + AUXCLK : in std_logic; -- auxiliary clock for sampling + RESET : in std_logic; + -- input signals + PING_IN : in std_logic; -- TX_K signal + PONG_IN : in std_logic; -- RX_K signal + -- test signals + PING_OUT : out std_logic; -- stretched TX_K signal + PONG_OUT : out std_logic; -- stretched RX_K signal + START_PING_OUT : out std_logic; -- rising edge of stretched TX_K signal + START_PONG_OUT : out std_logic; -- rising edge of stretched RX_K signal + TOGGLE_OUT : out std_logic; -- for checking by scope + -- result + DELAY_VALUE_OUT : out std_logic_vector(9 downto 0); -- result of measurement + DELAY_VALID_OUT : out std_logic; -- result of measurement is valid + -- remote control + FSM_ACTIVE_IN : in std_logic; + FSM_CE_IN : in std_logic; + FSM_RST_IN : in std_logic; + FSM_CLR_DONE_OUT : out std_logic + ); + end component ddmtd; + + component statistics is + port( + AUXCLK : in std_logic; + RESET : in std_logic; + DELAY_CLK : in std_logic; + DELAY_START_IN : in std_logic; + DELAY_STOP_IN : in std_logic; + DELAY_COARSE_OUT : out std_logic_vector(31 downto 0); + DELAY_VALUE_IN : in std_logic_vector(9 downto 0); + DELAY_VALID_IN : in std_logic; + FSM_START_IN : in std_logic; + FSM_CLR_DONE_IN : in std_logic; + FSM_ACTIVE_OUT : out std_logic; + FSM_CE_OUT : out std_logic; + FSM_RST_OUT : out std_logic; + FSM_DONE_OUT : out std_logic; + RD_CLK : in std_logic; + RD_ADDRESS_IN : in std_logic_vector(9 downto 0); + RD_DATA_OUT : out std_logic_vector(17 downto 0) + ); + end component statistics; + + -- Signals + signal tx_sync_q : std_logic; + signal rx_sync_q : std_logic; + signal start_tx_sync_i : std_logic; + signal start_rx_sync_i : std_logic; + signal stretched_tx_sync_i : std_logic; -- OBSELETE + signal stretched_rx_sync_i : std_logic; -- OBSELETE + signal delay_value_i : std_logic_vector(9 downto 0); + signal delay_valid_i : std_logic; + signal fsm_active_i : std_logic; + signal fsm_ce_i : std_logic; + signal fsm_rst_i : std_logic; + signal fsm_clr_done_i : std_logic; + signal cal_phase_q : std_logic; -- OBSELETE + signal toggle_q : std_logic; -- OBSELETE + signal coarse_delay_i : std_logic_vector(31 downto 0); + signal debug : std_logic_vector(15 downto 0); + + attribute HGROUP : string; +-- attribute BBOX : string; + attribute HGROUP of phaserbox_arch : architecture is "phaserbox_group"; +-- attribute BBOX of ddmtd_arch : architecture is "2,2"; + attribute syn_sharing : string; + attribute syn_sharing of phaserbox_arch : architecture is "off"; + attribute syn_hier : string; + attribute syn_hier of phaserbox_arch : architecture is "hard"; + +begin + + -- + cal_phase_q <= (TX_SYNC_IN xor RX_SYNC_IN) when rising_edge(TX_CLK_IN); + + -- clock domain transfer with defined placement + THE_CLOCKBOX: clockbox + port map( + SAMPLE_CLK => SAMPLE_CLK, + PING_IN => TX_SYNC_IN, + CLK_PING => TX_CLK_IN, + PONG_IN => RX_SYNC_IN, + CLK_PONG => RX_CLK_IN, + PING_OUT => tx_sync_q, + PONG_OUT => rx_sync_q + ); + + -- + THE_DDMTD: ddmtd + port map( + AUXCLK => SAMPLE_CLK, + RESET => RESET, + -- input signals + PING_IN => tx_sync_q, + PONG_IN => rx_sync_q, + -- test signals + PING_OUT => stretched_tx_sync_i, -- stretched TX_K signal + PONG_OUT => stretched_rx_sync_i, -- stretched RX_K signal + START_PING_OUT => start_tx_sync_i, + START_PONG_OUT => start_rx_sync_i, + TOGGLE_OUT => toggle_q, -- for checking by scope + -- result + DELAY_VALUE_OUT => delay_value_i, + DELAY_VALID_OUT => delay_valid_i, + -- remote control + FSM_ACTIVE_IN => fsm_active_i, + FSM_CE_IN => fsm_ce_i, + FSM_RST_IN => fsm_rst_i, + FSM_CLR_DONE_OUT => fsm_clr_done_i + ); + + -- + THE_STATISTICS: statistics + port map( + AUXCLK => SAMPLE_CLK, + RESET => RESET, + DELAY_CLK => TX_CLK_IN, + DELAY_START_IN => START_DELAY_IN, + DELAY_STOP_IN => STOP_DELAY_IN, + DELAY_COARSE_OUT => coarse_delay_i, + DELAY_VALUE_IN => delay_value_i, + DELAY_VALID_IN => delay_valid_i, + FSM_START_IN => HISTO_START_IN, + FSM_CLR_DONE_IN => fsm_clr_done_i, + FSM_ACTIVE_OUT => fsm_active_i, + FSM_CE_OUT => fsm_ce_i, + FSM_RST_OUT => fsm_rst_i, + FSM_DONE_OUT => HISTO_DONE_OUT, + RD_CLK => HISTO_CLK, + RD_ADDRESS_IN => HISTO_ADDR_IN, + RD_DATA_OUT => HISTO_DATA_OUT + ); + + -- DEBUG + debug(15 downto 6) <= (others => '0'); + debug(5) <= start_rx_sync_i; + debug(4) <= start_tx_sync_i; + debug(3) <= cal_phase_q; + debug(2) <= toggle_q; + debug(1) <= stretched_rx_sync_i; + debug(0) <= stretched_tx_sync_i; + + -- Outputs + COARSE_DELAY_OUT <= cal_phase_q & coarse_delay_i(30 downto 0); + DEBUG_OUT <= debug; + +end architecture; diff --git a/special/statistics.vhd b/special/statistics.vhd index 24f88a0..93517f1 100644 --- a/special/statistics.vhd +++ b/special/statistics.vhd @@ -179,13 +179,13 @@ DELAY_COARSE_OUT <= coarse_delay; end if; when PCTR => bsm <= x"4"; NEXT_STATE <= DLY1; - fsm_act_x <= '1'; + --fsm_act_x <= '1'; when DLY1 => bsm <= x"5"; if( DELAY_VALID_IN = '1' ) then NEXT_STATE <= WFD; else NEXT_STATE <= DLY1; - fsm_act_x <= '1'; + --fsm_act_x <= '1'; end if; when WFD => bsm <= x"6"; if( DELAY_VALID_IN = '1' ) then @@ -269,7 +269,7 @@ DELAY_COARSE_OUT <= coarse_delay; end process THE_SUM_CTR_PROC; sum_ctr_done <= std_logic(sum_ctr(18)); --- sum_ctr_done <= std_logic(sum_ctr(16)); +-- sum_ctr_done <= std_logic(sum_ctr(14)); -- mean value mean_sum_x <= mean_sum_q + unsigned(DELAY_VALUE_IN); -- 2.43.0