From c3d32c06712c86bff5cc93566c73f4ed633d07fd Mon Sep 17 00:00:00 2001 From: hadaq Date: Wed, 4 Jul 2012 09:39:28 +0000 Subject: [PATCH] *** empty log message *** --- tdc_test/trb3_periph.prj | 20 ++++++++++---------- tdc_test/trb3_periph.vhd | 22 +++++++++++----------- 2 files changed, 21 insertions(+), 21 deletions(-) diff --git a/tdc_test/trb3_periph.prj b/tdc_test/trb3_periph.prj index 0bccfa4..3f480bb 100644 --- a/tdc_test/trb3_periph.prj +++ b/tdc_test/trb3_periph.prj @@ -159,13 +159,13 @@ add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd" add_file -vhdl -lib "work" "trb3_periph.vhd" -add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.4/Adder_304.vhd" -add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.4/bit_sync.vhd" -add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.4/Channel.vhd" -add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.4/Encoder_304_Bit.vhd" -add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.4/FIFO_32x32_OutReg.vhd" -add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.4/Reference_channel.vhd" -add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.4/ROM_encoder_3.vhd" -add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.4/ROM_FIFO.vhd" -add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.4/TDC.vhd" -add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.4/up_counter.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.3/Adder_304.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.3/bit_sync.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.3/Channel.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.3/Encoder_304_Bit.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.3/FIFO_32x32_OutReg.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.3/Reference_channel.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.3/ROM_encoder_3.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.3/ROM_FIFO.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.3/TDC.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.3/up_counter.vhd" diff --git a/tdc_test/trb3_periph.vhd b/tdc_test/trb3_periph.vhd index 0de395a..6d7f153 100644 --- a/tdc_test/trb3_periph.vhd +++ b/tdc_test/trb3_periph.vhd @@ -33,7 +33,7 @@ entity trb3_periph is --Connection to ADA AddOn SPARE_LINE : inout std_logic_vector(3 downto 0); --inputs only INP : in std_logic_vector(63 downto 0); --- DAC_SDO : in std_logic; + DAC_SDO : in std_logic; DAC_SDI : out std_logic; DAC_SCK : out std_logic; DAC_CS : out std_logic_vector(3 downto 0); @@ -203,7 +203,7 @@ architecture trb3_periph_arch of trb3_periph is signal time_counter : unsigned(31 downto 0); --TDC - signal hit_in_i : std_logic_vector(63 downto 1); + signal hit_in_i : std_logic_vector(64 downto 1); --TDC component component TDC @@ -616,7 +616,7 @@ begin THE_TDC : TDC generic map ( - CHANNEL_NUMBER => 64, -- Number of TDC channels + CHANNEL_NUMBER => 34, -- Number of TDC channels STATUS_REG_NR => REGIO_NUM_STAT_REGS, CONTROL_REG_NR => REGIO_NUM_CTRL_REGS) port map ( @@ -624,7 +624,7 @@ begin CLK_TDC => CLK_PCLK_LEFT, -- Clock used for the time measurement CLK_READOUT => clk_100_i, -- Clock for the readout REFERENCE_TIME => timing_trg_received_i, -- Reference time input - HIT_IN => hit_in_i(64 downto 1), -- Channel start signals + HIT_IN => hit_in_i(33 downto 1), -- Channel start signals TRG_WIN_PRE => ctrl_reg(42 downto 32), -- Pre-Trigger window width TRG_WIN_POST => ctrl_reg(58 downto 48), -- Post-Trigger window width @@ -658,11 +658,11 @@ begin -- For single edge measurements hit_in_i(64 downto 1) <= INP(63 downto 0); --- -- For ToT Measurements --- hit_in_i(1) <= not timing_trg_received_i; --- Gen_Hit_In_Signals : for i in 1 to 19 generate --- hit_in_i(i*2) <= INP(i-1); --- hit_in_i(i*2+1) <= not INP(i-1); --- end generate Gen_Hit_In_Signals; - + ---- For ToT Measurements + --hit_in_i(1) <= not timing_trg_received_i; + --Gen_Hit_In_Signals : for i in 1 to 19 generate + -- hit_in_i(i*2) <= INP(i-1); + -- hit_in_i(i*2+1) <= not INP(i-1); + --end generate Gen_Hit_In_Signals; + end architecture; -- 2.43.0