From c426ca443b561b1e01fc097fed4312c6f4090d92 Mon Sep 17 00:00:00 2001 From: hadaq Date: Thu, 29 Apr 2010 08:02:28 +0000 Subject: [PATCH] *** empty log message *** --- rich.tex | 152 ++++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 151 insertions(+), 1 deletion(-) diff --git a/rich.tex b/rich.tex index c918bc9..ca63e76 100755 --- a/rich.tex +++ b/rich.tex @@ -223,7 +223,7 @@ The powerup values should allow stable operation. \subsubsection{APV control register} -For each APV frontend card a control \/ statsu register is implemented. The +For each APV frontend card a control \/ status register is implemented. The upper 16bit deliver status information, the lower 16bit are used as control register. @@ -251,4 +251,154 @@ register. \end{center} \end{table} +\subsubsection{ADC level register} +For digital header reconstruction from analog values this register provides +four settings. BIT\_LOW defines the maximum value for a digital Zero, +BIT\_HIGH the minimum value for a digital One, and FLAT\_LOW \/ FLAT\_HIGH +the limits for a flatline caused by a missing APV frontend card (which equals +to a flat line on ADC around half of the input value). + +\noindent Values are given in raw ADC units, the least significant nibble +of the value is fixed to zero.\\ +To set 0xA00 as BIT\_HIGH, 0xA0 has to be written to D[31:0] + +\noindent The APV sync state machines need correct values in this register +for operation. + +\noindent Powerup value of this register is the recommended value given in +table~\ref{richadclevel}. + +\begin{table} +\begin{center} +\begin{tabularx}{\textwidth}{|c|c|c|X|} +\hline +\textbf{Bits} & \textbf{write \/ read access} & \textbf{recommended value} & + \textbf{description} \\ +\hline +\hline +31 -- 24 & BIT\_HIGH & 0xA0 & bit One min level \\ +23 -- 16 & BIT\_LOW & 0x30 & bit Zero max level \\ +15 -- 8 & FLAT\_HIGH & 0x88 & flatline max level \\ +7 -- 0 & FLAT\_LOW & 0x78 & flatline min level \\ +\hline +\end{tabularx} +\caption{ADC level register} +\label{richadclevel} +\end{center} +\end{table} + +\subsubsection{TRG control register} + +The RICH ADCM features four timing trigger lines, which can in addition be +triggered by slow control access. Input lines are LVDS levels, have +$100\>\Omega$ termination onboard and are protected by a SN65LVDS33 receiver. + +\noindent It is recommended to use only hardware input 0 for external +triggers. \\ +The other three lines are reserved for future enhancements, namely a central +40MHz APV clock and centrally synchronized APV trigger pulses. + +\noindent Though the ADCMv3 design explicitly supports several APV data frames +per trigger, it is strictly recommended not to use this feature, as data +transport on Gigabit Ethernet may fail due to packet size overflow.\\ +Moreover, unpacking and analysis software will most likely not work with +multi-frame data. + +\noindent For reference only: the TRG\_x\_DEL is given in 40MHz APV clock +cycles, with 0x0 corresponding to the minimum three clock cycles delay +between two APV triggers. + +\noindent Multi-frame triggering only works with APV25S1 configured to +Peak or Deconvolution mode (please see the APV manual for details). Operating +the APV25S1 in Multi mode with multi-frame triggering will lead to data +corruption.\\ +\textbf{You have been warned.} + +\begin{table} +\begin{center} +\begin{tabularx}{\textwidth}{|c|c|c|X|} +\hline +\textbf{Bits} & \textbf{write \/ read access} & \textbf{recommended value} & + \textbf{description} \\ +\hline +\hline +31 -- 28 & TRG\_3\_NUM & 0x1 & number of APV frames \\ +27 -- 24 & TRG\_3\_DEL & 0x0 & delay between APV triggers \\ +23 -- 20 & TRG\_2\_NUM & 0x1 & number of APV frames \\ +19 -- 16 & TRG\_2\_DEL & 0x0 & delay between APV triggers \\ +15 -- 12 & TRG\_1\_NUM & 0x1 & number of APV frames \\ +11 -- 8 & TRG\_1\_DEL & 0x0 & delay between APV triggers \\ +7 -- 4 & TRG\_0\_NUM & 0x1 & number of APV frames \\ +7 -- 0 & TRG\_0\_DEL & 0x0 & delay between APV triggers \\ +\hline +\end{tabularx} +\caption{Trigger control register} +\label{richtrgctrl} +\end{center} +\end{table} + +\subsubsection{PLL control register} + +The ADCM FPGA uses several PLLs and DLLs for operation. Status and control +signals for these units are combined together with external trigger input +control bits in this register. + +\noindent Information from backplane switches (sector and module number) can +also be readback here for crosschecking. + +\noindent The clock phase between ADC and APV clock can be adjusted here. +The recommended value of 0x2 is set as powerup default. When changing this +number it is strongly recommended to check correct ADC sampling of APV data +by the internal ADC logic analyzers. + +\begin{table} +\begin{center} +\begin{tabularx}{\textwidth}{|c|X|X|X|} +\hline +\textbf{Bits} & \textbf{write access} & \textbf{read access} & + \textbf{description}\\ +\hline +\hline +31 & --- & SYSCLK\_LOCK & must be 1 for operation \\ +30 & --- & APVCLK\_LOCK & must be 1 for operation \\ +29 & --- & ADC1\_LOCK & must be 1 for operation \\ +28 & --- & ADC0\_LOCK & must be 1 for operation \\ +27 & --- & CTS\_LOCK & must be 1 for operation \\ +26 -- 24 & --- & reserved & reserved \\ +23 & --- & reserved & reserved \\ +22 -- 20 & --- & SECTOR\_ID & backplane switch setting \\ +19 & --- & reserved & reserved \\ +18 -- 16 & --- & MODULE\_ID & backplane switch setting \\ +15 -- 12 & EXT\_IN\_ENABLE & EXT\_IN\_ENABLE & activate ext. trg. input \\ +11 -- 8 & EXT\_IN\_INVERT & EXT\_IN\_INVERT & invert ext. trg. input \\ +7 & 40MHZ\_PLL\_RST & 40MHZ\_PLL\_RST & reset APV clock PLL \\ +6 & ADC1\_PLL\_RST & ADC1\_PLL\_RST & reset ADC1 clock PLL \\ +5 & ADC0\_PLL\_RST & ADC0\_PLL\_RST & reset ADC0 clock PLL \\ +4 & CTS\_PLL\_RST & CTS\_PLL\_RST & reset CTS clock PLL \\ +3 -- 0 & ADC\_APV\_DEL & ADC\_APV\_DEL & adjust clock phase \\ + +\hline +\end{tabularx} +\caption{PLL status and control register} +\label{richpllctrl} +\end{center} +\end{table} + + +\subsubsection{ADC snoop register} + +This SPI master controls FPGA internal ADC logic analyzer. It allows reading +back 1024 samples of ADC, but has no dedicated trigger features. Main purpose +is to control the correct ADC sampling time for APV data. + +\noindent It is strongly recommended to use the \textbf{trbrichcmd} command +for operating this unit. + +\begin{figure} + \centering + \includegraphics[width=0.8\textwidth]{adc_snoop.png} + \caption[RICH ADC snoop output]{RICH ADC snoop output, with BIT\_LOW + and BIT\_HIGH settings} + \label{fig:richadcsnoop} +\end{figure} -- 2.43.0