From c498abccdff07076d50d50ba5c92a5338cb90696 Mon Sep 17 00:00:00 2001 From: hadaq Date: Fri, 10 Aug 2012 08:55:52 +0000 Subject: [PATCH] *** empty log message *** --- tdc_releases/tdc_v0.2/source/Channel.vhd | 291 ++--- ...2x512_OutReg.vhd => FIFO_32x32_OutReg.vhd} | 761 ++++------- .../tdc_v0.2/source/Reference_channel.vhd | 364 ++---- tdc_releases/tdc_v0.2/source/TDC.vhd | 532 +++----- tdc_releases/tdc_v0.2/source/trb3_periph.vhd | 20 +- .../tdc_v0.2/trb3_periph_constraints.lpf | 1161 +++++++++++++++++ 6 files changed, 1819 insertions(+), 1310 deletions(-) rename tdc_releases/tdc_v0.2/source/{FIFO_32x512_OutReg.vhd => FIFO_32x32_OutReg.vhd} (63%) create mode 100644 tdc_releases/tdc_v0.2/trb3_periph_constraints.lpf diff --git a/tdc_releases/tdc_v0.2/source/Channel.vhd b/tdc_releases/tdc_v0.2/source/Channel.vhd index 12c57c8..0220f22 100644 --- a/tdc_releases/tdc_v0.2/source/Channel.vhd +++ b/tdc_releases/tdc_v0.2/source/Channel.vhd @@ -4,10 +4,16 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_arith.all; +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.version.all; + entity Channel is generic ( - CHANNEL_ID : integer range 0 to 64); + CHANNEL_ID : integer range 1 to 64); port ( RESET_WR : in std_logic; RESET_RD : in std_logic; @@ -19,89 +25,20 @@ entity Channel is FIFO_DATA_OUT : out std_logic_vector(31 downto 0); FIFO_EMPTY_OUT : out std_logic; FIFO_FULL_OUT : out std_logic; + FIFO_ALMOST_FULL_OUT : out std_logic; COARSE_COUNTER_IN : in std_logic_vector(10 downto 0); -- LOST_HIT_NUMBER : out std_logic_vector(23 downto 0); - MEASUREMENT_NUMBER : out std_logic_vector(23 downto 0); + HIT_DETECT_NUMBER : out std_logic_vector(23 downto 0); ENCODER_START_NUMBER : out std_logic_vector(23 downto 0); + FIFO_WR_NUMBER : out std_logic_vector(23 downto 0); -- - Channel_DEBUG_01 : out std_logic_vector(31 downto 0) --- Channel_DEBUG_02 : out std_logic_vector(31 downto 0); --- Channel_DEBUG_03 : out std_logic_vector(31 downto 0); --- Channel_DEBUG_04 : out std_logic_vector(31 downto 0); --- Channel_DEBUG_05 : out std_logic_vector(31 downto 0); --- Channel_DEBUG_06 : out std_logic_vector(31 downto 0); --- Channel_DEBUG_07 : out std_logic_vector(31 downto 0); --- Channel_DEBUG_08 : out std_logic_vector(31 downto 0); --- Channel_DEBUG_09 : out std_logic_vector(31 downto 0); --- Channel_DEBUG_10 : out std_logic_vector(31 downto 0); --- Channel_DEBUG_11 : out std_logic_vector(31 downto 0); --- Channel_DEBUG_12 : out std_logic_vector(31 downto 0) + Channel_DEBUG : out std_logic_vector(31 downto 0) ); end Channel; architecture Channel of Channel is - -------------------------------------------------------------------------------- --- Component Declarations -------------------------------------------------------------------------------- - - component Adder_304 - port ( - CLK : in std_logic; - RESET : in std_logic; - DataA : in std_logic_vector(303 downto 0); - DataB : in std_logic_vector(303 downto 0); - ClkEn : in std_logic; - Result : out std_logic_vector(303 downto 0)); - end component; --- - component Encoder_304_Bit - port ( - RESET : in std_logic; - CLK : in std_logic; - START_IN : in std_logic; - THERMOCODE_IN : in std_logic_vector(303 downto 0); - FINISHED_OUT : out std_logic; - BINARY_CODE_OUT : out std_logic_vector(9 downto 0); --- BUSY_OUT : out std_logic; - ENCODER_DEBUG : out std_logic_vector(31 downto 0)); - end component; --- - component FIFO_32x512_OutReg - port ( - Data : in std_logic_vector(31 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(31 downto 0); - Empty : out std_logic; - Full : out std_logic); - end component; --- - component edge_to_pulse - port ( - clock : in std_logic; - en_clk : in std_logic; - signal_in : in std_logic; - pulse : out std_logic); - end component; --- - component signal_sync - generic ( - WIDTH : integer; - DEPTH : integer); - port ( - RESET : in std_logic; - CLK0 : in std_logic; - CLK1 : in std_logic; - D_IN : in std_logic_vector(WIDTH-1 downto 0); - D_OUT : out std_logic_vector(WIDTH-1 downto 0)); - end component; ------------------------------------------------------------------------------- -- Signal Declarations ------------------------------------------------------------------------------- @@ -125,6 +62,7 @@ architecture Channel of Channel is signal fifo_data_in_i : std_logic_vector(31 downto 0); signal fifo_empty_i : std_logic; signal fifo_full_i : std_logic; + signal fifo_almost_full_i : std_logic; signal fifo_wr_en_i : std_logic; signal fifo_rd_en_i : std_logic; signal sync_q : std_logic_vector(3 downto 0); @@ -136,10 +74,13 @@ architecture Channel of Channel is ------------------------------------------------------------------------------- -- Debug Signals ------------------------------------------------------------------------------- - signal measurement_cntr : std_logic_vector(23 downto 0); - signal measurement_reg : std_logic_vector(23 downto 0); + + signal hit_detect_cntr : std_logic_vector(23 downto 0); + signal hit_detect_cntr_reg : std_logic_vector(23 downto 0); signal encoder_start_cntr : std_logic_vector(23 downto 0); signal encoder_start_cntr_reg : std_logic_vector(23 downto 0); + signal fifo_wr_cntr : std_logic_vector(23 downto 0); + signal fifo_wr_cntr_reg : std_logic_vector(23 downto 0); signal encoder_debug_i : std_logic_vector(31 downto 0); ------------------------------------------------------------------------------- @@ -149,6 +90,7 @@ architecture Channel of Channel is attribute syn_keep of ff_array_en_i : signal is true; attribute NOMERGE : string; attribute NOMERGE of hit_buf : signal is "true"; + --attribute NOMERGE of hit_in_i : signal is "true"; attribute NOMERGE of ff_array_en_i : signal is "true"; ------------------------------------------------------------------------------- @@ -160,28 +102,6 @@ begin hit_in_i <= HIT_IN; hit_buf <= not hit_in_i; - ----purpose: Registers the hit signal - --Hit_Register : process (CLK_WR, RESET_WR) - --begin - -- if rising_edge(CLK_WR) then - -- if RESET_WR = '1' then - -- hit_reg <= '0'; - -- else - -- hit_reg <= hit_in_i; - -- end if; - -- end if; - --end process Hit_Register; - - ----purpose: Toggles between rising and falling edges - --Toggle_Edge_Detection : process (hit_reg, hit_in_i) - --begin - -- if hit_reg = '1' then - -- hit_buf <= not hit_in_i; - -- else - -- hit_buf <= hit_in_i; - -- end if; - --end process Toggle_Edge_Detection; - --purpose: Tapped Delay Line 304 (Carry Chain) with wave launcher (21) double transition FC : Adder_304 port map ( @@ -189,46 +109,11 @@ begin RESET => RESET_WR, DataA => data_a_i, DataB => data_b_i, - ClkEn => '1', --ff_array_en_i, + ClkEn => '1', --ff_array_en_i, Result => result_i); - data_a_i <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000FF" & x"7FFFFFF"; + data_a_i <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" & x"7FFFFFF"; data_b_i <= x"000000000000000000000000000000000000000000000000000000000000000000000" & not(hit_buf) & x"000000" & "00" & hit_buf; - --FF_Array_Enable : process (hit_detect_i, release_delay_line_i) - --begin - -- if hit_detect_i = '1' then - -- ff_array_en_i <= '0'; - -- elsif release_delay_line_i = '1' then - -- ff_array_en_i <= '1'; - -- end if; - --end process FF_Array_Enable; - - ----purpose: Enables the signal for delay line releasing - --Release_DL : process (CLK_WR, RESET_WR) - --begin - -- if rising_edge(CLK_WR) then - -- if RESET_WR = '1' then - -- release_delay_line_i <= '0'; - -- elsif hit_detect_2reg = '1' then - -- release_delay_line_i <= '1'; - -- else - -- release_delay_line_i <= '0'; - -- end if; - -- end if; - --end process Release_DL; - - --purpose: Tapped Delay Line 304 (Carry Chain) with wave launcher (21) single transition - --FC : Adder_304 - -- port map ( - -- CLK => CLK_WR, - -- RESET => RESET_WR, - -- DataA => data_a_i, - -- DataB => data_b_i, - -- ClkEn => '1', - -- Result => result_i); - --data_a_i <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"; - --data_b_i <= x"000000000000000000000000000000000000000000000000000000000000000000000000000" & "000" & hit_in_i; - --purpose: Registers the hit detection bit Hit_Detect_Register : process (CLK_WR, RESET_WR) begin @@ -271,19 +156,7 @@ begin if rising_edge(CLK_WR) then if RESET_WR = '1' then encoder_start_i <= '0'; - --hit_time_edge_type_i <= '1'; - --hit_time_rising_i <= (others => '0'); - --hit_time_falling_i <= (others => '0'); hit_time_stamp_i <= (others => '0'); - --elsif hit_detect_i = '1' then - -- encoder_start_i <= '1'; - --hit_time_edge_type_i <= not hit_time_edge_type_i; - --if hit_time_edge_type_i = '1' then - -- hit_time_rising_i <= coarse_cntr_i-1; - --else - -- hit_time_falling_i <= coarse_cntr_i-1; - --end if; - --hit_time_stamp_i <= coarse_cntr_i-1; elsif hit_detect_reg = '1' then encoder_start_i <= '1'; hit_time_stamp_i <= coarse_cntr_i-2; @@ -299,65 +172,45 @@ begin RESET => RESET_WR, CLK => CLK_WR, START_IN => encoder_start_i, - THERMOCODE_IN => result_reg, --result_i, + THERMOCODE_IN => result_reg, --result_i, FINISHED_OUT => fifo_wr_en_i, BINARY_CODE_OUT => fine_counter_i, ENCODER_DEBUG => encoder_debug_i); - FIFO : FIFO_32x512_OutReg + FIFO : FIFO_32x32_OutReg port map ( - Data => fifo_data_in_i, - WrClock => CLK_WR, - RdClock => CLK_RD, - WrEn => fifo_wr_en_i, - RdEn => fifo_rd_en_i, - Reset => RESET_RD, - RPReset => RESET_RD, - Q => fifo_data_out_i, - Empty => fifo_empty_i, - Full => fifo_full_i); + Data => fifo_data_in_i, + WrClock => CLK_WR, + RdClock => CLK_RD, + WrEn => fifo_wr_en_i, + RdEn => fifo_rd_en_i, + Reset => RESET_RD, + RPReset => RESET_RD, + Q => fifo_data_out_i, + Empty => fifo_empty_i, + Full => fifo_full_i, + AlmostFull => fifo_almost_full_i); + fifo_data_in_i(31) <= '1'; -- data marker - fifo_data_in_i(30 downto 28) <= "000"; -- reserved bits - fifo_data_in_i(27 downto 22) <= conv_std_logic_vector(CHANNEL_ID, 6); -- channel number + fifo_data_in_i(30 downto 29) <= "00"; -- reserved bits + fifo_data_in_i(28 downto 22) <= conv_std_logic_vector(CHANNEL_ID, 7); -- channel number fifo_data_in_i(21 downto 12) <= fine_counter_i; -- fine time from the encoder fifo_data_in_i(11) <= '1'; --edge_type_i; -- rising '1' or falling '0' edge fifo_data_in_i(10 downto 0) <= hit_time_stamp_i; -- hit time stamp - --Toggle_Edge_Type : process (CLK_WR, RESET_WR) - --begin - -- if rising_edge(CLK_WR) then - -- if RESET_WR = '1' then - -- edge_type_i <= '1'; - -- elsif fifo_wr_en_i = '1' then - -- edge_type_i <= not edge_type_i; - -- end if; - -- end if; - --end process Toggle_Edge_Type; - - --Toggle_Edge_Hit_Time : process (CLK_WR, RESET_WR) - --begin - -- if rising_edge(CLK_WR) then - -- if RESET_WR = '1' then - -- hit_time_stamp_i <= (others => '0'); - -- elsif edge_type_i = '1' then - -- hit_time_stamp_i <= hit_time_rising_i; - -- else - -- hit_time_stamp_i <= hit_time_falling_i; - -- end if; - -- end if; - --end process Toggle_Edge_Hit_Time; - Register_Outputs : process (CLK_RD, RESET_RD) begin if rising_edge(CLK_RD) then if RESET_RD = '1' then - FIFO_DATA_OUT <= (others => '1'); - FIFO_EMPTY_OUT <= '0'; - FIFO_FULL_OUT <= '0'; + FIFO_DATA_OUT <= (others => '1'); + FIFO_EMPTY_OUT <= '0'; + FIFO_FULL_OUT <= '0'; + FIFO_ALMOST_FULL_OUT <= '0'; else - FIFO_DATA_OUT <= fifo_data_out_i; - FIFO_EMPTY_OUT <= fifo_empty_i; - FIFO_FULL_OUT <= fifo_full_i; + FIFO_DATA_OUT <= fifo_data_out_i; + FIFO_EMPTY_OUT <= fifo_empty_i; + FIFO_FULL_OUT <= fifo_full_i; + FIFO_ALMOST_FULL_OUT <= fifo_almost_full_i; end if; end if; end process Register_Outputs; @@ -420,7 +273,33 @@ begin ------------------------------------------------------------------------------- -- DEBUG ------------------------------------------------------------------------------- - --purpose: Counts the written hits + --purpose: Counts the detected hits + Hit_Detect_Counter : process (CLK_WR) + begin + if rising_edge(CLK_WR) then + if RESET_WR = '1' then + hit_detect_cntr <= (others => '0'); + elsif hit_pulse = '1' then + hit_detect_cntr <= hit_detect_cntr + 1; + end if; + end if; + end process Hit_Detect_Counter; + + --purpose: Synchronises the hit detect counter to the slowcontrol clock + Hit_Detect_Sync : signal_sync + generic map ( + WIDTH => 24, + DEPTH => 3) + port map ( + RESET => RESET_RD, + CLK0 => CLK_WR, + CLK1 => CLK_RD, + D_IN => hit_detect_cntr, + D_OUT => hit_detect_cntr_reg); + + HIT_DETECT_NUMBER <= hit_detect_cntr_reg; + + --purpose: Counts the encoder start times Encoder_Start_Counter : process (CLK_WR) begin if rising_edge(CLK_WR) then @@ -432,7 +311,7 @@ begin end if; end process Encoder_Start_Counter; - --purpose: Synchronises the measurement counter to the slowcontrol clock + --purpose: Synchronises the encoder start counter to the slowcontrol clock Encoder_Start_Sync : signal_sync generic map ( WIDTH => 24, @@ -447,19 +326,19 @@ begin ENCODER_START_NUMBER <= encoder_start_cntr_reg; --purpose: Counts the written hits - Measurement_Counter : process (CLK_WR) + FIFO_WR_Counter : process (CLK_WR) begin if rising_edge(CLK_WR) then if RESET_WR = '1' then - measurement_cntr <= (others => '0'); + fifo_wr_cntr <= (others => '0'); elsif fifo_wr_en_i = '1' then - measurement_cntr <= measurement_cntr + 1; + fifo_wr_cntr <= fifo_wr_cntr + 1; end if; end if; - end process Measurement_Counter; + end process FIFO_WR_Counter; - --purpose: Synchronises the measurement counter to the slowcontrol clock - Measurement_Sync : signal_sync + --purpose: Synchronises the fifo wr counter to the slowcontrol clock + FIFO_WR_Sync : signal_sync generic map ( WIDTH => 24, DEPTH => 3) @@ -467,15 +346,15 @@ begin RESET => RESET_RD, CLK0 => CLK_WR, CLK1 => CLK_RD, - D_IN => measurement_cntr, - D_OUT => measurement_reg); + D_IN => fifo_wr_cntr, + D_OUT => fifo_wr_cntr_reg); - MEASUREMENT_NUMBER <= measurement_reg; + FIFO_WR_NUMBER <= fifo_wr_cntr_reg; - Channel_DEBUG_01(0) <= hit_pulse; - Channel_DEBUG_01(1) <= encoder_start_i; - Channel_DEBUG_01(2) <= fifo_wr_en_i; - Channel_DEBUG_01(11 downto 3) <= encoder_debug_i(8 downto 0); + --Channel_DEBUG(0) <= hit_pulse; + --Channel_DEBUG(1) <= encoder_start_i; + --Channel_DEBUG(2) <= fifo_wr_en_i; + --Channel_DEBUG(11 downto 3) <= encoder_debug_i(8 downto 0); ------------------------------------------------------------------------------- end Channel; diff --git a/tdc_releases/tdc_v0.2/source/FIFO_32x512_OutReg.vhd b/tdc_releases/tdc_v0.2/source/FIFO_32x32_OutReg.vhd similarity index 63% rename from tdc_releases/tdc_v0.2/source/FIFO_32x512_OutReg.vhd rename to tdc_releases/tdc_v0.2/source/FIFO_32x32_OutReg.vhd index 8f46c78..5e50539 100644 --- a/tdc_releases/tdc_v0.2/source/FIFO_32x512_OutReg.vhd +++ b/tdc_releases/tdc_v0.2/source/FIFO_32x32_OutReg.vhd @@ -1,8 +1,8 @@ --- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) +-- VHDL netlist generated by SCUBA Diamond_1.4_Production (87) -- Module Version: 5.4 ---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 512 -width 32 -depth 512 -rdata_width 32 -regout -no_enable -pe -1 -pf -1 -e +--/opt/lattice/diamond/1.4/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 32 -width 32 -depth 32 -rdata_width 32 -regout -no_enable -pe -1 -pf 28 -e --- Fri Nov 11 11:15:59 2011 +-- Tue Jun 26 11:56:52 2012 library IEEE; use IEEE.std_logic_1164.all; @@ -11,7 +11,7 @@ library ecp3; use ecp3.components.all; -- synopsys translate_on -entity FIFO_32x512_OutReg is +entity FIFO_32x32_OutReg is port ( Data: in std_logic_vector(31 downto 0); WrClock: in std_logic; @@ -22,74 +22,49 @@ entity FIFO_32x512_OutReg is RPReset: in std_logic; Q: out std_logic_vector(31 downto 0); Empty: out std_logic; - Full: out std_logic); -end FIFO_32x512_OutReg; + Full: out std_logic; + AlmostFull: out std_logic); +end FIFO_32x32_OutReg; -architecture Structure of FIFO_32x512_OutReg is +architecture Structure of FIFO_32x32_OutReg is -- internal signal declarations signal invout_1: std_logic; signal invout_0: std_logic; - signal w_g2b_xor_cluster_1: std_logic; - signal r_g2b_xor_cluster_1: std_logic; signal w_gdata_0: std_logic; signal w_gdata_1: std_logic; signal w_gdata_2: std_logic; signal w_gdata_3: std_logic; signal w_gdata_4: std_logic; - signal w_gdata_5: std_logic; - signal w_gdata_6: std_logic; - signal w_gdata_7: std_logic; - signal w_gdata_8: std_logic; signal wptr_0: std_logic; signal wptr_1: std_logic; signal wptr_2: std_logic; signal wptr_3: std_logic; signal wptr_4: std_logic; signal wptr_5: std_logic; - signal wptr_6: std_logic; - signal wptr_7: std_logic; - signal wptr_8: std_logic; - signal wptr_9: std_logic; signal r_gdata_0: std_logic; signal r_gdata_1: std_logic; signal r_gdata_2: std_logic; signal r_gdata_3: std_logic; signal r_gdata_4: std_logic; - signal r_gdata_5: std_logic; - signal r_gdata_6: std_logic; - signal r_gdata_7: std_logic; - signal r_gdata_8: std_logic; signal rptr_0: std_logic; signal rptr_1: std_logic; signal rptr_2: std_logic; signal rptr_3: std_logic; signal rptr_4: std_logic; signal rptr_5: std_logic; - signal rptr_6: std_logic; - signal rptr_7: std_logic; - signal rptr_8: std_logic; - signal rptr_9: std_logic; signal w_gcount_0: std_logic; signal w_gcount_1: std_logic; signal w_gcount_2: std_logic; signal w_gcount_3: std_logic; signal w_gcount_4: std_logic; signal w_gcount_5: std_logic; - signal w_gcount_6: std_logic; - signal w_gcount_7: std_logic; - signal w_gcount_8: std_logic; - signal w_gcount_9: std_logic; signal r_gcount_0: std_logic; signal r_gcount_1: std_logic; signal r_gcount_2: std_logic; signal r_gcount_3: std_logic; signal r_gcount_4: std_logic; signal r_gcount_5: std_logic; - signal r_gcount_6: std_logic; - signal r_gcount_7: std_logic; - signal r_gcount_8: std_logic; - signal r_gcount_9: std_logic; signal w_gcount_r20: std_logic; signal w_gcount_r0: std_logic; signal w_gcount_r21: std_logic; @@ -102,14 +77,6 @@ architecture Structure of FIFO_32x512_OutReg is signal w_gcount_r4: std_logic; signal w_gcount_r25: std_logic; signal w_gcount_r5: std_logic; - signal w_gcount_r26: std_logic; - signal w_gcount_r6: std_logic; - signal w_gcount_r27: std_logic; - signal w_gcount_r7: std_logic; - signal w_gcount_r28: std_logic; - signal w_gcount_r8: std_logic; - signal w_gcount_r29: std_logic; - signal w_gcount_r9: std_logic; signal r_gcount_w20: std_logic; signal r_gcount_w0: std_logic; signal r_gcount_w21: std_logic; @@ -122,14 +89,6 @@ architecture Structure of FIFO_32x512_OutReg is signal r_gcount_w4: std_logic; signal r_gcount_w25: std_logic; signal r_gcount_w5: std_logic; - signal r_gcount_w26: std_logic; - signal r_gcount_w6: std_logic; - signal r_gcount_w27: std_logic; - signal r_gcount_w7: std_logic; - signal r_gcount_w28: std_logic; - signal r_gcount_w8: std_logic; - signal r_gcount_w29: std_logic; - signal r_gcount_w9: std_logic; signal empty_i: std_logic; signal rRst: std_logic; signal full_i: std_logic; @@ -141,16 +100,9 @@ architecture Structure of FIFO_32x512_OutReg is signal co0: std_logic; signal iwcount_4: std_logic; signal iwcount_5: std_logic; - signal co1: std_logic; - signal iwcount_6: std_logic; - signal iwcount_7: std_logic; signal co2: std_logic; - signal iwcount_8: std_logic; - signal iwcount_9: std_logic; - signal co4: std_logic; - signal wcount_9: std_logic; - signal co3: std_logic; - signal scuba_vhi: std_logic; + signal wcount_5: std_logic; + signal co1: std_logic; signal ircount_0: std_logic; signal ircount_1: std_logic; signal r_gctr_ci: std_logic; @@ -159,15 +111,9 @@ architecture Structure of FIFO_32x512_OutReg is signal co0_1: std_logic; signal ircount_4: std_logic; signal ircount_5: std_logic; - signal co1_1: std_logic; - signal ircount_6: std_logic; - signal ircount_7: std_logic; signal co2_1: std_logic; - signal ircount_8: std_logic; - signal ircount_9: std_logic; - signal co4_1: std_logic; - signal rcount_9: std_logic; - signal co3_1: std_logic; + signal rcount_5: std_logic; + signal co1_1: std_logic; signal rden_i: std_logic; signal cmp_ci: std_logic; signal wcount_r0: std_logic; @@ -175,55 +121,59 @@ architecture Structure of FIFO_32x512_OutReg is signal rcount_0: std_logic; signal rcount_1: std_logic; signal co0_2: std_logic; - signal wcount_r2: std_logic; + signal w_g2b_xor_cluster_0: std_logic; signal wcount_r3: std_logic; signal rcount_2: std_logic; signal rcount_3: std_logic; signal co1_2: std_logic; signal wcount_r4: std_logic; - signal wcount_r5: std_logic; - signal rcount_4: std_logic; - signal rcount_5: std_logic; - signal co2_2: std_logic; - signal w_g2b_xor_cluster_0: std_logic; - signal wcount_r7: std_logic; - signal rcount_6: std_logic; - signal rcount_7: std_logic; - signal co3_2: std_logic; - signal wcount_r8: std_logic; signal empty_cmp_clr: std_logic; - signal rcount_8: std_logic; + signal rcount_4: std_logic; signal empty_cmp_set: std_logic; signal empty_d: std_logic; signal empty_d_c: std_logic; - signal wren_i: std_logic; signal cmp_ci_1: std_logic; - signal rcount_w0: std_logic; - signal rcount_w1: std_logic; signal wcount_0: std_logic; signal wcount_1: std_logic; signal co0_3: std_logic; - signal rcount_w2: std_logic; - signal rcount_w3: std_logic; signal wcount_2: std_logic; signal wcount_3: std_logic; signal co1_3: std_logic; - signal rcount_w4: std_logic; - signal rcount_w5: std_logic; - signal wcount_4: std_logic; - signal wcount_5: std_logic; - signal co2_3: std_logic; - signal r_g2b_xor_cluster_0: std_logic; - signal rcount_w7: std_logic; - signal wcount_6: std_logic; - signal wcount_7: std_logic; - signal co3_3: std_logic; - signal rcount_w8: std_logic; signal full_cmp_clr: std_logic; - signal wcount_8: std_logic; + signal wcount_4: std_logic; signal full_cmp_set: std_logic; signal full_d: std_logic; signal full_d_c: std_logic; + signal scuba_vhi: std_logic; + signal iaf_setcount_0: std_logic; + signal iaf_setcount_1: std_logic; + signal af_set_ctr_ci: std_logic; + signal iaf_setcount_2: std_logic; + signal iaf_setcount_3: std_logic; + signal co0_4: std_logic; + signal iaf_setcount_4: std_logic; + signal iaf_setcount_5: std_logic; + signal co2_2: std_logic; + signal af_setcount_5: std_logic; + signal co1_4: std_logic; + signal wren_i: std_logic; + signal cmp_ci_2: std_logic; + signal rcount_w0: std_logic; + signal rcount_w1: std_logic; + signal af_setcount_0: std_logic; + signal af_setcount_1: std_logic; + signal co0_5: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal rcount_w3: std_logic; + signal af_setcount_2: std_logic; + signal af_setcount_3: std_logic; + signal co1_5: std_logic; + signal rcount_w4: std_logic; + signal af_set_cmp_clr: std_logic; + signal af_setcount_4: std_logic; + signal af_set_cmp_set: std_logic; + signal af_set: std_logic; + signal af_set_c: std_logic; signal scuba_vlo: std_logic; -- local component declarations @@ -339,42 +289,9 @@ architecture Structure of FIFO_32x512_OutReg is attribute MEM_INIT_FILE : string; attribute RESETMODE : string; attribute GSR : string; - attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "FIFO_32x512_OutReg.lpc"; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "FIFO_32x32_OutReg.lpc"; attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC"; - attribute GSR of FF_101 : label is "ENABLED"; - attribute GSR of FF_100 : label is "ENABLED"; - attribute GSR of FF_99 : label is "ENABLED"; - attribute GSR of FF_98 : label is "ENABLED"; - attribute GSR of FF_97 : label is "ENABLED"; - attribute GSR of FF_96 : label is "ENABLED"; - attribute GSR of FF_95 : label is "ENABLED"; - attribute GSR of FF_94 : label is "ENABLED"; - attribute GSR of FF_93 : label is "ENABLED"; - attribute GSR of FF_92 : label is "ENABLED"; - attribute GSR of FF_91 : label is "ENABLED"; - attribute GSR of FF_90 : label is "ENABLED"; - attribute GSR of FF_89 : label is "ENABLED"; - attribute GSR of FF_88 : label is "ENABLED"; - attribute GSR of FF_87 : label is "ENABLED"; - attribute GSR of FF_86 : label is "ENABLED"; - attribute GSR of FF_85 : label is "ENABLED"; - attribute GSR of FF_84 : label is "ENABLED"; - attribute GSR of FF_83 : label is "ENABLED"; - attribute GSR of FF_82 : label is "ENABLED"; - attribute GSR of FF_81 : label is "ENABLED"; - attribute GSR of FF_80 : label is "ENABLED"; - attribute GSR of FF_79 : label is "ENABLED"; - attribute GSR of FF_78 : label is "ENABLED"; - attribute GSR of FF_77 : label is "ENABLED"; - attribute GSR of FF_76 : label is "ENABLED"; - attribute GSR of FF_75 : label is "ENABLED"; - attribute GSR of FF_74 : label is "ENABLED"; - attribute GSR of FF_73 : label is "ENABLED"; - attribute GSR of FF_72 : label is "ENABLED"; - attribute GSR of FF_71 : label is "ENABLED"; - attribute GSR of FF_70 : label is "ENABLED"; - attribute GSR of FF_69 : label is "ENABLED"; attribute GSR of FF_68 : label is "ENABLED"; attribute GSR of FF_67 : label is "ENABLED"; attribute GSR of FF_66 : label is "ENABLED"; @@ -448,199 +365,133 @@ architecture Structure of FIFO_32x512_OutReg is begin -- component instantiation statements - AND2_t20: AND2 + AND2_t12: AND2 port map (A=>WrEn, B=>invout_1, Z=>wren_i); INV_1: INV port map (A=>full_i, Z=>invout_1); - AND2_t19: AND2 + AND2_t11: AND2 port map (A=>RdEn, B=>invout_0, Z=>rden_i); INV_0: INV port map (A=>empty_i, Z=>invout_0); - OR2_t18: OR2 + OR2_t10: OR2 port map (A=>Reset, B=>RPReset, Z=>rRst); - XOR2_t17: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t16: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t15: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t14: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t13: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t12: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t11: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t10: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - XOR2_t9: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); XOR2_t8: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); XOR2_t7: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); XOR2_t6: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); XOR2_t5: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); XOR2_t4: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); XOR2_t3: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); XOR2_t2: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); XOR2_t1: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); XOR2_t0: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - LUT4_23: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, - AD1=>w_gcount_r28, AD0=>w_gcount_r29, - DO0=>w_g2b_xor_cluster_0); + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - LUT4_22: ROM16X1A + LUT4_15: ROM16X1A generic map (initval=> X"6996") port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, AD1=>w_gcount_r24, AD0=>w_gcount_r25, - DO0=>w_g2b_xor_cluster_1); - - LUT4_21: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r8); - - LUT4_20: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, - AD1=>w_gcount_r29, AD0=>scuba_vlo, DO0=>wcount_r7); - - LUT4_19: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>wcount_r8, DO0=>wcount_r5); - - LUT4_18: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, - AD1=>w_gcount_r26, AD0=>wcount_r7, DO0=>wcount_r4); - - LUT4_17: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, - AD1=>w_gcount_r25, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r3); - - LUT4_16: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r2); - - LUT4_15: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r21, AD0=>scuba_vlo, DO0=>wcount_r1); + DO0=>w_g2b_xor_cluster_0); LUT4_14: ROM16X1A generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r20, AD0=>w_gcount_r21, DO0=>wcount_r0); + port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r4); LUT4_13: ROM16X1A generic map (initval=> X"6996") - port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, - AD1=>r_gcount_w28, AD0=>r_gcount_w29, - DO0=>r_g2b_xor_cluster_0); + port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, + AD1=>w_gcount_r25, AD0=>scuba_vlo, DO0=>wcount_r3); LUT4_12: ROM16X1A generic map (initval=> X"6996") - port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, - AD1=>r_gcount_w24, AD0=>r_gcount_w25, - DO0=>r_g2b_xor_cluster_1); + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, + AD1=>w_gcount_r23, AD0=>wcount_r4, DO0=>wcount_r1); LUT4_11: ROM16X1A generic map (initval=> X"6996") - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w8); + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>wcount_r3, DO0=>wcount_r0); LUT4_10: ROM16X1A generic map (initval=> X"6996") - port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, - AD1=>r_gcount_w29, AD0=>scuba_vlo, DO0=>rcount_w7); + port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, + AD1=>r_gcount_w24, AD0=>r_gcount_w25, + DO0=>r_g2b_xor_cluster_0); LUT4_9: ROM16X1A generic map (initval=> X"6996") - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, - AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5); + port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w4); LUT4_8: ROM16X1A generic map (initval=> X"6996") - port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, - AD1=>r_gcount_w26, AD0=>rcount_w7, DO0=>rcount_w4); + port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, + AD1=>r_gcount_w25, AD0=>scuba_vlo, DO0=>rcount_w3); LUT4_7: ROM16X1A generic map (initval=> X"6996") - port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, - AD1=>r_gcount_w25, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w3); + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, + AD1=>r_gcount_w23, AD0=>rcount_w4, DO0=>rcount_w1); LUT4_6: ROM16X1A generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w2); + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, + AD1=>r_gcount_w22, AD0=>rcount_w3, DO0=>rcount_w0); LUT4_5: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w21, AD0=>scuba_vlo, DO0=>rcount_w1); - - LUT4_4: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w20, AD0=>r_gcount_w21, DO0=>rcount_w0); - - LUT4_3: ROM16X1A generic map (initval=> X"0410") - port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29, + port map (AD3=>rptr_5, AD2=>rcount_5, AD1=>w_gcount_r25, AD0=>scuba_vlo, DO0=>empty_cmp_set); - LUT4_2: ROM16X1A + LUT4_4: ROM16X1A generic map (initval=> X"1004") - port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29, + port map (AD3=>rptr_5, AD2=>rcount_5, AD1=>w_gcount_r25, AD0=>scuba_vlo, DO0=>empty_cmp_clr); - LUT4_1: ROM16X1A + LUT4_3: ROM16X1A generic map (initval=> X"0140") - port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29, + port map (AD3=>wptr_5, AD2=>wcount_5, AD1=>r_gcount_w25, AD0=>scuba_vlo, DO0=>full_cmp_set); - LUT4_0: ROM16X1A + LUT4_2: ROM16X1A generic map (initval=> X"4001") - port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29, + port map (AD3=>wptr_5, AD2=>wcount_5, AD1=>r_gcount_w25, AD0=>scuba_vlo, DO0=>full_cmp_clr); + LUT4_1: ROM16X1A + generic map (initval=> X"4c32") + port map (AD3=>af_setcount_5, AD2=>wcount_5, AD1=>r_gcount_w25, + AD0=>wptr_5, DO0=>af_set_cmp_set); + + LUT4_0: ROM16X1A + generic map (initval=> X"8001") + port map (AD3=>af_setcount_5, AD2=>wcount_5, AD1=>r_gcount_w25, + AD0=>wptr_5, DO0=>af_set_cmp_clr); + pdp_ram_0_0_0: PDPW16KC generic map (CSDECODE_R=> "0b001", CSDECODE_W=> "0b001", GSR=> "DISABLED", REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) @@ -656,399 +507,280 @@ begin DI30=>Data(30), DI31=>Data(31), DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3, - ADW4=>wptr_4, ADW5=>wptr_5, ADW6=>wptr_6, ADW7=>wptr_7, - ADW8=>wptr_8, BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi, - BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, CSW0=>scuba_vhi, - CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo, - ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo, - ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2, - ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6, - ADR12=>rptr_7, ADR13=>rptr_8, CER=>scuba_vhi, CLKR=>RdClock, - CSR0=>rden_i, CSR1=>scuba_vlo, CSR2=>scuba_vlo, RST=>Reset, - DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), DO3=>Q(21), DO4=>Q(22), - DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), DO8=>Q(26), DO9=>Q(27), - DO10=>Q(28), DO11=>Q(29), DO12=>Q(30), DO13=>Q(31), - DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>Q(0), - DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), - DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), DO27=>Q(9), DO28=>Q(10), - DO29=>Q(11), DO30=>Q(12), DO31=>Q(13), DO32=>Q(14), - DO33=>Q(15), DO34=>Q(16), DO35=>Q(17)); - - FF_101: FD1P3BX + ADW4=>wptr_4, ADW5=>scuba_vlo, ADW6=>scuba_vlo, + ADW7=>scuba_vlo, ADW8=>scuba_vlo, BE0=>scuba_vhi, + BE1=>scuba_vhi, BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i, + CLKW=>WrClock, CSW0=>scuba_vhi, CSW1=>scuba_vlo, + CSW2=>scuba_vlo, ADR0=>scuba_vlo, ADR1=>scuba_vlo, + ADR2=>scuba_vlo, ADR3=>scuba_vlo, ADR4=>scuba_vlo, + ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2, ADR8=>rptr_3, + ADR9=>rptr_4, ADR10=>scuba_vlo, ADR11=>scuba_vlo, + ADR12=>scuba_vlo, ADR13=>scuba_vlo, CER=>scuba_vhi, + CLKR=>RdClock, CSR0=>rden_i, CSR1=>scuba_vlo, + CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(18), DO1=>Q(19), + DO2=>Q(20), DO3=>Q(21), DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), + DO7=>Q(25), DO8=>Q(26), DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), + DO12=>Q(30), DO13=>Q(31), DO14=>open, DO15=>open, DO16=>open, + DO17=>open, DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), + DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), + DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), DO30=>Q(12), + DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), DO34=>Q(16), + DO35=>Q(17)); + + FF_68: FD1P3BX port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, Q=>wcount_0); - FF_100: FD1P3DX + FF_67: FD1P3DX port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_1); - FF_99: FD1P3DX + FF_66: FD1P3DX port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_2); - FF_98: FD1P3DX + FF_65: FD1P3DX port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_3); - FF_97: FD1P3DX + FF_64: FD1P3DX port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_4); - FF_96: FD1P3DX + FF_63: FD1P3DX port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_5); - FF_95: FD1P3DX - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_94: FD1P3DX - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_93: FD1P3DX - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_92: FD1P3DX - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_91: FD1P3DX + FF_62: FD1P3DX port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_0); - FF_90: FD1P3DX + FF_61: FD1P3DX port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_1); - FF_89: FD1P3DX + FF_60: FD1P3DX port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_2); - FF_88: FD1P3DX + FF_59: FD1P3DX port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_3); - FF_87: FD1P3DX + FF_58: FD1P3DX port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_4); - FF_86: FD1P3DX - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + FF_57: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_5); - FF_85: FD1P3DX - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_84: FD1P3DX - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_83: FD1P3DX - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_82: FD1P3DX - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_81: FD1P3DX + FF_56: FD1P3DX port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_0); - FF_80: FD1P3DX + FF_55: FD1P3DX port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_1); - FF_79: FD1P3DX + FF_54: FD1P3DX port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_2); - FF_78: FD1P3DX + FF_53: FD1P3DX port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_3); - FF_77: FD1P3DX + FF_52: FD1P3DX port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_4); - FF_76: FD1P3DX + FF_51: FD1P3DX port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_5); - FF_75: FD1P3DX - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_74: FD1P3DX - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_73: FD1P3DX - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_72: FD1P3DX - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_71: FD1P3BX + FF_50: FD1P3BX port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, Q=>rcount_0); - FF_70: FD1P3DX + FF_49: FD1P3DX port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_1); - FF_69: FD1P3DX + FF_48: FD1P3DX port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_2); - FF_68: FD1P3DX + FF_47: FD1P3DX port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_3); - FF_67: FD1P3DX + FF_46: FD1P3DX port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_4); - FF_66: FD1P3DX + FF_45: FD1P3DX port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_5); - FF_65: FD1P3DX - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_64: FD1P3DX - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_63: FD1P3DX - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_62: FD1P3DX - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_61: FD1P3DX + FF_44: FD1P3DX port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_0); - FF_60: FD1P3DX + FF_43: FD1P3DX port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_1); - FF_59: FD1P3DX + FF_42: FD1P3DX port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_2); - FF_58: FD1P3DX + FF_41: FD1P3DX port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_3); - FF_57: FD1P3DX + FF_40: FD1P3DX port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_4); - FF_56: FD1P3DX - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + FF_39: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_5); - FF_55: FD1P3DX - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_54: FD1P3DX - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_53: FD1P3DX - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_52: FD1P3DX - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_51: FD1P3DX + FF_38: FD1P3DX port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_0); - FF_50: FD1P3DX + FF_37: FD1P3DX port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_1); - FF_49: FD1P3DX + FF_36: FD1P3DX port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_2); - FF_48: FD1P3DX + FF_35: FD1P3DX port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_3); - FF_47: FD1P3DX + FF_34: FD1P3DX port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_4); - FF_46: FD1P3DX + FF_33: FD1P3DX port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_5); - FF_45: FD1P3DX - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_44: FD1P3DX - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_43: FD1P3DX - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_42: FD1P3DX - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_41: FD1S3DX + FF_32: FD1S3DX port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - FF_40: FD1S3DX + FF_31: FD1S3DX port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - FF_39: FD1S3DX + FF_30: FD1S3DX port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - FF_38: FD1S3DX + FF_29: FD1S3DX port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - FF_37: FD1S3DX + FF_28: FD1S3DX port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - FF_36: FD1S3DX + FF_27: FD1S3DX port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - FF_35: FD1S3DX - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_34: FD1S3DX - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_33: FD1S3DX - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_32: FD1S3DX - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_31: FD1S3DX + FF_26: FD1S3DX port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - FF_30: FD1S3DX + FF_25: FD1S3DX port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - FF_29: FD1S3DX + FF_24: FD1S3DX port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - FF_28: FD1S3DX + FF_23: FD1S3DX port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - FF_27: FD1S3DX + FF_22: FD1S3DX port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - FF_26: FD1S3DX + FF_21: FD1S3DX port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - FF_25: FD1S3DX - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_24: FD1S3DX - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_23: FD1S3DX - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_22: FD1S3DX - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_21: FD1S3DX + FF_20: FD1S3DX port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r20); - FF_20: FD1S3DX + FF_19: FD1S3DX port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r21); - FF_19: FD1S3DX + FF_18: FD1S3DX port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r22); - FF_18: FD1S3DX + FF_17: FD1S3DX port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r23); - FF_17: FD1S3DX + FF_16: FD1S3DX port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r24); - FF_16: FD1S3DX + FF_15: FD1S3DX port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r25); - FF_15: FD1S3DX - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - FF_14: FD1S3DX - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); FF_13: FD1S3DX - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); FF_12: FD1S3DX - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); FF_11: FD1S3DX - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); FF_10: FD1S3DX - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); FF_9: FD1S3DX - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - FF_8: FD1S3DX - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + FF_8: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); FF_7: FD1S3DX - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - FF_6: FD1S3DX - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + FF_6: FD1P3BX + port map (D=>iaf_setcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_setcount_0); - FF_5: FD1S3DX - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); + FF_5: FD1P3DX + port map (D=>iaf_setcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_1); - FF_4: FD1S3DX - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); + FF_4: FD1P3BX + port map (D=>iaf_setcount_2, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_setcount_2); - FF_3: FD1S3DX - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); + FF_3: FD1P3DX + port map (D=>iaf_setcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_3); - FF_2: FD1S3DX - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); + FF_2: FD1P3DX + port map (D=>iaf_setcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_4); - FF_1: FD1S3BX - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + FF_1: FD1P3DX + port map (D=>iaf_setcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_5); FF_0: FD1S3DX - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + port map (D=>af_set, CK=>WrClock, CD=>Reset, Q=>AlmostFull); w_gctr_cia: FADD2B port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, @@ -1067,17 +799,6 @@ begin port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, NC0=>iwcount_4, NC1=>iwcount_5); - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - r_gctr_cia: FADD2B port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, @@ -1095,14 +816,6 @@ begin port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, NC0=>ircount_4, NC1=>ircount_5); - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - empty_cmp_ci_a: FADD2B port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); @@ -1112,20 +825,12 @@ begin B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, + port map (A0=>rcount_2, A1=>rcount_3, B0=>w_g2b_xor_cluster_0, B1=>wcount_r3, CI=>co0_2, GE=>co1_2); empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, - B1=>wcount_r5, CI=>co1_2, GE=>co2_2); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>w_g2b_xor_cluster_0, - B1=>wcount_r7, CI=>co2_2, GE=>co3_2); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>empty_cmp_set, B0=>wcount_r8, - B1=>empty_cmp_clr, CI=>co3_2, GE=>empty_d_c); + port map (A0=>rcount_4, A1=>empty_cmp_set, B0=>wcount_r4, + B1=>empty_cmp_clr, CI=>co1_2, GE=>empty_d_c); a0: FADD2B port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, @@ -1141,27 +846,61 @@ begin B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, + port map (A0=>wcount_2, A1=>wcount_3, B0=>r_g2b_xor_cluster_0, B1=>rcount_w3, CI=>co0_3, GE=>co1_3); full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, - B1=>rcount_w5, CI=>co1_3, GE=>co2_3); + port map (A0=>wcount_4, A1=>full_cmp_set, B0=>rcount_w4, + B1=>full_cmp_clr, CI=>co1_3, GE=>full_d_c); - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>r_g2b_xor_cluster_0, - B1=>rcount_w7, CI=>co2_3, GE=>co3_3); + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + af_set_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>af_set_ctr_ci, S0=>open, + S1=>open); + + af_set_ctr_0: CU2 + port map (CI=>af_set_ctr_ci, PC0=>af_setcount_0, + PC1=>af_setcount_1, CO=>co0_4, NC0=>iaf_setcount_0, + NC1=>iaf_setcount_1); - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>full_cmp_set, B0=>rcount_w8, - B1=>full_cmp_clr, CI=>co3_3, GE=>full_d_c); + af_set_ctr_1: CU2 + port map (CI=>co0_4, PC0=>af_setcount_2, PC1=>af_setcount_3, + CO=>co1_4, NC0=>iaf_setcount_2, NC1=>iaf_setcount_3); + + af_set_ctr_2: CU2 + port map (CI=>co1_4, PC0=>af_setcount_4, PC1=>af_setcount_5, + CO=>co2_2, NC0=>iaf_setcount_4, NC1=>iaf_setcount_5); + + af_set_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open); + + af_set_cmp_0: AGEB2 + port map (A0=>af_setcount_0, A1=>af_setcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_2, GE=>co0_5); + + af_set_cmp_1: AGEB2 + port map (A0=>af_setcount_2, A1=>af_setcount_3, + B0=>r_g2b_xor_cluster_0, B1=>rcount_w3, CI=>co0_5, GE=>co1_5); + + af_set_cmp_2: AGEB2 + port map (A0=>af_setcount_4, A1=>af_set_cmp_set, B0=>rcount_w4, + B1=>af_set_cmp_clr, CI=>co1_5, GE=>af_set_c); scuba_vlo_inst: VLO port map (Z=>scuba_vlo); - a1: FADD2B + a2: FADD2B port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + B1=>scuba_vlo, CI=>af_set_c, COUT=>open, S0=>af_set, S1=>open); Empty <= empty_i; @@ -1170,7 +909,7 @@ end Structure; -- synopsys translate_off library ecp3; -configuration Structure_CON of FIFO_32x512_OutReg is +configuration Structure_CON of FIFO_32x32_OutReg is for Structure for all:AGEB2 use entity ecp3.AGEB2(V); end for; for all:AND2 use entity ecp3.AND2(V); end for; diff --git a/tdc_releases/tdc_v0.2/source/Reference_channel.vhd b/tdc_releases/tdc_v0.2/source/Reference_channel.vhd index d98c9a9..f954058 100644 --- a/tdc_releases/tdc_v0.2/source/Reference_channel.vhd +++ b/tdc_releases/tdc_v0.2/source/Reference_channel.vhd @@ -4,152 +4,72 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_arith.all; +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.version.all; + entity Reference_Channel is generic ( - CHANNEL_ID : integer range 0 to 15); + CHANNEL_ID : integer range 0 to 0); port ( - RESET_WR : in std_logic; - RESET_RD : in std_logic; - CLK_WR : in std_logic; - CLK_RD : in std_logic; --- - HIT_IN : in std_logic; - READ_EN_IN : in std_logic; - VALID_TMG_TRG_IN : in std_logic; - SPIKE_DETECTED_IN : in std_logic; - MULTI_TMG_TRG_IN : in std_logic; - FIFO_DATA_OUT : out std_logic_vector(31 downto 0); - FIFO_EMPTY_OUT : out std_logic; - FIFO_FULL_OUT : out std_logic; - COARSE_COUNTER_IN : in std_logic_vector(10 downto 0); - TRIGGER_TIME_OUT : out std_logic_vector(10 downto 0); -- coarse time of the timing trigger - REF_DEBUG_OUT : out std_logic_vector(31 downto 0) + RESET_WR : in std_logic; + RESET_RD : in std_logic; + CLK_WR : in std_logic; + CLK_RD : in std_logic; -- --- Channel_DEBUG_01 : out std_logic_vector(31 downto 0); --- Channel_DEBUG_02 : out std_logic_vector(31 downto 0); --- Channel_DEBUG_03 : out std_logic_vector(31 downto 0); --- Channel_DEBUG_04 : out std_logic_vector(31 downto 0); --- Channel_DEBUG_05 : out std_logic_vector(31 downto 0); --- Channel_DEBUG_06 : out std_logic_vector(31 downto 0); --- Channel_DEBUG_07 : out std_logic_vector(31 downto 0); --- Channel_DEBUG_08 : out std_logic_vector(31 downto 0); --- Channel_DEBUG_09 : out std_logic_vector(31 downto 0); --- Channel_DEBUG_10 : out std_logic_vector(31 downto 0); --- Channel_DEBUG_11 : out std_logic_vector(31 downto 0); --- Channel_DEBUG_12 : out std_logic_vector(31 downto 0) + HIT_IN : in std_logic; + READ_EN_IN : in std_logic; + VALID_TMG_TRG_IN : in std_logic; + SPIKE_DETECTED_IN : in std_logic; + MULTI_TMG_TRG_IN : in std_logic; + FIFO_DATA_OUT : out std_logic_vector(31 downto 0); + FIFO_EMPTY_OUT : out std_logic; + FIFO_FULL_OUT : out std_logic; + FIFO_ALMOST_FULL_OUT : out std_logic; + COARSE_COUNTER_IN : in std_logic_vector(10 downto 0); + TRIGGER_TIME_OUT : out std_logic_vector(10 downto 0); -- coarse time of the timing trigger + REF_DEBUG_OUT : out std_logic_vector(31 downto 0) ); end Reference_Channel; architecture Reference_Channel of Reference_Channel is - -------------------------------------------------------------------------------- --- Component Declarations -------------------------------------------------------------------------------- - - component Adder_304 - port ( - CLK : in std_logic; - RESET : in std_logic; - DataA : in std_logic_vector(303 downto 0); - DataB : in std_logic_vector(303 downto 0); - ClkEn : in std_logic; - Result : out std_logic_vector(303 downto 0)); - end component; --- - component Encoder_304_Bit - port ( - RESET : in std_logic; - CLK : in std_logic; - START_IN : in std_logic; - THERMOCODE_IN : in std_logic_vector(303 downto 0); - FINISHED_OUT : out std_logic; - BINARY_CODE_OUT : out std_logic_vector(9 downto 0); - ENCODER_DEBUG : out std_logic_vector(31 downto 0)); - end component; --- - --component Encoder_304_ROMsuz - -- port ( - -- RESET : in std_logic; - -- CLK : in std_logic; - -- START_IN : in std_logic; - -- THERMOCODE_IN : in std_logic_vector(303 downto 0); - -- FINISHED_OUT : out std_logic; - -- BINARY_CODE_OUT : out std_logic_vector(9 downto 0); - -- ENCODER_DEBUG : out std_logic_vector(31 downto 0)); - --end component; --- - --component Encoder_304_Sngl_ROMsuz - -- port ( - -- RESET : in std_logic; - -- CLK : in std_logic; - -- START_IN : in std_logic; - -- THERMOCODE_IN : in std_logic_vector(303 downto 0); - -- FINISHED_OUT : out std_logic; - -- BINARY_CODE_OUT : out std_logic_vector(9 downto 0); - -- ENCODER_DEBUG : out std_logic_vector(31 downto 0)); - --end component; --- - component FIFO_32x512_OutReg - port ( - Data : in std_logic_vector(31 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(31 downto 0); - Empty : out std_logic; - Full : out std_logic); - end component; --- - component bit_sync - generic ( - DEPTH : integer); - port ( - RESET : in std_logic; - CLK0 : in std_logic; - CLK1 : in std_logic; - D_IN : in std_logic; - D_OUT : out std_logic); - end component; - -------------------------------------------------------------------------------- - ------------------------------------------------------------------------------- -- Signal Declarations ------------------------------------------------------------------------------- - signal data_a_i : std_logic_vector(303 downto 0); - signal data_b_i : std_logic_vector(303 downto 0); - signal result_i : std_logic_vector(303 downto 0); - signal result_reg : std_logic_vector(303 downto 0); - signal hit_in_i : std_logic; - signal hit_buf : std_logic; - signal hit_detect_i : std_logic; - signal hit_detect_reg : std_logic; - signal hit_detect_2reg : std_logic; - signal release_delay_line_i : std_logic; - signal result_2_reg : std_logic; - signal coarse_cntr_i : std_logic_vector(10 downto 0); - signal hit_time_stamp_i : std_logic_vector(10 downto 0); - signal fine_counter_i : std_logic_vector(9 downto 0); - signal fine_counter_reg : std_logic_vector(9 downto 0); - signal encoder_start_i : std_logic; - signal encoder_finished_i : std_logic; - signal encoder_debug_i : std_logic_vector(31 downto 0); - signal fifo_data_out_i : std_logic_vector(31 downto 0); - signal fifo_data_in_i : std_logic_vector(31 downto 0); - signal fifo_empty_i : std_logic; - signal fifo_full_i : std_logic; - signal fifo_wr_en_i : std_logic; - signal fifo_rd_en_i : std_logic; - signal valid_tmg_trg_i : std_logic; - signal multi_tmg_trg_i : std_logic; - signal spike_detected_i : std_logic; - signal ff_array_en_i : std_logic := '1'; + signal data_a_i : std_logic_vector(303 downto 0); + signal data_b_i : std_logic_vector(303 downto 0); + signal result_i : std_logic_vector(303 downto 0); + signal result_reg : std_logic_vector(303 downto 0); + signal hit_in_i : std_logic; + signal hit_buf : std_logic; + signal hit_detect_i : std_logic; + signal hit_detect_reg : std_logic; + signal hit_detect_2reg : std_logic; + signal dl_release_i : std_logic; + signal result_2_reg : std_logic; + signal coarse_cntr_i : std_logic_vector(10 downto 0); + signal hit_time_stamp_i : std_logic_vector(10 downto 0); + signal fine_counter_i : std_logic_vector(9 downto 0); + signal fine_counter_reg : std_logic_vector(9 downto 0); + signal encoder_start_i : std_logic; + signal encoder_finished_i : std_logic; + signal encoder_debug_i : std_logic_vector(31 downto 0); + signal fifo_data_out_i : std_logic_vector(31 downto 0); + signal fifo_data_in_i : std_logic_vector(31 downto 0); + signal fifo_empty_i : std_logic; + signal fifo_full_i : std_logic; + signal fifo_almost_full_i : std_logic; + signal fifo_wr_en_i : std_logic; + signal fifo_rd_en_i : std_logic; + signal valid_tmg_trg_i : std_logic; + signal multi_tmg_trg_i : std_logic; + signal spike_detected_i : std_logic; + signal ff_array_en_i : std_logic := '1'; type FSM is (IDLE, LOOK_FOR_VALIDITY, ENCODER_FINISHED, WAIT_FOR_FALLING_EDGE); signal FSM_CURRENT, FSM_NEXT : FSM; @@ -157,11 +77,14 @@ architecture Reference_Channel of Reference_Channel is signal fsm_debug_i : std_logic_vector(3 downto 0); signal fsm_debug_fsm : std_logic_vector(3 downto 0); - attribute syn_keep : boolean; - attribute syn_keep of hit_buf : signal is true; - attribute syn_keep of hit_in_i : signal is true; - attribute NOMERGE : string; - attribute NOMERGE of hit_buf : signal is "true"; + attribute syn_keep : boolean; + attribute syn_keep of hit_buf : signal is true; + attribute syn_keep of hit_in_i : signal is true; + attribute syn_keep of ff_array_en_i : signal is true; + attribute NOMERGE : string; + attribute NOMERGE of hit_buf : signal is "true"; + attribute NOMERGE of hit_in_i : signal is "true"; + attribute NOMERGE of ff_array_en_i : signal is "true"; ------------------------------------------------------------------------------- @@ -169,79 +92,21 @@ begin fifo_rd_en_i <= READ_EN_IN; coarse_cntr_i <= COARSE_COUNTER_IN; - hit_in_i <= HIT_IN; - hit_buf <= not hit_in_i; +-- hit_in_i <= HIT_IN; + hit_buf <= not HIT_IN; - ----purpose: Registers the hit signal - --Hit_Register : process (CLK_WR, RESET_WR) - --begin - -- if rising_edge(CLK_WR) then - -- if RESET_WR = '1' then - -- hit_reg <= '0'; - -- else - -- hit_reg <= hit_in_i; - -- end if; - -- end if; - --end process Hit_Register; - - ----purpose: Toggles between rising and falling edges - --Toggle_Edge_Detection : process (hit_reg, hit_in_i) - --begin - -- if hit_reg = '1' then - -- hit_buf <= not hit_in_i; - -- else - -- hit_buf <= hit_in_i; - -- end if; - --end process Toggle_Edge_Detection; - - --purpose: Tapped Delay Line 304 (Carry Chain) with wave launcher (21) + --purpose: Tapped Delay Line 304 (Carry Chain) with wave launcher (21) double transition FC : Adder_304 port map ( CLK => CLK_WR, RESET => RESET_WR, DataA => data_a_i, DataB => data_b_i, - ClkEn => '1', --ff_array_en_i, + ClkEn => '1', --ff_array_en_i, Result => result_i); - data_a_i <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000FF" & x"7FFFFFF"; + data_a_i <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" & x"7FFFFFF"; data_b_i <= x"000000000000000000000000000000000000000000000000000000000000000000000" & not(hit_buf) & x"000000" & "00" & hit_buf; - --FF_Array_Enable : process (hit_detect_i, release_delay_line_i) - --begin - -- if hit_detect_i = '1' then - -- ff_array_en_i <= '0'; - -- elsif release_delay_line_i = '1' then - -- ff_array_en_i <= '1'; - -- end if; - --end process FF_Array_Enable; - - ----purpose: Enables the signal for delay line releasing - --Release_DL : process (CLK_WR, RESET_WR) - --begin - -- if rising_edge(CLK_WR) then - -- if RESET_WR = '1' then - -- release_delay_line_i <= '0'; - -- elsif hit_detect_2reg = '1' then - -- release_delay_line_i <= '1'; - -- else - -- release_delay_line_i <= '0'; - -- end if; - -- end if; - --end process Release_DL; - - ----purpose: Tapped Delay Line 304 (Carry Chain) with wave launcher (21) single transition - --FC : Adder_304 - -- port map ( - -- CLK => CLK_WR, - -- RESET => RESET_WR, - -- DataA => data_a_i, - -- DataB => data_b_i, - -- ClkEn => '1', - -- Result => result_i); - --data_a_i <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"; - --data_b_i <= x"000000000000000000000000000000000000000000000000000000000000000000000000000" & "000" & hit_in_i; - - --purpose: Registers the 2nd bit of the carry chain Hit_Detect_Register : process (CLK_WR, RESET_WR) begin @@ -250,20 +115,18 @@ begin result_2_reg <= '0'; hit_detect_reg <= '0'; hit_detect_2reg <= '0'; --- result_29_reg <= '0'; else result_2_reg <= result_i(2); hit_detect_reg <= hit_detect_i; hit_detect_2reg <= hit_detect_reg; --- result_29_reg <= result_i(30); end if; end if; end process Hit_Detect_Register; --purpose: Detects the hit - Hit_Detect : process (result_2_reg, result_i) --result_29_reg + Hit_Detect : process (result_2_reg, result_i) begin - hit_detect_i <= ((not result_2_reg) and result_i(2)); -- or (result_29_reg and not(result_i(29))); + hit_detect_i <= ((not result_2_reg) and result_i(2)); end process Hit_Detect; --purpose: Double Synchroniser @@ -272,14 +135,12 @@ begin if rising_edge(CLK_WR) then if RESET_WR = '1' then result_reg <= (others => '1'); - elsif hit_detect_i = '1' then --or hit_trig_reset_i = '1' then + elsif hit_detect_i = '1' then result_reg <= result_i; end if; end if; end process Double_Syncroniser; --- Channel_DEBUG_01(0) <= result_reg(303); - --purpose: Start Encoder and captures the time stamp of the hit Start_Encoder : process (CLK_WR) begin @@ -320,48 +181,39 @@ begin end if; end process Register_Binary_Code; - FIFO : FIFO_32x512_OutReg + FIFO : FIFO_32x32_OutReg port map ( - Data => fifo_data_in_i, - WrClock => CLK_WR, - RdClock => CLK_RD, - WrEn => fifo_wr_en_i, - RdEn => fifo_rd_en_i, - Reset => RESET_RD, - RPReset => RESET_RD, - Q => fifo_data_out_i, - Empty => fifo_empty_i, - Full => fifo_full_i); - + Data => fifo_data_in_i, + WrClock => CLK_WR, + RdClock => CLK_RD, + WrEn => fifo_wr_en_i, + RdEn => fifo_rd_en_i, + Reset => RESET_RD, + RPReset => RESET_RD, + Q => fifo_data_out_i, + Empty => fifo_empty_i, + Full => fifo_full_i, + AlmostFull => fifo_almost_full_i); fifo_data_in_i(31) <= '1'; -- data marker - fifo_data_in_i(30 downto 28) <= "000"; -- reserved bits - fifo_data_in_i(27 downto 22) <= conv_std_logic_vector(CHANNEL_ID, 6); -- channel number + fifo_data_in_i(30 downto 29) <= "00"; -- reserved bits + fifo_data_in_i(28 downto 22) <= conv_std_logic_vector(CHANNEL_ID, 7); -- channel number fifo_data_in_i(21 downto 12) <= fine_counter_reg; -- fine time from the encoder - fifo_data_in_i(11) <= '1'; --edge_type_i; -- rising '1' or falling '0' edge + fifo_data_in_i(11) <= '1'; --edge_type_i; -- rising '1' or falling '0' edge fifo_data_in_i(10 downto 0) <= hit_time_stamp_i; -- hit time stamp - --Toggle_Edge_Type : process (CLK_WR, RESET_WR) - --begin - -- if rising_edge(CLK_WR) then - -- if RESET_WR = '1' then - -- edge_type_i <= '1'; - -- elsif fifo_wr_en_i = '1' then - -- edge_type_i <= not edge_type_i; - -- end if; - -- end if; - --end process Toggle_Edge_Type; - Register_Outputs : process (CLK_RD, RESET_RD) begin if rising_edge(CLK_RD) then if RESET_RD = '1' then - FIFO_DATA_OUT <= (others => '1'); - FIFO_EMPTY_OUT <= '0'; - FIFO_FULL_OUT <= '0'; + FIFO_DATA_OUT <= (others => '1'); + FIFO_EMPTY_OUT <= '0'; + FIFO_FULL_OUT <= '0'; + FIFO_ALMOST_FULL_OUT <= '0'; else - FIFO_DATA_OUT <= fifo_data_out_i; - FIFO_EMPTY_OUT <= fifo_empty_i; - FIFO_FULL_OUT <= fifo_full_i; + FIFO_DATA_OUT <= fifo_data_out_i; + FIFO_EMPTY_OUT <= fifo_empty_i; + FIFO_FULL_OUT <= fifo_full_i; + FIFO_ALMOST_FULL_OUT <= fifo_almost_full_i; end if; end if; end process Register_Outputs; @@ -391,14 +243,13 @@ begin case (FSM_CURRENT) is when IDLE => if hit_detect_i = '1' then - FSM_NEXT <= ENCODER_FINISHED; - fsm_debug_fsm <= x"1"; + FSM_NEXT <= ENCODER_FINISHED; else - FSM_NEXT <= IDLE; - fsm_debug_fsm <= x"2"; + FSM_NEXT <= IDLE; end if; + fsm_debug_fsm <= x"1"; - when ENCODER_FINISHED => + when ENCODER_FINISHED => if encoder_finished_i = '1' then FSM_NEXT <= LOOK_FOR_VALIDITY; elsif valid_tmg_trg_i = '1' then @@ -406,34 +257,21 @@ begin else FSM_NEXT <= ENCODER_FINISHED; end if; + fsm_debug_fsm <= x"2"; when LOOK_FOR_VALIDITY => if valid_tmg_trg_i = '1' then - FSM_NEXT <= IDLE; --WAIT_FOR_FALLING_EDGE; + FSM_NEXT <= IDLE; fifo_wr_en_fsm <= '1'; - fsm_debug_fsm <= x"4"; elsif multi_tmg_trg_i = '1' then - FSM_NEXT <= IDLE; - fsm_debug_fsm <= x"5"; + FSM_NEXT <= IDLE; elsif spike_detected_i = '1' then - FSM_NEXT <= IDLE; - fsm_debug_fsm <= x"6"; + FSM_NEXT <= IDLE; else - FSM_NEXT <= LOOK_FOR_VALIDITY; - fsm_debug_fsm <= x"7"; + FSM_NEXT <= LOOK_FOR_VALIDITY; end if; + fsm_debug_fsm <= x"3"; - when WAIT_FOR_FALLING_EDGE => - if encoder_finished_i = '1' then - FSM_NEXT <= IDLE; - fifo_wr_en_fsm <= '1'; - fsm_debug_fsm <= x"C"; - else - FSM_NEXT <= WAIT_FOR_FALLING_EDGE; - fifo_wr_en_fsm <= '0'; - fsm_debug_fsm <= x"D"; - end if; - when others => FSM_NEXT <= IDLE; end case; diff --git a/tdc_releases/tdc_v0.2/source/TDC.vhd b/tdc_releases/tdc_v0.2/source/TDC.vhd index 3743543..9f514c8 100644 --- a/tdc_releases/tdc_v0.2/source/TDC.vhd +++ b/tdc_releases/tdc_v0.2/source/TDC.vhd @@ -6,6 +6,12 @@ use IEEE.NUMERIC_STD.all; use STD.TEXTIO.all; use IEEE.STD_LOGIC_TEXTIO.all; +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.version.all; + -- synopsys translate_off -- library ecp2m; -- use ecp2m.components.all; @@ -13,7 +19,7 @@ use IEEE.STD_LOGIC_TEXTIO.all; entity TDC is generic ( - CHANNEL_NUMBER : integer range 0 to 64; + CHANNEL_NUMBER : integer range 2 to 65; STATUS_REG_NR : integer range 0 to 6; CONTROL_REG_NR : integer range 0 to 6); port ( @@ -55,90 +61,6 @@ end TDC; architecture TDC of TDC is -------------------------------------------------------------------------------- --- Component Declarations -------------------------------------------------------------------------------- - - component Reference_Channel - generic ( - CHANNEL_ID : integer range 0 to 0); - port ( - RESET_WR : in std_logic; - RESET_RD : in std_logic; - CLK_WR : in std_logic; - CLK_RD : in std_logic; - HIT_IN : in std_logic; - READ_EN_IN : in std_logic; - VALID_TMG_TRG_IN : in std_logic; - SPIKE_DETECTED_IN : in std_logic; - MULTI_TMG_TRG_IN : in std_logic; - FIFO_DATA_OUT : out std_logic_vector(31 downto 0); - FIFO_EMPTY_OUT : out std_logic; - FIFO_FULL_OUT : out std_logic; - COARSE_COUNTER_IN : in std_logic_vector(10 downto 0); - TRIGGER_TIME_OUT : out std_logic_vector(10 downto 0); - REF_DEBUG_OUT : out std_logic_vector(31 downto 0)); - end component; --- - component Channel - generic ( - CHANNEL_ID : integer range 1 to 64); - port ( - RESET_WR : in std_logic; - RESET_RD : in std_logic; - CLK_WR : in std_logic; - CLK_RD : in std_logic; - HIT_IN : in std_logic; - READ_EN_IN : in std_logic; - FIFO_DATA_OUT : out std_logic_vector(31 downto 0); - FIFO_EMPTY_OUT : out std_logic; - FIFO_FULL_OUT : out std_logic; - COARSE_COUNTER_IN : in std_logic_vector(10 downto 0); - LOST_HIT_NUMBER : out std_logic_vector(23 downto 0); - MEASUREMENT_NUMBER : out std_logic_vector(23 downto 0); - ENCODER_START_NUMBER : out std_logic_vector(23 downto 0); - Channel_DEBUG_01 : out std_logic_vector(31 downto 0) - ); - end component; --- - component ROM_FIFO - port ( - Address : in std_logic_vector(7 downto 0); - OutClock : in std_logic; - OutClockEn : in std_logic; - Reset : in std_logic; - Q : out std_logic_vector(3 downto 0)); - end component; --- - component up_counter - generic ( - NUMBER_OF_BITS : positive); - port ( - CLK : in std_logic; - RESET : in std_logic; - COUNT_OUT : out std_logic_vector(NUMBER_OF_BITS-1 downto 0); - UP_IN : in std_logic); - end component; --- - component edge_to_pulse - port ( - clock : in std_logic; - en_clk : in std_logic; - signal_in : in std_logic; - pulse : out std_logic); - end component; --- - component bit_sync - generic ( - DEPTH : integer); - port ( - RESET : in std_logic; - CLK0 : in std_logic; - CLK1 : in std_logic; - D_IN : in std_logic; - D_OUT : out std_logic); - end component; - ------------------------------------------------------------------------------- -- Signal Declarations ------------------------------------------------------------------------------- @@ -198,26 +120,28 @@ architecture TDC of TDC is signal wr_trailer_i : std_logic; -- Other Signals - signal fifo_full_i : std_logic; - signal mask_i : std_logic_vector(CHANNEL_NUMBER downto 0); - signal fifo_nr : integer range 0 to CHANNEL_NUMBER := CHANNEL_NUMBER; - signal fifo_nr_next : integer range 0 to CHANNEL_NUMBER := CHANNEL_NUMBER; - signal TW_pre : std_logic_vector(10 downto 0); - signal TW_post : std_logic_vector(10 downto 0); - signal channel_hit_time : std_logic_vector(10 downto 0); - signal trg_win_l : std_logic; - signal trg_win_r : std_logic; - type Std_Logic_8_array is array (0 to (CHANNEL_NUMBER/8-1)) of std_logic_vector(3 downto 0); - signal fifo_nr_hex : Std_Logic_8_array; - signal coarse_cnt : std_logic_vector(10 downto 0); - signal reset_coarse_cnt : std_logic; - signal channel_full_i : std_logic_vector(CHANNEL_NUMBER-1 downto 0); - signal channel_empty_i : std_logic_vector(CHANNEL_NUMBER-1 downto 0); - signal channel_empty_reg : std_logic_vector(CHANNEL_NUMBER-1 downto 0); + signal fifo_full_i : std_logic; + signal fifo_almost_full_i : std_logic; + signal mask_i : std_logic_vector(71 downto 0); + signal fifo_nr : integer range 0 to CHANNEL_NUMBER := CHANNEL_NUMBER; + signal fifo_nr_next : integer range 0 to CHANNEL_NUMBER := CHANNEL_NUMBER; + signal TW_pre : std_logic_vector(10 downto 0); + signal TW_post : std_logic_vector(10 downto 0); + signal channel_hit_time : std_logic_vector(10 downto 0); + signal trg_win_l : std_logic; + signal trg_win_r : std_logic; + type Std_Logic_8_array is array (0 to 8) of std_logic_vector(3 downto 0); + signal fifo_nr_hex : Std_Logic_8_array; + signal coarse_cnt : std_logic_vector(10 downto 0); + signal reset_coarse_cnt : std_logic; + signal channel_full_i : std_logic_vector(CHANNEL_NUMBER-1 downto 0); + signal channel_almost_full_i : std_logic_vector(CHANNEL_NUMBER-1 downto 0); + signal channel_empty_i : std_logic_vector(CHANNEL_NUMBER-1 downto 0); + signal channel_empty_reg : std_logic_vector(CHANNEL_NUMBER-1 downto 0); type channel_data_array is array (0 to CHANNEL_NUMBER) of std_logic_vector(31 downto 0); - signal channel_data_i : channel_data_array; - signal channel_data_reg : channel_data_array; - signal hit_in_i : std_logic_vector(CHANNEL_NUMBER-1 downto 0); + signal channel_data_i : channel_data_array; + signal channel_data_reg : channel_data_array; + signal hit_in_i : std_logic_vector(CHANNEL_NUMBER-1 downto 1); -- Slow Control Signals signal ch_en_i : std_logic_vector(63 downto 0); @@ -227,11 +151,13 @@ architecture TDC of TDC is -- 0: triggerless signal readout_trigger_mode_200 : std_logic := '1'; -- trigger mode signal synchronised to the coarse counter clk signal logic_anal_control : std_logic_vector(3 downto 0); + signal debug_mode_en_i : std_logic; -- Statistics Signals type statistics_array_12 is array (1 to CHANNEL_NUMBER-1) of std_logic_vector(11 downto 0); type statistics_array_24 is array (1 to CHANNEL_NUMBER-1) of std_logic_vector(23 downto 0); signal trig_number : std_logic_vector(23 downto 0); + signal release_number : std_logic_vector(23 downto 0); signal valid_tmg_trig_number : std_logic_vector(23 downto 0); signal valid_timing_trg_pulse : std_logic; signal valid_NOtmg_trig_number : std_logic_vector(23 downto 0); @@ -256,25 +182,30 @@ architecture TDC of TDC is signal wait_time : std_logic_vector(23 downto 0); signal empty_channels : std_logic_vector(CHANNEL_NUMBER-1 downto 0); signal total_empty_channel : std_logic_vector(23 downto 0); - signal channel_lost_hits : statistics_array_24; - signal channel_measurement : statistics_array_24; + signal channel_lost_hit_number : statistics_array_24; + signal channel_hit_detect_number : statistics_array_24; signal channel_encoder_start_number : statistics_array_24; + signal channel_fifo_wr_number : statistics_array_24; signal stop_status_i : std_logic; -- Test signals - signal ref_debug_i : std_logic_vector(31 downto 0); + signal ref_debug_i : std_logic_vector(31 downto 0); type channel_debug_array is array (1 to CHANNEL_NUMBER-1) of std_logic_vector(31 downto 0); - signal channel_debug_01_i : channel_debug_array; + signal channel_debug_i : channel_debug_array; ------------------------------------------------------------------------------- begin ------------------------------------------------------------------------------- -- Slow control signals ------------------------------------------------------------------------------- - ch_en_i <= CONTROL_REG_IN(3*32+31 downto 2*32+0); - trigger_win_en <= CONTROL_REG_IN(1*32+31); + logic_anal_control <= CONTROL_REG_IN(3 downto 0) when rising_edge(CLK_READOUT); + debug_mode_en_i <= CONTROL_REG_IN(4); readout_trigger_mode <= CONTROL_REG_IN(12); - logic_anal_control <= CONTROL_REG_IN(3 downto 0); + + trigger_win_en <= CONTROL_REG_IN(1*32+31); + + ch_en_i <= CONTROL_REG_IN(3*32+31 downto 2*32+0); + ------------------------------------------------------------------------------- -- The Reset Signal Genaration (Synchronous with the fine time clock) ------------------------------------------------------------------------------- @@ -293,25 +224,26 @@ begin generic map ( CHANNEL_ID => 0) port map ( - RESET_WR => reset_tdc, - RESET_RD => RESET, - CLK_WR => CLK_TDC, - CLK_RD => CLK_READOUT, - HIT_IN => REFERENCE_TIME, - READ_EN_IN => rd_en_i(0), - VALID_TMG_TRG_IN => VALID_TIMING_TRG_IN, - SPIKE_DETECTED_IN => SPIKE_DETECTED_IN, - MULTI_TMG_TRG_IN => MULTI_TMG_TRG_IN, - FIFO_DATA_OUT => channel_data_i(0), - FIFO_EMPTY_OUT => channel_empty_i(0), - FIFO_FULL_OUT => channel_full_i(0), - COARSE_COUNTER_IN => coarse_cnt, - TRIGGER_TIME_OUT => trigger_time_i, - REF_DEBUG_OUT => ref_debug_i); + RESET_WR => reset_tdc, + RESET_RD => RESET, + CLK_WR => CLK_TDC, + CLK_RD => CLK_READOUT, + HIT_IN => REFERENCE_TIME, + READ_EN_IN => rd_en_i(0), + VALID_TMG_TRG_IN => VALID_TIMING_TRG_IN, + SPIKE_DETECTED_IN => SPIKE_DETECTED_IN, + MULTI_TMG_TRG_IN => MULTI_TMG_TRG_IN, + FIFO_DATA_OUT => channel_data_i(0), + FIFO_EMPTY_OUT => channel_empty_i(0), + FIFO_FULL_OUT => channel_full_i(0), + FIFO_ALMOST_FULL_OUT => channel_almost_full_i(0), + COARSE_COUNTER_IN => coarse_cnt, + TRIGGER_TIME_OUT => trigger_time_i, + REF_DEBUG_OUT => ref_debug_i); -- Channel enable signals GEN_Channel_Enable : for i in 1 to CHANNEL_NUMBER-1 generate - hit_in_i(i) <= HIT_IN(i) and ch_en_i(i); + hit_in_i(i) <= HIT_IN(i) and ch_en_i(i-1); end generate GEN_Channel_Enable; -- Channels @@ -329,11 +261,13 @@ begin FIFO_DATA_OUT => channel_data_i(i), FIFO_EMPTY_OUT => channel_empty_i(i), FIFO_FULL_OUT => channel_full_i(i), + FIFO_ALMOST_FULL_OUT => channel_almost_full_i(i), COARSE_COUNTER_IN => coarse_cnt, - LOST_HIT_NUMBER => channel_lost_hits(i), - MEASUREMENT_NUMBER => channel_measurement(i), + LOST_HIT_NUMBER => channel_lost_hit_number(i), + HIT_DETECT_NUMBER => channel_hit_detect_number(i), ENCODER_START_NUMBER => channel_encoder_start_number(i), - Channel_DEBUG_01 => channel_debug_01_i(i)); + FIFO_WR_NUMBER => channel_fifo_wr_number(i), + Channel_DEBUG => channel_debug_i(i)); end generate GEN_Channels; channel_data_i(CHANNEL_NUMBER) <= x"FFFFFFFF"; @@ -348,7 +282,7 @@ begin UP_IN => '1'); -- Trigger mode control register synchronised to the coarse counter clk - Readout_trigger_mode_sync: bit_sync + Readout_trigger_mode_sync : bit_sync generic map ( DEPTH => 3) port map ( @@ -358,7 +292,7 @@ begin D_IN => readout_trigger_mode, D_OUT => readout_trigger_mode_200); - Valid_timing_trigger_sync: bit_sync + Valid_timing_trigger_sync : bit_sync generic map ( DEPTH => 3) port map ( @@ -374,7 +308,7 @@ begin en_clk => '1', signal_in => valid_timing_trg_200, pulse => valid_timing_trg_pulse_200); - + ------------------------------------------------------------------------------- @@ -398,7 +332,7 @@ begin end if; end if; end process Coarse_Counter_Reset; - + -- Reference Time (Coarse) -- purpose: If the timing trigger is valid, the coarse time of the reference @@ -528,14 +462,14 @@ begin fifo_nr_next <= conv_integer("00010" & fifo_nr_hex(2)(2 downto 0)); elsif fifo_nr_hex(3)(3) /= '1' then fifo_nr_next <= conv_integer("00011" & fifo_nr_hex(3)(2 downto 0)); - --elsif fifo_nr_hex(4)(3) /= '1' then - -- fifo_nr_next <= conv_integer("00100" & fifo_nr_hex(4)(2 downto 0)); - --elsif fifo_nr_hex(5)(3) /= '1' then - -- fifo_nr_next <= conv_integer("00101" & fifo_nr_hex(5)(2 downto 0)); - --elsif fifo_nr_hex(6)(3) /= '1' then - -- fifo_nr_next <= conv_integer("00110" & fifo_nr_hex(6)(2 downto 0)); - --elsif fifo_nr_hex(7)(3) /= '1' then - -- fifo_nr_next <= conv_integer("00111" & fifo_nr_hex(7)(2 downto 0)); + elsif fifo_nr_hex(4)(3) /= '1' then + fifo_nr_next <= conv_integer("00100" & fifo_nr_hex(4)(2 downto 0)); + elsif fifo_nr_hex(5)(3) /= '1' then + fifo_nr_next <= conv_integer("00101" & fifo_nr_hex(5)(2 downto 0)); + elsif fifo_nr_hex(6)(3) /= '1' then + fifo_nr_next <= conv_integer("00110" & fifo_nr_hex(6)(2 downto 0)); + elsif fifo_nr_hex(7)(3) /= '1' then + fifo_nr_next <= conv_integer("00111" & fifo_nr_hex(7)(2 downto 0)); else fifo_nr_next <= CHANNEL_NUMBER; end if; @@ -567,7 +501,7 @@ begin stop_status_i <= '0'; else if wr_header_i = '1' then - data_out_reg <= "001" & "0000000000000" & header_error_bits; + data_out_reg <= "001" & "00000" & TRG_CODE_IN & header_error_bits; data_wr_reg <= '1'; stop_status_i <= '0'; elsif wr_ch_data_reg = '1' and trigger_win_en = '1' then @@ -588,23 +522,25 @@ begin end if; stop_status_i <= '0'; elsif wr_ch_data_reg = '1' and trigger_win_en = '0' then - data_out_reg <= "1000" & channel_data_reg(fifo_nr)(27 downto 0); + data_out_reg <= channel_data_reg(fifo_nr); data_wr_reg <= '1'; stop_status_i <= '0'; elsif wr_status_i = '1' then case i is - when 0 => data_out_reg <= "010" & "00000" & valid_tmg_trig_number; - when 1 => data_out_reg <= "010" & "00001" & trig_number; - when 2 => data_out_reg <= "010" & "00010" & valid_NOtmg_trig_number; - when 3 => data_out_reg <= "010" & "00011" & invalid_trig_number; - when 4 => data_out_reg <= "010" & "00100" & multi_tmg_trig_number; - when 5 => data_out_reg <= "010" & "00101" & spurious_trig_number; - when 6 => data_out_reg <= "010" & "00110" & wrong_readout_number; - when 7 => data_out_reg <= "010" & "00111" & spike_number; - when 8 => data_out_reg <= "010" & "01000" & idle_time; - when 9 => data_out_reg <= "010" & "01001" & wait_time; - stop_status_i <= '1'; - when 10 => data_out_reg <= "010" & "01010" & total_empty_channel; + when 0 => data_out_reg <= "010" & "00000" & trig_number; + when 1 => data_out_reg <= "010" & "00001" & release_number; + when 2 => data_out_reg <= "010" & "00010" & valid_tmg_trig_number; + when 3 => data_out_reg <= "010" & "00011" & valid_NOtmg_trig_number; + when 4 => data_out_reg <= "010" & "00100" & invalid_trig_number; + when 5 => data_out_reg <= "010" & "00101" & multi_tmg_trig_number; + when 6 => data_out_reg <= "010" & "00110" & spurious_trig_number; + when 7 => data_out_reg <= "010" & "00111" & wrong_readout_number; + when 8 => data_out_reg <= "010" & "01000" & spike_number; + when 9 => data_out_reg <= "010" & "01001" & idle_time; + when 10 => data_out_reg <= "010" & "01010" & wait_time; + stop_status_i <= '1'; + when 11 => data_out_reg <= "010" & "01011" & total_empty_channel; + i := -1; when others => null; end case; data_wr_reg <= '1'; @@ -635,11 +571,11 @@ begin begin if rising_edge(CLK_READOUT) then if RESET = '1' then - channel_data_reg <= (others => x"00000000"); - channel_empty_reg <= (others => '0'); + channel_data_reg <= (others => x"00000000"); + channel_empty_reg <= (others => '0'); else - channel_data_reg <= channel_data_i; - channel_empty_reg <= channel_empty_i; + channel_data_reg <= channel_data_i; + channel_empty_reg <= channel_empty_i; end if; end if; end process Delay_Channel_Data; @@ -694,7 +630,7 @@ begin FSM_PROC : process (FSM_CURRENT, VALID_TIMING_TRG_IN, VALID_NOTIMING_TRG_IN, trg_win_end_i, fifo_nr_next, fifo_nr, channel_empty_reg, TRG_DATA_VALID_IN, INVALID_TRG_IN, TMGTRG_TIMEOUT_IN, - TRG_TYPE_IN, SPURIOUS_TRG_IN, stop_status_i) + TRG_TYPE_IN, SPURIOUS_TRG_IN, stop_status_i, debug_mode_en_i) begin start_trg_win_cnt_fsm <= '0'; @@ -710,143 +646,144 @@ begin readout_fsm <= '0'; wait_fsm <= '0'; wr_status_fsm <= '0'; + fsm_debug_fsm <= x"00"; + FSM_NEXT <= IDLE; case (FSM_CURRENT) is when IDLE => if VALID_TIMING_TRG_IN = '1' then FSM_NEXT <= WAIT_FOR_TRG_WIND_END; start_trg_win_cnt_fsm <= '1'; - fsm_debug_fsm <= x"01"; elsif VALID_NOTIMING_TRG_IN = '1' then if TRG_TYPE_IN = x"E" then - FSM_NEXT <= SEND_STATUS; - fsm_debug_fsm <= x"02"; + FSM_NEXT <= SEND_STATUS; else - FSM_NEXT <= SEND_TRG_RELEASE_A; - fsm_debug_fsm <= x"03"; + FSM_NEXT <= SEND_TRG_RELEASE_A; end if; wr_header_fsm <= '1'; elsif INVALID_TRG_IN = '1' then - FSM_NEXT <= SEND_TRG_RELEASE_A; - fsm_debug_fsm <= x"04"; + FSM_NEXT <= SEND_TRG_RELEASE_A; + data_finished_fsm <= '1'; else - FSM_NEXT <= IDLE; - fsm_debug_fsm <= x"05"; + FSM_NEXT <= IDLE; end if; - idle_fsm <= '1'; + idle_fsm <= '1'; + fsm_debug_fsm <= x"01"; -- when WAIT_FOR_TRG_WIND_END => if trg_win_end_i = '1' then - FSM_NEXT <= WR_HEADER; - fsm_debug_fsm <= x"06"; + FSM_NEXT <= WR_HEADER; else - FSM_NEXT <= WAIT_FOR_TRG_WIND_END; - fsm_debug_fsm <= x"07"; + FSM_NEXT <= WAIT_FOR_TRG_WIND_END; end if; - wait_fsm <= '1'; + wait_fsm <= '1'; + fsm_debug_fsm <= x"02"; ------------------------------------------------------------------------------- -- Readout process starts when WR_HEADER => FSM_NEXT <= WAIT_FOR_FIFO_NR_A; wr_header_fsm <= '1'; - fsm_debug_fsm <= x"08"; readout_fsm <= '1'; + fsm_debug_fsm <= x"03"; when WAIT_FOR_FIFO_NR_A => FSM_NEXT <= WAIT_FOR_FIFO_NR_B; updt_index_fsm <= '1'; - fsm_debug_fsm <= x"0A"; wait_fsm <= '1'; + fsm_debug_fsm <= x"04"; when WAIT_FOR_FIFO_NR_B => FSM_NEXT <= APPLY_MASK; - fsm_debug_fsm <= x"0C"; wait_fsm <= '1'; + fsm_debug_fsm <= x"05"; when APPLY_MASK => if fifo_nr_next = CHANNEL_NUMBER then - FSM_NEXT <= WAIT_FOR_LVL1_TRG_A; - data_finished_fsm <= '1'; - fsm_debug_fsm <= x"0D"; + if debug_mode_en_i = '1' then + FSM_NEXT <= SEND_STATUS; + else + FSM_NEXT <= WAIT_FOR_LVL1_TRG_A; + data_finished_fsm <= '1'; + end if; else FSM_NEXT <= RD_CHANNEL_A; rd_en_fsm(fifo_nr) <= '1'; updt_mask_fsm <= '1'; - fsm_debug_fsm <= x"0E"; end if; - wait_fsm <= '1'; + wait_fsm <= '1'; + fsm_debug_fsm <= x"06"; when RD_CHANNEL_A => FSM_NEXT <= RD_CHANNEL_B; rd_en_fsm(fifo_nr) <= '1'; - fsm_debug_fsm <= x"0F"; readout_fsm <= '1'; - + fsm_debug_fsm <= x"07"; + when RD_CHANNEL_B => FSM_NEXT <= RD_CHANNEL_C; rd_en_fsm(fifo_nr) <= '1'; - fsm_debug_fsm <= x"10"; readout_fsm <= '1'; - + fsm_debug_fsm <= x"08"; + when RD_CHANNEL_C => if channel_empty_reg(fifo_nr) = '1' then FSM_NEXT <= WAIT_FOR_FIFO_NR_B; wr_ch_data_fsm <= '0'; updt_index_fsm <= '1'; - fsm_debug_fsm <= x"11"; else FSM_NEXT <= RD_CHANNEL_C; wr_ch_data_fsm <= '1'; rd_en_fsm(fifo_nr) <= '1'; - fsm_debug_fsm <= x"12"; end if; - readout_fsm <= '1'; + readout_fsm <= '1'; + fsm_debug_fsm <= x"09"; ------------------------------------------------------------------------------- when WAIT_FOR_LVL1_TRG_A => if TRG_DATA_VALID_IN = '1' then - FSM_NEXT <= WAIT_FOR_LVL1_TRG_B; - fsm_debug_fsm <= x"13"; + FSM_NEXT <= WAIT_FOR_LVL1_TRG_B; elsif TMGTRG_TIMEOUT_IN = '1' then - FSM_NEXT <= IDLE; - fsm_debug_fsm <= x"14"; + FSM_NEXT <= IDLE; else - FSM_NEXT <= WAIT_FOR_LVL1_TRG_A; - fsm_debug_fsm <= x"15"; + FSM_NEXT <= WAIT_FOR_LVL1_TRG_A; end if; - wait_fsm <= '1'; + wait_fsm <= '1'; + fsm_debug_fsm <= x"0A"; -- when WAIT_FOR_LVL1_TRG_B => FSM_NEXT <= WAIT_FOR_LVL1_TRG_C; - fsm_debug_fsm <= x"16"; wait_fsm <= '1'; + fsm_debug_fsm <= x"0B"; -- when WAIT_FOR_LVL1_TRG_C => if SPURIOUS_TRG_IN = '1' then wrong_readout_fsm <= '1'; end if; FSM_NEXT <= SEND_TRG_RELEASE_A; - fsm_debug_fsm <= x"17"; wait_fsm <= '1'; + fsm_debug_fsm <= x"0C"; -- when SEND_STATUS => -- here the status of the TDC should be sent if stop_status_i = '1' then - FSM_NEXT <= SEND_TRG_RELEASE_A; + if debug_mode_en_i = '1' then + FSM_NEXT <= WAIT_FOR_LVL1_TRG_A; + else + FSM_NEXT <= SEND_TRG_RELEASE_A; + end if; data_finished_fsm <= '1'; - fsm_debug_fsm <= x"18"; else FSM_NEXT <= SEND_STATUS; wr_status_fsm <= '1'; - fsm_debug_fsm <= x"19"; end if; + fsm_debug_fsm <= x"0D"; -- when SEND_TRG_RELEASE_A => FSM_NEXT <= SEND_TRG_RELEASE_B; trg_release_fsm <= '1'; - fsm_debug_fsm <= x"1A"; + fsm_debug_fsm <= x"0E"; -- when SEND_TRG_RELEASE_B => FSM_NEXT <= IDLE; - fsm_debug_fsm <= x"1B"; + fsm_debug_fsm <= x"0F"; -- when others => FSM_NEXT <= IDLE; @@ -858,28 +795,23 @@ begin -- Header-Trailor Error & Warning Bits ------------------------------------------------------------------------------- -- Error, warning bits set in the header - header_error_bits(15 downto 2) <= (others => '0'); + header_error_bits(15 downto 3) <= (others => '0'); header_error_bits(0) <= '0'; --header_error_bits(0) <= lost_hit_i; -- if there is at least one lost hit (can be more if the FIFO is full). header_error_bits(1) <= fifo_full_i; -- if the channel FIFO is full. - --header_error_bits(2) <= fifo_almost_full_i; -- if the channel FIFO is almost full. + header_error_bits(2) <= fifo_almost_full_i; -- if the channel FIFO is almost full. -- Error, warning bits set in the trailer trailer_error_bits <= (others => '0'); -- trailer_error_bits (0) <= wrong_readout_i; -- if there is a wrong readout because of a spurious timing trigger. - -- Information bits sent after a status trigger - -- <= lost_hits_nr_i; -- total number of lost hits. - - fifo_full_i <= channel_full_i(15) or channel_full_i(14) or channel_full_i(13) or channel_full_i(12) or - channel_full_i(11) or channel_full_i(10) or channel_full_i(9) or channel_full_i(8) or - channel_full_i(7) or channel_full_i(6) or channel_full_i(5) or channel_full_i(4) or - channel_full_i(3) or channel_full_i(2) or channel_full_i(1) or channel_full_i(0); + fifo_full_i <= or_all(channel_full_i); + fifo_almost_full_i <= or_all(channel_almost_full_i); ------------------------------------------------------------------------------- -- Debug and statistics words ------------------------------------------------------------------------------- - + edge_to_pulse_1 : edge_to_pulse port map ( clock => CLK_READOUT, @@ -934,6 +866,18 @@ begin end if; end process Statistics_Trigger_Number; + -- purpose: Internal release number counter + Statistics_Release_Number : process (CLK_READOUT, RESET) + begin + if rising_edge(CLK_READOUT) then + if RESET = '1' then + release_number <= (others => '0'); + elsif trg_release_reg = '1' then + release_number <= release_number + 1; + end if; + end if; + end process Statistics_Release_Number; + -- purpose: Internal valid timing trigger number counter Statistics_Valid_Timing_Trigger_Number : process (CLK_READOUT, RESET) begin @@ -1071,116 +1015,53 @@ begin -- Logic Analyser Signals ------------------------------------------------------------------------------- -- Logic Analyser and Test Signals - --REG_LOGIC_ANALYSER_OUTPUT : process (CLK_READOUT, RESET) - --begin - -- if rising_edge(CLK_READOUT) then - -- if RESET = '1' then - -- logic_analyser_reg <= (others => '0'); - -- elsif logic_anal_control = x"1" then TRBNET connections debugging - -- logic_analyser_reg(7 downto 0) <= fsm_debug_reg; - -- logic_analyser_reg(8) <= REFERENCE_TIME; - -- logic_analyser_reg(9) <= VALID_TIMING_TRG_IN; - -- logic_analyser_reg(10) <= VALID_NOTIMING_TRG_IN; - -- logic_analyser_reg(11) <= INVALID_TRG_IN; - -- logic_analyser_reg(12) <= TRG_DATA_VALID_IN; - -- logic_analyser_reg(13) <= data_wr_reg; - -- logic_analyser_reg(14) <= data_finished_reg; - -- logic_analyser_reg(15) <= trg_release_reg; - -- elsif logic_anal_control = x"2" then Reference channel debugging - -- logic_analyser_reg <= ref_debug_i(15 downto 0); - -- elsif logic_anal_control = x"3" then Hit input debugging - -- logic_analyser_reg(7 downto 1) <= HIT_IN(7 downto 1); - -- elsif logic_anal_control = x"4" then -- Hit input debugging - -- logic_analyser_reg(15 downto 0) <= HIT_IN(31 downto 16); - -- elsif logic_anal_control = x"5" then -- Hit input debugging - -- logic_analyser_reg(15 downto 0) <= HIT_IN(47 downto 32); - -- elsif logic_anal_control = x"6" then -- Hit input debugging - -- logic_analyser_reg(15 downto 0) <= HIT_IN(63 downto 48); - -- logic_analyser_reg(15 downto 7) <= (others => '0'); - -- elsif logic_anal_control = x"7" then Data out - -- logic_analyser_reg(7 downto 0) <= fsm_debug_reg; - -- logic_analyser_reg(8) <= REFERENCE_TIME; - -- logic_analyser_reg(13) <= data_wr_reg; - -- logic_analyser_reg(12 downto 9) <= data_out_reg(25 downto 22); - -- logic_analyser_reg(14) <= data_out_reg(26); - -- logic_analyser_reg(15) <= RESET; - - -- elsif logic_anal_control = x"8" then Data out - -- logic_analyser_reg(0) <= HIT_IN(2); - -- logic_analyser_reg(1) <= CLK_TDC; - -- logic_analyser_reg(2) <= channel_debug_01_i(2)(1); encoder_start - -- logic_analyser_reg(3) <= channel_debug_01_i(2)(2); fifo_wr_en - -- logic_analyser_reg(7 downto 4) <= channel_debug_01_i(2)(6 downto 3); interval register - -- logic_analyser_reg(12 downto 9) <= channel_debug_01_i(2)(10 downto 7); interval register - -- logic_analyser_reg(14) <= channel_debug_01_i(2)(11); interval register - -- logic_analyser_reg(8) <= REFERENCE_TIME; - -- logic_analyser_reg(13) <= data_wr_reg; - -- logic_analyser_reg(15) <= RESET; - - -- elsif logic_anal_control = x"9" then Data out - -- logic_analyser_reg(0) <= HIT_IN(3); - -- logic_analyser_reg(1) <= CLK_TDC; - -- logic_analyser_reg(2) <= channel_debug_01_i(3)(1); encoder_start - -- logic_analyser_reg(3) <= channel_debug_01_i(3)(2); fifo_wr_en - -- logic_analyser_reg(7 downto 4) <= channel_debug_01_i(3)(6 downto 3); interval register - -- logic_analyser_reg(12 downto 9) <= channel_debug_01_i(3)(10 downto 7); interval register - -- logic_analyser_reg(14) <= channel_debug_01_i(3)(11); interval register - -- logic_analyser_reg(8) <= REFERENCE_TIME; - -- logic_analyser_reg(13) <= data_wr_reg; - -- logic_analyser_reg(15) <= RESET; - - -- end if; - -- end if; - --end process REG_LOGIC_ANALYSER_OUTPUT; - - --- REG_LOGIC_ANALYSER_OUTPUT : process (CLK_TDC, reset_tdc) --- begin --- if rising_edge(CLK_TDC) then --- if reset_tdc = '1' then --- logic_analyser_reg <= (others => '0'); --- logic_analyser_2reg <= (others => '0'); --- elsif logic_anal_control = x"1" then --TRBNET connections debugging --- logic_analyser_reg(0) <= HIT_IN(3); --- logic_analyser_reg(1) <= RESET; --- logic_analyser_reg(2) <= channel_debug_01_i(3)(1); --encoder_start --- logic_analyser_reg(3) <= channel_debug_01_i(3)(2); --fifo_wr_en --- logic_analyser_reg(7 downto 4) <= channel_debug_01_i(3)(6 downto 3); --interval register --- logic_analyser_reg(12 downto 9) <= channel_debug_01_i(3)(10 downto 7); --interval register --- logic_analyser_reg(14) <= channel_debug_01_i(3)(11); --interval register --- logic_analyser_reg(8) <= REFERENCE_TIME; ----- logic_analyser_reg(13) <= data_wr_reg; --- logic_analyser_2reg <= logic_analyser_reg; --- else --- logic_analyser_reg <= (others => '0'); --- logic_analyser_2reg <= logic_analyser_reg; --- end if; --- end if; --- end process REG_LOGIC_ANALYSER_OUTPUT; - - --LOGIC_ANALYSER_OUT(14 downto 0) <= logic_analyser_2reg(14 downto 0); - --LOGIC_ANALYSER_OUT(15) <= CLK_TDC; + REG_LOGIC_ANALYSER_OUTPUT : process (CLK_READOUT, RESET) + begin + if rising_edge(CLK_READOUT) then + if RESET = '1' then + logic_analyser_reg <= (others => '0'); + elsif logic_anal_control = x"1" then -- TRBNET connections debugging + logic_analyser_reg(7 downto 0) <= fsm_debug_reg; + logic_analyser_reg(8) <= REFERENCE_TIME; + logic_analyser_reg(9) <= VALID_TIMING_TRG_IN; + logic_analyser_reg(10) <= VALID_NOTIMING_TRG_IN; + logic_analyser_reg(11) <= INVALID_TRG_IN; + logic_analyser_reg(12) <= TRG_DATA_VALID_IN; + logic_analyser_reg(13) <= data_wr_reg; + logic_analyser_reg(14) <= data_finished_reg; + logic_analyser_reg(15) <= trg_release_reg; + + elsif logic_anal_control = x"2" then -- Reference channel debugging + logic_analyser_reg <= ref_debug_i(15 downto 0); + + elsif logic_anal_control = x"3" then -- Data out + logic_analyser_reg(7 downto 0) <= fsm_debug_reg; + logic_analyser_reg(8) <= REFERENCE_TIME; + logic_analyser_reg(9) <= data_wr_reg; + logic_analyser_reg(15 downto 10) <= data_out_reg(27 downto 22); + + elsif logic_anal_control = x"4" then -- channel debugging + logic_analyser_reg <= channel_debug_i(1)(15 downto 0); + end if; + end if; + end process REG_LOGIC_ANALYSER_OUTPUT; + LOGIC_ANALYSER_OUT <= logic_analyser_reg; ------------------------------------------------------------------------------- -- STATUS REGISTERS ------------------------------------------------------------------------------- -- Register 0x80 - TDC_DEBUG(7 downto 0) <= fsm_debug_reg; --- --- TDC_DEBUG(15 downto 8) <= --- --- TDC_DEBUG(23 downto 16) <= + TDC_DEBUG(7 downto 0) <= fsm_debug_reg; + TDC_DEBUG(15 downto 8) <= std_logic_vector(to_unsigned(CHANNEL_NUMBER-1, 8)); + TDC_DEBUG(16) <= REFERENCE_TIME when rising_edge(CLK_READOUT); -- -- TDC_DEBUG(27 downto 24) <= -- -- TDC_DEBUG(31 downto 28) <= --- Register 0x81 - TDC_DEBUG(1*32+CHANNEL_NUMBER-1 downto 1*32+0) <= channel_empty_i; - --- Register 0x82 --- TDC_DEBUG(2*32+7 downto 2*32+0) <= channel_empty_i(63 downto 32); + -- Register 0x81 & 0x82 + TDC_DEBUG(1*32+CHANNEL_NUMBER-2 downto 1*32+0) <= channel_empty_i(CHANNEL_NUMBER-1 downto 1); -- Register 0x83 TDC_DEBUG(3*32+31 downto 3*32+0) <= "00000" & TRG_WIN_POST & "00000" & TRG_WIN_PRE; @@ -1219,21 +1100,30 @@ begin TDC_DEBUG(14*32+23 downto 14*32+0) <= total_empty_channel; -- Register 0x8f - TDC_DEBUG(15*32+23 downto 15*32+0) <= channel_lost_hits(3); + TDC_DEBUG(15*32+23 downto 15*32+0) <= release_number; -- Register 0x90 - TDC_DEBUG(16*32+23 downto 16*32+0) <= channel_measurement(3); + TDC_DEBUG(16*32+23 downto 16*32+0) <= channel_lost_hit_number(1); -- Register 0x91 - TDC_DEBUG(17*32+23 downto 17*32+0) <= channel_encoder_start_number(3); + TDC_DEBUG(17*32+23 downto 17*32+0) <= channel_hit_detect_number(1); -- Register 0x92 - TDC_DEBUG(18*32+23 downto 18*32+0) <= channel_lost_hits(2); + TDC_DEBUG(18*32+23 downto 18*32+0) <= channel_encoder_start_number(1); -- Register 0x93 - TDC_DEBUG(19*32+23 downto 19*32+0) <= channel_measurement(2); + TDC_DEBUG(19*32+23 downto 19*32+0) <= channel_fifo_wr_number(1); + +---- Register 0x94 +-- TDC_DEBUG(20*32+23 downto 20*32+0) <= channel_lost_hit_number(2); + +---- Register 0x95 +-- TDC_DEBUG(21*32+23 downto 21*32+0) <= channel_hit_detect_number(2); + +---- Register 0x96 +-- TDC_DEBUG(22*32+23 downto 22*32+0) <= channel_encoder_start_number(2); --- Register 0x94 - TDC_DEBUG(20*32+23 downto 20*32+0) <= channel_encoder_start_number(2); +---- Register 0x97 +-- TDC_DEBUG(23*32+23 downto 23*32+0) <= channel_fifo_wr_number(2); end TDC; diff --git a/tdc_releases/tdc_v0.2/source/trb3_periph.vhd b/tdc_releases/tdc_v0.2/source/trb3_periph.vhd index bb6a3de..5be486e 100644 --- a/tdc_releases/tdc_v0.2/source/trb3_periph.vhd +++ b/tdc_releases/tdc_v0.2/source/trb3_periph.vhd @@ -199,7 +199,7 @@ architecture trb3_periph_arch of trb3_periph is signal time_counter : unsigned(31 downto 0); --TDC - signal hit_in_i : std_logic_vector(31 downto 1); + signal hit_in_i : std_logic_vector(64 downto 1); --TDC component component TDC @@ -582,7 +582,7 @@ begin THE_TDC : TDC generic map ( - CHANNEL_NUMBER => 32, -- Number of TDC channels + CHANNEL_NUMBER => 5, -- Number of TDC channels STATUS_REG_NR => REGIO_NUM_STAT_REGS, CONTROL_REG_NR => REGIO_NUM_CTRL_REGS) port map ( @@ -590,7 +590,7 @@ begin CLK_TDC => CLK_PCLK_LEFT, -- Clock used for the time measurement CLK_READOUT => clk_100_i, -- Clock for the readout REFERENCE_TIME => timing_trg_received_i, -- Reference time input - HIT_IN => hit_in_i(31 downto 1), -- Channel start signals + HIT_IN => hit_in_i(4 downto 1), -- Channel start signals TRG_WIN_PRE => ctrl_reg(42 downto 32), -- Pre-Trigger window width TRG_WIN_POST => ctrl_reg(58 downto 48), -- Post-Trigger window width -- @@ -620,12 +620,14 @@ begin LOGIC_ANALYSER_OUT => TEST_LINE, CONTROL_REG_IN => ctrl_reg); + -- For single edge measurements + hit_in_i(64 downto 1) <= INP(63 downto 0); - hit_in_i(1) <= not timing_trg_received_i; - - Gen_Hit_In_Signals : for i in 1 to 15 generate - hit_in_i(i*2) <= INP(i-1); - hit_in_i(i*2+1) <= not INP(i-1); - end generate Gen_Hit_In_Signals; + ---- For ToT Measurements + --hit_in_i(1) <= not timing_trg_received_i; + --Gen_Hit_In_Signals : for i in 1 to 3 generate + -- hit_in_i(i*2) <= INP(i-1); + -- hit_in_i(i*2+1) <= not INP(i-1); + --end generate Gen_Hit_In_Signals; end architecture; diff --git a/tdc_releases/tdc_v0.2/trb3_periph_constraints.lpf b/tdc_releases/tdc_v0.2/trb3_periph_constraints.lpf new file mode 100644 index 0000000..b046770 --- /dev/null +++ b/tdc_releases/tdc_v0.2/trb3_periph_constraints.lpf @@ -0,0 +1,1161 @@ +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +BLOCK RD_DURING_WR_PATHS ; + +################################################################# +# Basic Settings +################################################################# + + SYSCONFIG MCCLK_FREQ = 20; + +################################################################# +# Reset Nets +################################################################# +GSR_NET NET "GSR_N"; + + +################################################################# +# Locate Serdes and media interfaces +################################################################# +LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ; + + +REGION "MEDIA_UPLINK" "R90C110D" 25 10; +REGION "REGION_SPI" "R11C164D" 10 18 DEVSIZE; +#REGION "REGION_IOBUF" "R10C43D" 88 86 DEVSIZE; + +LOCATE UGROUP "THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ; +LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ; + +LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ; + +MULTICYCLE TO CELL "THE_MEDIA_DOWNLINK/SCI_DATA_OUT*" 50 ns; +MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns; +MULTICYCLE TO CELL "THE_RESET_HANDLER/final_reset*" 30 ns; + +################################################################# +# TDC Constraints +################################################################# +############################################################################## +## REGION DECLERATION ## +############################################################################## +REGION "Region_E&F_0" "R105C2D" 6 60 DEVSIZE; +REGION "Region_E&F_1" "R92C2D" 10 60 DEVSIZE; +REGION "Region_E&F_2" "R74C2D" 10 60 DEVSIZE; +REGION "Region_E&F_3" "R56C2D" 10 60 DEVSIZE; +REGION "Region_E&F_4" "R38C2D" 10 60 DEVSIZE; +REGION "Region_E&F_5" "R24C2D" 6 60 DEVSIZE; +REGION "Region_E&F_6" "R11C2D" 10 60 DEVSIZE; + +REGION "Region_E&F_7" "R105C122D" 6 60 DEVSIZE; +REGION "Region_E&F_8" "R92C122D" 10 60 DEVSIZE; +REGION "Region_E&F_9" "R74C122D" 10 60 DEVSIZE; +REGION "Region_E&F_10" "R56C122D" 10 60 DEVSIZE; +REGION "Region_E&F_11" "R38C122D" 10 60 DEVSIZE; +REGION "Region_E&F_12" "R24C122D" 6 60 DEVSIZE; +REGION "Region_E&F_13" "R11C122D" 10 60 DEVSIZE; + +REGION "Region_E&F_14" "R11C62D" 10 60 DEVSIZE; +REGION "Region_E&F_15" "R24C62D" 6 60 DEVSIZE; +REGION "Region_E&F_16" "R38C62D" 10 60 DEVSIZE; +REGION "Region_E&F_17" "R56C62D" 10 60 DEVSIZE; +REGION "Region_E&F_18" "R74C62D" 10 60 DEVSIZE; + +############################################################################## +## REFERENCE CHANNEL PLACEMENT ## +############################################################################## +UGROUP "Ref_Ch" BBOX 1 51 + BLKNAME THE_TDC/The_Reference_Time/FC; +LOCATE UGROUP "Ref_Ch" SITE "R113C2D" ; +UGROUP "hit_ref_ch" + BLKNAME TRIGGER_LEFT_pad_RNIM301; #BLKNAME THE_TDC/The_Reference_Time/hit_buf_RNO; +LOCATE UGROUP "hit_ref_ch" SITE "R114C4D" ; +UGROUP "Encoder_ref" BBOX 2 28 + BLKNAME THE_TDC/The_Reference_Time/Encoder; +LOCATE UGROUP "Encoder_ref" REGION "Region_E&F_0" ; +UGROUP "FIFO_ref" BBOX 2 14 + BLKNAME THE_TDC/The_Reference_Time/FIFO; +LOCATE UGROUP "FIFO_ref" REGION "Region_E&F_0" ; + + +############################################################################## +## DELAY LINE and HIT BUFFER PLACEMENTS ## +############################################################################## +# +UGROUP "FC_1" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_1_Channels/FC; +LOCATE UGROUP "FC_1" SITE "R111C2D" ; +UGROUP "hit_1" + BLKNAME THE_TDC/GEN_Channels_1_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_1" SITE "R112C4D" ; +# +UGROUP "FC_2" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_2_Channels/FC; +LOCATE UGROUP "FC_2" SITE "R104C2D" ; +UGROUP "hit_2" + BLKNAME THE_TDC/GEN_Channels_2_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_2" SITE "R105C4D" ; +# +UGROUP "FC_3" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_3_Channels/FC; +LOCATE UGROUP "FC_3" SITE "R102C2D" ; +UGROUP "hit_3" + BLKNAME THE_TDC/GEN_Channels_3_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_3" SITE "R103C4D" ; +# +UGROUP "FC_4" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_4_Channels/FC; +LOCATE UGROUP "FC_4" SITE "R91C2D" ; +UGROUP "hit_4" + BLKNAME THE_TDC/GEN_Channels_4_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_4" SITE "R92C4D" ; +# +UGROUP "FC_5" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_5_Channels/FC; +LOCATE UGROUP "FC_5" SITE "R89C2D" ; +UGROUP "hit_5" + BLKNAME THE_TDC/GEN_Channels_5_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_5" SITE "R90C4D" ; +# +UGROUP "FC_6" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_6_Channels/FC; +LOCATE UGROUP "FC_6" SITE "R86C2D" ; +UGROUP "hit_6" + BLKNAME THE_TDC/GEN_Channels_6_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_6" SITE "R87C4D" ; +# +UGROUP "FC_7" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_7_Channels/FC; +LOCATE UGROUP "FC_7" SITE "R84C2D" ; +UGROUP "hit_7" + BLKNAME THE_TDC/GEN_Channels_7_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_7" SITE "R85C4D" ; +# +UGROUP "FC_8" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_8_Channels/FC; +LOCATE UGROUP "FC_8" SITE "R73C2D" ; +UGROUP "hit_8" + BLKNAME THE_TDC/GEN_Channels_8_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_8" SITE "R74C4D" ; +# +UGROUP "FC_9" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_9_Channels/FC; +LOCATE UGROUP "FC_9" SITE "R71C2D" ; +UGROUP "hit_9" + BLKNAME THE_TDC/GEN_Channels_9_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_9" SITE "R72C4D" ; +# +UGROUP "FC_10" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_10_Channels/FC; +LOCATE UGROUP "FC_10" SITE "R68C2D" ; +UGROUP "hit_10" + BLKNAME THE_TDC/GEN_Channels_10_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_10" SITE "R69C4D" ; +# +UGROUP "FC_11" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_11_Channels/FC; +LOCATE UGROUP "FC_11" SITE "R66C2D" ; +UGROUP "hit_11" + BLKNAME THE_TDC/GEN_Channels_11_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_11" SITE "R67C4D" ; +# +UGROUP "FC_12" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_12_Channels/FC; +LOCATE UGROUP "FC_12" SITE "R55C2D" ; +UGROUP "hit_12" + BLKNAME THE_TDC/GEN_Channels_12_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_12" SITE "R56C4D" ; +# +UGROUP "FC_13" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_13_Channels/FC; +LOCATE UGROUP "FC_13" SITE "R53C2D" ; +UGROUP "hit_13" + BLKNAME THE_TDC/GEN_Channels_13_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_13" SITE "R54C4D" ; +# +UGROUP "FC_14" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_14_Channels/FC; +LOCATE UGROUP "FC_14" SITE "R50C2D" ; +UGROUP "hit_14" + BLKNAME THE_TDC/GEN_Channels_14_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_14" SITE "R51C4D" ; +# +UGROUP "FC_15" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_15_Channels/FC; +LOCATE UGROUP "FC_15" SITE "R48C2D" ; +UGROUP "hit_15" + BLKNAME THE_TDC/GEN_Channels_15_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_15" SITE "R49C4D" ; +# +UGROUP "FC_16" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_16_Channels/FC; +LOCATE UGROUP "FC_16" SITE "R37C2D" ; +UGROUP "hit_16" + BLKNAME THE_TDC/GEN_Channels_16_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_16" SITE "R38C4D" ; +# +UGROUP "FC_17" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_17_Channels/FC; +LOCATE UGROUP "FC_17" SITE "R35C2D" ; +UGROUP "hit_17" + BLKNAME THE_TDC/GEN_Channels_17_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_17" SITE "R36C4D" ; +# +UGROUP "FC_18" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_18_Channels/FC; +LOCATE UGROUP "FC_18" SITE "R32C2D" ; +UGROUP "hit_18" + BLKNAME THE_TDC/GEN_Channels_18_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_18" SITE "R33C4D" ; +# +UGROUP "FC_19" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_19_Channels/FC; +LOCATE UGROUP "FC_19" SITE "R30C2D" ; +UGROUP "hit_19" + BLKNAME THE_TDC/GEN_Channels_19_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_19" SITE "R31C4D" ; +# +UGROUP "FC_20" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_20_Channels/FC; +LOCATE UGROUP "FC_20" SITE "R23C2D" ; +UGROUP "hit_20" + BLKNAME THE_TDC/GEN_Channels_20_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_20" SITE "R24C4D" ; +# +UGROUP "FC_21" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_21_Channels/FC; +LOCATE UGROUP "FC_21" SITE "R21C2D" ; +UGROUP "hit_21" + BLKNAME THE_TDC/GEN_Channels_21_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_21" SITE "R22C4D" ; +# +UGROUP "FC_22" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_22_Channels/FC; +LOCATE UGROUP "FC_22" SITE "R10C2D" ; +UGROUP "hit_22" + BLKNAME THE_TDC/GEN_Channels_22_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_22" SITE "R11C4D" ; +# +UGROUP "FC_23" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_23_Channels/FC; +LOCATE UGROUP "FC_23" SITE "R8C2D" ; +UGROUP "hit_23" + BLKNAME THE_TDC/GEN_Channels_23_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_23" SITE "R9C4D" ; +# + + + + +UGROUP "FC_24" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_24_Channels/FC; +LOCATE UGROUP "FC_24" SITE "R113C125D" ; +UGROUP "hit_24" + BLKNAME THE_TDC/GEN_Channels_24_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_24" SITE "R114C127D" ; +# +UGROUP "FC_25" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_25_Channels/FC; +LOCATE UGROUP "FC_25" SITE "R111C125D" ; +UGROUP "hit_25" + BLKNAME THE_TDC/GEN_Channels_25_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_25" SITE "R112C127D" ; +# +UGROUP "FC_26" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_26_Channels/FC; +LOCATE UGROUP "FC_26" SITE "R104C125D" ; +UGROUP "hit_26" + BLKNAME THE_TDC/GEN_Channels_26_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_26" SITE "R105C127D" ; +# +UGROUP "FC_27" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_27_Channels/FC; +LOCATE UGROUP "FC_27" SITE "R102C125D" ; +UGROUP "hit_27" + BLKNAME THE_TDC/GEN_Channels_27_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_27" SITE "R103C127D" ; +# +UGROUP "FC_28" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_28_Channels/FC; +LOCATE UGROUP "FC_28" SITE "R91C125D" ; +UGROUP "hit_28" + BLKNAME THE_TDC/GEN_Channels_28_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_28" SITE "R92C127D" ; +# +UGROUP "FC_29" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_29_Channels/FC; +LOCATE UGROUP "FC_29" SITE "R89C125D" ; +UGROUP "hit_29" + BLKNAME THE_TDC/GEN_Channels_29_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_29" SITE "R90C127D" ; +# +UGROUP "FC_30" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_30_Channels/FC; +LOCATE UGROUP "FC_30" SITE "R86C125D" ; +UGROUP "hit_30" + BLKNAME THE_TDC/GEN_Channels_30_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_30" SITE "R87C127D" ; +# +UGROUP "FC_31" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_31_Channels/FC; +LOCATE UGROUP "FC_31" SITE "R84C125D" ; +UGROUP "hit_31" + BLKNAME THE_TDC/GEN_Channels_31_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_31" SITE "R85C127D" ; +# +UGROUP "FC_32" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_32_Channels/FC; +LOCATE UGROUP "FC_32" SITE "R73C125D" ; +UGROUP "hit_32" + BLKNAME THE_TDC/GEN_Channels_32_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_32" SITE "R74C127D" ; +# +UGROUP "FC_33" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_33_Channels/FC; +LOCATE UGROUP "FC_33" SITE "R71C125D" ; +UGROUP "hit_33" + BLKNAME THE_TDC/GEN_Channels_33_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_33" SITE "R72C127D" ; +# +UGROUP "FC_34" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_34_Channels/FC; +LOCATE UGROUP "FC_34" SITE "R68C125D" ; +UGROUP "hit_34" + BLKNAME THE_TDC/GEN_Channels_34_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_34" SITE "R69C127D" ; +# +UGROUP "FC_35" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_35_Channels/FC; +LOCATE UGROUP "FC_35" SITE "R66C125D" ; +UGROUP "hit_35" + BLKNAME THE_TDC/GEN_Channels_35_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_35" SITE "R67C127D" ; +# +UGROUP "FC_36" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_36_Channels/FC; +LOCATE UGROUP "FC_36" SITE "R55C125D" ; +UGROUP "hit_36" + BLKNAME THE_TDC/GEN_Channels_36_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_36" SITE "R56C127D" ; +# +UGROUP "FC_37" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_37_Channels/FC; +LOCATE UGROUP "FC_37" SITE "R53C125D" ; +UGROUP "hit_37" + BLKNAME THE_TDC/GEN_Channels_37_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_37" SITE "R54C127D" ; +# +UGROUP "FC_38" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_38_Channels/FC; +LOCATE UGROUP "FC_38" SITE "R50C125D" ; +UGROUP "hit_38" + BLKNAME THE_TDC/GEN_Channels_38_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_38" SITE "R51C127D" ; +# +UGROUP "FC_39" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_39_Channels/FC; +LOCATE UGROUP "FC_39" SITE "R48C125D" ; +UGROUP "hit_39" + BLKNAME THE_TDC/GEN_Channels_39_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_39" SITE "R49C127D" ; +# +UGROUP "FC_40" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_40_Channels/FC; +LOCATE UGROUP "FC_40" SITE "R37C125D" ; +UGROUP "hit_40" + BLKNAME THE_TDC/GEN_Channels_40_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_40" SITE "R38C127D" ; +# +UGROUP "FC_41" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_41_Channels/FC; +LOCATE UGROUP "FC_41" SITE "R35C125D" ; +UGROUP "hit_41" + BLKNAME THE_TDC/GEN_Channels_41_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_41" SITE "R36C127D" ; +# +UGROUP "FC_42" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_42_Channels/FC; +LOCATE UGROUP "FC_42" SITE "R32C125D" ; +UGROUP "hit_42" + BLKNAME THE_TDC/GEN_Channels_42_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_42" SITE "R33C127D" ; +# +UGROUP "FC_43" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_43_Channels/FC; +LOCATE UGROUP "FC_43" SITE "R30C125D" ; +UGROUP "hit_43" + BLKNAME THE_TDC/GEN_Channels_43_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_43" SITE "R31C127D" ; +# +UGROUP "FC_44" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_44_Channels/FC; +LOCATE UGROUP "FC_44" SITE "R23C125D" ; +UGROUP "hit_44" + BLKNAME THE_TDC/GEN_Channels_44_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_44" SITE "R24C127D" ; +# +UGROUP "FC_45" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_45_Channels/FC; +LOCATE UGROUP "FC_45" SITE "R21C125D" ; +UGROUP "hit_45" + BLKNAME THE_TDC/GEN_Channels_45_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_45" SITE "R22C127D" ; +# +UGROUP "FC_46" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_46_Channels/FC; +LOCATE UGROUP "FC_46" SITE "R10C125D" ; +UGROUP "hit_46" + BLKNAME THE_TDC/GEN_Channels_46_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_46" SITE "R11C127D" ; +# +UGROUP "FC_47" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_47_Channels/FC; +LOCATE UGROUP "FC_47" SITE "R8C125D" ; +UGROUP "hit_47" + BLKNAME THE_TDC/GEN_Channels_47_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_47" SITE "R9C127D" ; +# + + + + + +UGROUP "FC_48" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_48_Channels/FC; +LOCATE UGROUP "FC_48" SITE "R8C66D" ; +UGROUP "hit_48" + BLKNAME THE_TDC/GEN_Channels_48_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_48" SITE "R9C68D" ; +# +UGROUP "FC_49" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_49_Channels/FC; +LOCATE UGROUP "FC_49" SITE "R10C66D" ; +UGROUP "hit_49" + BLKNAME THE_TDC/GEN_Channels_49_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_49" SITE "R11C68D" ; +# +UGROUP "FC_50" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_50_Channels/FC; +LOCATE UGROUP "FC_50" SITE "R21C66D" ; +UGROUP "hit_50" + BLKNAME THE_TDC/GEN_Channels_50_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_50" SITE "R22C68D" ; +# +UGROUP "FC_51" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_51_Channels/FC; +LOCATE UGROUP "FC_51" SITE "R23C66D" ; +UGROUP "hit_51" + BLKNAME THE_TDC/GEN_Channels_51_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_51" SITE "R24C68D" ; +# +UGROUP "FC_52" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_52_Channels/FC; +LOCATE UGROUP "FC_52" SITE "R30C66D" ; +UGROUP "hit_52" + BLKNAME THE_TDC/GEN_Channels_52_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_52" SITE "R31C68D" ; +# +UGROUP "FC_53" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_53_Channels/FC; +LOCATE UGROUP "FC_53" SITE "R32C66D" ; +UGROUP "hit_53" + BLKNAME THE_TDC/GEN_Channels_53_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_53" SITE "R33C68D" ; +# +UGROUP "FC_54" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_54_Channels/FC; +LOCATE UGROUP "FC_54" SITE "R35C66D" ; +UGROUP "hit_54" + BLKNAME THE_TDC/GEN_Channels_54_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_54" SITE "R36C68D" ; +# +UGROUP "FC_55" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_55_Channels/FC; +LOCATE UGROUP "FC_55" SITE "R37C66D" ; +UGROUP "hit_55" + BLKNAME THE_TDC/GEN_Channels_55_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_55" SITE "R38C68D" ; +# +UGROUP "FC_56" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_56_Channels/FC; +LOCATE UGROUP "FC_56" SITE "R48C66D" ; +UGROUP "hit_56" + BLKNAME THE_TDC/GEN_Channels_56_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_56" SITE "R49C68D" ; +# +UGROUP "FC_57" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_57_Channels/FC; +LOCATE UGROUP "FC_57" SITE "R50C66D" ; +UGROUP "hit_57" + BLKNAME THE_TDC/GEN_Channels_57_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_57" SITE "R51C68D" ; +# +UGROUP "FC_58" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_58_Channels/FC; +LOCATE UGROUP "FC_58" SITE "R53C66D" ; +UGROUP "hit_58" + BLKNAME THE_TDC/GEN_Channels_58_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_58" SITE "R54C68D" ; +# +UGROUP "FC_59" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_59_Channels/FC; +LOCATE UGROUP "FC_59" SITE "R55C66D" ; +UGROUP "hit_59" + BLKNAME THE_TDC/GEN_Channels_59_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_59" SITE "R56C68D" ; +# +UGROUP "FC_60" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_60_Channels/FC; +LOCATE UGROUP "FC_60" SITE "R66C66D" ; +UGROUP "hit_60" + BLKNAME THE_TDC/GEN_Channels_60_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_60" SITE "R67C68D" ; +# +UGROUP "FC_61" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_61_Channels/FC; +LOCATE UGROUP "FC_61" SITE "R68C66D" ; +UGROUP "hit_61" + BLKNAME THE_TDC/GEN_Channels_61_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_61" SITE "R69C68D" ; +# +UGROUP "FC_62" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_62_Channels/FC; +LOCATE UGROUP "FC_62" SITE "R71C66D" ; +UGROUP "hit_62" + BLKNAME THE_TDC/GEN_Channels_62_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_62" SITE "R72C68D" ; +# +UGROUP "FC_63" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_63_Channels/FC; +LOCATE UGROUP "FC_63" SITE "R73C66D" ; +UGROUP "hit_63" + BLKNAME THE_TDC/GEN_Channels_63_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_63" SITE "R74C68D" ; +# +UGROUP "FC_64" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_64_Channels/FC; +LOCATE UGROUP "FC_64" SITE "R84C66D" ; +UGROUP "hit_64" + BLKNAME THE_TDC/GEN_Channels_64_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_64" SITE "R85C68D" ; + + + + +############################################################################## +## CHANNEL PLACEMENTS ## +############################################################################## +UGROUP "Encoder_1" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_1_Channels/Encoder; +LOCATE UGROUP "Encoder_1" REGION "Region_E&F_0" ; +UGROUP "FIFO_1" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_1_Channels/FIFO; +LOCATE UGROUP "FIFO_1" REGION "Region_E&F_0" ; +UGROUP "Encoder_2" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_2_Channels/Encoder; +LOCATE UGROUP "Encoder_2" REGION "Region_E&F_1" ; +UGROUP "FIFO_2" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_2_Channels/FIFO; +LOCATE UGROUP "FIFO_2" REGION "Region_E&F_1" ; +UGROUP "Encoder_3" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_3_Channels/Encoder; +LOCATE UGROUP "Encoder_3" REGION "Region_E&F_1" ; +UGROUP "FIFO_3" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_3_Channels/FIFO; +LOCATE UGROUP "FIFO_3" REGION "Region_E&F_1" ; +UGROUP "Encoder_4" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_4_Channels/Encoder; +LOCATE UGROUP "Encoder_4" REGION "Region_E&F_1" ; +UGROUP "FIFO_4" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_4_Channels/FIFO; +LOCATE UGROUP "FIFO_4" REGION "Region_E&F_1" ; +UGROUP "Encoder_5" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_5_Channels/Encoder; +LOCATE UGROUP "Encoder_5" REGION "Region_E&F_1" ; +UGROUP "FIFO_5" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_5_Channels/FIFO; +LOCATE UGROUP "FIFO_5" REGION "Region_E&F_1" ; +UGROUP "Encoder_6" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_6_Channels/Encoder; +LOCATE UGROUP "Encoder_6" REGION "Region_E&F_2" ; +UGROUP "FIFO_6" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_6_Channels/FIFO; +LOCATE UGROUP "FIFO_6" REGION "Region_E&F_2" ; +UGROUP "Encoder_7" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_7_Channels/Encoder; +LOCATE UGROUP "Encoder_7" REGION "Region_E&F_2" ; +UGROUP "FIFO_7" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_7_Channels/FIFO; +LOCATE UGROUP "FIFO_7" REGION "Region_E&F_2" ; +UGROUP "Encoder_8" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_8_Channels/Encoder; +LOCATE UGROUP "Encoder_8" REGION "Region_E&F_2" ; +UGROUP "FIFO_8" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_8_Channels/FIFO; +LOCATE UGROUP "FIFO_8" REGION "Region_E&F_2" ; +UGROUP "Encoder_9" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_9_Channels/Encoder; +LOCATE UGROUP "Encoder_9" REGION "Region_E&F_2" ; +UGROUP "FIFO_9" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_9_Channels/FIFO; +LOCATE UGROUP "FIFO_9" REGION "Region_E&F_2" ; +UGROUP "Encoder_10" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_10_Channels/Encoder; +LOCATE UGROUP "Encoder_10" REGION "Region_E&F_3" ; +UGROUP "FIFO_10" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_10_Channels/FIFO; +LOCATE UGROUP "FIFO_10" REGION "Region_E&F_3" ; +UGROUP "Encoder_11" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_11_Channels/Encoder; +LOCATE UGROUP "Encoder_11" REGION "Region_E&F_3" ; +UGROUP "FIFO_11" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_11_Channels/FIFO; +LOCATE UGROUP "FIFO_11" REGION "Region_E&F_3" ; +UGROUP "Encoder_12" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_12_Channels/Encoder; +LOCATE UGROUP "Encoder_12" REGION "Region_E&F_3" ; +UGROUP "FIFO_12" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_12_Channels/FIFO; +LOCATE UGROUP "FIFO_12" REGION "Region_E&F_3" ; +UGROUP "Encoder_13" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_13_Channels/Encoder; +LOCATE UGROUP "Encoder_13" REGION "Region_E&F_3" ; +UGROUP "FIFO_13" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_13_Channels/FIFO; +LOCATE UGROUP "FIFO_13" REGION "Region_E&F_3" ; +UGROUP "Encoder_14" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_14_Channels/Encoder; +LOCATE UGROUP "Encoder_14" REGION "Region_E&F_4" ; +UGROUP "FIFO_14" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_14_Channels/FIFO; +LOCATE UGROUP "FIFO_14" REGION "Region_E&F_4" ; +UGROUP "Encoder_15" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_15_Channels/Encoder; +LOCATE UGROUP "Encoder_15" REGION "Region_E&F_4" ; +UGROUP "FIFO_15" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_15_Channels/FIFO; +LOCATE UGROUP "FIFO_15" REGION "Region_E&F_4" ; +UGROUP "Encoder_16" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_16_Channels/Encoder; +LOCATE UGROUP "Encoder_16" REGION "Region_E&F_4" ; +UGROUP "FIFO_16" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_16_Channels/FIFO; +LOCATE UGROUP "FIFO_16" REGION "Region_E&F_4" ; +UGROUP "Encoder_17" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_17_Channels/Encoder; +LOCATE UGROUP "Encoder_17" REGION "Region_E&F_4" ; +UGROUP "FIFO_17" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_17_Channels/FIFO; +LOCATE UGROUP "FIFO_17" REGION "Region_E&F_4" ; +UGROUP "Encoder_18" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_18_Channels/Encoder; +LOCATE UGROUP "Encoder_18" REGION "Region_E&F_5" ; +UGROUP "FIFO_18" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_18_Channels/FIFO; +LOCATE UGROUP "FIFO_18" REGION "Region_E&F_5" ; +UGROUP "Encoder_19" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_19_Channels/Encoder; +LOCATE UGROUP "Encoder_19" REGION "Region_E&F_5" ; +UGROUP "FIFO_19" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_19_Channels/FIFO; +LOCATE UGROUP "FIFO_19" REGION "Region_E&F_5" ; +UGROUP "Encoder_20" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_20_Channels/Encoder; +LOCATE UGROUP "Encoder_20" REGION "Region_E&F_6" ; +UGROUP "FIFO_20" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_20_Channels/FIFO; +LOCATE UGROUP "FIFO_20" REGION "Region_E&F_6" ; +UGROUP "Encoder_21" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_21_Channels/Encoder; +LOCATE UGROUP "Encoder_21" REGION "Region_E&F_6" ; +UGROUP "FIFO_21" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_21_Channels/FIFO; +LOCATE UGROUP "FIFO_21" REGION "Region_E&F_6" ; +UGROUP "Encoder_22" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_22_Channels/Encoder; +LOCATE UGROUP "Encoder_22" REGION "Region_E&F_6" ; +UGROUP "FIFO_22" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_22_Channels/FIFO; +LOCATE UGROUP "FIFO_22" REGION "Region_E&F_6" ; +UGROUP "Encoder_23" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_23_Channels/Encoder; +LOCATE UGROUP "Encoder_23" REGION "Region_E&F_6" ; +UGROUP "FIFO_23" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_23_Channels/FIFO; +LOCATE UGROUP "FIFO_23" REGION "Region_E&F_6" ; +UGROUP "Encoder_24" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_24_Channels/Encoder; +LOCATE UGROUP "Encoder_24" REGION "Region_E&F_7" ; +UGROUP "FIFO_24" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_24_Channels/FIFO; +LOCATE UGROUP "FIFO_24" REGION "Region_E&F_7" ; +UGROUP "Encoder_25" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_25_Channels/Encoder; +LOCATE UGROUP "Encoder_25" REGION "Region_E&F_7" ; +UGROUP "FIFO_25" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_25_Channels/FIFO; +LOCATE UGROUP "FIFO_25" REGION "Region_E&F_7" ; +UGROUP "Encoder_26" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_26_Channels/Encoder; +LOCATE UGROUP "Encoder_26" REGION "Region_E&F_8" ; +UGROUP "FIFO_26" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_26_Channels/FIFO; +LOCATE UGROUP "FIFO_26" REGION "Region_E&F_8" ; +UGROUP "Encoder_27" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_27_Channels/Encoder; +LOCATE UGROUP "Encoder_27" REGION "Region_E&F_8" ; +UGROUP "FIFO_27" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_27_Channels/FIFO; +LOCATE UGROUP "FIFO_27" REGION "Region_E&F_8" ; +UGROUP "Encoder_28" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_28_Channels/Encoder; +LOCATE UGROUP "Encoder_28" REGION "Region_E&F_8" ; +UGROUP "FIFO_28" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_28_Channels/FIFO; +LOCATE UGROUP "FIFO_28" REGION "Region_E&F_8" ; +UGROUP "Encoder_29" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_29_Channels/Encoder; +LOCATE UGROUP "Encoder_29" REGION "Region_E&F_8" ; +UGROUP "FIFO_29" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_29_Channels/FIFO; +LOCATE UGROUP "FIFO_29" REGION "Region_E&F_8" ; +UGROUP "Encoder_30" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_30_Channels/Encoder; +LOCATE UGROUP "Encoder_30" REGION "Region_E&F_9" ; +UGROUP "FIFO_30" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_30_Channels/FIFO; +LOCATE UGROUP "FIFO_30" REGION "Region_E&F_9" ; +UGROUP "Encoder_31" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_31_Channels/Encoder; +LOCATE UGROUP "Encoder_31" REGION "Region_E&F_9" ; +UGROUP "FIFO_31" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_31_Channels/FIFO; +LOCATE UGROUP "FIFO_31" REGION "Region_E&F_9" ; +UGROUP "Encoder_32" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_32_Channels/Encoder; +LOCATE UGROUP "Encoder_32" REGION "Region_E&F_9" ; +UGROUP "FIFO_32" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_32_Channels/FIFO; +LOCATE UGROUP "FIFO_32" REGION "Region_E&F_9" ; +UGROUP "Encoder_33" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_33_Channels/Encoder; +LOCATE UGROUP "Encoder_33" REGION "Region_E&F_9" ; +UGROUP "FIFO_33" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_33_Channels/FIFO; +LOCATE UGROUP "FIFO_33" REGION "Region_E&F_9" ; +UGROUP "Encoder_34" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_34_Channels/Encoder; +LOCATE UGROUP "Encoder_34" REGION "Region_E&F_10" ; +UGROUP "FIFO_34" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_34_Channels/FIFO; +LOCATE UGROUP "FIFO_34" REGION "Region_E&F_10" ; +UGROUP "Encoder_35" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_35_Channels/Encoder; +LOCATE UGROUP "Encoder_35" REGION "Region_E&F_10" ; +UGROUP "FIFO_35" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_35_Channels/FIFO; +LOCATE UGROUP "FIFO_35" REGION "Region_E&F_10" ; +UGROUP "Encoder_36" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_36_Channels/Encoder; +LOCATE UGROUP "Encoder_36" REGION "Region_E&F_10" ; +UGROUP "FIFO_36" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_36_Channels/FIFO; +LOCATE UGROUP "FIFO_36" REGION "Region_E&F_10" ; +UGROUP "Encoder_37" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_37_Channels/Encoder; +LOCATE UGROUP "Encoder_37" REGION "Region_E&F_10" ; +UGROUP "FIFO_37" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_37_Channels/FIFO; +LOCATE UGROUP "FIFO_37" REGION "Region_E&F_10" ; +UGROUP "Encoder_38" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_38_Channels/Encoder; +LOCATE UGROUP "Encoder_38" REGION "Region_E&F_11" ; +UGROUP "FIFO_38" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_38_Channels/FIFO; +LOCATE UGROUP "FIFO_38" REGION "Region_E&F_11" ; +UGROUP "Encoder_39" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_39_Channels/Encoder; +LOCATE UGROUP "Encoder_39" REGION "Region_E&F_11" ; +UGROUP "FIFO_39" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_39_Channels/FIFO; +LOCATE UGROUP "FIFO_39" REGION "Region_E&F_11" ; +UGROUP "Encoder_40" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_40_Channels/Encoder; +LOCATE UGROUP "Encoder_40" REGION "Region_E&F_11" ; +UGROUP "FIFO_40" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_40_Channels/FIFO; +LOCATE UGROUP "FIFO_40" REGION "Region_E&F_11" ; +UGROUP "Encoder_41" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_41_Channels/Encoder; +LOCATE UGROUP "Encoder_41" REGION "Region_E&F_11" ; +UGROUP "FIFO_41" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_41_Channels/FIFO; +LOCATE UGROUP "FIFO_41" REGION "Region_E&F_11" ; +UGROUP "Encoder_42" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_42_Channels/Encoder; +LOCATE UGROUP "Encoder_42" REGION "Region_E&F_12" ; +UGROUP "FIFO_42" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_42_Channels/FIFO; +LOCATE UGROUP "FIFO_42" REGION "Region_E&F_12" ; +UGROUP "Encoder_43" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_43_Channels/Encoder; +LOCATE UGROUP "Encoder_43" REGION "Region_E&F_12" ; +UGROUP "FIFO_43" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_43_Channels/FIFO; +LOCATE UGROUP "FIFO_43" REGION "Region_E&F_12" ; +UGROUP "Encoder_44" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_44_Channels/Encoder; +LOCATE UGROUP "Encoder_44" REGION "Region_E&F_13" ; +UGROUP "FIFO_44" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_44_Channels/FIFO; +LOCATE UGROUP "FIFO_44" REGION "Region_E&F_13" ; +UGROUP "Encoder_45" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_45_Channels/Encoder; +LOCATE UGROUP "Encoder_45" REGION "Region_E&F_13" ; +UGROUP "FIFO_45" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_45_Channels/FIFO; +LOCATE UGROUP "FIFO_45" REGION "Region_E&F_13" ; +UGROUP "Encoder_46" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_46_Channels/Encoder; +LOCATE UGROUP "Encoder_46" REGION "Region_E&F_13" ; +UGROUP "FIFO_46" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_46_Channels/FIFO; +LOCATE UGROUP "FIFO_46" REGION "Region_E&F_13" ; +UGROUP "Encoder_47" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_47_Channels/Encoder; +LOCATE UGROUP "Encoder_47" REGION "Region_E&F_13" ; +UGROUP "FIFO_47" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_47_Channels/FIFO; +LOCATE UGROUP "FIFO_47" REGION "Region_E&F_13" ; +UGROUP "Encoder_48" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_48_Channels/Encoder; +LOCATE UGROUP "Encoder_48" REGION "Region_E&F_14" ; +UGROUP "FIFO_48" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_48_Channels/FIFO; +LOCATE UGROUP "FIFO_48" REGION "Region_E&F_14" ; +UGROUP "Encoder_49" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_49_Channels/Encoder; +LOCATE UGROUP "Encoder_49" REGION "Region_E&F_14" ; +UGROUP "FIFO_49" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_49_Channels/FIFO; +LOCATE UGROUP "FIFO_49" REGION "Region_E&F_14" ; +UGROUP "Encoder_50" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_50_Channels/Encoder; +LOCATE UGROUP "Encoder_50" REGION "Region_E&F_14" ; +UGROUP "FIFO_50" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_50_Channels/FIFO; +LOCATE UGROUP "FIFO_50" REGION "Region_E&F_14" ; +UGROUP "Encoder_51" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_51_Channels/Encoder; +LOCATE UGROUP "Encoder_51" REGION "Region_E&F_14" ; +UGROUP "FIFO_51" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_51_Channels/FIFO; +LOCATE UGROUP "FIFO_51" REGION "Region_E&F_14" ; +UGROUP "Encoder_52" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_52_Channels/Encoder; +LOCATE UGROUP "Encoder_52" REGION "Region_E&F_15" ; +UGROUP "FIFO_52" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_52_Channels/FIFO; +LOCATE UGROUP "FIFO_52" REGION "Region_E&F_15" ; +UGROUP "Encoder_53" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_53_Channels/Encoder; +LOCATE UGROUP "Encoder_53" REGION "Region_E&F_15" ; +UGROUP "FIFO_53" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_53_Channels/FIFO; +LOCATE UGROUP "FIFO_53" REGION "Region_E&F_15" ; +UGROUP "Encoder_54" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_54_Channels/Encoder; +LOCATE UGROUP "Encoder_54" REGION "Region_E&F_16" ; +UGROUP "FIFO_54" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_54_Channels/FIFO; +LOCATE UGROUP "FIFO_54" REGION "Region_E&F_16" ; +UGROUP "Encoder_55" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_55_Channels/Encoder; +LOCATE UGROUP "Encoder_55" REGION "Region_E&F_16" ; +UGROUP "FIFO_55" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_55_Channels/FIFO; +LOCATE UGROUP "FIFO_55" REGION "Region_E&F_16" ; +UGROUP "Encoder_56" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_56_Channels/Encoder; +LOCATE UGROUP "Encoder_56" REGION "Region_E&F_16" ; +UGROUP "FIFO_56" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_56_Channels/FIFO; +LOCATE UGROUP "FIFO_56" REGION "Region_E&F_16" ; +UGROUP "Encoder_57" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_57_Channels/Encoder; +LOCATE UGROUP "Encoder_57" REGION "Region_E&F_16" ; +UGROUP "FIFO_57" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_57_Channels/FIFO; +LOCATE UGROUP "FIFO_57" REGION "Region_E&F_16" ; +UGROUP "Encoder_58" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_58_Channels/Encoder; +LOCATE UGROUP "Encoder_58" REGION "Region_E&F_17" ; +UGROUP "FIFO_58" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_58_Channels/FIFO; +LOCATE UGROUP "FIFO_58" REGION "Region_E&F_17" ; +UGROUP "Encoder_59" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_59_Channels/Encoder; +LOCATE UGROUP "Encoder_59" REGION "Region_E&F_17" ; +UGROUP "FIFO_59" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_59_Channels/FIFO; +LOCATE UGROUP "FIFO_59" REGION "Region_E&F_17" ; +UGROUP "Encoder_60" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_60_Channels/Encoder; +LOCATE UGROUP "Encoder_60" REGION "Region_E&F_17" ; +UGROUP "FIFO_60" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_60_Channels/FIFO; +LOCATE UGROUP "FIFO_60" REGION "Region_E&F_17" ; +UGROUP "Encoder_61" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_61_Channels/Encoder; +LOCATE UGROUP "Encoder_61" REGION "Region_E&F_17" ; +UGROUP "FIFO_61" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_61_Channels/FIFO; +LOCATE UGROUP "FIFO_61" REGION "Region_E&F_17" ; +UGROUP "Encoder_62" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_62_Channels/Encoder; +LOCATE UGROUP "Encoder_62" REGION "Region_E&F_18" ; +UGROUP "FIFO_62" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_62_Channels/FIFO; +LOCATE UGROUP "FIFO_62" REGION "Region_E&F_18" ; +UGROUP "Encoder_63" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_63_Channels/Encoder; +LOCATE UGROUP "Encoder_63" REGION "Region_E&F_18" ; +UGROUP "FIFO_63" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_63_Channels/FIFO; +LOCATE UGROUP "FIFO_63" REGION "Region_E&F_18" ; +UGROUP "Encoder_64" BBOX 2 28 + BLKNAME THE_TDC/GEN_Channels_64_Channels/Encoder; +LOCATE UGROUP "Encoder_64" REGION "Region_E&F_18" ; +UGROUP "FIFO_64" BBOX 2 14 + BLKNAME THE_TDC/GEN_Channels_64_Channels/FIFO; +LOCATE UGROUP "FIFO_64" REGION "Region_E&F_18" ; + + +############################################################################## +## FF ARRAY ENABLE PLACEMENT ## +############################################################################## +UGROUP "ff_en_0" BBOX 1 1 + BLKNAME THE_TDC/The_Reference_Time/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_0" SITE "R113C27D" ; +UGROUP "ff_en_1" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_1_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_1" SITE "R111C27D" ; +UGROUP "ff_en_2" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_2_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_2" SITE "R104C27D" ; +UGROUP "ff_en_3" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_3_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_3" SITE "R102C27D" ; +UGROUP "ff_en_4" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_4_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_4" SITE "R91C27D" ; +UGROUP "ff_en_5" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_5_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_5" SITE "R89C27D" ; +UGROUP "ff_en_6" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_6_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_6" SITE "R86C27D" ; +UGROUP "ff_en_7" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_7_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_7" SITE "R84C27D" ; +UGROUP "ff_en_8" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_8_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_8" SITE "R73C27D" ; +UGROUP "ff_en_9" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_9_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_9" SITE "R71C27D" ; + + +UGROUP "ff_en_10" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_10_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_10" SITE "R68C27D" ; +UGROUP "ff_en_11" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_11_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_11" SITE "R66C27D" ; +UGROUP "ff_en_12" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_12_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_12" SITE "R55C27D" ; +UGROUP "ff_en_13" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_13_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_13" SITE "R53C27D" ; +UGROUP "ff_en_14" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_14_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_14" SITE "R50C27D" ; +UGROUP "ff_en_15" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_15_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_15" SITE "R48C27D" ; +UGROUP "ff_en_16" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_16_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_16" SITE "R37C27D" ; +UGROUP "ff_en_17" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_17_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_17" SITE "R35C27D" ; +UGROUP "ff_en_18" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_18_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_18" SITE "R32C27D" ; +UGROUP "ff_en_19" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_19_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_19" SITE "R30C27D" ; + + +UGROUP "ff_en_20" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_20_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_20" SITE "R23C27D" ; +UGROUP "ff_en_21" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_21_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_21" SITE "R21C27D" ; +UGROUP "ff_en_22" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_22_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_22" SITE "R10C27D" ; +UGROUP "ff_en_23" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_23_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_23" SITE "R8C27D" ; +UGROUP "ff_en_24" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_24_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_24" SITE "R113C150D" ; +UGROUP "ff_en_25" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_25_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_25" SITE "R111C150D" ; +UGROUP "ff_en_26" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_26_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_26" SITE "R104C150D" ; +UGROUP "ff_en_27" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_27_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_27" SITE "R102C150D" ; +UGROUP "ff_en_28" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_28_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_28" SITE "R91C150D" ; +UGROUP "ff_en_29" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_29_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_29" SITE "R89C150D" ; + + +UGROUP "ff_en_30" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_30_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_30" SITE "R86C150D" ; +UGROUP "ff_en_31" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_31_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_31" SITE "R84C150D" ; +UGROUP "ff_en_32" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_32_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_32" SITE "R73C150D" ; +UGROUP "ff_en_33" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_33_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_33" SITE "R71C150D" ; +UGROUP "ff_en_34" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_34_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_34" SITE "R68C150D" ; +UGROUP "ff_en_35" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_35_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_35" SITE "R66C150D" ; +UGROUP "ff_en_36" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_36_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_36" SITE "R55C150D" ; +UGROUP "ff_en_37" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_37_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_37" SITE "R53C150D" ; +UGROUP "ff_en_38" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_38_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_38" SITE "R50C150D" ; +UGROUP "ff_en_39" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_39_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_39" SITE "R48C150D" ; + + +UGROUP "ff_en_40" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_40_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_40" SITE "R37C150D" ; +UGROUP "ff_en_41" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_41_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_41" SITE "R35C150D" ; +UGROUP "ff_en_42" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_42_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_42" SITE "R32C150D" ; +UGROUP "ff_en_43" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_43_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_43" SITE "R30C150D" ; +UGROUP "ff_en_44" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_44_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_44" SITE "R23C150D" ; +UGROUP "ff_en_45" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_45_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_45" SITE "R21C150D" ; +UGROUP "ff_en_46" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_46_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_46" SITE "R10C150D" ; +UGROUP "ff_en_47" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_47_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_47" SITE "R8C150D" ; +UGROUP "ff_en_48" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_48_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_48" SITE "R8C91D" ; +UGROUP "ff_en_49" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_49_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_49" SITE "R10C91D" ; + + +UGROUP "ff_en_50" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_50_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_50" SITE "R21C91D" ; +UGROUP "ff_en_51" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_51_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_51" SITE "R23C91D" ; +UGROUP "ff_en_52" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_52_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_52" SITE "R30C91D" ; +UGROUP "ff_en_53" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_53_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_53" SITE "R32C91D" ; +UGROUP "ff_en_54" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_54_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_54" SITE "R35C91D" ; +UGROUP "ff_en_55" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_55_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_55" SITE "R37C91D" ; +UGROUP "ff_en_56" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_56_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_56" SITE "R48C91D" ; +UGROUP "ff_en_57" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_57_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_57" SITE "R50C91D" ; +UGROUP "ff_en_58" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_58_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_58" SITE "R53C91D" ; +UGROUP "ff_en_59" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_59_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_59" SITE "R55C91D" ; + + +UGROUP "ff_en_60" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_60_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_60" SITE "R66C91D" ; +UGROUP "ff_en_61" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_61_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_61" SITE "R68C91D" ; +UGROUP "ff_en_62" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_62_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_62" SITE "R71C91D" ; +UGROUP "ff_en_63" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_63_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_63" SITE "R73C91D" ; +UGROUP "ff_en_64" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_64_Channels/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_64" SITE "R84C91D" ; + +############################################################################## + +MULTICYCLE TO CELL "THE_TDC/GEN_Channels_*_Channels/lost_hit_cntr_*" 3.000000 X ; +MULTICYCLE TO CELL "THE_TDC/GEN_Channels_*_Channels/hit_detect_cntr_*" 3.000000 X ; +MULTICYCLE TO CELL "THE_TDC/GEN_Channels_*_Channels/encoder_start_cntr_*" 3.000000 X ; +MULTICYCLE TO CELL "THE_TDC/GEN_Channels_*_Channels/fifo_wr_cntr_*" 3.000000 X ; + +MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" 3.000000 X ; +MULTICYCLE TO CELL "THE_TDC/GEN_Channels_*_Channels/hit_time_stamp_i_*" 2.000000 X ; +MULTICYCLE TO CELL "THE_TDC/The_Reference_Time/hit_time_stamp_i_*" 2.000000 X ; + +#MULTICYCLE TO CELL "THE_TDC_logic_analyser_regio_*" 2.000000 X ; + +#MAXDELAY NET "THE_TDC/The_Reference_Time/hit_buf" 0.700000 nS DATAPATH_ONLY ; +MAXDELAY NET "TRIGGER_LEFT_c_i" 0.700000 nS DATAPATH_ONLY ; +MAXDELAY NET "THE_TDC/GEN_Channels_*_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ; + -- 2.43.0