From c4f808feddcf8e950ad575d71f90f8a0ce789fd8 Mon Sep 17 00:00:00 2001 From: Cahit Date: Thu, 2 May 2013 10:41:24 +0200 Subject: [PATCH] intermediate commit -cu --- tdc_releases/tdc_v1.5/TDC.vhd | 19 ++++++++++++++++++- tdc_releases/tdc_v1.5/trb3_periph.vhd | 16 ++++++++-------- wasa/trb3_periph_padiwa.vhd | 4 ++-- 3 files changed, 28 insertions(+), 11 deletions(-) diff --git a/tdc_releases/tdc_v1.5/TDC.vhd b/tdc_releases/tdc_v1.5/TDC.vhd index b6295af..fef3f95 100644 --- a/tdc_releases/tdc_v1.5/TDC.vhd +++ b/tdc_releases/tdc_v1.5/TDC.vhd @@ -108,6 +108,9 @@ architecture TDC of TDC is signal logic_anal_data_i : std_logic_vector(3*32-1 downto 0); -- Hit signals signal hit_in_i : std_logic_vector(CHANNEL_NUMBER-1 downto 1); + signal hit_latch : std_logic_vector(CHANNEL_NUMBER-1 downto 1); + signal hit_reg : std_logic_vector(CHANNEL_NUMBER-1 downto 1); + signal hit_2reg : std_logic_vector(CHANNEL_NUMBER-1 downto 1); -- To the channels signal rd_en_i : std_logic_vector(CHANNEL_NUMBER-1 downto 0); signal trg_win_end_i : std_logic; @@ -160,6 +163,20 @@ begin -- Reset signal reset_tdc <= RESET; + -- Blocks the input after the rising edge against short pulses + GEN_HitBlock : for i in 1 to CHANNEL_NUMBER-1 generate + TheStretcher : process (HIT_IN, hit_2reg) + begin + if hit_2reg(i) = '1' then + hit_latch(i) <= '0'; + elsif rising_edge(HIT_IN(i)) then + hit_latch(i) <= '1'; + end if; + end process TheStretcher; + end generate GEN_HitBlock; + hit_reg <= hit_latch when rising_edge(CLK_TDC); + hit_2reg <= hit_reg when rising_edge(CLK_TDC); + -- Channel and calibration enable signals GEN_Channel_Enable : for i in 1 to CHANNEL_NUMBER-1 generate process (ch_en_i, calibration_on, HIT_CALIBRATION, HIT_IN) @@ -168,7 +185,7 @@ begin if calibration_on = '1' then hit_in_i(i) <= HIT_CALIBRATION; else - hit_in_i(i) <= HIT_IN(i); + hit_in_i(i) <= hit_latch(i); --HIT_IN(i); end if; else hit_in_i(i) <= '0'; diff --git a/tdc_releases/tdc_v1.5/trb3_periph.vhd b/tdc_releases/tdc_v1.5/trb3_periph.vhd index d4baaaa..a36e0ac 100644 --- a/tdc_releases/tdc_v1.5/trb3_periph.vhd +++ b/tdc_releases/tdc_v1.5/trb3_periph.vhd @@ -357,7 +357,7 @@ begin BROADCAST_BITMASK => x"FF", BROADCAST_SPECIAL_ADDR => x"48", REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)), - REGIO_HARDWARE_VERSION => x"91000860", -- regio_hardware_version_i, + REGIO_HARDWARE_VERSION => x"91000060", -- regio_hardware_version_i, REGIO_INIT_ADDRESS => x"f305", REGIO_USE_VAR_ENDPOINT_ID => c_YES, CLOCK_FREQUENCY => 125, @@ -720,14 +720,14 @@ begin THE_TDC : TDC generic map ( - CHANNEL_NUMBER => 5, -- Number of TDC channels + CHANNEL_NUMBER => 65, -- Number of TDC channels CONTROL_REG_NR => 5) -- Number of control regs - higher than 8 check tdc_ctrl_addr port map ( RESET => reset_i, CLK_TDC => CLK_PCLK_LEFT, -- Clock used for the time measurement CLK_READOUT => clk_100_i, -- Clock for the readout REFERENCE_TIME => timing_trg_received_i, -- Reference time input - HIT_IN => hit_in_i(4 downto 1), -- Channel start signals + HIT_IN => hit_in_i(64 downto 1), -- Channel start signals HIT_CALIBRATION => clk_20_i, -- Hits for calibrating the TDC TRG_WIN_PRE => tdc_ctrl_reg(42 downto 32), -- Pre-Trigger window width TRG_WIN_POST => tdc_ctrl_reg(58 downto 48), -- Post-Trigger window width @@ -794,13 +794,13 @@ begin CONTROL_REG_IN => tdc_ctrl_reg); -- For single edge measurements - -- hit_in_i <= INP; + hit_in_i <= INP; -- For ToT Measurements - Gen_Hit_In_Signals : for i in 1 to 32 generate - hit_in_i(i*2-1) <= INP(i-1); - hit_in_i(i*2) <= not INP(i-1); - end generate Gen_Hit_In_Signals; + --Gen_Hit_In_Signals : for i in 1 to 32 generate + -- hit_in_i(i*2-1) <= INP(i-1); + -- hit_in_i(i*2) <= not INP(i-1); + --end generate Gen_Hit_In_Signals; -- !!!!! IMPORTANT !!!!! Don't forget to set the REGIO_HARDWARE_VERSION !!!!! end architecture; diff --git a/wasa/trb3_periph_padiwa.vhd b/wasa/trb3_periph_padiwa.vhd index ea5649d..b6b8b50 100644 --- a/wasa/trb3_periph_padiwa.vhd +++ b/wasa/trb3_periph_padiwa.vhd @@ -408,7 +408,7 @@ begin BROADCAST_BITMASK => x"FF", BROADCAST_SPECIAL_ADDR => x"48", REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)), - REGIO_HARDWARE_VERSION => x"91004860", + REGIO_HARDWARE_VERSION => x"91004060", REGIO_INIT_ADDRESS => x"f306", REGIO_USE_VAR_ENDPOINT_ID => c_YES, CLOCK_FREQUENCY => 100, @@ -860,7 +860,7 @@ begin -- For single edge measurements - -- hit_in_i <= INP; + --hit_in_i <= INP; -- For ToT Measurements Gen_Hit_In_Signals : for i in 1 to 32 generate -- 2.43.0