From c5045999dd33d7a6abd869c88ac11c81f47e8a52 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Wed, 16 Feb 2011 08:32:49 +0000 Subject: [PATCH] *** empty log message *** --- design/cores/fifo_32to64x512_dualclock.ipx | 9 + design/cores/fifo_32to64x512_dualclock.lpc | 48 + design/cores/fifo_32to64x512_dualclock.vhd | 226 ++++ design/cores/fifo_64x512_dualclock.ipx | 9 + design/cores/fifo_64x512_dualclock.lpc | 48 + design/cores/fifo_64x512_dualclock.vhd | 226 ++++ design/cores/fifo_8x512_dualclock.ipx | 9 + design/cores/fifo_8x512_dualclock.lpc | 48 + design/cores/fifo_8x512_dualclock.vhd | 181 +++ design/dma_adapter.vhd | 15 +- design/dma_core.vhd | 1214 +++++++++----------- design/pci_core.vhd | 189 +-- design/wb_tlc.vhd | 111 +- design/wb_tlc_cpld.vhd | 98 +- pcie_components.vhd | 387 ++++--- pexor.p2t | 2 +- pexor.prj | 70 +- pexor.vhd | 128 ++- size.txt | 20 +- 19 files changed, 1889 insertions(+), 1149 deletions(-) create mode 100644 design/cores/fifo_32to64x512_dualclock.ipx create mode 100644 design/cores/fifo_32to64x512_dualclock.lpc create mode 100644 design/cores/fifo_32to64x512_dualclock.vhd create mode 100644 design/cores/fifo_64x512_dualclock.ipx create mode 100644 design/cores/fifo_64x512_dualclock.lpc create mode 100644 design/cores/fifo_64x512_dualclock.vhd create mode 100644 design/cores/fifo_8x512_dualclock.ipx create mode 100644 design/cores/fifo_8x512_dualclock.lpc create mode 100644 design/cores/fifo_8x512_dualclock.vhd diff --git a/design/cores/fifo_32to64x512_dualclock.ipx b/design/cores/fifo_32to64x512_dualclock.ipx new file mode 100644 index 0000000..f7abf7c --- /dev/null +++ b/design/cores/fifo_32to64x512_dualclock.ipx @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/design/cores/fifo_32to64x512_dualclock.lpc b/design/cores/fifo_32to64x512_dualclock.lpc new file mode 100644 index 0000000..78be3b0 --- /dev/null +++ b/design/cores/fifo_32to64x512_dualclock.lpc @@ -0,0 +1,48 @@ +[Device] +Family=latticescm +PartType=LFSCM3GA40EP1 +PartName=LFSCM3GA40EP1-7FF1152C +SpeedGrade=7 +Package=FFBGA1152 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.4 +ModuleName=fifo_32to64x512_dualclock +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=02/03/2011 +Time=10:32:26 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Only +RDepth=512 +RWidth=72 +WDepth=1024 +WWidth=36 +regout=0 +CtrlByRdEn=0 +EmpFlg=1 +PeMode=Static - Single Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=1 +PfMode=Static - Single Threshold +PfAssert=940 +PfDeassert=506 +Reset=Async +RDataCount=0 +WDataCount=0 +EnECC=0 diff --git a/design/cores/fifo_32to64x512_dualclock.vhd b/design/cores/fifo_32to64x512_dualclock.vhd new file mode 100644 index 0000000..fd24d10 --- /dev/null +++ b/design/cores/fifo_32to64x512_dualclock.vhd @@ -0,0 +1,226 @@ +-- VHDL netlist generated by SCUBA Diamond_1.1_Production (517) +-- Module Version: 5.4 +--/d/sugar/lattice/diamond/1.1/ispfpga/bin/lin/scuba -w -n fifo_32to64x512_dualclock -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 1024 -width 36 -rwidth 72 -no_enable -pe 10 -pf 940 -e + +-- Thu Feb 3 10:32:26 2011 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library SCM; +use SCM.COMPONENTS.all; +-- synopsys translate_on + +entity fifo_32to64x512_dualclock is + port ( + Data: in std_logic_vector(35 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(71 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostEmpty: out std_logic; + AlmostFull: out std_logic); +end fifo_32to64x512_dualclock; + +architecture Structure of fifo_32to64x512_dualclock is + + -- internal signal declarations + signal scuba_vhi: std_logic; + signal Empty_int: std_logic; + signal Full_int: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component FIFO16KA + -- synopsys translate_off + generic (FULLPOINTER1 : in std_logic_vector(14 downto 0); + FULLPOINTER : in std_logic_vector(14 downto 0); + AFPOINTER1 : in std_logic_vector(14 downto 0); + AEPOINTER1 : in std_logic_vector(14 downto 0); + AFPOINTER : in std_logic_vector(14 downto 0); + AEPOINTER : in std_logic_vector(14 downto 0); + CSDECODE_R : in std_logic_vector(1 downto 0); + CSDECODE_W : in std_logic_vector(1 downto 0); + RESETMODE : in String; REGMODE : in String; + DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer); + -- synopsys translate_on + port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; + DI3: in std_logic; DI4: in std_logic; DI5: in std_logic; + DI6: in std_logic; DI7: in std_logic; DI8: in std_logic; + DI9: in std_logic; DI10: in std_logic; DI11: in std_logic; + DI12: in std_logic; DI13: in std_logic; + DI14: in std_logic; DI15: in std_logic; + DI16: in std_logic; DI17: in std_logic; + DI18: in std_logic; DI19: in std_logic; + DI20: in std_logic; DI21: in std_logic; + DI22: in std_logic; DI23: in std_logic; + DI24: in std_logic; DI25: in std_logic; + DI26: in std_logic; DI27: in std_logic; + DI28: in std_logic; DI29: in std_logic; + DI30: in std_logic; DI31: in std_logic; + DI32: in std_logic; DI33: in std_logic; + DI34: in std_logic; DI35: in std_logic; + FULLI: in std_logic; CSW0: in std_logic; + CSW1: in std_logic; EMPTYI: in std_logic; + CSR0: in std_logic; CSR1: in std_logic; WE: in std_logic; + RE: in std_logic; CLKW: in std_logic; CLKR: in std_logic; + RST: in std_logic; RPRST: in std_logic; + DO0: out std_logic; DO1: out std_logic; + DO2: out std_logic; DO3: out std_logic; + DO4: out std_logic; DO5: out std_logic; + DO6: out std_logic; DO7: out std_logic; + DO8: out std_logic; DO9: out std_logic; + DO10: out std_logic; DO11: out std_logic; + DO12: out std_logic; DO13: out std_logic; + DO14: out std_logic; DO15: out std_logic; + DO16: out std_logic; DO17: out std_logic; + DO18: out std_logic; DO19: out std_logic; + DO20: out std_logic; DO21: out std_logic; + DO22: out std_logic; DO23: out std_logic; + DO24: out std_logic; DO25: out std_logic; + DO26: out std_logic; DO27: out std_logic; + DO28: out std_logic; DO29: out std_logic; + DO30: out std_logic; DO31: out std_logic; + DO32: out std_logic; DO33: out std_logic; + DO34: out std_logic; DO35: out std_logic; + EF: out std_logic; AEF: out std_logic; AFF: out std_logic; + FF: out std_logic); + end component; + attribute FULLPOINTER1 : string; + attribute FULLPOINTER : string; + attribute AFPOINTER1 : string; + attribute AFPOINTER : string; + attribute AEPOINTER1 : string; + attribute AEPOINTER : string; + attribute RESETMODE : string; + attribute REGMODE : string; + attribute CSDECODE_R : string; + attribute CSDECODE_W : string; + attribute DATA_WIDTH_R : string; + attribute DATA_WIDTH_W : string; + attribute FULLPOINTER1 of fifo_32to64x512_dualclock_0_1 : label is "0b011111111100001"; + attribute FULLPOINTER of fifo_32to64x512_dualclock_0_1 : label is "0b011111111110001"; + attribute AFPOINTER1 of fifo_32to64x512_dualclock_0_1 : label is "0b011101010100001"; + attribute AFPOINTER of fifo_32to64x512_dualclock_0_1 : label is "0b011101010110001"; + attribute AEPOINTER1 of fifo_32to64x512_dualclock_0_1 : label is "0b000000101111111"; + attribute AEPOINTER of fifo_32to64x512_dualclock_0_1 : label is "0b000000101011111"; + attribute RESETMODE of fifo_32to64x512_dualclock_0_1 : label is "ASYNC"; + attribute REGMODE of fifo_32to64x512_dualclock_0_1 : label is "NOREG"; + attribute CSDECODE_R of fifo_32to64x512_dualclock_0_1 : label is "0b11"; + attribute CSDECODE_W of fifo_32to64x512_dualclock_0_1 : label is "0b11"; + attribute DATA_WIDTH_R of fifo_32to64x512_dualclock_0_1 : label is "36"; + attribute DATA_WIDTH_W of fifo_32to64x512_dualclock_0_1 : label is "18"; + attribute FULLPOINTER1 of fifo_32to64x512_dualclock_1_0 : label is "0b000000000000000"; + attribute FULLPOINTER of fifo_32to64x512_dualclock_1_0 : label is "0b111111111111111"; + attribute AFPOINTER1 of fifo_32to64x512_dualclock_1_0 : label is "0b000000000000000"; + attribute AFPOINTER of fifo_32to64x512_dualclock_1_0 : label is "0b111111111111111"; + attribute AEPOINTER1 of fifo_32to64x512_dualclock_1_0 : label is "0b000000000000000"; + attribute AEPOINTER of fifo_32to64x512_dualclock_1_0 : label is "0b111111111111111"; + attribute RESETMODE of fifo_32to64x512_dualclock_1_0 : label is "ASYNC"; + attribute REGMODE of fifo_32to64x512_dualclock_1_0 : label is "NOREG"; + attribute CSDECODE_R of fifo_32to64x512_dualclock_1_0 : label is "0b11"; + attribute CSDECODE_W of fifo_32to64x512_dualclock_1_0 : label is "0b11"; + attribute DATA_WIDTH_R of fifo_32to64x512_dualclock_1_0 : label is "36"; + attribute DATA_WIDTH_W of fifo_32to64x512_dualclock_1_0 : label is "18"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + fifo_32to64x512_dualclock_0_1: FIFO16KA + -- synopsys translate_off + generic map (FULLPOINTER1=> "011111111100001", FULLPOINTER=> "011111111110001", + AFPOINTER1=> "011101010100001", AFPOINTER=> "011101010110001", + AEPOINTER1=> "000000101111111", AEPOINTER=> "000000101011111", + RESETMODE=> "ASYNC", REGMODE=> "NOREG", CSDECODE_R=> "11", + CSDECODE_W=> "11", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 18) + -- synopsys translate_on + port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), + DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), + DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), + DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), + DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), + DI18=>scuba_vlo, DI19=>scuba_vlo, DI20=>scuba_vlo, + DI21=>scuba_vlo, DI22=>scuba_vlo, DI23=>scuba_vlo, + DI24=>scuba_vlo, DI25=>scuba_vlo, DI26=>scuba_vlo, + DI27=>scuba_vlo, DI28=>scuba_vlo, DI29=>scuba_vlo, + DI30=>scuba_vlo, DI31=>scuba_vlo, DI32=>scuba_vlo, + DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo, + FULLI=>Full_int, CSW0=>scuba_vhi, CSW1=>scuba_vhi, + EMPTYI=>Empty_int, CSR0=>scuba_vhi, CSR1=>scuba_vhi, + WE=>WrEn, RE=>RdEn, CLKW=>WrClock, CLKR=>RdClock, RST=>Reset, + RPRST=>RPReset, DO0=>Q(36), DO1=>Q(37), DO2=>Q(38), + DO3=>Q(39), DO4=>Q(40), DO5=>Q(41), DO6=>Q(42), DO7=>Q(43), + DO8=>Q(44), DO9=>Q(45), DO10=>Q(46), DO11=>Q(47), + DO12=>Q(48), DO13=>Q(49), DO14=>Q(50), DO15=>Q(51), + DO16=>Q(52), DO17=>Q(53), DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), + DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), + DO26=>Q(8), DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), + DO30=>Q(12), DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), + DO34=>Q(16), DO35=>Q(17), EF=>Empty_int, AEF=>AlmostEmpty, + AFF=>AlmostFull, FF=>Full_int); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + fifo_32to64x512_dualclock_1_0: FIFO16KA + -- synopsys translate_off + generic map (FULLPOINTER1=> "000000000000000", FULLPOINTER=> "111111111111111", + AFPOINTER1=> "000000000000000", AFPOINTER=> "111111111111111", + AEPOINTER1=> "000000000000000", AEPOINTER=> "111111111111111", + RESETMODE=> "ASYNC", REGMODE=> "NOREG", CSDECODE_R=> "11", + CSDECODE_W=> "11", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 18) + -- synopsys translate_on + port map (DI0=>Data(18), DI1=>Data(19), DI2=>Data(20), + DI3=>Data(21), DI4=>Data(22), DI5=>Data(23), DI6=>Data(24), + DI7=>Data(25), DI8=>Data(26), DI9=>Data(27), DI10=>Data(28), + DI11=>Data(29), DI12=>Data(30), DI13=>Data(31), + DI14=>Data(32), DI15=>Data(33), DI16=>Data(34), + DI17=>Data(35), DI18=>scuba_vlo, DI19=>scuba_vlo, + DI20=>scuba_vlo, DI21=>scuba_vlo, DI22=>scuba_vlo, + DI23=>scuba_vlo, DI24=>scuba_vlo, DI25=>scuba_vlo, + DI26=>scuba_vlo, DI27=>scuba_vlo, DI28=>scuba_vlo, + DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo, + DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo, + DI35=>scuba_vlo, FULLI=>Full_int, CSW0=>scuba_vhi, + CSW1=>scuba_vhi, EMPTYI=>Empty_int, CSR0=>scuba_vhi, + CSR1=>scuba_vhi, WE=>WrEn, RE=>RdEn, CLKW=>WrClock, + CLKR=>RdClock, RST=>Reset, RPRST=>RPReset, DO0=>Q(54), + DO1=>Q(55), DO2=>Q(56), DO3=>Q(57), DO4=>Q(58), DO5=>Q(59), + DO6=>Q(60), DO7=>Q(61), DO8=>Q(62), DO9=>Q(63), DO10=>Q(64), + DO11=>Q(65), DO12=>Q(66), DO13=>Q(67), DO14=>Q(68), + DO15=>Q(69), DO16=>Q(70), DO17=>Q(71), DO18=>Q(18), + DO19=>Q(19), DO20=>Q(20), DO21=>Q(21), DO22=>Q(22), + DO23=>Q(23), DO24=>Q(24), DO25=>Q(25), DO26=>Q(26), + DO27=>Q(27), DO28=>Q(28), DO29=>Q(29), DO30=>Q(30), + DO31=>Q(31), DO32=>Q(32), DO33=>Q(33), DO34=>Q(34), + DO35=>Q(35), EF=>open, AEF=>open, AFF=>open, FF=>open); + + Empty <= Empty_int; + Full <= Full_int; +end Structure; + +-- synopsys translate_off +library SCM; +configuration Structure_CON of fifo_32to64x512_dualclock is + for Structure + for all:VHI use entity SCM.VHI(V); end for; + for all:VLO use entity SCM.VLO(V); end for; + for all:FIFO16KA use entity SCM.FIFO16KA(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/design/cores/fifo_64x512_dualclock.ipx b/design/cores/fifo_64x512_dualclock.ipx new file mode 100644 index 0000000..0ae6510 --- /dev/null +++ b/design/cores/fifo_64x512_dualclock.ipx @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/design/cores/fifo_64x512_dualclock.lpc b/design/cores/fifo_64x512_dualclock.lpc new file mode 100644 index 0000000..fbc4515 --- /dev/null +++ b/design/cores/fifo_64x512_dualclock.lpc @@ -0,0 +1,48 @@ +[Device] +Family=latticescm +PartType=LFSCM3GA40EP1 +PartName=LFSCM3GA40EP1-7FF1152C +SpeedGrade=7 +Package=FFBGA1152 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.4 +ModuleName=fifo_64x512_dualclock +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=02/03/2011 +Time=09:57:06 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Only +RDepth=512 +RWidth=72 +WDepth=512 +WWidth=72 +regout=0 +CtrlByRdEn=0 +EmpFlg=1 +PeMode=Static - Single Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=1 +PfMode=Static - Single Threshold +PfAssert=464 +PfDeassert=506 +Reset=Async +RDataCount=0 +WDataCount=0 +EnECC=0 diff --git a/design/cores/fifo_64x512_dualclock.vhd b/design/cores/fifo_64x512_dualclock.vhd new file mode 100644 index 0000000..d58c338 --- /dev/null +++ b/design/cores/fifo_64x512_dualclock.vhd @@ -0,0 +1,226 @@ +-- VHDL netlist generated by SCUBA Diamond_1.1_Production (517) +-- Module Version: 5.4 +--/d/sugar/lattice/diamond/1.1/ispfpga/bin/lin/scuba -w -n fifo_64x512_dualclock -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 512 -width 72 -rwidth 72 -no_enable -pe 10 -pf 464 -e + +-- Thu Feb 3 09:57:06 2011 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library SCM; +use SCM.COMPONENTS.all; +-- synopsys translate_on + +entity fifo_64x512_dualclock is + port ( + Data: in std_logic_vector(71 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(71 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostEmpty: out std_logic; + AlmostFull: out std_logic); +end fifo_64x512_dualclock; + +architecture Structure of fifo_64x512_dualclock is + + -- internal signal declarations + signal scuba_vlo: std_logic; + signal scuba_vhi: std_logic; + signal Empty_int: std_logic; + signal Full_int: std_logic; + + -- local component declarations + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component FIFO16KA + -- synopsys translate_off + generic (FULLPOINTER1 : in std_logic_vector(14 downto 0); + FULLPOINTER : in std_logic_vector(14 downto 0); + AFPOINTER1 : in std_logic_vector(14 downto 0); + AEPOINTER1 : in std_logic_vector(14 downto 0); + AFPOINTER : in std_logic_vector(14 downto 0); + AEPOINTER : in std_logic_vector(14 downto 0); + CSDECODE_R : in std_logic_vector(1 downto 0); + CSDECODE_W : in std_logic_vector(1 downto 0); + RESETMODE : in String; REGMODE : in String; + DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer); + -- synopsys translate_on + port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; + DI3: in std_logic; DI4: in std_logic; DI5: in std_logic; + DI6: in std_logic; DI7: in std_logic; DI8: in std_logic; + DI9: in std_logic; DI10: in std_logic; DI11: in std_logic; + DI12: in std_logic; DI13: in std_logic; + DI14: in std_logic; DI15: in std_logic; + DI16: in std_logic; DI17: in std_logic; + DI18: in std_logic; DI19: in std_logic; + DI20: in std_logic; DI21: in std_logic; + DI22: in std_logic; DI23: in std_logic; + DI24: in std_logic; DI25: in std_logic; + DI26: in std_logic; DI27: in std_logic; + DI28: in std_logic; DI29: in std_logic; + DI30: in std_logic; DI31: in std_logic; + DI32: in std_logic; DI33: in std_logic; + DI34: in std_logic; DI35: in std_logic; + FULLI: in std_logic; CSW0: in std_logic; + CSW1: in std_logic; EMPTYI: in std_logic; + CSR0: in std_logic; CSR1: in std_logic; WE: in std_logic; + RE: in std_logic; CLKW: in std_logic; CLKR: in std_logic; + RST: in std_logic; RPRST: in std_logic; + DO0: out std_logic; DO1: out std_logic; + DO2: out std_logic; DO3: out std_logic; + DO4: out std_logic; DO5: out std_logic; + DO6: out std_logic; DO7: out std_logic; + DO8: out std_logic; DO9: out std_logic; + DO10: out std_logic; DO11: out std_logic; + DO12: out std_logic; DO13: out std_logic; + DO14: out std_logic; DO15: out std_logic; + DO16: out std_logic; DO17: out std_logic; + DO18: out std_logic; DO19: out std_logic; + DO20: out std_logic; DO21: out std_logic; + DO22: out std_logic; DO23: out std_logic; + DO24: out std_logic; DO25: out std_logic; + DO26: out std_logic; DO27: out std_logic; + DO28: out std_logic; DO29: out std_logic; + DO30: out std_logic; DO31: out std_logic; + DO32: out std_logic; DO33: out std_logic; + DO34: out std_logic; DO35: out std_logic; + EF: out std_logic; AEF: out std_logic; AFF: out std_logic; + FF: out std_logic); + end component; + attribute FULLPOINTER1 : string; + attribute FULLPOINTER : string; + attribute AFPOINTER1 : string; + attribute AFPOINTER : string; + attribute AEPOINTER1 : string; + attribute AEPOINTER : string; + attribute RESETMODE : string; + attribute REGMODE : string; + attribute CSDECODE_R : string; + attribute CSDECODE_W : string; + attribute DATA_WIDTH_R : string; + attribute DATA_WIDTH_W : string; + attribute FULLPOINTER1 of fifo_64x512_dualclock_0_1 : label is "0b011111111000001"; + attribute FULLPOINTER of fifo_64x512_dualclock_0_1 : label is "0b011111111100001"; + attribute AFPOINTER1 of fifo_64x512_dualclock_0_1 : label is "0b011100111000001"; + attribute AFPOINTER of fifo_64x512_dualclock_0_1 : label is "0b011100111100001"; + attribute AEPOINTER1 of fifo_64x512_dualclock_0_1 : label is "0b000000101111111"; + attribute AEPOINTER of fifo_64x512_dualclock_0_1 : label is "0b000000101011111"; + attribute RESETMODE of fifo_64x512_dualclock_0_1 : label is "ASYNC"; + attribute REGMODE of fifo_64x512_dualclock_0_1 : label is "NOREG"; + attribute CSDECODE_R of fifo_64x512_dualclock_0_1 : label is "0b11"; + attribute CSDECODE_W of fifo_64x512_dualclock_0_1 : label is "0b11"; + attribute DATA_WIDTH_R of fifo_64x512_dualclock_0_1 : label is "36"; + attribute DATA_WIDTH_W of fifo_64x512_dualclock_0_1 : label is "36"; + attribute FULLPOINTER1 of fifo_64x512_dualclock_1_0 : label is "0b000000000000000"; + attribute FULLPOINTER of fifo_64x512_dualclock_1_0 : label is "0b111111111111111"; + attribute AFPOINTER1 of fifo_64x512_dualclock_1_0 : label is "0b000000000000000"; + attribute AFPOINTER of fifo_64x512_dualclock_1_0 : label is "0b111111111111111"; + attribute AEPOINTER1 of fifo_64x512_dualclock_1_0 : label is "0b000000000000000"; + attribute AEPOINTER of fifo_64x512_dualclock_1_0 : label is "0b111111111111111"; + attribute RESETMODE of fifo_64x512_dualclock_1_0 : label is "ASYNC"; + attribute REGMODE of fifo_64x512_dualclock_1_0 : label is "NOREG"; + attribute CSDECODE_R of fifo_64x512_dualclock_1_0 : label is "0b11"; + attribute CSDECODE_W of fifo_64x512_dualclock_1_0 : label is "0b11"; + attribute DATA_WIDTH_R of fifo_64x512_dualclock_1_0 : label is "36"; + attribute DATA_WIDTH_W of fifo_64x512_dualclock_1_0 : label is "36"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + fifo_64x512_dualclock_0_1: FIFO16KA + -- synopsys translate_off + generic map (FULLPOINTER1=> "011111111000001", FULLPOINTER=> "011111111100001", + AFPOINTER1=> "011100111000001", AFPOINTER=> "011100111100001", + AEPOINTER1=> "000000101111111", AEPOINTER=> "000000101011111", + RESETMODE=> "ASYNC", REGMODE=> "NOREG", CSDECODE_R=> "11", + CSDECODE_W=> "11", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) + -- synopsys translate_on + port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), + DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), + DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), + DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), + DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), + DI18=>Data(18), DI19=>Data(19), DI20=>Data(20), + DI21=>Data(21), DI22=>Data(22), DI23=>Data(23), + DI24=>Data(24), DI25=>Data(25), DI26=>Data(26), + DI27=>Data(27), DI28=>Data(28), DI29=>Data(29), + DI30=>Data(30), DI31=>Data(31), DI32=>Data(32), + DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), + FULLI=>Full_int, CSW0=>scuba_vhi, CSW1=>scuba_vhi, + EMPTYI=>Empty_int, CSR0=>scuba_vhi, CSR1=>scuba_vhi, + WE=>WrEn, RE=>RdEn, CLKW=>WrClock, CLKR=>RdClock, RST=>Reset, + RPRST=>RPReset, DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), + DO3=>Q(21), DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), + DO8=>Q(26), DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), + DO12=>Q(30), DO13=>Q(31), DO14=>Q(32), DO15=>Q(33), + DO16=>Q(34), DO17=>Q(35), DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), + DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), + DO26=>Q(8), DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), + DO30=>Q(12), DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), + DO34=>Q(16), DO35=>Q(17), EF=>Empty_int, AEF=>AlmostEmpty, + AFF=>AlmostFull, FF=>Full_int); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + fifo_64x512_dualclock_1_0: FIFO16KA + -- synopsys translate_off + generic map (FULLPOINTER1=> "000000000000000", FULLPOINTER=> "111111111111111", + AFPOINTER1=> "000000000000000", AFPOINTER=> "111111111111111", + AEPOINTER1=> "000000000000000", AEPOINTER=> "111111111111111", + RESETMODE=> "ASYNC", REGMODE=> "NOREG", CSDECODE_R=> "11", + CSDECODE_W=> "11", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) + -- synopsys translate_on + port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38), + DI3=>Data(39), DI4=>Data(40), DI5=>Data(41), DI6=>Data(42), + DI7=>Data(43), DI8=>Data(44), DI9=>Data(45), DI10=>Data(46), + DI11=>Data(47), DI12=>Data(48), DI13=>Data(49), + DI14=>Data(50), DI15=>Data(51), DI16=>Data(52), + DI17=>Data(53), DI18=>Data(54), DI19=>Data(55), + DI20=>Data(56), DI21=>Data(57), DI22=>Data(58), + DI23=>Data(59), DI24=>Data(60), DI25=>Data(61), + DI26=>Data(62), DI27=>Data(63), DI28=>Data(64), + DI29=>Data(65), DI30=>Data(66), DI31=>Data(67), + DI32=>Data(68), DI33=>Data(69), DI34=>Data(70), + DI35=>Data(71), FULLI=>Full_int, CSW0=>scuba_vhi, + CSW1=>scuba_vhi, EMPTYI=>Empty_int, CSR0=>scuba_vhi, + CSR1=>scuba_vhi, WE=>WrEn, RE=>RdEn, CLKW=>WrClock, + CLKR=>RdClock, RST=>Reset, RPRST=>RPReset, DO0=>Q(54), + DO1=>Q(55), DO2=>Q(56), DO3=>Q(57), DO4=>Q(58), DO5=>Q(59), + DO6=>Q(60), DO7=>Q(61), DO8=>Q(62), DO9=>Q(63), DO10=>Q(64), + DO11=>Q(65), DO12=>Q(66), DO13=>Q(67), DO14=>Q(68), + DO15=>Q(69), DO16=>Q(70), DO17=>Q(71), DO18=>Q(36), + DO19=>Q(37), DO20=>Q(38), DO21=>Q(39), DO22=>Q(40), + DO23=>Q(41), DO24=>Q(42), DO25=>Q(43), DO26=>Q(44), + DO27=>Q(45), DO28=>Q(46), DO29=>Q(47), DO30=>Q(48), + DO31=>Q(49), DO32=>Q(50), DO33=>Q(51), DO34=>Q(52), + DO35=>Q(53), EF=>open, AEF=>open, AFF=>open, FF=>open); + + Empty <= Empty_int; + Full <= Full_int; +end Structure; + +-- synopsys translate_off +library SCM; +configuration Structure_CON of fifo_64x512_dualclock is + for Structure + for all:VHI use entity SCM.VHI(V); end for; + for all:VLO use entity SCM.VLO(V); end for; + for all:FIFO16KA use entity SCM.FIFO16KA(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/design/cores/fifo_8x512_dualclock.ipx b/design/cores/fifo_8x512_dualclock.ipx new file mode 100644 index 0000000..2400daf --- /dev/null +++ b/design/cores/fifo_8x512_dualclock.ipx @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/design/cores/fifo_8x512_dualclock.lpc b/design/cores/fifo_8x512_dualclock.lpc new file mode 100644 index 0000000..b10f5d5 --- /dev/null +++ b/design/cores/fifo_8x512_dualclock.lpc @@ -0,0 +1,48 @@ +[Device] +Family=latticescm +PartType=LFSCM3GA40EP1 +PartName=LFSCM3GA40EP1-6FF1020C +SpeedGrade=6 +Package=FFBGA1020 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.4 +ModuleName=fifo_8x512_dualclock +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=02/03/2011 +Time=10:30:21 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Only +RDepth=512 +RWidth=8 +WDepth=512 +WWidth=8 +regout=0 +CtrlByRdEn=0 +EmpFlg=1 +PeMode=Static - Single Threshold +PeAssert=1 +PeDeassert=12 +FullFlg=1 +PfMode=Static - Single Threshold +PfAssert=484 +PfDeassert=506 +Reset=Async +RDataCount=0 +WDataCount=0 +EnECC=0 diff --git a/design/cores/fifo_8x512_dualclock.vhd b/design/cores/fifo_8x512_dualclock.vhd new file mode 100644 index 0000000..cc29e2c --- /dev/null +++ b/design/cores/fifo_8x512_dualclock.vhd @@ -0,0 +1,181 @@ +-- VHDL netlist generated by SCUBA Diamond_1.1_Production (517) +-- Module Version: 5.4 +--/d/sugar/lattice/diamond/1.1/ispfpga/bin/lin/scuba -w -n fifo_8x512_dualclock -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 512 -width 8 -rwidth 8 -no_enable -pe 1 -pf 484 -e + +-- Thu Feb 3 10:30:21 2011 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library SCM; +use SCM.COMPONENTS.all; +-- synopsys translate_on + +entity fifo_8x512_dualclock is + port ( + Data: in std_logic_vector(7 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(7 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostEmpty: out std_logic; + AlmostFull: out std_logic); +end fifo_8x512_dualclock; + +architecture Structure of fifo_8x512_dualclock is + + -- internal signal declarations + signal scuba_vhi: std_logic; + signal Empty_int: std_logic; + signal Full_int: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component FIFO16KA + -- synopsys translate_off + generic (FULLPOINTER1 : in std_logic_vector(14 downto 0); + FULLPOINTER : in std_logic_vector(14 downto 0); + AFPOINTER1 : in std_logic_vector(14 downto 0); + AEPOINTER1 : in std_logic_vector(14 downto 0); + AFPOINTER : in std_logic_vector(14 downto 0); + AEPOINTER : in std_logic_vector(14 downto 0); + CSDECODE_R : in std_logic_vector(1 downto 0); + CSDECODE_W : in std_logic_vector(1 downto 0); + RESETMODE : in String; REGMODE : in String; + DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer); + -- synopsys translate_on + port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; + DI3: in std_logic; DI4: in std_logic; DI5: in std_logic; + DI6: in std_logic; DI7: in std_logic; DI8: in std_logic; + DI9: in std_logic; DI10: in std_logic; DI11: in std_logic; + DI12: in std_logic; DI13: in std_logic; + DI14: in std_logic; DI15: in std_logic; + DI16: in std_logic; DI17: in std_logic; + DI18: in std_logic; DI19: in std_logic; + DI20: in std_logic; DI21: in std_logic; + DI22: in std_logic; DI23: in std_logic; + DI24: in std_logic; DI25: in std_logic; + DI26: in std_logic; DI27: in std_logic; + DI28: in std_logic; DI29: in std_logic; + DI30: in std_logic; DI31: in std_logic; + DI32: in std_logic; DI33: in std_logic; + DI34: in std_logic; DI35: in std_logic; + FULLI: in std_logic; CSW0: in std_logic; + CSW1: in std_logic; EMPTYI: in std_logic; + CSR0: in std_logic; CSR1: in std_logic; WE: in std_logic; + RE: in std_logic; CLKW: in std_logic; CLKR: in std_logic; + RST: in std_logic; RPRST: in std_logic; + DO0: out std_logic; DO1: out std_logic; + DO2: out std_logic; DO3: out std_logic; + DO4: out std_logic; DO5: out std_logic; + DO6: out std_logic; DO7: out std_logic; + DO8: out std_logic; DO9: out std_logic; + DO10: out std_logic; DO11: out std_logic; + DO12: out std_logic; DO13: out std_logic; + DO14: out std_logic; DO15: out std_logic; + DO16: out std_logic; DO17: out std_logic; + DO18: out std_logic; DO19: out std_logic; + DO20: out std_logic; DO21: out std_logic; + DO22: out std_logic; DO23: out std_logic; + DO24: out std_logic; DO25: out std_logic; + DO26: out std_logic; DO27: out std_logic; + DO28: out std_logic; DO29: out std_logic; + DO30: out std_logic; DO31: out std_logic; + DO32: out std_logic; DO33: out std_logic; + DO34: out std_logic; DO35: out std_logic; + EF: out std_logic; AEF: out std_logic; AFF: out std_logic; + FF: out std_logic); + end component; + attribute FULLPOINTER1 : string; + attribute FULLPOINTER : string; + attribute AFPOINTER1 : string; + attribute AFPOINTER : string; + attribute AEPOINTER1 : string; + attribute AEPOINTER : string; + attribute RESETMODE : string; + attribute REGMODE : string; + attribute CSDECODE_R : string; + attribute CSDECODE_W : string; + attribute DATA_WIDTH_R : string; + attribute DATA_WIDTH_W : string; + attribute FULLPOINTER1 of fifo_8x512_dualclock_0_0 : label is "0b011111111000001"; + attribute FULLPOINTER of fifo_8x512_dualclock_0_0 : label is "0b011111111100001"; + attribute AFPOINTER1 of fifo_8x512_dualclock_0_0 : label is "0b011110001000001"; + attribute AFPOINTER of fifo_8x512_dualclock_0_0 : label is "0b011110001100001"; + attribute AEPOINTER1 of fifo_8x512_dualclock_0_0 : label is "0b000000001011111"; + attribute AEPOINTER of fifo_8x512_dualclock_0_0 : label is "0b000000000111111"; + attribute RESETMODE of fifo_8x512_dualclock_0_0 : label is "ASYNC"; + attribute REGMODE of fifo_8x512_dualclock_0_0 : label is "NOREG"; + attribute CSDECODE_R of fifo_8x512_dualclock_0_0 : label is "0b11"; + attribute CSDECODE_W of fifo_8x512_dualclock_0_0 : label is "0b11"; + attribute DATA_WIDTH_R of fifo_8x512_dualclock_0_0 : label is "36"; + attribute DATA_WIDTH_W of fifo_8x512_dualclock_0_0 : label is "36"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + fifo_8x512_dualclock_0_0: FIFO16KA + -- synopsys translate_off + generic map (FULLPOINTER1=> "011111111000001", FULLPOINTER=> "011111111100001", + AFPOINTER1=> "011110001000001", AFPOINTER=> "011110001100001", + AEPOINTER1=> "000000001011111", AEPOINTER=> "000000000111111", + RESETMODE=> "ASYNC", REGMODE=> "NOREG", CSDECODE_R=> "11", + CSDECODE_W=> "11", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) + -- synopsys translate_on + port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), + DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), + DI8=>scuba_vlo, DI9=>scuba_vlo, DI10=>scuba_vlo, + DI11=>scuba_vlo, DI12=>scuba_vlo, DI13=>scuba_vlo, + DI14=>scuba_vlo, DI15=>scuba_vlo, DI16=>scuba_vlo, + DI17=>scuba_vlo, DI18=>scuba_vlo, DI19=>scuba_vlo, + DI20=>scuba_vlo, DI21=>scuba_vlo, DI22=>scuba_vlo, + DI23=>scuba_vlo, DI24=>scuba_vlo, DI25=>scuba_vlo, + DI26=>scuba_vlo, DI27=>scuba_vlo, DI28=>scuba_vlo, + DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo, + DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo, + DI35=>scuba_vlo, FULLI=>Full_int, CSW0=>scuba_vhi, + CSW1=>scuba_vhi, EMPTYI=>Empty_int, CSR0=>scuba_vhi, + CSR1=>scuba_vhi, WE=>WrEn, RE=>RdEn, CLKW=>WrClock, + CLKR=>RdClock, RST=>Reset, RPRST=>RPReset, DO0=>open, + DO1=>open, DO2=>open, DO3=>open, DO4=>open, DO5=>open, + DO6=>open, DO7=>open, DO8=>open, DO9=>open, DO10=>open, + DO11=>open, DO12=>open, DO13=>open, DO14=>open, DO15=>open, + DO16=>open, DO17=>open, DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), + DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), + DO26=>open, DO27=>open, DO28=>open, DO29=>open, DO30=>open, + DO31=>open, DO32=>open, DO33=>open, DO34=>open, DO35=>open, + EF=>Empty_int, AEF=>AlmostEmpty, AFF=>AlmostFull, + FF=>Full_int); + + Empty <= Empty_int; + Full <= Full_int; +end Structure; + +-- synopsys translate_off +library SCM; +configuration Structure_CON of fifo_8x512_dualclock is + for Structure + for all:VHI use entity SCM.VHI(V); end for; + for all:VLO use entity SCM.VLO(V); end for; + for all:FIFO16KA use entity SCM.FIFO16KA(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/design/dma_adapter.vhd b/design/dma_adapter.vhd index af10c01..d318620 100644 --- a/design/dma_adapter.vhd +++ b/design/dma_adapter.vhd @@ -155,7 +155,7 @@ THE_WBS_INTERFACE : dma_wbs -- TX Fifo ----------------------------------------------------------------------- THE_DMA_TX_FIFO : dma_tx_fifo - port( + port map( wb_clk_i => WB_CLK_IN, clk_125 => CLK_125_IN, rstn => RSTN_IN, @@ -195,6 +195,8 @@ THE_DMA_TX_FIFO : dma_tx_fifo -- DMA CA ----------------------------------------------------------------------- +credit_available = credit_available_p or credit_available_np; + PROC_DMA_CA : process(CLK_125_IN) begin if rising_edge(CLK_125_IN) then @@ -204,13 +206,16 @@ PROC_DMA_CA : process(CLK_125_IN) else if tx_ph = '1' then if (TX_CA_PH_IN(8) = '1' or unsigned(TX_CA_PH_IN(7 downto 0)) > to_unsigned(1,8)) - or (TX_CA_PD_IN(12) = '1' or unsigned(TX_CA_PD_IN(11 downto 1)) >= unsigned(tx_pd(3 downto 0))) then + and (TX_CA_PD_IN(12) = '1' or unsigned(TX_CA_PD_IN(11 downto 1)) >= unsigned(tx_pd(3 downto 0))) then credit_available_p <= '1'; else credit_available_p <= '0'; end if; + else + credit_available_p <= '0'; end if; - if TX_CA_NPH_IN = '1' then + + if tx_nph = '1' then if TX_CA_NPH_IN(8) = '1' or unsigned(TX_CA_NPH_IN(7 downto 0) > to_unsigned(1,8)) then credit_available_np <= '1'; else @@ -269,7 +274,9 @@ PROC_DMA_CTRL : process(CLK_125_IN) THE_RX_FIFO : dma_rx_fifo port( -v + wb_clk_i => WB_CLK_IN, + clk_125 => CLK_125_IN, + rstn => RSTN_IN, rx_st => RX_ST_IN, rx_end => RX_END_IN, diff --git a/design/dma_core.vhd b/design/dma_core.vhd index 52e3d51..248c6e0 100644 --- a/design/dma_core.vhd +++ b/design/dma_core.vhd @@ -5,735 +5,577 @@ USE IEEE.numeric_std.ALL; library work; use work.trb_net_std.all; use work.trb_net_components.all; +use work.pcie_components.all; use work.version.all; entity dma_core is port( - RSTN : in std_logic; - CLK : in std_logic; - - DMA_ADDR : out std_logic_vector(31 downto 0); - DMA_WDAT : out std_logic_vector(63 downto 0); - DMA_RDAT : in std_logic_vector(63 downto 0); - DMA_SEL : out std_logic_vector(7 downto 0); - DMA_WE : out std_logic; - DMA_CYC : out std_logic; - DMA_STB : out std_logic; - DMA_LOCK : out std_logic; - DMA_CTI : out std_logic_vector(2 downto 0); - DMA_ACK : in std_logic; - DMA_ERR : in std_logic; - DMA_RETRY : in std_logic; - DMA_EOD : in std_logic; - - S_ADDR : in std_logic_vector(31 downto 0); - S_WDAT : in std_logic_vector(31 downto 0); - S_RDAT : out std_logic_vector(31 downto 0); - S_CYC : in std_logic; - S_STB : in std_logic; - S_SEL : in std_logic_vector(3 downto 0); - S_WE : in std_logic; - S_ACK : out std_logic; - S_ERR : out std_logic; - - MAX_BURST_SIZE : out std_logic_vector(15 downto 0) + RESET_IN : in std_logic; + CLK_IN : in std_logic; + CLK_125_IN : in std_logic; + + DMA_START_ADDR_IN : in std_logic_vector(31 downto 0); --0x700 + DMA_LENGTH_IN : in std_logic_vector(31 downto 0); --0x701 + DMA_CONTROL_IN : in std_logic_vector(31 downto 0); --0x702 write + --0: activate + --1: reset dma handler (not implemented) + DMA_STATUS_OUT : out std_logic_vector(31 downto 0); --0x702 read + --0: active + --1: buffer full - waiting for reactivation + --31..8: data length in 32bit words + DMA_CONFIG_IN : in std_logic_vector(31 downto 0); --0x703 + --7..0 max burst size + + API_RUNNING_IN : in std_logic; + API_DATA_IN : in std_logic_vector(15 downto 0); + API_PACKET_NUM_IN : in std_logic_vector(2 downto 0); + API_TYP_IN : in std_logic_vector(2 downto 0); + API_DATAREADY_IN : in std_logic; + API_READ_OUT : out std_logic; + + REQUESTOR_ID_IN : in std_logic_vector(15 downto 0); + + TX_ST_OUT : out std_logic; --tx first word + TX_END_OUT : out std_logic; --tx last word + TX_DWEN_OUT : out std_logic; --tx use only upper 32 bit + TX_DATA_OUT : out std_logic_vector(63 downto 0); --tx data out + TX_REQ_OUT : out std_logic; --tx request out + TX_RDY_IN : in std_logic; --tx arbiter can read + TX_VAL_IN : in std_logic; --tx data is valid + TX_CA_PH_IN : in std_logic_vector(8 downto 0); --header credit for write + TX_CA_PD_IN : in std_logic_vector(12 downto 0); --data credits in 32 bit words + TX_CA_NPH_IN : in std_logic_vector(8 downto 0); --header credit for read + + RX_CR_CPLH_OUT : out std_logic; + RX_CR_CPLD_OUT : out std_logic_vector(7 downto 0); + UNEXP_CMPL_OUT : out std_logic; + RX_ST_IN : in std_logic; + RX_END_IN : in std_logic; + RX_DWEN_IN : in std_logic; + RX_DATA_IN : in std_logic_vector(63 downto 0); + + STATUS_REG_OUT : out std_logic_vector(127 downto 0); + DEBUG_OUT : out std_logic_vector(31 downto 0) ); end entity; architecture dma_core_arch of dma_core is - signal dma_addr : std_logic_vector(31 downto 0); --memory start address for DMA - signal dma_start : std_logic; --dma start pulse - signal dma_size : std_logic_vector(7 downto 0); --number of 64bit words to transfer (max. 32) + signal reset_i : std_logic; + + signal credit_available_np : std_logic := '0'; + signal credit_available_p : std_logic := '0'; + + signal tx_wr_en : std_logic := '0'; + signal tx_rd_en : std_logic := '0'; + signal tx_empty : std_logic := '0'; + signal tx_full : std_logic := '0'; + signal tx_almost_empty : std_logic := '0'; + signal tx_almost_full : std_logic := '0'; + signal tx_data_in : std_logic_vector(35 downto 0) := (others => '0'); + signal tx_fifo_data_out : std_logic_vector(71 downto 0) := (others => '0'); + + signal tx_length_wr_en : std_logic := '0'; + signal tx_length_rd_en : std_logic := '0'; + signal tx_length_empty : std_logic := '0'; + signal tx_length_full : std_logic := '0'; + signal tx_length_almost_empty : std_logic := '0'; + signal tx_length_almost_full : std_logic := '0'; + signal tx_length_data_in : std_logic_vector(7 downto 0) := (others => '0'); + signal tx_length_data_out : std_logic_vector(7 downto 0) := (others => '0'); + + type copy_state_t is (IDLE, RUNNING, LAST_WORD, BUFFER_FULL_WAIT); + signal copy_state : copy_state_t; + + signal copy_length : unsigned(6 downto 0) := (others => '0'); + signal current_address : unsigned(31 downto 0) := (others => '0'); + signal buf_API_READ_OUT : std_logic := '0'; + + type send_state_t is (SEND_IDLE, SEND_CREDIT_WAIT, SEND_START, SEND_FIRST, SEND_DATA); + signal send_state : send_state_t; + signal tx_length : unsigned(6 downto 0) := (others => '0'); + signal last_words : std_logic := '0'; + signal finished : std_logic := '0'; + signal finished_sys : std_logic := '0'; + signal busy : std_logic := '0'; + + signal tx_req_i : std_logic; + signal tx_end_i : std_logic; + signal send_state_bits : std_logic_vector(3 downto 0); + signal copy_state_bits : std_logic_vector(1 downto 0); + + + signal total_length : unsigned(23 downto 0); + signal current_buffer : unsigned(23 downto 0) := (others => '0'); + signal tx_fifo_padding : std_logic_vector(3 downto 0); + signal api_running_rising : std_logic; + signal api_running_falling : std_logic; + signal api_starts : std_logic; + signal last_api_running : std_logic; + signal buf_TX_DATA_OUT : std_logic_vector(63 downto 0); + signal buffer_full_strobe : std_logic; + signal buffer_full : std_logic; begin -PROC_SEND : process(CLK) +----------------------------------------------------------------------- +-- I/O +----------------------------------------------------------------------- +reset_i <= RESET_IN; + +API_READ_OUT <= buf_API_READ_OUT; + + +PROC_DETECT_START : process(CLK_IN) begin - if rising_edge(CLK) then - if RSTN = '0' then - write_state <= IDLE; - curr_dest <= (others => '0'); - fifo_read_en <= '0'; - else - fifo_read_en <= '0'; - DMA_CYC <= '0'; - DMA_STB <= '0'; - DMA_WE <= '0'; - DMA_CTI <= "000"; + if rising_edge(CLK_IN) then + last_api_running <= API_RUNNING_IN; + api_running_rising <= API_RUNNING_IN and not last_api_running; + api_running_falling<= not API_RUNNING_IN and last_api_running; + end if; + end process; - case write_state is +----------------------------------------------------------------------- +-- Copy Data from API +----------------------------------------------------------------------- +PROC_COPY_DATA : process(CLK_IN) + begin + if rising_edge(CLK_IN) then + if reset_i = '1' then + tx_wr_en <= '0'; + tx_length_wr_en <= '0'; + copy_state <= IDLE; + buf_API_READ_OUT <= '0'; + copy_length <= (others => '0'); --length counter while copying + buffer_full_strobe <= '0'; + else + tx_wr_en <= '0'; + tx_length_wr_en <= '0'; + last_words <= '0'; + tx_fifo_padding <= x"0"; + buffer_full_strobe <= '0'; + case copy_state is when IDLE => - if dma_start = '1' then - write_state <= PREPARE_DATA; - write_size <= dma_size; - write_addr <= dma_addr; + copy_state_bits <= "00"; + if DMA_CONTROL_IN(0) = '1' then + total_length <= (others => '0'); + current_address <= unsigned(DMA_START_ADDR_IN); + end if; + if busy = '1' and API_RUNNING_IN = '1' and tx_almost_full = '0' then --DMA enable and API running + if --Enough space in buffer for one burst + current_address + unsigned(DMA_CONTROL_IN(7 downto 0)) * to_unsigned(4,32) + < unsigned(DMA_START_ADDR_IN) + unsigned(DMA_LENGTH_IN) * to_unsigned(4,32) then + tx_data_in( 7 downto 0) <= std_logic_vector(current_address(31 downto 24)); + tx_data_in(15 downto 8) <= std_logic_vector(current_address(23 downto 16)); + tx_data_in(23 downto 16) <= std_logic_vector(current_address(15 downto 8)); + tx_data_in(31 downto 24) <= std_logic_vector(current_address( 7 downto 0)); + tx_data_in(35 downto 32) <= x"0"; + buf_API_READ_OUT <= '1'; + copy_length <= (others => '0'); + copy_state <= RUNNING; + tx_wr_en <= '1'; + tx_fifo_padding <= x"8"; + else + buffer_full_strobe <= '1'; + copy_state <= BUFFER_FULL_WAIT; + end if; end if; - when PREPARE_DATA => + when RUNNING => + copy_state_bits <= "01"; + if API_DATAREADY_IN = '1' then + tx_data_in <= x"0" & "00000001000000" + & API_PACKET_NUM_IN(2) & API_PACKET_NUM_IN(0) & API_DATA_IN(15 downto 0); + tx_wr_en <= '1'; + copy_length <= copy_length + to_unsigned(1,7); + total_length <= total_length + to_unsigned(1,1); + current_address <= current_address + to_unsigned(4,32); +-- if copy_length = unsigned(DMA_CONFIG_IN(6 downto 0)) - to_unsigned(1,1) then +-- buf_API_READ_OUT <= '0'; +-- els + if copy_length = unsigned(DMA_CONFIG_IN(6 downto 0)) then + buf_API_READ_OUT <= '0'; + copy_state <= LAST_WORD; + end if; + end if; + if API_RUNNING_IN = '0' then + buf_API_READ_OUT <= '0'; + copy_state <= LAST_WORD; + end if; + + when LAST_WORD => + copy_state_bits <= "10"; + tx_data_in <= (others => '0'); + tx_wr_en <= not copy_length(0); --write padding + tx_fifo_padding <= x"8"; + last_words <= not API_RUNNING_IN; + tx_length_wr_en <= '1'; + copy_state <= IDLE; + + when BUFFER_FULL_WAIT => + copy_state_bits <= "11"; + if DMA_CONTROL_IN(0) = '1' then + copy_state <= IDLE; + end if; end case; + end if; end if; end process; + tx_length_data_in <= last_words & std_logic_vector(copy_length); + + + + + +----------------------------------------------------------------------- +-- TX Fifo +----------------------------------------------------------------------- +THE_TX_FIFO : fifo_32to64x512_dualclock + port map ( + Data(7 downto 0) => tx_data_in(31 downto 24), + Data(15 downto 8) => tx_data_in(23 downto 16), + Data(23 downto 16) => tx_data_in(15 downto 8), + Data(31 downto 24) => tx_data_in(7 downto 0), + Data(35 downto 32) => tx_fifo_padding, + WrClock => CLK_IN, + RdClock => CLK_125_IN, + WrEn => tx_wr_en, + RdEn => tx_rd_en, + Reset => reset_i, + RPReset => reset_i, + Q => tx_fifo_data_out, + Empty => tx_empty, + Full => tx_full, + AlmostEmpty => tx_almost_empty, + AlmostFull => tx_almost_full --at 464 words + ); + +THE_TX_LENGTH_FIFO : fifo_8x512_dualclock + port map ( + Data => tx_length_data_in, + WrClock => CLK_IN, + RdClock => CLK_125_IN, + WrEn => tx_length_wr_en, + RdEn => tx_length_rd_en, + Reset => reset_i, + RPReset => reset_i, + Q => tx_length_data_out, + Empty => tx_length_empty, + Full => tx_length_full, + AlmostEmpty => tx_length_almost_empty, + AlmostFull => tx_length_almost_full + ); + + +----------------------------------------------------------------------- +-- Send Data State Machine +----------------------------------------------------------------------- +PROC_DMA_SEND : process(CLK_125_IN) + begin + if rising_edge(CLK_125_IN) then + if reset_i = '1' then + tx_length_rd_en <= '0'; + tx_rd_en <= '0'; + finished <= '0'; + send_state <= SEND_IDLE; + TX_ST_OUT <= '0'; + tx_end_i <= '0'; + TX_DWEN_OUT <= '0'; + buf_TX_DATA_OUT <= (others => '0'); + tx_req_i <= '0'; + else -end architecture; - -module simple_dma_core ( - ,clk, - ,rstn - ,a_addr,a_wdat,a_rdat,a_sel,a_we,a_cyc,a_stb,a_lock,a_cti,a_ack,a_err,a_retry,a_eod - ,b_addr,b_wdat,b_rdat,b_sel,b_we,b_cyc,b_stb,b_lock,b_cti,b_ack,b_err,b_retry,b_eod - ,b_active - ,s_addr,s_wdat,s_rdat,s_cyc,s_stb,s_sel,s_we,s_ack,s_err,a_active - ,max_burst_size, -///// output from rx - ,wb_rx_clk_i - ,rp_stat_0,rp_stat_1,rp_stat_2,rp_stat_3 - ,rp_addr_0,rp_addr_1,rp_addr_2,rp_addr_3 - ,rp_data_0, rp_data_1, rp_data_2, rp_data_3 - ,ddma_en, - ,int, - ,debug -); - -input clk; -input rstn; -output[31:0] a_addr; -output[63:0] a_wdat; -input[63:0] a_rdat; -output[7:0] a_sel; -output a_we; -output a_cyc; -output a_stb; -output a_lock; -output[2:0] a_cti; -input a_ack; -input a_err; -input a_retry; -input a_eod; - -output[31:0] b_addr; -output[63:0] b_wdat; -input[63:0] b_rdat; -output[7:0] b_sel; -output b_we; -output b_cyc; -output b_stb; -output b_lock; -output[2:0] b_cti; -input b_ack; -input b_err; -input b_retry; -input b_eod; - -input[31:0]s_addr; -input[31:0]s_wdat; -output[31:0]s_rdat; -input s_cyc; -input s_stb; -input[3:0] s_sel; -input s_we; -output s_ack; -output s_err; -output a_active; -output b_active; -output[15:0]max_burst_size; -output ddma_en; - - - -input[3:0] wb_rx_clk_i; -input [31:0] rp_stat_0,rp_stat_1,rp_stat_2,rp_stat_3; -input [31:0] rp_addr_0,rp_addr_1,rp_addr_2,rp_addr_3; -input [31:0] rp_data_0, rp_data_1, rp_data_2, rp_data_3; - - - -output int; -output[31:0] debug; -//---------------------------------------------------------- - - -reg a_cyc,b_cyc0,b_cyc; -reg a_stb,b_stb0,b_stb; -reg[2:0] a_cti,b_cti0,b_cti; -//reg a_sel,b_sel; -reg[31:0] a_addr,b_addr0; - -reg [31:0]b_addr; -reg[63:0] b_wdat0; -reg [63:0]b_wdat; -reg b_we0,a_we,b_we; - -wire[31:0] b_addr1[0:3]; -wire[63:0]b_wdat1[0:3]; -wire b_cyc1[0:3]; -wire b_stb1[0:3]; -wire b_we1[0:3]; -wire[2:0] b_cti1[0:3]; - -reg[31:0] wb_dat_local; -reg int; - -reg[31:0] dma_source; -reg[31:0] dma_dest; -reg[31:0] dma_size; -reg[31:0] dma_burst; -reg[31:0] dma_ctrl; -reg[7:0] dma_astat; -reg[31:0] int_ctrl; -reg[31:0] int_status; - -wire s_rd,s_wr; - -reg [31:0] curr_source,curr_dest; -reg [15:0] curr_size,curr_burst,curr_burst2,curr_size2; - - -reg [3:0] sma,sman; -wire [31:0] rdat; -reg s_stb_i; - -reg wr_ena; -reg rd_ena; - -reg[15:0] xfersize,xferburst; -wire[63:0] temp_out; -reg [63:0] temp_out2; -reg[63:0] temp_read2; -wire full,empty; -reg[3:0] smb,smbn; - -reg[2:0] dma_pulse; - -reg rd_ena_p; - -reg[63:0] fifo_wdat; -wire[63:0] fifo_rdat; -reg[63:0] fifo_rdat2; -reg[7:0] exitcounter; -wire[3:0] ddma_ena; -wire[3:0] sfp_busy; + tx_length_rd_en <= '0'; + tx_rd_en <= '0'; + finished <= '0'; + + case send_state is + when SEND_IDLE => + send_state_bits <= x"0"; + tx_end_i <= '0'; + TX_DWEN_OUT <= '0'; + if tx_length_empty = '0' and tx_length_rd_en = '0' then + tx_length_rd_en <= '1'; + elsif tx_length_rd_en = '1' then + send_state <= SEND_CREDIT_WAIT; + end if; -wire[3:0] wr_lenreg; -wire[16:0]ddma_len[0:3]; -wire[3:0]ddma_busy; -wire[3:0]ddma_end; -reg ddma_act; + when SEND_CREDIT_WAIT => + send_state_bits <= x"1"; + if tx_length_data_out(6 downto 0) = "0000000" then --no data + finished <= tx_length_data_out(7); + send_state <= SEND_IDLE; + elsif (TX_CA_PH_IN(8) = '1' or unsigned(TX_CA_PH_IN(7 downto 0)) > to_unsigned(1,8)) + and (TX_CA_PD_IN(12) = '1' or unsigned(TX_CA_PD_IN(8 downto 2)) >= unsigned(tx_length_data_out(6 downto 0))) + then + TX_ST_OUT <= '0'; + tx_end_i <= '0'; + TX_DWEN_OUT <= '0'; + buf_TX_DATA_OUT <= '0' & --R + "10" & --Fmt + "00000" & --Type + '0' & --R + "000" & --TC + "0000" & --R + '0' & --TD + '0' & --EP + "10" & --Attr + "00" & --R + "000" & tx_length_data_out(6 downto 0) & --Length + REQUESTOR_ID_IN & --Requestor ID + x"00" & -- Tag + x"FF"; --Byte Enables + tx_rd_en <= '1'; -- + tx_req_i <= '1'; + tx_length <= unsigned(tx_length_data_out(6 downto 0)); + send_state <= SEND_START; + end if; -wire[31:0]ddma_deb[0:3]; + when SEND_START => + send_state_bits <= x"2"; + if TX_RDY_IN = '1' then + if TX_VAL_IN = '1' then + TX_ST_OUT <= '1'; + if tx_length > to_unsigned(1,3) then + tx_rd_en <= '1'; + end if; + tx_length <= tx_length - to_unsigned(1,1); + send_state <= SEND_DATA; --SEND_FIRST; + tx_req_i <= '0'; + end if; + end if; -assign max_burst_size = |ddma_ena ? 16'h80 : dma_burst[15:0]; +-- when SEND_FIRST => +-- send_state_bits <= x"3"; +-- TX_ST_OUT <= '0'; +-- TX_DWEN_OUT <= tx_fifo_data_out(71); +-- buf_TX_DATA_OUT <= tx_fifo_data_out(31 downto 0) & tx_fifo_data_out(67 downto 36); +-- if TX_VAL_IN = '1' then +-- if tx_length > to_unsigned(2,3) then +-- tx_rd_en <= '1'; +-- tx_length <= tx_length - to_unsigned(2,3); +-- send_state <= SEND_DATA; +-- elsif tx_length > to_unsigned(1,3) then +-- tx_length <= tx_length - to_unsigned(2,3); +-- send_state <= SEND_DATA; +-- elsif tx_length = to_unsigned(1,3) then +-- finished <= tx_length_data_out(7); +-- tx_length <= tx_length - to_unsigned(1,3); +-- send_state <= SEND_DATA; +-- else +-- tx_end_i <= '1'; +-- finished <= tx_length_data_out(7); +-- send_state <= SEND_IDLE; +-- end if; +-- end if; + + when SEND_DATA => + send_state_bits <= x"7"; + TX_ST_OUT <= '0'; + TX_DWEN_OUT <= tx_fifo_data_out(71); + buf_TX_DATA_OUT <= tx_fifo_data_out(31 downto 0) & tx_fifo_data_out(67 downto 36); + + if TX_VAL_IN = '1' then + if tx_length > to_unsigned(2,3) then + tx_rd_en <= '1'; + tx_length <= tx_length - to_unsigned(2,3); + elsif tx_length > to_unsigned(1,3) then + tx_length <= tx_length - to_unsigned(2,3); + elsif tx_length = to_unsigned(1,3) then + tx_length <= tx_length - to_unsigned(1,3); + else + tx_end_i <= '1'; + finished <= tx_length_data_out(7); + send_state <= SEND_IDLE; + end if; + end if; +-- +-- if TX_VAL_IN = '1' and tx_length > to_unsigned(2,3) then +-- tx_rd_en <= '1'; +-- end if; +-- +-- if TX_VAL_IN = '1' and tx_length > to_unsigned(1,3) then +-- tx_length <= tx_length - to_unsigned(2,3); +-- elsif TX_VAL_IN = '1' and tx_length = to_unsigned(1,3) then +-- tx_length <= tx_length - to_unsigned(1,3); +-- end if; +-- +-- if TX_VAL_IN = '1' and tx_length = to_unsigned(0,7) then +-- tx_end_i <= '1'; +-- finished <= tx_length_data_out(7); +-- send_state <= SEND_IDLE; +-- else +-- tx_end_i <= '0'; +-- end if; -assign ddma_en = |ddma_ena; -assign s_rd = s_stb && ~s_we; -assign s_wr = s_stb && s_we; -assign s_rdat = wb_dat_local; -assign s_ack = s_stb_i && s_cyc; + end case; -assign ddma_ena = dma_ctrl[4:1]; + end if; + end if; + end process; +TX_END_OUT <= tx_end_i; +TX_REQ_OUT <= tx_req_i; +TX_DATA_OUT <= buf_TX_DATA_OUT; + +----------------------------------------------------------------------- +-- Clock Domain Transfers +----------------------------------------------------------------------- + +THE_finished_strobe_SYNC : pulse_sync + port map( + CLK_A_IN => CLK_125_IN, + RESET_A_IN => RESET_IN, + PULSE_A_IN => finished, + CLK_B_IN => CLK_IN, + RESET_B_IN => RESET_IN, + PULSE_B_OUT => finished_sys + ); +----------------------------------------------------------------------- +-- Status Flags +----------------------------------------------------------------------- -always @ (posedge clk or negedge rstn) -begin - if(~rstn) +--DMA has been enabled and the API did not finish running +PROC_BUSY : process(CLK_IN) begin - dma_source <= 32'd0; - dma_dest <= 32'd0; - dma_size <= 32'd0; - dma_ctrl <= 32'd0; - dma_burst <= 32'd0; - int_ctrl <= 32'd0; - int_status <= 32'd0; - - end - else - begin - - s_stb_i <= s_stb; - int_status <= int_ctrl; - if(s_stb) - begin - case (s_addr[4:2]) - - 3'b000: // 0x0 = source register - begin - if (s_rd) - begin - wb_dat_local <= dma_source; - end - else if (s_wr) - begin - dma_source <= s_wdat; - end - end - 3'b001: // 0x4 = dest - begin - if (s_rd) - wb_dat_local <= dma_dest; - else if (s_wr) - begin - dma_dest <= s_wdat; - end - end - 3'b010: // 0x8 = len - begin - if (s_rd) - wb_dat_local <= dma_size; - else if (s_wr) - begin - dma_size <= s_wdat; - end - end - 3'b011: // 0xc = burstsize ( bits 15:0) - begin - if (s_rd) - wb_dat_local <= dma_burst; - else if (s_wr) - begin - dma_burst <= s_wdat; - end - end - 3'b100: // 0x10 = dma control - begin - if (s_rd) - wb_dat_local <= dma_ctrl; - else if (s_wr) - begin - dma_ctrl <= s_wdat; - end - end - 3'b101: // 0x14 = interrupt control - begin - if (s_rd) - wb_dat_local <= int_ctrl; - else if (s_wr) - begin - int_ctrl <= s_wdat; - end - end - 3'b110: // 0x18 = interrupt status - begin - if (s_rd) - begin - wb_dat_local <= int_status; - end - end - default: - wb_dat_local <= 32'd0; - endcase - end - else if(dma_astat[0]) - dma_ctrl[0] <= 1'b0; - else if(ddma_act) - begin - dma_ctrl[0] <= |ddma_busy; - if(wr_lenreg[0]) dma_size <= ddma_len[0]; - else if(wr_lenreg[1]) dma_size <= ddma_len[1]; - else if(wr_lenreg[2]) dma_size <= ddma_len[2]; - else if(wr_lenreg[3]) dma_size <= ddma_len[3]; - end - end -end - -always @ (posedge clk) -begin - ddma_act <= |ddma_ena; -end - - - -always @(posedge clk) -begin - dma_pulse[0] <= dma_ctrl[0]; - dma_pulse[1] <= dma_pulse[0]; - dma_pulse[2] <= dma_pulse[0] && ~dma_pulse[1]; -end - + if rising_edge(CLK_IN) then + if RESET_IN = '1' then + busy <= '0'; + elsif DMA_CONTROL_IN(0) = '1' then + busy <= '1'; + elsif finished_sys = '1' then + busy <= '0'; + end if; + end if; + end process; -always @(posedge clk) -begin - int <= |int_ctrl; +--Buffer in RAM is full +PROC_BUFFER_FULL : process(CLK_IN) + begin + if rising_edge(CLK_IN) then + if RESET_IN = '1' or DMA_CONTROL_IN(0) = '1' then + buffer_full <= '0'; + elsif buffer_full_strobe = '1' then + buffer_full <= '1'; + end if; + end if; + end process; -end +PROC_STATUS_OUT : process(CLK_IN) + begin + if rising_edge(CLK_IN) then + DMA_STATUS_OUT(0) <= busy; + DMA_STATUS_OUT(1) <= buffer_full; + DMA_STATUS_OUT(7 downto 2) <= (others => '0'); + DMA_STATUS_OUT(31 downto 8) <= std_logic_vector(total_length); + end if; + end process; -assign b_sel = 8'b1111111; -assign a_sel = 8'b1111111; +----------------------------------------------------------------------- +-- RX Path +----------------------------------------------------------------------- +RX_CR_CPLH_OUT <= '0'; +RX_CR_CPLD_OUT <= (others => '0'); +UNEXP_CMPL_OUT <= '0'; + +----------------------------------------------------------------------- +-- Status Register +----------------------------------------------------------------------- +STATUS_REG_OUT(0) <= busy; +STATUS_REG_OUT(1) <= tx_req_i; +STATUS_REG_OUT(2) <= TX_VAL_IN; +STATUS_REG_OUT(3) <= TX_RDY_IN; +STATUS_REG_OUT(7 downto 4) <= send_state_bits; +STATUS_REG_OUT(9 downto 8) <= copy_state_bits; +STATUS_REG_OUT(10) <= API_DATAREADY_IN; +STATUS_REG_OUT(11) <= API_RUNNING_IN; +STATUS_REG_OUT(12) <= tx_empty; +STATUS_REG_OUT(13) <= tx_length_empty; +STATUS_REG_OUT(14) <= tx_almost_full; +STATUS_REG_OUT(15) <= tx_end_i; +STATUS_REG_OUT(22 downto 16) <= std_logic_vector(copy_length); +STATUS_REG_OUT(23) <= buffer_full; +STATUS_REG_OUT(31 downto 24) <= (others => '0'); + +STATUS_REG_OUT(40 downto 32) <= TX_CA_PH_IN; +STATUS_REG_OUT(53 downto 41) <= TX_CA_PD_IN; +STATUS_REG_OUT(62 downto 54) <= TX_CA_NPH_IN; +STATUS_REG_OUT(63) <= '0'; + +STATUS_REG_OUT(95 downto 64) <= x"00000000"; + +STATUS_REG_OUT(127 downto 96)<= std_logic_vector(current_address); + +----------------------------------------------------------------------- +-- Debug +----------------------------------------------------------------------- +process(CLK_IN) + begin + if rising_edge(CLK_IN) then + DEBUG_OUT(0) <= busy; + DEBUG_OUT(1) <= DMA_CONTROL_IN(0); + DEBUG_OUT(2) <= API_DATAREADY_IN; + DEBUG_OUT(3) <= buf_API_READ_OUT; + DEBUG_OUT(4) <= tx_rd_en; + DEBUG_OUT(5) <= tx_empty; + DEBUG_OUT(6) <= tx_length_empty; + DEBUG_OUT(7) <= tx_length_data_out(7); + DEBUG_OUT(8) <= tx_req_i; + DEBUG_OUT(9) <= TX_RDY_IN; + DEBUG_OUT(10)<= TX_VAL_IN; + DEBUG_OUT(11)<= tx_end_i; + DEBUG_OUT(13 downto 12) <= copy_state_bits; + DEBUG_OUT(15 downto 14) <= send_state_bits(1 downto 0); + DEBUG_OUT(23 downto 16) <= API_DATA_IN(7 downto 0); + DEBUG_OUT(31 downto 24) <= buf_TX_DATA_OUT(7 downto 0); + end if; + end process; +end architecture; -always @(*) -begin - if(b_cyc1[0]) - begin - b_addr <= b_addr1[0]; - b_we <= b_we1[0]; - b_cti <= b_cti1[0]; - b_stb <= b_stb1[0]; - b_cyc <= b_cyc1[0]; - b_wdat <= b_wdat1[0]; - end - else if(b_cyc1[1]) - begin - b_addr <= b_addr1[1]; - b_we <= b_we1[1]; - b_cti <= b_cti1[1]; - b_stb <= b_stb1[1]; - b_cyc <= b_cyc1[1]; - b_wdat <= b_wdat1[1]; - end - else if(b_cyc1[2]) - begin - b_addr <= b_addr1[2]; - b_we <= b_we1[2]; - b_cti <= b_cti1[2]; - b_stb <= b_stb1[2]; - b_cyc <= b_cyc1[2]; - b_wdat <= b_wdat1[2]; - end - else if(b_cyc1[3]) - begin - b_addr <= b_addr1[3]; - b_we <= b_we1[3]; - b_cti <= b_cti1[3]; - b_stb <= b_stb1[3]; - b_cyc <= b_cyc1[3]; - b_wdat <= b_wdat1[3]; - end - else - begin - b_addr <= b_addr0; - b_we <= b_we0; - b_cti <= b_cti0; - b_stb <= b_stb0; - b_cyc <= b_cyc0; - b_wdat <= b_wdat0; - end -end - -assign debug = ddma_deb[0]; - -/*assign debug[0] = b_cyc; -assign debug[1] = b_stb; -assign debug[2] = b_we; -assign debug[3] = b_ack; -*/ - - -//control Wishbone read from DPRAM -always @ ( posedge clk or negedge rstn) -begin - if(~rstn) - begin - sma <= 4'h0; - end - else - begin - case (sma) - 4'h0: - begin - a_cyc <= 1'b0; a_stb <= 1'b0; - dma_astat[0] <= 1'b0; - wr_ena <= 1'b0; - curr_source <= dma_source; - curr_burst <= {3'b000,dma_burst[31:3]}; - curr_size <= {3'b000,dma_size[31:3]}; - if(dma_pulse[2] && ~(|ddma_ena)) - sma <= 4'h1; - else - sma <= 4'h0; - end - 4'h1: - begin - a_addr <= curr_source; - a_cyc <= 1'b1; a_cti <= 3'b010; - if(~full) - begin - a_stb <= 1'b1; - if(a_ack) - begin - fifo_wdat <= a_rdat; - wr_ena <= 1'b1; - curr_burst <= curr_burst - 1; - end - else - begin - wr_ena <= 1'b0; - end - - end - else - begin - a_stb <= 1'b0; - end - if(curr_burst == 31'd1) - begin - - a_stb <= 1'b0; - a_cyc <= 1'b0; - sma <= 4'h2; - end - end - 4'h2: - begin - wr_ena <= 1'b0; - curr_burst <= {3'b000,dma_burst[31:3]}; - sma <= 4'h3; - end - 4'h3: - begin - curr_size <= curr_size - curr_burst; - sma <= 4'h4; - end - 4'h4: - begin - if(curr_size > 16'd0) - begin - curr_source <= curr_source + dma_burst; - exitcounter <= 8'd10; // 20 - sma <= 4'h7; - end - else - begin - sma <= 4'h5; - exitcounter <= 8'd100; - end - end - 4'h5: - begin - exitcounter <= exitcounter - 1; - if(exitcounter == 8'd10) - begin - dma_astat[0] <= 1'b1; - end - if(exitcounter == 8'd0) - begin - sma <= 4'b0; - end - end - - 4'h7: - begin - exitcounter <= exitcounter - 1; - if(exitcounter == 8'd0) - begin - sma <= 4'h1; - end - end - - - - - - endcase - end -end -/* Verilog module instantiation template generated by SCUBA ispLever_v72_PROD_Build (44) */ -/* Module Version: 5.0 */ -/* Tue Jan 20 14:52:35 2009 */ - -/* parameterized module instance */ -simpledma_fifo simplefifo (.Data(fifo_wdat ), .WrClock(clk ), .RdClock(clk ), .WrEn(wr_ena ), - .RdEn(rd_ena ), .Reset(~rstn ), .RPReset(1'b0 ), .Q(fifo_rdat ), .Empty(empty ), .Full( ), - .AlmostEmpty( ), .AlmostFull(full )); - -/* Verilog module instantiation template generated by SCUBA ispLever_v72_PROD_Build (44) */ -/* Module Version: 5.0 */ -/* Wed Jan 28 10:44:53 2009 */ - - -//Read fifo and write to DMA adaptor -always @ (posedge clk or negedge rstn) -begin - if(~rstn) - begin - smb <= 4'h0; - curr_dest <= 32'd0; - rd_ena <= 1'b0; - end - else - // rd_ena_p <= rd_ena; - - - case(smb) - 4'h0: - begin - curr_dest <= dma_dest; rd_ena <= 1'b0; - b_cyc0 <= 1'b0; b_stb0 <= 1'b0; b_we0 <= 1'b0; b_cti0 <= 3'b000; - curr_burst2 <= dma_burst[31:0]; - curr_size2 <= dma_size[31:0]; - - if(dma_pulse[2] && ~(|ddma_ena)) - begin - smb <= 4'h1; - end - end - 4'h1: - begin - b_addr0 <= curr_dest; - b_cti0 <= 3'b010; b_we0 <= 1'b1; - if(~empty ) - begin - b_cyc0 <= 1'b1; - rd_ena <= 1'b1; - smb <= 4'h2; - end - end - 4'h2: - begin - smb <= 4'h3; - end - 4'h3: - begin - smb <= 4'h4; - end - 4'h4: // fifo data out start here - begin - b_stb0 <= 1'b1; - b_wdat0 <= fifo_rdat; - curr_burst2 <= curr_burst2 - 8; - smb <= 4'h5; - end - 4'h5: - begin // b_ack received - b_wdat0 <= fifo_rdat2; - curr_burst2 <= curr_burst2 - 8; - smb <= 4'h6; - end - 4'h6: - begin // b_ack received - b_wdat0 <= fifo_rdat2; - curr_burst2 <= curr_burst2 - 8; - if(curr_burst2 == 31'd0) - begin - rd_ena <= 1'b0; - smb <= 4'h7; - end - - end - 4'h7: - begin - b_stb0 <= 1'b0; b_cyc0 <= 1'b0; b_we0 <= 1'b0; - curr_size2 <= curr_size2 - dma_burst; - curr_burst2 <= dma_burst; - smb <= 4'h8; - end - 4'h8: - begin - if(curr_size2 > 16'd0) - begin - curr_dest <= curr_dest + dma_burst; - smb <= 4'h1; - end - else - begin - smb <= 4'h9; - end - end - 4'h9: - begin - smb <= 1'h0; - end - endcase -end -always @ (posedge clk) -begin - fifo_rdat2 <= fifo_rdat; -end - - - -//Read data from SFP -> remove -direct_dma f_ddma0(.clk(clk),.rstn(rstn), - .ddma_ena(ddma_ena[0]), - .ddma_dest(dma_dest), - .wb_rx_clk_i(wb_rx_clk_i[0]), - .rp_stat(rp_stat_0), - .rp_data(rp_data_0), - .b_addr(b_addr1[0]), - .b_wdat(b_wdat1[0]), - .b_sel(), - .b_we(b_we1[0]), - .b_cyc(b_cyc1[0]), - .b_stb(b_stb1[0]), - .b_cti(b_cti1[0]), - .b_ack(b_ack), - .wr_lenreg(wr_lenreg[0]), - .ddma_len(ddma_len[0]), - .ddma_busy(ddma_busy[0]), - .ddma_end(ddma_end[0]), - .debug(ddma_deb[0])); - -direct_dma f_ddma1(.clk(clk),.rstn(rstn), - .ddma_ena(ddma_ena[1]), - .ddma_dest(dma_dest), - .wb_rx_clk_i(wb_rx_clk_i[1]), - .rp_stat(rp_stat_1), - .rp_data(rp_data_1), - .b_addr(b_addr1[1]), - .b_wdat(b_wdat1[1]), - .b_sel(), - .b_we(b_we1[1]), - .b_cyc(b_cyc1[1]), - .b_stb(b_stb1[1]), - .b_cti(b_cti1[1]), - .b_ack(b_ack), - .wr_lenreg(wr_lenreg[1]), - .ddma_len(ddma_len[1]), - .ddma_busy(ddma_busy[1]), - .ddma_end(ddma_end[1]), - .debug(ddma_deb[1])); - -direct_dma f_ddma2(.clk(clk),.rstn(rstn), - .ddma_ena(ddma_ena[2]), - .ddma_dest(dma_dest), - .wb_rx_clk_i(wb_rx_clk_i[2]), - .rp_stat(rp_stat_2), - .rp_data(rp_data_2), - .b_addr(b_addr1[2]), - .b_wdat(b_wdat1[2]), - .b_sel(), - .b_we(b_we1[2]), - .b_cyc(b_cyc1[2]), - .b_stb(b_stb1[2]), - .b_cti(b_cti1[2]), - .b_ack(b_ack), - .wr_lenreg(wr_lenreg[2]), - .ddma_len(ddma_len[2]), - .ddma_busy(ddma_busy[2]), - .ddma_end(ddma_end[2]), - .debug(ddma_deb[2])); - -direct_dma f_ddma3(.clk(clk),.rstn(rstn), - .ddma_ena(ddma_ena[3]), - .ddma_dest(dma_dest), - .wb_rx_clk_i(wb_rx_clk_i[3]), - .rp_stat(rp_stat_3), - .rp_data(rp_data_3), - .b_addr(b_addr1[3]), - .b_wdat(b_wdat1[3]), - .b_sel(), - .b_we(b_we1[3]), - .b_cyc(b_cyc1[3]), - .b_stb(b_stb1[3]), - .b_cti(b_cti1[3]), - .b_ack(b_ack), - .wr_lenreg(wr_lenreg[3]), - .ddma_len(ddma_len[3]), - .ddma_busy(ddma_busy[3]), - .ddma_end(ddma_end[3]), - .debug(ddma_deb[3])); - - - -endmodule +-- ----------------------------------------------------------------------- +-- -- DMA CA +-- ----------------------------------------------------------------------- +-- +-- PROC_DMA_CA : process(CLK_125_IN) +-- begin +-- if rising_edge(CLK_125_IN) then +-- if reset_i = '1' then +-- credit_available_p <= '0'; +-- credit_available_np <= '0'; +-- else +-- if tx_ph = '1' then --write credits +-- if (TX_CA_PH_IN(8) = '1' or unsigned(TX_CA_PH_IN(7 downto 0)) > to_unsigned(1,8)) +-- and (TX_CA_PD_IN(12) = '1' or unsigned(TX_CA_PD_IN(11 downto 1)) >= unsigned(tx_pd(3 downto 0))) then +-- credit_available_p <= '1'; +-- else +-- credit_available_p <= '0'; +-- end if; +-- else +-- credit_available_p <= '0'; +-- end if; +-- +-- if tx_nph = '1' then --read credits +-- if TX_CA_NPH_IN(8) = '1' or unsigned(TX_CA_NPH_IN(7 downto 0) > to_unsigned(1,8)) then +-- credit_available_np <= '1'; +-- else +-- credit_available_np <= '0'; +-- end if; +-- else +-- credit_available_np <= '0'; +-- end if; +-- end if; +-- end if; +-- end process; diff --git a/design/pci_core.vhd b/design/pci_core.vhd index 0e4d72f..81119ae 100644 --- a/design/pci_core.vhd +++ b/design/pci_core.vhd @@ -34,21 +34,25 @@ entity pci_core is BUS_LOCK_OUT : out std_logic; BUS_ACK_IN : in std_logic; - - --DMA - DMA_ADDR : in std_logic_vector(31 downto 0); - DMA_WDAT : in std_logic_vector(63 downto 0); - DMA_RDAT : out std_logic_vector(63 downto 0); - DMA_SEL : in std_logic_vector(7 downto 0); - DMA_WE : in std_logic; - DMA_CYC : in std_logic; - DMA_STB : in std_logic; - DMA_LOCK : in std_logic; - DMA_CTI : in std_logic_vector(2 downto 0); - DMA_ACK : out std_logic; - DMA_ERR : out std_logic; - DMA_RETRY : out std_logic; - DMA_EOD : out std_logic; + REQUESTOR_ID_OUT : out std_logic_vector(15 downto 0); + TX_ST_IN : in std_logic; --tx first word + TX_END_IN : in std_logic; --tx last word + TX_DWEN_IN : in std_logic; --tx use only upper 32 bit + TX_DATA_IN : in std_logic_vector(63 downto 0); --tx data out + TX_REQ_IN : in std_logic; --tx request out + TX_RDY_OUT : out std_logic; --tx arbiter can read + TX_VAL_OUT : out std_logic; --tx data is valid + TX_CA_PH_OUT : out std_logic_vector(8 downto 0); --header credit for write + TX_CA_PD_OUT : out std_logic_vector(12 downto 0); --data credits in 32 bit words + TX_CA_NPH_OUT : out std_logic_vector(8 downto 0); --header credit for read + + RX_CR_CPLH_IN : in std_logic; + RX_CR_CPLD_IN : in std_logic_vector(7 downto 0); + UNEXP_CMPL_IN : in std_logic; + RX_ST_OUT : out std_logic; + RX_END_OUT : out std_logic; + RX_DWEN_OUT : out std_logic; + RX_DATA_OUT : out std_logic_vector(63 downto 0); --Debug DEBUG_OUT : out std_logic_vector(31 downto 0) @@ -105,17 +109,7 @@ architecture pci_arch of pci_core is signal requestor_id_i : std_logic_vector(15 downto 0); - signal dma_req_adp_i : std_logic_vector(1 downto 0); - signal dma_ack_i : std_logic_vector(1 downto 0); - signal burst_len_i : std_logic_vector(15 downto 0); - signal active_ch_i : std_logic_vector(1 downto 0); - signal tx_st_dma_i : std_logic; - signal tx_end_dma_i : std_logic; - signal tx_dwen_dma_i : std_logic; - signal tx_data_dma_i : std_logic_vector(63 downto 0); - signal tx_req_dma_i : std_logic; - signal tx_rdy_dma_i : std_logic; - signal debug_dma_apater_i : std_logic_vector(31 downto 0); + signal debug_wb_tlc_i : std_logic_vector(31 downto 0); signal tx_rdy_ur_i : std_logic; @@ -321,66 +315,54 @@ rst_n <= not RESET_IN; ----------------------------------------------------------------------- requestor_id_i <= bus_num_i & dev_num_i & func_num_i; - -THE_DMA_ADAPTER : dma_adapter - port map( - RSTN => rst_n, - CLK_125 => clk_125_i, - ENABLE => '1', - - WB_CLK_I => CLK_WB_IN, - WB_RST_I => rst_n, - WB_DAT_I => DMA_WDAT, - WB_ADR_I => DMA_ADDR, - WB_CYC_I => DMA_CYC, - WB_LOCK_I => DMA_LOCK, - WB_SEL_I => DMA_SEL, - WB_STB_I => DMA_STB, - WB_WE_I => DMA_WE, - WB_DAT_O => DMA_RDAT, - WB_ACK_O => DMA_ACK, - WB_ERR_O => DMA_ERR, - WB_RTY_O => DMA_RETRY, - - DMA_REQ => dma_req_adp_i, - DMA_ACK => dma_ack_i, - BURST_LEN => burst_len_i, - ACTIVE_CH => active_ch_i, - REQUESTOR_ID => requestor_id_i, - - TX_ST => tx_st_dma_i, - TX_END => tx_end_dma_i, - TX_DWEN => tx_dwen_dma_i, - TX_DATA => tx_data_dma_i, - TX_REQ => tx_req_dma_i, - TX_RDY => tx_rdy_dma_i, - TX_VAL => tx_val_i, - TX_CA_PH => tx_ca_ph_i, - TX_CA_PD => tx_ca_pd_i, - TX_CA_NPH => tx_ca_nph_i, - - RX_CR_CPLH => open, - RX_CR_CPLD => open, - UNEXP_CMPL => open, - RX_ST => rx_st_i, - RX_END => rx_end_i, - RX_DWEN => rx_dwen_i, - RX_DATA => rx_data_i, - - DEBUG => debug_dma_apater_i - ); - --- DMA_ERR <= '0'; --- DMA_ACK <= '0'; --- DMA_RETRY <= '0'; --- DMA_RDAT <= (others => '0'); - --- tx_data_dma_i <= (others => '0'); --- tx_st_dma_i <= '0'; --- tx_end_dma_i <= '0'; --- tx_dwen_dma_i <= '0'; --- tx_req_dma_i <= '0'; - +-- +-- THE_DMA_ADAPTER : dma_adapter +-- port map( +-- RSTN => rst_n, +-- CLK_125 => clk_125_i, +-- ENABLE => '1', +-- +-- WB_CLK_I => CLK_WB_IN, +-- WB_RST_I => rst_n, +-- WB_DAT_I => DMA_WDAT, +-- WB_ADR_I => DMA_ADDR, +-- WB_CYC_I => DMA_CYC, +-- WB_LOCK_I => DMA_LOCK, +-- WB_SEL_I => DMA_SEL, +-- WB_STB_I => DMA_STB, +-- WB_WE_I => DMA_WE, +-- WB_DAT_O => DMA_RDAT, +-- WB_ACK_O => DMA_ACK, +-- WB_ERR_O => DMA_ERR, +-- WB_RTY_O => DMA_RETRY, +-- +-- DMA_REQ => dma_req_adp_i, --out +-- DMA_ACK => dma_ack_i, --in +-- BURST_LEN => burst_len_i, --in +-- ACTIVE_CH => active_ch_i, --in +-- REQUESTOR_ID => requestor_id_i, --in +-- +-- TX_ST => tx_st_dma_i, +-- TX_END => tx_end_dma_i, +-- TX_DWEN => tx_dwen_dma_i, +-- TX_DATA => tx_data_dma_i, +-- TX_REQ => tx_req_dma_i, +-- TX_RDY => tx_rdy_dma_i, +-- TX_VAL => tx_val_i, +-- TX_CA_PH => tx_ca_ph_i, +-- TX_CA_PD => tx_ca_pd_i, +-- TX_CA_NPH => tx_ca_nph_i, +-- +-- RX_CR_CPLH => open, +-- RX_CR_CPLD => open, +-- UNEXP_CMPL => open, +-- RX_ST => rx_st_i, +-- RX_END => rx_end_i, +-- RX_DWEN => rx_dwen_i, +-- RX_DATA => rx_data_i, +-- +-- DEBUG => debug_dma_apater_i +-- ); ----------------------------------------------------------------------- @@ -470,12 +452,12 @@ THE_TX_ARBITER : ip_tx_arbiter TX_DWEN_0 => tx_dwen_wbm_i, TX_RDY_0 => tx_rdy_wbm_i, - TX_REQ_1 => tx_req_dma_i, - TX_DIN_1 => tx_data_dma_i, - TX_SOP_1 => tx_st_dma_i, - TX_EOP_1 => tx_end_dma_i, - TX_DWEN_1 => tx_dwen_dma_i, - TX_RDY_1 => tx_rdy_dma_i, + TX_REQ_1 => TX_REQ_IN, + TX_DIN_1 => TX_DATA_IN, + TX_SOP_1 => TX_ST_IN, + TX_EOP_1 => TX_END_IN, + TX_DWEN_1 => TX_DWEN_IN, + TX_RDY_1 => TX_RDY_OUT, TX_REQ_2 => '0', TX_DIN_2 => (others => '0'), @@ -499,6 +481,29 @@ THE_TX_ARBITER : ip_tx_arbiter TX_RDY => tx_rdy_i ); + + + +----------------------------------------------------------------------- +-- DMA Connection +----------------------------------------------------------------------- + TX_VAL_OUT <= tx_val_i; + RX_ST_OUT <= rx_st_i; + RX_END_OUT <= rx_end_i; + RX_DWEN_OUT <= rx_dwen_i; + RX_DATA_OUT <= rx_data_i; + + TX_CA_PH_OUT <= tx_ca_ph_i; --header credit for write + TX_CA_PD_OUT <= tx_ca_pd_i; --data credits in 32 bit words + TX_CA_NPH_OUT <= tx_ca_nph_i; --header credit for read + + REQUESTOR_ID_OUT <= requestor_id_i; + +-- These are open in Wolfgangs Code +-- RX_CR_CPLH_IN : in std_logic; +-- RX_CR_CPLD_IN : in std_logic_vector(7 downto 0); +-- UNEXP_CMPL_IN : in std_logic; + ----------------------------------------------------------------------- -- TLP Handler ----------------------------------------------------------------------- diff --git a/design/wb_tlc.vhd b/design/wb_tlc.vhd index d1c4b26..83ecb0f 100644 --- a/design/wb_tlc.vhd +++ b/design/wb_tlc.vhd @@ -130,8 +130,8 @@ signal rx_eop_p : std_logic; type cpld_state_t is (CPLD_IDLE, CPLD_ACK, CPLD_DAT); signal cpld_state : cpld_state_t; - signal byte_cnt : unsigned(11 downto 0); - signal la : std_logic_vector( 7 downto 0); +-- signal byte_cnt : unsigned(11 downto 0); +-- signal la : std_logic_vector( 7 downto 0); signal din_p : std_logic_vector(31 downto 0); signal tran_id_p : std_logic_vector(23 downto 0); @@ -332,7 +332,7 @@ begin cmpl_d(63 downto 48) <= x"4A" & '0' & tran_tc & x"0"; cmpl_d(47 downto 32) <= "00" & tran_attr & "00" & tran_len; cmpl_d(31 downto 16) <= COMP_ID_IN; - cmpl_d(15 downto 0) <= x"0" & std_logic_vector(byte_cnt); + cmpl_d(15 downto 0) <= x"0" & tran_len & "00"; cmpl_wen <= '0'; cmpl_eop <= '0'; cmpl_dwen <= '0'; @@ -343,14 +343,14 @@ begin cmpl_d(63 downto 48) <= x"4A" & '0' & tran_tc & x"0"; cmpl_d(47 downto 32) <= "00" & tran_attr & "00" & tran_len; cmpl_d(31 downto 16) <= COMP_ID_IN; - cmpl_d(15 downto 0) <= x"0" & std_logic_vector(byte_cnt); + cmpl_d(15 downto 0) <= x"0" & tran_len & "00"; if WB_ACK_IN = '1' then cmpl_sop <= '1'; cmpl_wen <= '1'; cpld_state <= CPLD_DAT; end if; when CPLD_DAT => - cmpl_d(63 downto 32) <= tran_id_p & la; + cmpl_d(63 downto 32) <= tran_id_p & "0" & tran_addr(4 downto 0) & "00"; cmpl_d(31 downto 0) <= din_p; cmpl_sop <= '0'; cmpl_eop <= '1'; @@ -362,55 +362,6 @@ begin end process; ------------------------------------------------------------------------ --- Calculate correct byte length ------------------------------------------------------------------------ - THE_CPLD_BYTE_CNT_PROC : process(WB_CLK_IN) - variable cnt_be_leading_0 : unsigned(1 downto 0); - variable cnt_be_trailing_0 : unsigned(1 downto 0); - begin - if rising_edge(WB_CLK_IN) then - if tran_be(4) = '1' then - cnt_be_trailing_0 := to_unsigned(0,2); - elsif tran_be(5) = '1' then - cnt_be_trailing_0 := to_unsigned(1,2); - elsif tran_be(6) = '1' then - cnt_be_trailing_0 := to_unsigned(2,2); - elsif tran_be(7) = '1' then - cnt_be_trailing_0 := to_unsigned(3,2); - else --if tran_be(7 downto 4) = "0000" then - cnt_be_trailing_0 := to_unsigned(0,2); - end if; - - if tran_len(9 downto 0) = "0000000001" then - if tran_be(7) = '1' then - cnt_be_leading_0 := to_unsigned(0,2); - elsif tran_be(6) = '1' then - cnt_be_leading_0 := to_unsigned(1,2); - elsif tran_be(5) = '1' then - cnt_be_leading_0 := to_unsigned(2,2); - else --if tran_be(7 downto 4) = "0000" then - cnt_be_leading_0 := to_unsigned(3,2); - end if; - else - if tran_be(3) = '1' then - cnt_be_leading_0 := to_unsigned(0,2); - elsif tran_be(2) = '1' then - cnt_be_leading_0 := to_unsigned(1,2); - elsif tran_be(1) = '1' then - cnt_be_leading_0 := to_unsigned(2,2); - else --if tran_be(3 downto 0) = "0001" then - cnt_be_leading_0 := to_unsigned(3,2); - end if; - end if; - - byte_cnt <= unsigned(tran_len)*to_unsigned(4,2) - cnt_be_leading_0 - cnt_be_trailing_0; - la <= '0' & tran_addr & std_logic_vector(cnt_be_trailing_0); - - end if; - end process; - - ----------------------------------------------------------------------- -- TLC Completion FiFo ----------------------------------------------------------------------- @@ -614,4 +565,54 @@ end architecture; -- FIFO_WRN_OUT => to_req_fifo_wrn, -- FIFO_WEN_OUT => to_req_fifo_wen, -- FIFO_BAR_OUT => to_req_fifo_bar --- ); \ No newline at end of file +-- ); + + +-- +-- ----------------------------------------------------------------------- +-- -- Calculate correct byte length +-- ----------------------------------------------------------------------- +-- THE_CPLD_BYTE_CNT_PROC : process(WB_CLK_IN) +-- variable cnt_be_leading_0 : unsigned(1 downto 0); +-- variable cnt_be_trailing_0 : unsigned(1 downto 0); +-- begin +-- if rising_edge(WB_CLK_IN) then +-- if tran_be(4) = '1' then +-- cnt_be_trailing_0 := to_unsigned(0,2); +-- elsif tran_be(5) = '1' then +-- cnt_be_trailing_0 := to_unsigned(1,2); +-- elsif tran_be(6) = '1' then +-- cnt_be_trailing_0 := to_unsigned(2,2); +-- elsif tran_be(7) = '1' then +-- cnt_be_trailing_0 := to_unsigned(3,2); +-- else --if tran_be(7 downto 4) = "0000" then +-- cnt_be_trailing_0 := to_unsigned(0,2); +-- end if; +-- +-- if tran_len(9 downto 0) = "0000000001" then +-- if tran_be(7) = '1' then +-- cnt_be_leading_0 := to_unsigned(0,2); +-- elsif tran_be(6) = '1' then +-- cnt_be_leading_0 := to_unsigned(1,2); +-- elsif tran_be(5) = '1' then +-- cnt_be_leading_0 := to_unsigned(2,2); +-- else --if tran_be(7 downto 4) = "0000" then +-- cnt_be_leading_0 := to_unsigned(3,2); +-- end if; +-- else +-- if tran_be(3) = '1' then +-- cnt_be_leading_0 := to_unsigned(0,2); +-- elsif tran_be(2) = '1' then +-- cnt_be_leading_0 := to_unsigned(1,2); +-- elsif tran_be(1) = '1' then +-- cnt_be_leading_0 := to_unsigned(2,2); +-- else --if tran_be(3 downto 0) = "0001" then +-- cnt_be_leading_0 := to_unsigned(3,2); +-- end if; +-- end if; +-- +-- byte_cnt <= unsigned(tran_len)*to_unsigned(4,2) - cnt_be_leading_0 - cnt_be_trailing_0; +-- la <= '0' & tran_addr & std_logic_vector(cnt_be_trailing_0); +-- +-- end if; +-- end process; diff --git a/design/wb_tlc_cpld.vhd b/design/wb_tlc_cpld.vhd index f462e4d..aa7ed3d 100644 --- a/design/wb_tlc_cpld.vhd +++ b/design/wb_tlc_cpld.vhd @@ -39,10 +39,10 @@ architecture wb_tlc_cpld_arch of wb_tlc_cpld is type state_t is (IDLE, ACK, DAT); signal state : state_t; -signal byte_cnt : unsigned(11 downto 0); +-- signal byte_cnt : unsigned(11 downto 0); signal dout : std_logic_vector(63 downto 0); signal din_p : std_logic_vector(31 downto 0); -signal la : std_logic_vector( 7 downto 0); +-- signal la : std_logic_vector( 7 downto 0); signal tran_id_p : std_logic_vector(23 downto 0); @@ -68,7 +68,7 @@ begin DOUT_DATA_OUT(63 downto 48) <= x"4A" & '0' & TRAN_TC_IN & x"0"; DOUT_DATA_OUT(47 downto 32) <= "00" & TRAN_ATTR_IN & "00" & TRAN_LENGTH_IN; DOUT_DATA_OUT(31 downto 16) <= COMP_ID_IN; - DOUT_DATA_OUT(15 downto 0) <= x"0" & std_logic_vector(byte_cnt); + DOUT_DATA_OUT(15 downto 0) <= x"0" & TRAN_LENGTH_IN & "00"; --std_logic_vector(byte_cnt); DOUT_WEN_OUT <= '0'; DOUT_EOP_OUT <= '0'; DOUT_DWEN_OUT <= '0'; @@ -79,14 +79,14 @@ begin DOUT_DATA_OUT(63 downto 48) <= x"4A" & '0' & TRAN_TC_IN & x"0"; DOUT_DATA_OUT(47 downto 32) <= "00" & TRAN_ATTR_IN & "00" & TRAN_LENGTH_IN; DOUT_DATA_OUT(31 downto 16) <= COMP_ID_IN; - DOUT_DATA_OUT(15 downto 0) <= x"0" & std_logic_vector(byte_cnt); + DOUT_DATA_OUT(15 downto 0) <= x"0" & TRAN_LENGTH_IN & "00"; --std_logic_vector(byte_cnt); if VALID_IN = '1' then DOUT_SOP_OUT <= '1'; DOUT_WEN_OUT <= '1'; state <= DAT; end if; when DAT => - DOUT_DATA_OUT(63 downto 32) <= tran_id_p & la; + DOUT_DATA_OUT(63 downto 32) <= tran_id_p & '0' & TRAN_ADDR_IN & "00"; --la; DOUT_DATA_OUT(31 downto 0) <= din_p; DOUT_SOP_OUT <= '0'; DOUT_EOP_OUT <= '1'; @@ -101,50 +101,50 @@ begin ----------------------------------------------------------------------- -- Calculate correct byte length ----------------------------------------------------------------------- - THE_BYTE_CNT_PROC : process(WB_CLK_IN) - variable cnt_be_leading_0 : unsigned(1 downto 0); - variable cnt_be_trailing_0 : unsigned(1 downto 0); - begin - if rising_edge(WB_CLK_IN) then - if TRAN_BE_IN(4) = '1' then - cnt_be_trailing_0 := to_unsigned(0,2); - elsif TRAN_BE_IN(5) = '1' then - cnt_be_trailing_0 := to_unsigned(1,2); - elsif TRAN_BE_IN(6) = '1' then - cnt_be_trailing_0 := to_unsigned(2,2); - elsif TRAN_BE_IN(7) = '1' then - cnt_be_trailing_0 := to_unsigned(3,2); - else --if TRAN_BE_IN(7 downto 4) = "0000" then - cnt_be_trailing_0 := to_unsigned(0,2); - end if; - - if TRAN_LENGTH_IN(9 downto 0) = "0000000001" then - if TRAN_BE_IN(7) = '1' then - cnt_be_leading_0 := to_unsigned(0,2); - elsif TRAN_BE_IN(6) = '1' then - cnt_be_leading_0 := to_unsigned(1,2); - elsif TRAN_BE_IN(5) = '1' then - cnt_be_leading_0 := to_unsigned(2,2); - else --if TRAN_BE_IN(7 downto 4) = "0000" then - cnt_be_leading_0 := to_unsigned(3,2); - end if; - else - if TRAN_BE_IN(3) = '1' then - cnt_be_leading_0 := to_unsigned(0,2); - elsif TRAN_BE_IN(2) = '1' then - cnt_be_leading_0 := to_unsigned(1,2); - elsif TRAN_BE_IN(1) = '1' then - cnt_be_leading_0 := to_unsigned(2,2); - else --if TRAN_BE_IN(3 downto 0) = "0001" then - cnt_be_leading_0 := to_unsigned(3,2); - end if; - end if; - - byte_cnt <= unsigned(TRAN_LENGTH_IN)*to_unsigned(4,2) - cnt_be_leading_0 - cnt_be_trailing_0; - la <= '0' & TRAN_ADDR_IN & std_logic_vector(cnt_be_trailing_0); - - end if; - end process; +-- THE_BYTE_CNT_PROC : process(WB_CLK_IN) +-- variable cnt_be_leading_0 : unsigned(1 downto 0); +-- variable cnt_be_trailing_0 : unsigned(1 downto 0); +-- begin +-- if rising_edge(WB_CLK_IN) then +-- if TRAN_BE_IN(4) = '1' then +-- cnt_be_trailing_0 := to_unsigned(0,2); +-- elsif TRAN_BE_IN(5) = '1' then +-- cnt_be_trailing_0 := to_unsigned(1,2); +-- elsif TRAN_BE_IN(6) = '1' then +-- cnt_be_trailing_0 := to_unsigned(2,2); +-- elsif TRAN_BE_IN(7) = '1' then +-- cnt_be_trailing_0 := to_unsigned(3,2); +-- else --if TRAN_BE_IN(7 downto 4) = "0000" then +-- cnt_be_trailing_0 := to_unsigned(0,2); +-- end if; +-- +-- if TRAN_LENGTH_IN(9 downto 0) = "0000000001" then +-- if TRAN_BE_IN(7) = '1' then +-- cnt_be_leading_0 := to_unsigned(0,2); +-- elsif TRAN_BE_IN(6) = '1' then +-- cnt_be_leading_0 := to_unsigned(1,2); +-- elsif TRAN_BE_IN(5) = '1' then +-- cnt_be_leading_0 := to_unsigned(2,2); +-- else --if TRAN_BE_IN(7 downto 4) = "0000" then +-- cnt_be_leading_0 := to_unsigned(3,2); +-- end if; +-- else +-- if TRAN_BE_IN(3) = '1' then +-- cnt_be_leading_0 := to_unsigned(0,2); +-- elsif TRAN_BE_IN(2) = '1' then +-- cnt_be_leading_0 := to_unsigned(1,2); +-- elsif TRAN_BE_IN(1) = '1' then +-- cnt_be_leading_0 := to_unsigned(2,2); +-- else --if TRAN_BE_IN(3 downto 0) = "0001" then +-- cnt_be_leading_0 := to_unsigned(3,2); +-- end if; +-- end if; + +-- byte_cnt <= unsigned(TRAN_LENGTH_IN)*to_unsigned(4,2); +-- la <= '0' & TRAN_ADDR_IN & '0'; + +-- end if; +-- end process; end architecture; \ No newline at end of file diff --git a/pcie_components.vhd b/pcie_components.vhd index 9b96aca..a9a126c 100644 --- a/pcie_components.vhd +++ b/pcie_components.vhd @@ -29,26 +29,27 @@ component pci_core is BUS_CYC_OUT : out std_logic; BUS_STB_OUT : out std_logic; BUS_LOCK_OUT : out std_logic; --- BUS_CTI_OUT : out std_logic_vector(2 downto 0); BUS_ACK_IN : in std_logic; --- BUS_ERR_IN : in std_logic; --- BUS_RETRY_IN : in std_logic; --- BUS_EOD_IN : in std_logic; - - --DMA - DMA_ADDR : in std_logic_vector(31 downto 0); - DMA_WDAT : in std_logic_vector(63 downto 0); - DMA_RDAT : out std_logic_vector(63 downto 0); - DMA_SEL : in std_logic_vector(7 downto 0); - DMA_WE : in std_logic; - DMA_CYC : in std_logic; - DMA_STB : in std_logic; - DMA_LOCK : in std_logic; - DMA_CTI : in std_logic_vector(2 downto 0); - DMA_ACK : out std_logic; - DMA_ERR : out std_logic; - DMA_RETRY : out std_logic; - DMA_EOD : out std_logic; + + REQUESTOR_ID_OUT : out std_logic_vector(15 downto 0); + TX_ST_IN : in std_logic; --tx first word + TX_END_IN : in std_logic; --tx last word + TX_DWEN_IN : in std_logic; --tx use only upper 32 bit + TX_DATA_IN : in std_logic_vector(63 downto 0); --tx data out + TX_REQ_IN : in std_logic; --tx request out + TX_RDY_OUT : out std_logic; --tx arbiter can read + TX_VAL_OUT : out std_logic; --tx data is valid + TX_CA_PH_OUT : out std_logic_vector(8 downto 0); --header credit for write + TX_CA_PD_OUT : out std_logic_vector(12 downto 0); --data credits in 32 bit words + TX_CA_NPH_OUT : out std_logic_vector(8 downto 0); --header credit for read + + RX_CR_CPLH_IN : in std_logic; + RX_CR_CPLD_IN : in std_logic_vector(7 downto 0); + UNEXP_CMPL_IN : in std_logic; + RX_ST_OUT : out std_logic; + RX_END_OUT : out std_logic; + RX_DWEN_OUT : out std_logic; + RX_DATA_OUT : out std_logic_vector(63 downto 0); --Debug DEBUG_OUT : out std_logic_vector(31 downto 0) @@ -79,61 +80,63 @@ component UR_gen is ); end component; - -component dma_adapter is +component dma_core is port( - rstn : in std_logic; - clk_125 : in std_logic; - enable : in std_logic; - - wb_clk_i : in std_logic; - wb_rst_i : in std_logic; - wb_dat_i : in std_logic_vector(63 downto 0); - wb_adr_i : in std_logic_vector(31 downto 0); - wb_cyc_i : in std_logic; - wb_lock_i : in std_logic; - wb_sel_i : in std_logic_vector(7 downto 0); - wb_stb_i : in std_logic; - wb_we_i : in std_logic; - wb_dat_o : out std_logic_vector(63 downto 0); - wb_ack_o : out std_logic; - wb_err_o : out std_logic; - wb_rty_o : out std_logic; - - dma_req : out std_logic_vector(1 downto 0); - dma_ack : in std_logic_vector(1 downto 0); - burst_len : in std_logic_vector(15 downto 0); - active_ch : in std_logic_vector(1 downto 0); - requestor_id : in std_logic_vector(15 downto 0); - - tx_st : out std_logic; - tx_end : out std_logic; - tx_dwen : out std_logic; - tx_data : out std_logic_vector(63 downto 0); - tx_req : out std_logic; - tx_rdy : in std_logic; - tx_val : in std_logic; - tx_ca_ph : in std_logic_vector(8 downto 0); - tx_ca_pd : in std_logic_vector(12 downto 0); - tx_ca_nph : in std_logic_vector(8 downto 0); - - rx_cr_cplh : out std_logic; - rx_cr_cpld : out std_logic_vector(7 downto 0); - unexp_cmpl : out std_logic; - rx_st : in std_logic; - rx_end : in std_logic; - rx_dwen : in std_logic; - rx_data : in std_logic_vector(63 downto 0); - - debug : out std_logic_vector(31 downto 0) + RESET_IN : in std_logic; + CLK_IN : in std_logic; + CLK_125_IN : in std_logic; + + DMA_START_ADDR_IN : in std_logic_vector(31 downto 0); --0x700 + DMA_LENGTH_IN : in std_logic_vector(31 downto 0); --0x701 + DMA_CONTROL_IN : in std_logic_vector(31 downto 0); --0x702 write + --0: activate + --31..24: max burst size, 32 bit words + DMA_STATUS_OUT : out std_logic_vector(31 downto 0); --0x702 read + --0: active + --1; buffer full - waiting + --31..8: data length in 32bit words + DMA_CONFIG_IN : in std_logic_vector(31 downto 0); --0x703 + --7..0 max burst size + + API_RUNNING_IN : in std_logic; + API_DATA_IN : in std_logic_vector(15 downto 0); + API_PACKET_NUM_IN : in std_logic_vector(2 downto 0); + API_TYP_IN : in std_logic_vector(2 downto 0); + API_DATAREADY_IN : in std_logic; + API_READ_OUT : out std_logic; + +-- DMA_REQ_OUT : out std_logic_vector(1 downto 0); +-- DMA_ACK_IN : in std_logic_vector(1 downto 0); +-- BURST_LEN_IN : in std_logic_vector(15 downto 0); +-- ACTIVE_CH_IN : in std_logic_vector(1 downto 0); + REQUESTOR_ID_IN : in std_logic_vector(15 downto 0); + + TX_ST_OUT : out std_logic; --tx first word + TX_END_OUT : out std_logic; --tx last word + TX_DWEN_OUT : out std_logic; --tx use only upper 32 bit + TX_DATA_OUT : out std_logic_vector(63 downto 0); --tx data out + TX_REQ_OUT : out std_logic; --tx request out + TX_RDY_IN : in std_logic; --tx arbiter can read + TX_VAL_IN : in std_logic; --tx data is valid + TX_CA_PH_IN : in std_logic_vector(8 downto 0); --header credit for write + TX_CA_PD_IN : in std_logic_vector(12 downto 0); --data credits in 32 bit words + TX_CA_NPH_IN : in std_logic_vector(8 downto 0); --header credit for read + + RX_CR_CPLH_OUT : out std_logic; + RX_CR_CPLD_OUT : out std_logic_vector(7 downto 0); + UNEXP_CMPL_OUT : out std_logic; + RX_ST_IN : in std_logic; + RX_END_IN : in std_logic; + RX_DWEN_IN : in std_logic; + RX_DATA_IN : in std_logic_vector(63 downto 0); + + STATUS_REG_OUT : out std_logic_vector(127 downto 0); + DEBUG_OUT : out std_logic_vector(31 downto 0) + ); end component; - - - - component pciexp2 is port( rst_n : in std_logic; @@ -598,120 +601,136 @@ component wb_tlc_cpld_fifo is ); end component; - -component dma_rx_fifo is - port( - wb_clk : in std_logic; - clk_125 : in std_logic; - rstn : in std_logic; - - rx_st : in std_logic; - rx_end : in std_logic; - rx_dwen : in std_logic; - rx_data : in std_logic_vector(63 downto 0); - - active_ch : in std_logic_vector(1 downto 0); - ch1_rdy : out std_logic; - ch1_size : in std_logic_vector(11 downto 0); - ch1_rden : in std_logic; - ch1_pending : in std_logic; - ch_data : out std_logic_vector(63 downto 0); - ch_dv : out std_logic; - cplh_cr : out std_logic; - cpld_cr : out std_logic_vector(7 downto 0); - unexp_cmpl : out std_logic; - debug : out std_logic_vector(15 downto 0) - ); -end component; - - - - -component dma_tx_fifo is - port( - wb_clk : in std_logic; - clk_125 : in std_logic; - rstn : in std_logic; - - tx_st_in : in std_logic; - tx_end_in : in std_logic; - tx_dwen_in : in std_logic; - tx_dv : in std_logic; - tx_cv : in std_logic; - tx_data_in : in std_logic_vector(63 downto 0); - tx_pd_in : in std_logic_vector(4 downto 0); - tx_nph_in : in std_logic; - tx_ph_in : in std_logic; - - tx_st_out : out std_logic; - tx_end_out : out std_logic; - tx_dwen_out : out std_logic; - tx_nph_out : out std_logic; - tx_ph_out : out std_logic; - tx_data_out : out std_logic_vector(63 downto 0); - tx_pd_out : out std_logic_vector(3 downto 0); - empty : out std_logic; - full : out std_logic; - - credit_read : in std_logic; - data_read : in std_logic; - cr_avail : in std_logic; - tx_rdy : in std_logic; - tx_val : in std_logic; - tx_req : out std_logic; - - debug : out std_logic_vector(7 downto 0) - ); -end component; - - - -component dma_wbs is - port( - wb_clk_i : in std_logic; - wb_rst_i : in std_logic; - wb_dat_i : in std_logic_vector(63 downto 0); - wb_adr_i : in std_logic_vector(31 downto 0); - wb_cyc_i : in std_logic; - wb_lock_i : in std_logic; - wb_sel_i : in std_logic_vector(7 downto 0); - wb_stb_i : in std_logic; - wb_we_i : in std_logic; - wb_dat_o : out std_logic_vector(63 downto 0); - wb_ack_o : out std_logic; - wb_err_o : out std_logic; - wb_rty_o : out std_logic; - - dma_req : out std_logic_vector(1 downto 0); - dma_ack : in std_logic_vector(1 downto 0); - burst_len : in std_logic_vector(15 downto 0); - active_ch : in std_logic_vector(1 downto 0); - requestor_id : in std_logic_vector(15 downto 0); - enable : in std_logic; - - c_pd : out std_logic_vector(4 downto 0); - c_nph : out std_logic; - c_ph : out std_logic; - tx_dwen : out std_logic; - tx_nlfy : out std_logic; - tx_end : out std_logic; - tx_st : out std_logic; - tx_dv : out std_logic; - tx_cv : out std_logic; - tx_full : in std_logic; - tx_data : out std_logic_vector(63 downto 0); - - ch1_rdy : in std_logic; - ch1_size : out std_logic_vector(11 downto 0); - ch1_rden : out std_logic; - ch1_pending : out std_logic; - ch_data : in std_logic_vector(63 downto 0); - ch_dv : in std_logic; - - debug : out std_logic_vector(31 downto 0) - ); -end component; - - +-- +-- component dma_rx_fifo is +-- port( +-- wb_clk : in std_logic; +-- clk_125 : in std_logic; +-- rstn : in std_logic; +-- +-- rx_st : in std_logic; +-- rx_end : in std_logic; +-- rx_dwen : in std_logic; +-- rx_data : in std_logic_vector(63 downto 0); +-- +-- active_ch : in std_logic_vector(1 downto 0); +-- ch1_rdy : out std_logic; +-- ch1_size : in std_logic_vector(11 downto 0); +-- ch1_rden : in std_logic; +-- ch1_pending : in std_logic; +-- ch_data : out std_logic_vector(63 downto 0); +-- ch_dv : out std_logic; +-- cplh_cr : out std_logic; +-- cpld_cr : out std_logic_vector(7 downto 0); +-- unexp_cmpl : out std_logic; +-- debug : out std_logic_vector(15 downto 0) +-- ); +-- end component; +-- +-- +-- +-- +-- component dma_tx_fifo is +-- port( +-- wb_clk : in std_logic; +-- clk_125 : in std_logic; +-- rstn : in std_logic; +-- +-- tx_st_in : in std_logic; +-- tx_end_in : in std_logic; +-- tx_dwen_in : in std_logic; +-- tx_dv : in std_logic; +-- tx_cv : in std_logic; +-- tx_data_in : in std_logic_vector(63 downto 0); +-- tx_pd_in : in std_logic_vector(4 downto 0); +-- tx_nph_in : in std_logic; +-- tx_ph_in : in std_logic; +-- +-- tx_st_out : out std_logic; +-- tx_end_out : out std_logic; +-- tx_dwen_out : out std_logic; +-- tx_nph_out : out std_logic; +-- tx_ph_out : out std_logic; +-- tx_data_out : out std_logic_vector(63 downto 0); +-- tx_pd_out : out std_logic_vector(3 downto 0); +-- empty : out std_logic; +-- full : out std_logic; +-- +-- credit_read : in std_logic; +-- data_read : in std_logic; +-- cr_avail : in std_logic; +-- tx_rdy : in std_logic; +-- tx_val : in std_logic; +-- tx_req : out std_logic; +-- +-- debug : out std_logic_vector(7 downto 0) +-- ); +-- end component; +-- +-- +-- +-- component dma_wbs is +-- port( +-- wb_clk_i : in std_logic; +-- wb_rst_i : in std_logic; +-- wb_dat_i : in std_logic_vector(63 downto 0); +-- wb_adr_i : in std_logic_vector(31 downto 0); +-- wb_cyc_i : in std_logic; +-- wb_lock_i : in std_logic; +-- wb_sel_i : in std_logic_vector(7 downto 0); +-- wb_stb_i : in std_logic; +-- wb_we_i : in std_logic; +-- wb_dat_o : out std_logic_vector(63 downto 0); +-- wb_ack_o : out std_logic; +-- wb_err_o : out std_logic; +-- wb_rty_o : out std_logic; +-- +-- dma_req : out std_logic_vector(1 downto 0); +-- dma_ack : in std_logic_vector(1 downto 0); +-- burst_len : in std_logic_vector(15 downto 0); +-- active_ch : in std_logic_vector(1 downto 0); +-- requestor_id : in std_logic_vector(15 downto 0); +-- enable : in std_logic; +-- +-- c_pd : out std_logic_vector(4 downto 0); +-- c_nph : out std_logic; +-- c_ph : out std_logic; +-- tx_dwen : out std_logic; +-- tx_nlfy : out std_logic; +-- tx_end : out std_logic; +-- tx_st : out std_logic; +-- tx_dv : out std_logic; +-- tx_cv : out std_logic; +-- tx_full : in std_logic; +-- tx_data : out std_logic_vector(63 downto 0); +-- +-- ch1_rdy : in std_logic; +-- ch1_size : out std_logic_vector(11 downto 0); +-- ch1_rden : out std_logic; +-- ch1_pending : out std_logic; +-- ch_data : in std_logic_vector(63 downto 0); +-- ch_dv : in std_logic; +-- +-- debug : out std_logic_vector(31 downto 0) +-- ); +-- end component; + + component fifo_32to64x512_dualclock + port (Data: in std_logic_vector(35 downto 0); + WrClock: in std_logic; RdClock: in std_logic; + WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; + RPReset: in std_logic; Q: out std_logic_vector(71 downto 0); + Empty: out std_logic; Full: out std_logic; + AlmostEmpty: out std_logic; AlmostFull: out std_logic); + end component; + + component fifo_8x512_dualclock + port (Data: in std_logic_vector(7 downto 0); + WrClock: in std_logic; RdClock: in std_logic; + WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; + RPReset: in std_logic; Q: out std_logic_vector(7 downto 0); + Empty: out std_logic; Full: out std_logic; + AlmostEmpty: out std_logic; AlmostFull: out std_logic); + end component; end package; diff --git a/pexor.p2t b/pexor.p2t index 9ce01fc..5640bb8 100644 --- a/pexor.p2t +++ b/pexor.p2t @@ -4,7 +4,7 @@ -n 1 -y -s 12 --t 1 +-t 6 -c 1 -e 2 -m nodelist.txt diff --git a/pexor.prj b/pexor.prj index 86adfdc..046a814 100644 --- a/pexor.prj +++ b/pexor.prj @@ -42,24 +42,24 @@ add_file -vhdl -lib work "../trbnet/trb_net16_ibuf.vhd" add_file -vhdl -lib work "../trbnet/trb_net16_api_base.vhd" add_file -vhdl -lib work "../trbnet/trb_net16_iobuf.vhd" add_file -vhdl -lib work "../trbnet/trb_net16_io_multiplexer.vhd" -add_file -vhdl -lib work "../trbnet/trb_net16_trigger.vhd" -add_file -vhdl -lib work "../trbnet/trb_net16_ipudata.vhd" -add_file -vhdl -lib work "../trbnet/trb_net16_endpoint_hades_full.vhd" -add_file -vhdl -lib work "../trbnet/trb_net_onewire_listener.vhd" +# add_file -vhdl -lib work "../trbnet/trb_net16_trigger.vhd" +# add_file -vhdl -lib work "../trbnet/trb_net16_ipudata.vhd" +# add_file -vhdl -lib work "../trbnet/trb_net16_endpoint_hades_full.vhd" +# add_file -vhdl -lib work "../trbnet/trb_net_onewire_listener.vhd" add_file -vhdl -lib work "../trbnet/special/spi_master.vhd" add_file -vhdl -lib work "../trbnet/special/spi_slim.vhd" add_file -vhdl -lib work "../trbnet/special/spi_databus_memory.vhd" -add_file -vhdl -lib work "../trbnet/special/handler_data.vhd" -add_file -vhdl -lib work "../trbnet/special/handler_lvl1.vhd" -add_file -vhdl -lib work "../trbnet/special/handler_ipu.vhd" -add_file -vhdl -lib work "../trbnet/special/handler_trigger_and_data.vhd" +# add_file -vhdl -lib work "../trbnet/special/handler_data.vhd" +# add_file -vhdl -lib work "../trbnet/special/handler_lvl1.vhd" +# add_file -vhdl -lib work "../trbnet/special/handler_ipu.vhd" +# add_file -vhdl -lib work "../trbnet/special/handler_trigger_and_data.vhd" add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" add_file -vhdl -lib work "../trbnet/trb_net16_hub_base.vhd" add_file -vhdl -lib work "../trbnet/trb_net16_hub_logic.vhd" add_file -vhdl -lib work "../trbnet/trb_net16_hub_ipu_logic.vhd" -add_file -vhdl -lib work "../trbnet/trb_net16_endpoint_hades_full_handler.vhd" +# add_file -vhdl -lib work "../trbnet/trb_net16_endpoint_hades_full_handler.vhd" add_file -vhdl -lib work "../trbnet/special/trb_net_bridge_pcie_endpoint_hub.vhd" -add_file -vhdl -lib work "../trbnet/special/trb_net_bridge_pcie_endpoint.vhd" +# add_file -vhdl -lib work "../trbnet/special/trb_net_bridge_pcie_endpoint.vhd" add_file -vhdl -lib work "../trbnet/special/trb_net_bridge_pcie_apl.vhd" add_file -vhdl -lib work "../trbnet/basics/wide_adder_17x16.vhd" @@ -72,23 +72,23 @@ add_file -vhdl -lib work "../trbnet/lattice/scm/spi_dpram_32_to_8.vhd" add_file -vhdl -lib work "../trbnet/lattice/scm/lattice_scm_fifo_18x1k.vhd" add_file -vhdl -lib work "../trbnet/lattice/scm/trb_net16_fifo_arch.vhd" add_file -vhdl -lib work "../trbnet/special/trb_net_reset_handler.vhd" -add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_36x256_oreg.vhd" -add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_36x512_oreg.vhd" -add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_36x1k_oreg.vhd" -add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_36x2k_oreg.vhd" -add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_36x4k_oreg.vhd" -add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_36x8k_oreg.vhd" -add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_36x16k_oreg.vhd" -add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_36x32k_oreg.vhd" -add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_18x256_oreg.vhd" -add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_18x512_oreg.vhd" -add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_18x1k_oreg.vhd" -add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_18x2k_oreg.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_36x256_oreg.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_36x512_oreg.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_36x1k_oreg.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_36x2k_oreg.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_36x4k_oreg.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_36x8k_oreg.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_36x16k_oreg.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_36x32k_oreg.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_18x256_oreg.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_18x512_oreg.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_18x1k_oreg.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_18x2k_oreg.vhd" add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_19x16_obuf.vhd" add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_var_oreg.vhd" add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_med_scm_sfp_gbe.vhd" -add_file -vhdl -lib work "../trbnet/media_interfaces/scm_sfp/serdes_gbe_0_200.vhd" -add_file -vhdl -lib work "../trbnet/media_interfaces/scm_sfp/serdes_gbe_0_100.vhd" +# add_file -vhdl -lib work "../trbnet/media_interfaces/scm_sfp/serdes_gbe_0_200.vhd" +# add_file -vhdl -lib work "../trbnet/media_interfaces/scm_sfp/serdes_gbe_0_100.vhd" add_file -vhdl -lib work "../trbnet/media_interfaces/scm_sfp/serdes_gbe_0_100_ext.vhd" add_file -vhdl -lib work "../trbnet/media_interfaces/scm_sfp/serdes_100_ext.vhd" add_file -vhdl -lib work "../trbnet/lattice/scm/trb_net_fifo_16bit_bram_dualport.vhd" @@ -101,9 +101,12 @@ add_file -vhdl -lib work "design/wb_tlc.vhd" add_file -vhdl -lib work "design/wb_tlc_cpld.vhd" add_file -vhdl -lib work "design/cores/cpld_fifo.vhd" add_file -vhdl -lib work "../trbnet/lattice/scm/fifo_72x512.vhd" +add_file -vhdl -lib work "design/dma_core.vhd" add_file -verilog "/d/sugar/lattice/diamond/1.1/cae_library/synthesis/verilog/scm.v" +add_file -vhdl -lib work "design/cores/fifo_32to64x512_dualclock.vhd" +add_file -vhdl -lib work "design/cores/fifo_8x512_dualclock.vhd" add_file -vhdl -lib work "design/pci_core.vhd" add_file -verilog "vcode/pci_exp_ddefines.v" add_file -verilog "vcode/pci_exp_params.v" @@ -113,15 +116,16 @@ add_file -verilog "vcode/ip_tx_arbiter.v" add_file -verilog "vcode/UR_gen.v" -add_file -verilog "vcode/tx_fifo.v" -add_file -verilog "vcode/tx_cpld_fifo.v" -add_file -verilog "vcode/rx_ram_dp.v" -add_file -verilog "vcode/dma_rx_fifo.v" -add_file -verilog "vcode/dma_tx_fifo.v" -add_file -verilog "vcode/dma_ca.v" -add_file -verilog "vcode/dma_ctrl.v" -add_file -verilog "vcode/dma_wbs.v" -add_file -verilog "vcode/dma_adapter.v" +# add_file -verilog "vcode/tx_fifo.v" +# add_file -verilog "vcode/tx_cpld_fifo.v" +# add_file -verilog "vcode/rx_ram_dp.v" +# add_file -verilog "vcode/dma_rx_fifo.v" +# add_file -verilog "vcode/dma_tx_fifo.v" +# add_file -verilog "vcode/dma_ca.v" +# add_file -verilog "vcode/dma_ctrl.v" +# add_file -verilog "vcode/dma_wbs.v" +# add_file -verilog "vcode/dma_adapter.v" + add_file -verilog "vcode/tlc_fifo.v" diff --git a/pexor.vhd b/pexor.vhd index 14484c3..b9eba72 100644 --- a/pexor.vhd +++ b/pexor.vhd @@ -39,6 +39,7 @@ entity pexor is SPI_SCK_OUT : out std_logic; SPI_CS_OUT : out std_logic; SPI_SI_OUT : out std_logic; + PROGRMN_OUT : out std_logic; --Tempsens SDA_TMP : inout std_logic; SCK_TMP : out std_logic; @@ -133,20 +134,6 @@ architecture pexor_arch of pexor is signal bus_ack : std_logic; - signal dma_addr : std_logic_vector(31 downto 0); - signal dma_dout : std_logic_vector(63 downto 0); - signal dma_din : std_logic_vector(63 downto 0); - signal dma_sel : std_logic_vector(7 downto 0); - signal dma_we : std_logic; - signal dma_cyc : std_logic; - signal dma_stb : std_logic; - signal dma_lock : std_logic; - signal dma_cti : std_logic_vector(2 downto 0); - signal dma_ack : std_logic; - signal dma_err : std_logic; - signal dma_retry : std_logic; - signal dma_eod : std_logic; - signal debug_pci_core : std_logic_vector(31 downto 0); signal send_network_reset : std_logic; signal send_network_reset_falling : std_logic; @@ -155,6 +142,27 @@ architecture pexor_arch of pexor is signal res_cnt : unsigned(4 downto 0); + signal tx_st_in : std_logic; --tx first word + signal tx_end_in : std_logic; --tx last word + signal tx_dwen_in : std_logic; --tx use only upper 32 bit + signal tx_data_in : std_logic_vector(63 downto 0); --tx data out + signal tx_req_in : std_logic; --tx request out + signal tx_rdy_out : std_logic; --tx arbiter can read + signal tx_val_out : std_logic; --tx data is valid + signal tx_ca_ph_out : std_logic_vector(8 downto 0); --header credit for write + signal tx_ca_pd_out : std_logic_vector(12 downto 0); --data credits in 32 bit words + signal tx_ca_nph_out : std_logic_vector(8 downto 0); --header credit for read + + signal rx_cr_cplh_in : std_logic; + signal rx_cr_cpld_in : std_logic_vector(7 downto 0); + signal unexp_cmpl_in : std_logic; + signal rx_st_out : std_logic; + signal rx_end_out : std_logic; + signal rx_dwen_out : std_logic; + signal rx_data_out : std_logic_vector(63 downto 0); + signal requestor_id : std_logic_vector(15 downto 0); + signal debug_endpoint : std_logic_vector(31 downto 0); + begin --------------------------------------------------------------------------- @@ -310,6 +318,7 @@ med_stat_op(31 downto 16) <= x"000" & "0111"; port map( RESET => reset_i_trbnet, CLK => clk_150_i, + CLK_125_IN => clk_125_i, BUS_ADDR_IN => bus_addr, BUS_WDAT_IN => bus_dout, @@ -321,6 +330,11 @@ med_stat_op(31 downto 16) <= x"000" & "0111"; BUS_LOCK_IN => bus_lock, BUS_ACK_OUT => bus_ack, + SPI_CLK_OUT => SPI_SCK_OUT, + SPI_D_OUT => SPI_SI_OUT, + SPI_D_IN => SPI_D_IN, + SPI_CE_OUT => SPI_CS_OUT, + MED_DATAREADY_IN => med_dataready_in, MED_DATA_IN => med_data_in, MED_PACKET_NUM_IN => med_packet_num_in, @@ -331,12 +345,33 @@ med_stat_op(31 downto 16) <= x"000" & "0111"; MED_PACKET_NUM_OUT => med_packet_num_out, MED_READ_IN => med_read_in, + --DMA + REQUESTOR_ID_IN => requestor_id, + TX_ST_OUT => tx_st_in, + TX_END_OUT => tx_end_in, + TX_DWEN_OUT => tx_dwen_in, + TX_DATA_OUT => tx_data_in, + TX_REQ_OUT => tx_req_in, + TX_RDY_IN => tx_rdy_out, + TX_VAL_IN => tx_val_out, + TX_CA_PH_IN => tx_ca_ph_out, + TX_CA_PD_IN => tx_ca_pd_out, + TX_CA_NPH_IN => tx_ca_nph_out, + + RX_CR_CPLH_OUT => rx_cr_cplh_in, + RX_CR_CPLD_OUT => rx_cr_cpld_in, + UNEXP_CMPL_OUT => unexp_cmpl_in, + RX_ST_IN => rx_st_out, + RX_END_IN => rx_end_out, + RX_DWEN_IN => rx_dwen_out, + RX_DATA_IN => rx_data_out, MED_STAT_OP_IN => med_stat_op, MED_CTRL_OP_OUT => buf_med_ctrl_op, SEND_RESET_OUT => send_network_reset, - DEBUG_OUT => open + PROGRMN_OUT => open, + DEBUG_OUT => debug_endpoint ); --------------------------------------------------------------------------- @@ -371,19 +406,25 @@ med_stat_op(31 downto 16) <= x"000" & "0111"; BUS_ACK_IN => bus_ack, --DMA - DMA_ADDR => dma_addr, - DMA_WDAT => dma_din, - DMA_RDAT => dma_dout, - DMA_SEL => dma_sel, - DMA_WE => dma_we, - DMA_CYC => dma_cyc, - DMA_STB => dma_stb, - DMA_LOCK => dma_lock, - DMA_CTI => dma_cti, - DMA_ACK => dma_ack, - DMA_ERR => dma_err, - DMA_RETRY => dma_retry, - DMA_EOD => dma_eod, + REQUESTOR_ID_OUT => requestor_id, + TX_ST_IN => tx_st_in, + TX_END_IN => tx_end_in, + TX_DWEN_IN => tx_dwen_in, + TX_DATA_IN => tx_data_in, + TX_REQ_IN => tx_req_in, + TX_RDY_OUT => tx_rdy_out, + TX_VAL_OUT => tx_val_out, + TX_CA_PH_OUT => tx_ca_ph_out, + TX_CA_PD_OUT => tx_ca_pd_out, + TX_CA_NPH_OUT => tx_ca_nph_out, + + RX_CR_CPLH_IN => rx_cr_cplh_in, + RX_CR_CPLD_IN => rx_cr_cpld_in, + UNEXP_CMPL_IN => unexp_cmpl_in, + RX_ST_OUT => rx_st_out, + RX_END_OUT => rx_end_out, + RX_DWEN_OUT => rx_dwen_out, + RX_DATA_OUT => rx_data_out, --Debug DEBUG_OUT => debug_pci_core @@ -392,16 +433,13 @@ med_stat_op(31 downto 16) <= x"000" & "0111"; - --------------------------------------------------------------------------- -- Unused IO --------------------------------------------------------------------------- SFP2_TX_DIS <= '1'; SFP3_TX_DIS <= '1'; SFP4_TX_DIS <= '1'; - SPI_SCK_OUT <= '0'; - SPI_CS_OUT <= '0'; - SPI_SI_OUT <= '0'; + SDA_TMP <= '0'; SCK_TMP <= '0'; plluser <= (others => '0'); @@ -424,18 +462,20 @@ med_stat_op(31 downto 16) <= x"000" & "0111"; led(7) <= not send_network_reset; - test(3 downto 0) <= bus_din(3 downto 0); - test(4) <= bus_dout(0); - - - test(5) <= bus_we; - test(6) <= bus_stb; - test(7) <= bus_ack; - --- test(15 downto 8) <= debug_pci_core(23 downto 16); - test(8) <= bus_ack; - test(9) <= bus_dout(15); - test(15 downto 10) <= debug_pci_core(21 downto 16); +-- test(3 downto 0) <= bus_din(3 downto 0); +-- test(4) <= bus_dout(0); +-- +-- +-- test(5) <= bus_we; +-- test(6) <= bus_stb; +-- test(7) <= bus_ack; +-- +-- -- test(15 downto 8) <= debug_pci_core(23 downto 16); +-- test(8) <= bus_ack; +-- test(9) <= bus_dout(15); +-- test(15 downto 10) <= debug_pci_core(21 downto 16); + + test(15 downto 0) <= debug_endpoint(15 downto 0); -- test(3 downto 0) <= med_stat_op(7 downto 4); --fsm state -- test(5 downto 4) <= med_stat_debug(46 downto 45); --tx_k diff --git a/size.txt b/size.txt index dad804c..468b3e4 100644 --- a/size.txt +++ b/size.txt @@ -115,4 +115,22 @@ MACO 2/10 20% used -22.01.11 + + +02.02.11 + IO 94/788 11% used + LOGIC 11536/20952 55% used + SPECIAL 51/462 11% used + + PIO (prelim) 94/696 13% used + 94/562 16% bonded + + SLICE 11516/20256 56% used + IOLOGIC 20/696 2% used + + GSR 1/1 100% used + PLL 2/8 25% used + CLKDIV 2/20 10% used + EBR 42/216 19% used + PCS 2/4 50% used + MACO 2/10 20% used -- 2.43.0