From c509c5568549f79fce5e303398ce8ac43ea99a72 Mon Sep 17 00:00:00 2001 From: Andreas Neiser Date: Tue, 9 Jun 2015 09:36:51 +0200 Subject: [PATCH] Try to fix readout bug --- ADC/source/adc_handler.vhd | 15 +++++++++++---- ADC/source/adc_processor_cfd.vhd | 19 +++++++++++-------- 2 files changed, 22 insertions(+), 12 deletions(-) diff --git a/ADC/source/adc_handler.vhd b/ADC/source/adc_handler.vhd index 53867a6..6e875b2 100644 --- a/ADC/source/adc_handler.vhd +++ b/ADC/source/adc_handler.vhd @@ -87,6 +87,9 @@ architecture adc_handler_arch of adc_handler is signal trigger_in_i : std_logic; type state_cfd_t is (IDLE, DO_RELEASE, RELEASE_DIRECT, WAIT_FOR_END, WRITE_EPOCH); signal state_cfd : state_cfd_t; + + signal RDO_CFD_write : std_logic := '0'; + signal RDO_CFD_data : std_logic_vector(31 downto 0) := (others => '0'); -- 000 - 0ff configuration -- 000 reset, buffer clear strobes @@ -224,6 +227,8 @@ begin adc_stop <= buffer_ctrl_reg(0); config.baseline_always_on <= buffer_ctrl_reg(4); + READOUT_TX_CFD.data_finished <= '1'; + PROC_BUS : process begin wait until rising_edge(CLK); @@ -417,8 +422,10 @@ begin epoch_counter_save_sys <= epoch_counter_save; READOUT_TX_CFD.busy_release <= '0'; READOUT_TX_CFD.data_finished <= '0'; - READOUT_TX_CFD.data <= (others => '0'); - READOUT_TX_CFD.data_write <= '0'; + READOUT_TX_CFD.data <= RDO_CFD_data; + READOUT_TX_CFD.data_write <= RDO_CFD_write; + RDO_CFD_data <= (others => '0'); + RDO_CFD_write <= '0'; case state_cfd is when IDLE => @@ -448,8 +455,8 @@ begin end if; when WRITE_EPOCH => - READOUT_TX_CFD.data <= x"1" & std_logic_vector(resize(epoch_counter_save_sys,28)); - READOUT_TX_CFD.data_write <= '1'; + RDO_CFD_data <= x"1" & std_logic_vector(resize(epoch_counter_save_sys,28)); + RDO_CFD_write <= '1'; state_cfd <= RELEASE_DIRECT; end case; end process PROC_READOUT_CFD; diff --git a/ADC/source/adc_processor_cfd.vhd b/ADC/source/adc_processor_cfd.vhd index 3a9931b..eb1707d 100644 --- a/ADC/source/adc_processor_cfd.vhd +++ b/ADC/source/adc_processor_cfd.vhd @@ -65,6 +65,9 @@ architecture arch of adc_processor_cfd is signal busy_in_adc, busy_in_sys : std_logic := '0'; signal busy_out_adc, busy_out_sys : std_logic_vector(CHANNELS-1 downto 0) := (others => '0'); + signal RDO_write : std_logic := '0'; + signal RDO_data : std_logic_vector(31 downto 0) := (others => '0'); + --type epoch_counter_t is array(CHANNELS - 1 downto 0) of unsigned(23 downto 0); --signal epoch_counter, epoch_counter_save : epoch_counter_t; --signal epoch_counter_sys, epoch_counter_adc : epoch_counter_t; @@ -119,8 +122,8 @@ begin Q => ram_data_sys(i)); end generate; - -- <= RDO_write_main when rising_edge(CLK_SYS); - --READOUT_TX.data <= RDO_data_main when rising_edge(CLK_SYS); + READOUT_TX.data_write <= RDO_write when rising_edge(CLK_SYS); + READOUT_TX.data <= RDO_data when rising_edge(CLK_SYS); readout_reset <= CONTROL(12) when rising_edge(CLK_SYS); statebits <= std_logic_vector(to_unsigned(state_t'pos(state), 8)); @@ -131,8 +134,8 @@ begin wait until rising_edge(CLK_SYS); READOUT_TX.busy_release <= '0'; READOUT_TX.data_finished <= '0'; - READOUT_TX.data <= (others => '0'); - READOUT_TX.data_write <= '0'; + RDO_data <= (others => '0'); + RDO_write <= '0'; busy_in_sys <= '0'; @@ -217,15 +220,15 @@ begin state <= WAIT_BSY; end if; else - READOUT_TX.data <= ram_data_sys(channelselect); - READOUT_TX.data_write <= not CONF_sys.ChannelDisable(DEVICE * CHANNELS + channelselect); + RDO_data <= ram_data_sys(channelselect); + RDO_write <= not CONF_sys.ChannelDisable(DEVICE * CHANNELS + channelselect); ram_counter(channelselect) <= ram_counter(channelselect) + 1; end if; when SEND_STATUS => - READOUT_TX.data_write <= '1'; - READOUT_TX.data <= x"20000000"; + RDO_write <= '1'; + RDO_data <= x"20000000"; -- nothing implemented yet state <= RELEASE_DIRECT; end case; -- 2.43.0