From c5296abf61a0d3acc78e1cca971924f17a8f3663 Mon Sep 17 00:00:00 2001 From: Adrian Weber Date: Fri, 2 Oct 2020 13:54:51 +0200 Subject: [PATCH] combiner CTS with calibration and TDC activated. --- combiner_cts/code_EBR/Calibration.vhd | 14 +++++- combiner_cts/combiner.vhd | 62 +++++++++++++-------------- combiner_cts/config.vhd | 16 +++---- 3 files changed, 51 insertions(+), 41 deletions(-) diff --git a/combiner_cts/code_EBR/Calibration.vhd b/combiner_cts/code_EBR/Calibration.vhd index 012a4db..892c644 100644 --- a/combiner_cts/code_EBR/Calibration.vhd +++ b/combiner_cts/code_EBR/Calibration.vhd @@ -42,7 +42,17 @@ entity TDC_Calibration is ); end TDC_Calibration; -architecture Behavioral of TDC_Calibration is +architecture TDC_Calibration_arch of TDC_Calibration is + + -- Placer Directives + attribute HGROUP : string; + -- for whole architecture + attribute HGROUP of TDC_Calibration_arch : architecture is "calibration_group"; + attribute syn_sharing : string; + attribute syn_sharing of TDC_Calibration_arch : architecture is "off"; + attribute syn_hier : string; + attribute syn_hier of TDC_Calibration_arch : architecture is "hard"; + signal Dout_int : std_logic_vector(21 downto 0); signal DIN_i_Mem : std_logic_vector(31 downto 0) := (others => '0'); signal DIN_i_Mem_ready : std_logic; @@ -677,4 +687,4 @@ begin end process; end generate TX_stat; -end Behavioral; +end TDC_Calibration_arch; diff --git a/combiner_cts/combiner.vhd b/combiner_cts/combiner.vhd index d0ff924..3021cc9 100644 --- a/combiner_cts/combiner.vhd +++ b/combiner_cts/combiner.vhd @@ -153,8 +153,8 @@ architecture arch of combiner is signal back_slave_ready_i : std_logic_vector(12 downto 1); signal master_ready_override_i : std_logic_vector(12 downto 1); - signal monitor_inputs_i : std_logic_vector(MONITOR_INPUT_NUM-1 downto 0); - signal trig_gen_out_i : std_logic_vector(TRIG_GEN_OUTPUT_NUM-1 downto 0); + --signal monitor_inputs_i : std_logic_vector(MONITOR_INPUT_NUM-1 downto 0); + --signal trig_gen_out_i : std_logic_vector(TRIG_GEN_OUTPUT_NUM-1 downto 0); signal trigger_busy_i : std_logic; signal cts_trigger_out : std_logic; @@ -1050,9 +1050,9 @@ THE_CRI_INTERFACE : entity work.trb_net16_cri_interface ADC_MISO => ADC_DOUT, ADC_CLK => ADC_CLK, --Trigger & Monitor - MONITOR_INPUTS => monitor_inputs_i(25 downto 0), - TRIG_GEN_INPUTS => monitor_inputs_i(23 downto 0), - TRIG_GEN_OUTPUTS => trig_gen_out_i, + MONITOR_INPUTS => (others => '0'),--monitor_inputs_i(25 downto 0), + TRIG_GEN_INPUTS => (others => '0'),--monitor_inputs_i(23 downto 0), + TRIG_GEN_OUTPUTS => open,--trig_gen_out_i, --SED SED_ERROR_OUT => sed_error_i, --Slowcontrol @@ -1112,38 +1112,38 @@ THE_CRI_INTERFACE : entity work.trb_net16_cri_interface --cts_ext_trigger <= TRIGGER_IN; -- TRIGGER_OUT <= cts_trigger_out; -- trigger from internal CTS to DiRICH/Power - monitor_inputs_i(11 downto 0) <= BACK_TRIG1; - monitor_inputs_i(23 downto 12) <= BACK_TRIG2; - monitor_inputs_i(25 downto 24) <= trig_gen_out_i(1 downto 0); + --monitor_inputs_i(11 downto 0) <= BACK_TRIG1; + --monitor_inputs_i(23 downto 12) <= BACK_TRIG2; + --monitor_inputs_i(25 downto 24) <= trig_gen_out_i(1 downto 0); ------------------------------------------------------------------------------- -- TDC ------------------------------------------------------------------------------- --gen_TDC: if (INCLUDE_TDC = c_YES) generate --- THE_TDC : entity work.TDC_record --- generic map ( --- CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels per module --- STATUS_REG_NR => 21, -- Number of status regs --- DEBUG => c_YES, --- SIMULATION => c_NO) --- port map ( --- RESET => reset_i, --- CLK_TDC => clk_full_osc, --- CLK_READOUT => clk_sys, -- Clock for the readout --- REFERENCE_TIME => cts_trigger_out, -- Reference time input --- HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals --- HIT_CAL_IN => clk_full_osc,--clk_cal, -- Hits for calibrating the TDC --FIXME: here we need a good cal clock! --- -- Trigger signals from handler --- BUSRDO_RX => cts_rdo_rx, --- BUSRDO_TX => cts_rdo_additional(INCLUDE_ETM),--_TDCcal --- -- Slow control bus --- BUS_RX => bustdc_rx, --- BUS_TX => bustdc_tx, --- -- Dubug signals --- INFO_IN => timer, --- LOGIC_ANALYSER_OUT => open --- ); + THE_TDC : entity work.TDC_record + generic map ( + CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels per module + STATUS_REG_NR => 21, -- Number of status regs + DEBUG => c_YES, + SIMULATION => c_NO) + port map ( + RESET => reset_i, + CLK_TDC => clk_full_osc, + CLK_READOUT => clk_sys, -- Clock for the readout + REFERENCE_TIME => cts_trigger_out, -- Reference time input + HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals + HIT_CAL_IN => clk_full_osc,--clk_cal, -- Hits for calibrating the TDC --FIXME: here we need a good cal clock! + -- Trigger signals from handler + BUSRDO_RX => cts_rdo_rx, + BUSRDO_TX => cts_rdo_additional(INCLUDE_ETM),--_TDCcal + -- Slow control bus + BUS_RX => bustdc_rx, + BUS_TX => bustdc_tx, + -- Dubug signals + INFO_IN => timer, + LOGIC_ANALYSER_OUT => open + ); -- end generate;--TDC -- For single edge measurements diff --git a/combiner_cts/config.vhd b/combiner_cts/config.vhd index d066aaf..2c6fc1c 100644 --- a/combiner_cts/config.vhd +++ b/combiner_cts/config.vhd @@ -44,14 +44,14 @@ package config is --input monitor and trigger generation logic - constant INCLUDE_CALIBRATION : integer := c_NO; - constant INCLUDE_TDC : integer := c_NO;--YES; -- IMPORTANT: TDC part into entity has to be commented in/out by hand + constant INCLUDE_CALIBRATION : integer := c_YES; + constant INCLUDE_TDC : integer := c_YES; -- IMPORTANT: TDC part into entity has to be commented in/out by hand -- (no generic possible due to constraints naming) - constant INCLUDE_TRIGGER_LOGIC : integer := c_YES; + constant INCLUDE_TRIGGER_LOGIC : integer := c_NO; constant INCLUDE_STATISTICS : integer := c_YES; - constant TRIG_GEN_INPUT_NUM : integer := 24; - constant TRIG_GEN_OUTPUT_NUM : integer := 2; - constant MONITOR_INPUT_NUM : integer := 26; + constant TRIG_GEN_INPUT_NUM : integer := 0; + constant TRIG_GEN_OUTPUT_NUM : integer := 0; + constant MONITOR_INPUT_NUM : integer := 32; constant INCLUDE_GBE : integer := c_NO; @@ -59,9 +59,9 @@ package config is constant GEN_BUSY_OUTPUT : integer := c_NO; constant TRIGGER_COIN_COUNT : integer := 1; - constant TRIGGER_PULSER_COUNT : integer := 3; + constant TRIGGER_PULSER_COUNT : integer := 2; constant TRIGGER_RAND_PULSER : integer := 1; - constant TRIGGER_ADDON_COUNT : integer := 4; + constant TRIGGER_ADDON_COUNT : integer := 2; constant PERIPH_TRIGGER_COUNT : integer := 0; constant ADDON_LINE_COUNT : integer := 2;--44; constant CTS_OUTPUT_MULTIPLEXERS : integer := 1; -- 2.43.0