From c5806d2d32e2defdd94e07c8d5a18e2b8f310695 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Tue, 5 May 2015 18:01:19 +0200 Subject: [PATCH] new files for fpgatest design --- fpgatest/code/cdt_test.vhd | 186 +++++++++ fpgatest/code/pll.ipx | 8 + fpgatest/code/pll.lpc | 69 ++++ fpgatest/code/pll.vhd | 123 ++++++ fpgatest/compile_constraints.pl | 15 + fpgatest/compile_periph_frankfurt.pl | 123 ++++++ fpgatest/config.vhd | 80 ++++ fpgatest/trb3_central.p2t | 21 + fpgatest/trb3_periph_test.prj | 157 ++++++++ fpgatest/trb3_periph_test.vhd | 467 ++++++++++++++++++++++ fpgatest/trb3_periph_test_constraints.lpf | 32 ++ 11 files changed, 1281 insertions(+) create mode 100644 fpgatest/code/cdt_test.vhd create mode 100644 fpgatest/code/pll.ipx create mode 100644 fpgatest/code/pll.lpc create mode 100644 fpgatest/code/pll.vhd create mode 100755 fpgatest/compile_constraints.pl create mode 100755 fpgatest/compile_periph_frankfurt.pl create mode 100644 fpgatest/config.vhd create mode 100644 fpgatest/trb3_central.p2t create mode 100644 fpgatest/trb3_periph_test.prj create mode 100644 fpgatest/trb3_periph_test.vhd create mode 100644 fpgatest/trb3_periph_test_constraints.lpf diff --git a/fpgatest/code/cdt_test.vhd b/fpgatest/code/cdt_test.vhd new file mode 100644 index 0000000..f7cf606 --- /dev/null +++ b/fpgatest/code/cdt_test.vhd @@ -0,0 +1,186 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.trb_net_std.all; + +entity cdt_test is + port( + CLK_200 : in std_logic; + + CLK_100 : in std_logic; + BUS_RX : in CTRLBUS_RX; + BUS_TX : out CTRLBUS_TX; + + + DEBUG : out std_logic_vector(31 downto 0) + ); +end entity; + + +architecture cdt_arch of cdt_test is + +component pll is + port ( + CLK: in std_logic; + RESET: in std_logic; + FINEDELB0: in std_logic; + FINEDELB1: in std_logic; + FINEDELB2: in std_logic; + FINEDELB3: in std_logic; + DPHASE0: in std_logic; + DPHASE1: in std_logic; + DPHASE2: in std_logic; + DPHASE3: in std_logic; + CLKOP: out std_logic; + CLKOS: out std_logic; + CLKOK: out std_logic; + LOCK: out std_logic); +end component; + + signal clk_200_i, clk_100_i : std_logic; + signal pll_lock : std_logic; + signal dphase, finedel : std_logic_vector(3 downto 0); + + signal reset : std_logic; + + signal ct_fifo_write, ct_fifo_read : std_logic; + signal ct_fifo_empty, ct_fifo_full : std_logic; + signal ct_fifo_dout, ct_fifo_din : std_logic_vector(17 downto 0); + + signal last_fifo_read, fifo_valid : std_logic; + signal last_data : std_logic_vector(17 downto 0); + signal error_flag : std_logic; + + signal timer : unsigned(3 downto 0) := (others => '0'); + signal input_counter : unsigned(17 downto 0); + + signal reg : std_logic_vector(31 downto 0) := x"00000400"; + +begin + + +proc_reg : process begin + wait until rising_edge(CLK_100); + if BUS_RX.write = '1' then + BUS_TX.ack <= '1'; + reg <= BUS_RX.data; + else + BUS_TX.ack <= '0'; + end if; + BUS_TX.unknown <= '0'; + BUS_TX.nack <= '0'; +end process; + + + +reset <= not pll_lock or reg(0); + +---------------------------------------------------------------------- +-- The PLL +---------------------------------------------------------------------- +--finedel: x*130ps +--dphase: 1/16 clock cycle of 200, 312 ps + +-- output: 200 MHz, can be shifted plus a fixed 100 Mhz + +THE_PLL : pll + port map( + CLK => CLK_200, + RESET => reg(0), + FINEDELB0 => finedel(0), + FINEDELB1 => finedel(1), + FINEDELB2 => finedel(2), + FINEDELB3 => finedel(3), + DPHASE0 => dphase(0), + DPHASE1 => dphase(1), + DPHASE2 => dphase(2), + DPHASE3 => dphase(3), + CLKOP => open, + CLKOS => clk_200_i, + CLKOK => clk_100_i, + LOCK => pll_lock + ); + + +dphase <= reg(11 downto 8); +finedel <= reg( 7 downto 4); + +---------------------------------------------------------------------- +-- Clock Domain Transfer +---------------------------------------------------------------------- +THE_CT_FIFO : entity work.lattice_ecp3_fifo_18x16_dualport_oreg + port map( + Data => ct_fifo_din, + WrClock => clk_200_i, + RdClock => clk_100_i, + WrEn => ct_fifo_write, + RdEn => ct_fifo_read, + Reset => reset, + RPReset => reset, + Q(17 downto 0) => ct_fifo_dout, + Empty => ct_fifo_empty, + Full => ct_fifo_full, + AlmostFull => open + ); + + + +-- writes increasing numbers into the fifo, every second clock cycle, and a pause after five values +proc_input : process begin + wait until rising_edge(clk_200_i); + timer <= timer + 1; + + ct_fifo_din <= std_logic_vector(input_counter); + ct_fifo_write <= '0'; + + case timer is + when 0 => input_counter <= input_counter + 1; + when 1 => ct_fifo_write <= '1'; + when 2 => input_counter <= input_counter + 1; + when 3 => ct_fifo_write <= '1'; + when 4 => input_counter <= input_counter + 1; + when 5 => ct_fifo_write <= '1'; + when 6 => input_counter <= input_counter + 1; + when 7 => ct_fifo_write <= '1'; + when 8 => input_counter <= input_counter + 1; + when 9 => ct_fifo_write <= '1'; + when 12 => timer <= x"0"; + when others => null; + end case; + + if reset = '1' then + timer <= x"1"; + input_counter <= (others => '0'); + end if; +end process; + + + +ct_fifo_read <= not ct_fifo_empty; + +-- read from fifo when not empty, compare read value with last one +proc_output : process begin + wait until rising_edge(clk_100_i); + + last_fifo_read <= ct_fifo_read; + fifo_valid <= last_fifo_read; + + error_flag <= '0'; + + if fifo_valid = '1' then + last_data <= ct_fifo_dout; + if unsigned(last_data) + 1 /= unsigned(ct_fifo_dout) then + error_flag <= '1'; + end if; + end if; + +end process; + +DEBUG(11 downto 0) <= ct_fifo_din(11 downto 0); +DEBUG(27 downto 16) <= ct_fifo_dout(11 downto 0); +DEBUG(28) <= ct_fifo_write; +DEBUG(29) <= ct_fifo_read; +DEBUG(30) <= ct_fifo_empty; +DEBUG(31) <= error_flag; + +end architecture; \ No newline at end of file diff --git a/fpgatest/code/pll.ipx b/fpgatest/code/pll.ipx new file mode 100644 index 0000000..b566c2b --- /dev/null +++ b/fpgatest/code/pll.ipx @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/fpgatest/code/pll.lpc b/fpgatest/code/pll.lpc new file mode 100644 index 0000000..8f3361c --- /dev/null +++ b/fpgatest/code/pll.lpc @@ -0,0 +1,69 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN672C +SpeedGrade=8 +Package=FPBGA672 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PLL +CoreRevision=5.7 +ModuleName=pll +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=04/17/2015 +Time=17:34:37 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=None +Order=None +IO=0 +Type=ehxpllb +mode=normal +IFrq=200 +Div=1 +ClkOPBp=0 +Post=4 +U_OFrq=200 +OP_Tol=0.0 +OFrq=200.000000 +DutyTrimP=Rising +DelayMultP=0 +fb_mode=CLKOP +Mult=1 +Phase=0.0 +Duty=8 +DelayMultS=0 +DPD=50% Duty +DutyTrimS=Rising +DelayMultD=0 +ClkOSDelay=0 +PhaseDuty=Dynamic +CLKOK_INPUT=CLKOP +SecD=2 +U_KFrq=100 +OK_Tol=0.0 +KFrq=100.000000 +ClkRst=0 +PCDR=1 +FINDELA=0 +VcoRate= +Bandwidth=2.970786 +;DelayControl=No +EnCLKOS=1 +ClkOSBp=0 +EnCLKOK=1 +ClkOKBp=0 +enClkOK2=0 + +[Command] +cmd_line= -w -n pll -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl DYNAMIC -fclkop 200 -fclkop_tol 0.0 -fb_mode CLOCKTREE -duty50 -fclkok 100 -fclkok_tol 0.0 -clkoki 0 -use_rst -noclkok2 -bw diff --git a/fpgatest/code/pll.vhd b/fpgatest/code/pll.vhd new file mode 100644 index 0000000..748ed4f --- /dev/null +++ b/fpgatest/code/pll.vhd @@ -0,0 +1,123 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80 +-- Module Version: 5.7 +--/d/jspc29/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n pll -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl DYNAMIC -fclkop 200 -fclkop_tol 0.0 -fb_mode CLOCKTREE -duty50 -fclkok 100 -fclkok_tol 0.0 -clkoki 0 -use_rst -noclkok2 -bw + +-- Fri Apr 17 17:34:37 2015 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity pll is + port ( + CLK: in std_logic; + RESET: in std_logic; + FINEDELB0: in std_logic; + FINEDELB1: in std_logic; + FINEDELB2: in std_logic; + FINEDELB3: in std_logic; + DPHASE0: in std_logic; + DPHASE1: in std_logic; + DPHASE2: in std_logic; + DPHASE3: in std_logic; + CLKOP: out std_logic; + CLKOS: out std_logic; + CLKOK: out std_logic; + LOCK: out std_logic); + attribute dont_touch : boolean; + attribute dont_touch of pll : entity is true; +end pll; + +architecture Structure of pll is + + -- internal signal declarations + signal CLKOS_t: std_logic; + signal DPHASE3_inv: std_logic; + signal CLKOP_t: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component EHXPLLF + generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String; + DELAY_PWD : in String; DELAY_VAL : in Integer; + CLKOS_TRIM_DELAY : in Integer; + CLKOS_TRIM_POL : in String; + CLKOP_TRIM_DELAY : in Integer; + CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String; + CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; + PHASE_DELAY_CNTL : in String; DUTY : in Integer; + PHASEADJ : in String; CLKOK_DIV : in Integer; + CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; + CLKI_DIV : in Integer; FIN : in String); + port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; + RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic; + DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; + DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; + DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic; + FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic; + CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic; + LOCK: out std_logic; CLKINTFB: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + attribute FREQUENCY_PIN_CLKOP : string; + attribute FREQUENCY_PIN_CLKOS : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute FREQUENCY_PIN_CLKOK : string; + attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "200.000000"; + attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "200.000000"; + attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000"; + attribute FREQUENCY_PIN_CLKOK of PLLInst_0 : label is "100.000000"; + attribute syn_keep : boolean; + attribute syn_noprune : boolean; + attribute syn_noprune of Structure : architecture is true; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + INV_0: INV + port map (A=>DPHASE3, Z=>DPHASE3_inv); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLInst_0: EHXPLLF + generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED", + CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED", + CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=> 0, + CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING", + CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING", + PHASE_DELAY_CNTL=> "DYNAMIC", DUTY=> 8, PHASEADJ=> "0.0", + CLKOK_DIV=> 2, CLKOP_DIV=> 4, CLKFB_DIV=> 1, CLKI_DIV=> 1, + FIN=> "200.000000") + port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>RESET, RSTK=>scuba_vlo, + WRDEL=>scuba_vlo, DRPAI3=>DPHASE3, DRPAI2=>DPHASE2, + DRPAI1=>DPHASE1, DRPAI0=>DPHASE0, DFPAI3=>DPHASE3_inv, + DFPAI2=>DPHASE2, DFPAI1=>DPHASE1, DFPAI0=>DPHASE0, + FDA3=>FINEDELB3, FDA2=>FINEDELB2, FDA1=>FINEDELB1, + FDA0=>FINEDELB0, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t, + CLKOK=>CLKOK, CLKOK2=>open, LOCK=>LOCK, CLKINTFB=>open); + + CLKOS <= CLKOS_t; + CLKOP <= CLKOP_t; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of pll is + for Structure + for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/fpgatest/compile_constraints.pl b/fpgatest/compile_constraints.pl new file mode 100755 index 0000000..6c84125 --- /dev/null +++ b/fpgatest/compile_constraints.pl @@ -0,0 +1,15 @@ +#!/usr/bin/perl +use Data::Dumper; +use warnings; +use strict; + +my $workdir = shift @ARGV || 'workdir'; +unless(-d $workdir) { + print "Creating workdir $workdir\n"; + mkdir $workdir or die "cant create $workdir: $!"; +} + +my $TOPNAME = "trb3_periph_test"; #Name of top-level entity + +system("cp ../base/trb3_periph.lpf $workdir/$TOPNAME.lpf"); +system("cat ".$TOPNAME."_constraints.lpf >> $workdir/$TOPNAME.lpf"); diff --git a/fpgatest/compile_periph_frankfurt.pl b/fpgatest/compile_periph_frankfurt.pl new file mode 100755 index 0000000..ecee22b --- /dev/null +++ b/fpgatest/compile_periph_frankfurt.pl @@ -0,0 +1,123 @@ +#!/usr/bin/perl +use Data::Dumper; +use warnings; +use strict; +use FileHandle; + + + +################################################################################### +#Settings for this project +my $TOPNAME = "trb3_periph_test"; #Name of top-level entity +my $lm_license_file_for_synplify = "1702\@hadeb05.gsi.de"; #"27000\@lxcad01.gsi.de"; +my $lm_license_file_for_par = "1702\@hadeb05.gsi.de"; + +my $lattice_path = '/d/jspc29/lattice/diamond/3.4_x64'; +my $synplify_path = '/d/jspc29/lattice/synplify/J-2014.09-SP2/'; +################################################################################### + + +$ENV{'PAR_DESIGN_NAME'}=$TOPNAME; +$ENV{'SYNPLIFY'}=$synplify_path; +$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1; +$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify; +my $tpmap = $TOPNAME . "_map" ; + + +my $FAMILYNAME="LatticeECP3"; +my $DEVICENAME="LFE3-150EA"; +my $PACKAGE="FPBGA672"; +my $SPEEDGRADE="8"; + +my $WORKDIR = "workdir"; +unless(-d $WORKDIR) { + mkdir $WORKDIR or die "can't create workdir '$WORKDIR': $!"; + system ("cd workdir; ../../base/linkdesignfiles.sh; cd ..;"); +} + +system ("./compile_constraints.pl"); +system ("../base/make_version_vhd.pl"); + + +#my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj"; +my $c="$lattice_path/bin/lin64/synpwrap -fg -options -batch $TOPNAME.prj"; +my $r=execute($c, "do_not_exit" ); +checksrr(); + +$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par; + +$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -path "../" -path "." -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |; +execute($c); + +$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|; +execute($c); + +$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|; +execute($c); + +$c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|; +execute($c); + +system("rm $TOPNAME.ncd"); + +#$c=qq|mpartrce -p "../$TOPNAME.p2t" -log "$TOPNAME.log" -o "$TOPNAME.rpt" -pr "$TOPNAME.prf" -tf "$TOPNAME.pt" "|.$TOPNAME.qq|_map.ncd" "$TOPNAME.ncd"|; +# $c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|; +$c=qq|$lattice_path/ispfpga/bin/lin/par -w -l 5 -i 6 -t 4 -c 0 -e 0 -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF $tpmap.ncd $TOPNAME.ncd $TOPNAME.prf|; +execute($c); + +$c=qq|$lattice_path/ispfpga/bin/lin/ltxt2ptxt $TOPNAME.ncd|; +execute($c); + +$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No $TOPNAME.ncd $TOPNAME.bit $TOPNAME.prf &|; +# $c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); + +# TWR Timing Report +$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); + +$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); + +#IOR IO Timing Report +$c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); + +chdir ".."; + +exit; + + + + +sub execute { + my ($c, $op) = @_; + #print "option: $op \n"; + $op = "" if(!$op); + print "\n\ncommand to execute: $c \n"; + $r=system($c); + if($r) { + print "$!"; + if($op ne "do_not_exit") { + exit; + } + } + return $r; + } + + +sub checksrr { + chdir "workdir"; + my $fh = new FileHandle("<$TOPNAME".".srr"); + my @a = <$fh>; + $fh -> close; + foreach (@a) { + if(/\@E:/) { + print "\n"; + $c="cat $TOPNAME.srr | grep \"\@E\""; + system($c); + print "\n\n"; + exit 129; + } + } + } \ No newline at end of file diff --git a/fpgatest/config.vhd b/fpgatest/config.vhd new file mode 100644 index 0000000..9abb4c4 --- /dev/null +++ b/fpgatest/config.vhd @@ -0,0 +1,80 @@ +library ieee; +USE IEEE.std_logic_1164.ALL; +use ieee.numeric_std.all; +use work.trb_net_std.all; + +package config is + + +------------------------------------------------------------------------------ +--Begin of design configuration +------------------------------------------------------------------------------ + +--Run wih 125 MHz instead of 100 MHz + constant USE_125_MHZ : integer := c_NO; --not implemented yet! + constant USE_EXTERNALCLOCK : integer := c_NO; --not implemented yet! + +--Use sync mode, RX clock for all parts of the FPGA + constant USE_RXCLOCK : integer := c_NO; --not implemented yet! + +--Address settings + constant INIT_ADDRESS : std_logic_vector := x"F3EE"; + constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"EE"; + + +------------------------------------------------------------------------------ +--End of design configuration +------------------------------------------------------------------------------ + + +------------------------------------------------------------------------------ +--Select settings by configuration +------------------------------------------------------------------------------ + type intlist_t is array(0 to 7) of integer; + type hw_info_t is array(0 to 7) of unsigned(31 downto 0); + constant HW_INFO_BASE : unsigned(31 downto 0) := x"91000000"; + + constant CLOCK_FREQUENCY_ARR : intlist_t := (100,125, others => 0); + constant MEDIA_FREQUENCY_ARR : intlist_t := (200,125, others => 0); + + --declare constants, filled in body + constant HARDWARE_INFO : std_logic_vector(31 downto 0); + constant CLOCK_FREQUENCY : integer; + constant MEDIA_FREQUENCY : integer; + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0); + + +end; + +package body config is +--compute correct configuration mode + + constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector( + HW_INFO_BASE ); + constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_125_MHZ); + constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_125_MHZ); + + + +function generateIncludedFeatures return std_logic_vector is + variable t : std_logic_vector(63 downto 0); +begin + t := (others => '0'); + t(63 downto 56) := std_logic_vector(to_unsigned(0,8)); --table version 20 + t(7 downto 0) := (others => '0'); --std_logic_vector(to_unsigned(ADC_SAMPLING_RATE,8)); + t(11 downto 8) := (others => '0'); --std_logic_vector(to_unsigned(ADC_PROCESSING_TYPE,4)); --processing type + t(14 downto 14) := "0"; --std_logic_vector(to_unsigned(ADC_BASELINE_LOGIC,1)); + t(15 downto 15) := "0"; --std_logic_vector(to_unsigned(ADC_TRIGGER_LOGIC,1)); + t(23 downto 16) := (others => '0'); --std_logic_vector(to_unsigned(ADC_CHANNELS,8)); + t(42 downto 42) := "1"; --std_logic_vector(to_unsigned(INCLUDE_SPI,1)); + t(44 downto 44) := "0"; --std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1)); + t(51 downto 48) := x"0";--std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4)); + t(52 downto 52) := std_logic_vector(to_unsigned(USE_125_MHZ,1)); + t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1)); + t(54 downto 54) := std_logic_vector(to_unsigned(USE_EXTERNALCLOCK,1)); + return t; +end function; + + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures; + +end package body; \ No newline at end of file diff --git a/fpgatest/trb3_central.p2t b/fpgatest/trb3_central.p2t new file mode 100644 index 0000000..a2ff9eb --- /dev/null +++ b/fpgatest/trb3_central.p2t @@ -0,0 +1,21 @@ +-w +-i 15 +-l 5 +-n 1 +-y +-s 15 +-t 19 +-c 1 +-e 2 +#-g guidefile.ncd +#-m nodelist.txt +# -w +# -i 6 +# -l 5 +# -n 1 +# -t 1 +# -s 1 +# -c 0 +# -e 0 +# +-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1 diff --git a/fpgatest/trb3_periph_test.prj b/fpgatest/trb3_periph_test.prj new file mode 100644 index 0000000..1c00af9 --- /dev/null +++ b/fpgatest/trb3_periph_test.prj @@ -0,0 +1,157 @@ + +# implementation: "workdir" +impl -add workdir -type fpga + +# device options +set_option -technology LATTICE-ECP3 +set_option -part LFE3_150EA +set_option -package FN672C +set_option -speed_grade -8 +set_option -part_companion "" + +# compilation/mapping options +set_option -default_enum_encoding sequential +set_option -symbolic_fsm_compiler 1 +set_option -top_module "trb3_periph_test" +set_option -resource_sharing true + +# map options +set_option -frequency 200 +set_option -fanout_limit 100 +set_option -disable_io_insertion 0 +set_option -retiming 0 +set_option -pipe 0 +#set_option -force_gsr +set_option -force_gsr false +set_option -fixgatedclocks false #3 +set_option -fixgeneratedclocks false #3 +set_option -compiler_compatible true + + +# simulation options +set_option -write_verilog 0 +set_option -write_vhdl 1 + +# automatic place and route (vendor) options +set_option -write_apr_constraint 0 + +# set result format/file last +project -result_format "edif" +project -result_file "workdir/trb3_periph_test.edf" + +#implementation attributes + +set_option -vlog_std v2001 +set_option -project_relative_includes 1 +impl -active "workdir" + +#################### + + + +#add_file options + +add_file -vhdl -lib work "version.vhd" +add_file -vhdl -lib work "config.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" +add_file -vhdl -lib "work" "../base/trb3_components.vhd" + +add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd" +add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd" +add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd" + +add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd" +add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" +add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd" + +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" + +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" +add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd" + +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" + +add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd" +add_file -vhdl -lib "work" "../base/cores/pll_in200_out40.vhd" +add_file -vhdl -lib "work" "../base/cores/pll_adc10bit.vhd" +add_file -vhdl -lib "work" "../base/cores/dqsinput_7x5.vhd" +add_file -vhdl -lib "work" "../base/cores/dqsinput_5x5.vhd" +add_file -vhdl -lib "work" "../base/cores/fifo_cdt_200_50.vhd" +add_file -vhdl -lib "work" "../base/code/sedcheck.vhd" + + +add_file -vhdl -lib "work" "code/cdt_test.vhd" +add_file -vhdl -lib "work" "code/pll.vhd" + +add_file -vhdl -lib "work" "trb3_periph_test.vhd" +#add_file -constraint "trb3_periph_test.sdc" diff --git a/fpgatest/trb3_periph_test.vhd b/fpgatest/trb3_periph_test.vhd new file mode 100644 index 0000000..1ef7427 --- /dev/null +++ b/fpgatest/trb3_periph_test.vhd @@ -0,0 +1,467 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.version.all; +use work.config.all; + + + +entity trb3_periph_test is + port( + --Clocks + CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz + CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA + CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right! + CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right! + + --Trigger + TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out + TRIGGER_RIGHT : in std_logic; --right side trigger input from fan-out + + --Serdes + CLK_SERDES_INT_LEFT : in std_logic; --Clock Manager 1/(1357), off, 125 MHz possible + CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 2/(1357), 200 MHz, only in case of problems + SERDES_INT_TX : out std_logic_vector(3 downto 0); + SERDES_INT_RX : in std_logic_vector(3 downto 0); + SERDES_ADDON_TX : out std_logic_vector(11 downto 0); + SERDES_ADDON_RX : in std_logic_vector(11 downto 0); + + --Inter-FPGA Communication + FPGA5_COMM : inout std_logic_vector(11 downto 0); + --Bit 0/1 input, serial link RX active + --Bit 2/3 output, serial link TX active + --others yet undefined + --Connection to AddOn + SPARE_LINE : inout std_logic_vector(5 downto 0); --inputs only + DQUL : inout std_logic_vector(45 downto 0); + DQLL : inout std_logic_vector(47 downto 0); + DQUR : inout std_logic_vector(33 downto 0); + DQLR : inout std_logic_vector(35 downto 0); + + --Flash ROM & Reboot + FLASH_CLK : out std_logic; + FLASH_CS : out std_logic; + FLASH_DIN : out std_logic; + FLASH_DOUT : in std_logic; + PROGRAMN : out std_logic; --reboot FPGA + + --Misc + TEMPSENS : inout std_logic; --Temperature Sensor + CODE_LINE : in std_logic_vector(1 downto 0); + LED_GREEN : out std_logic; + LED_ORANGE : out std_logic; + LED_RED : out std_logic; + LED_YELLOW : out std_logic; + SUPPL : in std_logic; --terminated diff pair, PCLK, Pads + + --Test Connectors + TEST_LINE : out std_logic_vector(15 downto 0) + ); + + + attribute syn_useioff : boolean; + --no IO-FF for LEDs relaxes timing constraints + attribute syn_useioff of LED_GREEN : signal is false; + attribute syn_useioff of LED_ORANGE : signal is false; + attribute syn_useioff of LED_RED : signal is false; + attribute syn_useioff of LED_YELLOW : signal is false; + attribute syn_useioff of TEMPSENS : signal is false; + attribute syn_useioff of PROGRAMN : signal is false; + attribute syn_useioff of CODE_LINE : signal is false; + attribute syn_useioff of TRIGGER_LEFT : signal is false; + attribute syn_useioff of TRIGGER_RIGHT : signal is false; + + --important signals _with_ IO-FF + attribute syn_useioff of FLASH_CLK : signal is true; + attribute syn_useioff of FLASH_CS : signal is true; + attribute syn_useioff of FLASH_DIN : signal is true; + attribute syn_useioff of FLASH_DOUT : signal is true; + attribute syn_useioff of FPGA5_COMM : signal is true; + attribute syn_useioff of TEST_LINE : signal is true; + attribute syn_useioff of DQLL : signal is true; + attribute syn_useioff of DQUL : signal is true; + attribute syn_useioff of DQLR : signal is true; + attribute syn_useioff of DQUR : signal is true; + attribute syn_useioff of SPARE_LINE : signal is true; + + +end entity; + +architecture trb3_periph_arch of trb3_periph_test is + --Constants + constant POWER_TEST : integer := 0; + constant CDT_TEST : integer := 1; + + attribute syn_keep : boolean; + attribute syn_preserve : boolean; + + --Clock / Reset + signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL + signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL + signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic. + signal clear_i : std_logic; + signal reset_i : std_logic; + signal GSR_N : std_logic; + attribute syn_keep of GSR_N : signal is true; + attribute syn_preserve of GSR_N : signal is true; + + --Media Interface + signal med_stat_op : std_logic_vector (1*16-1 downto 0); + signal med_ctrl_op : std_logic_vector (1*16-1 downto 0); + signal med_stat_debug : std_logic_vector (1*64-1 downto 0); + signal med_ctrl_debug : std_logic_vector (1*64-1 downto 0); + signal med_data_out : std_logic_vector (1*16-1 downto 0); + signal med_packet_num_out : std_logic_vector (1*3-1 downto 0); + signal med_dataready_out : std_logic; + signal med_read_out : std_logic; + signal med_data_in : std_logic_vector (1*16-1 downto 0); + signal med_packet_num_in : std_logic_vector (1*3-1 downto 0); + signal med_dataready_in : std_logic; + signal med_read_in : std_logic; + + --Slow Control channel + signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); + signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); + signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0); + signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0); + + --Timer + signal global_time : std_logic_vector(31 downto 0); + signal local_time : std_logic_vector(7 downto 0); + signal time_since_last_trg : std_logic_vector(31 downto 0); + signal timer_ticks : std_logic_vector(1 downto 0); + + signal sed_debug : std_logic_vector(31 downto 0); + + signal regio_rx, busmem_rx, bussed_rx, bustest_rx : CTRLBUS_RX; + signal regio_tx, busmem_tx, bussed_tx, bustest_tx : CTRLBUS_TX; + signal readout_rx : READOUT_RX; + signal readout_tx : READOUT_TX; + + --FPGA Test + signal time_counter : unsigned(31 downto 0); + + type a_t is array(0 to 33) of std_logic_vector(1000 downto 0); + signal c : a_t; + attribute syn_keep of c : signal is true; + attribute syn_preserve of c : signal is true; + + signal test_debug : std_logic_vector(31 downto 0); + +begin +--------------------------------------------------------------------------- +-- Reset Generation +--------------------------------------------------------------------------- + +GSR_N <= pll_lock; + +THE_RESET_HANDLER : trb_net_reset_handler + generic map( + RESET_DELAY => x"FEEE" + ) + port map( + CLEAR_IN => '0', -- reset input (high active, async) + CLEAR_N_IN => '1', -- reset input (low active, async) + CLK_IN => clk_200_i, -- raw master clock, NOT from PLL/DLL! + SYSCLK_IN => clk_100_i, -- PLL/DLL remastered clock + PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async) + RESET_IN => '0', -- general reset signal (SYSCLK) + TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK) + CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE! + RESET_OUT => reset_i, -- synchronous reset out (SYSCLK) + DEBUG_OUT => open + ); + + +--------------------------------------------------------------------------- +-- Clock Handling +--------------------------------------------------------------------------- +THE_MAIN_PLL : pll_in200_out100 + port map( + CLK => CLK_GPLL_RIGHT, + RESET => '0', + CLKOP => clk_100_i, + CLKOK => clk_200_i, + LOCK => pll_lock + ); + + +--------------------------------------------------------------------------- +-- The TrbNet media interface (to other FPGA) +--------------------------------------------------------------------------- +THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp + generic map( + SERDES_NUM => 1, --number of serdes in quad + EXT_CLOCK => c_NO, --use internal clock + USE_200_MHZ => c_YES, --run on 200 MHz clock + USE_CTC => c_NO + ) + port map( + CLK => clk_200_i, + SYSCLK => clk_100_i, + RESET => reset_i, + CLEAR => clear_i, + CLK_EN => '1', + --Internal Connection + MED_DATA_IN => med_data_out, + MED_PACKET_NUM_IN => med_packet_num_out, + MED_DATAREADY_IN => med_dataready_out, + MED_READ_OUT => med_read_in, + MED_DATA_OUT => med_data_in, + MED_PACKET_NUM_OUT => med_packet_num_in, + MED_DATAREADY_OUT => med_dataready_in, + MED_READ_IN => med_read_out, + REFCLK2CORE_OUT => open, + --SFP Connection + SD_RXD_P_IN => SERDES_INT_RX(2), + SD_RXD_N_IN => SERDES_INT_RX(3), + SD_TXD_P_OUT => SERDES_INT_TX(2), + SD_TXD_N_OUT => SERDES_INT_TX(3), + SD_REFCLK_P_IN => open, + SD_REFCLK_N_IN => open, + SD_PRSNT_N_IN => FPGA5_COMM(0), + SD_LOS_IN => FPGA5_COMM(0), + SD_TXDIS_OUT => FPGA5_COMM(2), + -- Status and control port + STAT_OP => med_stat_op, + CTRL_OP => med_ctrl_op, + STAT_DEBUG => med_stat_debug, + CTRL_DEBUG => (others => '0') + ); + +--------------------------------------------------------------------------- +-- Endpoint +--------------------------------------------------------------------------- + + THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record + generic map( + REGIO_NUM_STAT_REGS => 0, + REGIO_NUM_CTRL_REGS => 0, + ADDRESS_MASK => x"FFFF", + BROADCAST_BITMASK => x"ff", + BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR, + REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)), + REGIO_HARDWARE_VERSION => HARDWARE_INFO, + REGIO_INIT_ADDRESS => INIT_ADDRESS, + REGIO_USE_VAR_ENDPOINT_ID => c_YES, + REGIO_INCLUDED_FEATURES => INCLUDED_FEATURES, + CLOCK_FREQUENCY => CLOCK_FREQUENCY, + TIMING_TRIGGER_RAW => c_YES, + --Configure data handler + DATA_INTERFACE_NUMBER => 1, + DATA_BUFFER_DEPTH => 9, + DATA_BUFFER_WIDTH => 32, + DATA_BUFFER_FULL_THRESH => 2**9-255, + TRG_RELEASE_AFTER_DATA => c_YES, + HEADER_BUFFER_DEPTH => 9, + HEADER_BUFFER_FULL_THRESH => 2**9-16 + ) + port map( + CLK => clk_100_i, + RESET => reset_i, + CLK_EN => '1', + MED_DATAREADY_OUT => med_dataready_out, + MED_DATA_OUT => med_data_out, + MED_PACKET_NUM_OUT => med_packet_num_out, + MED_READ_IN => med_read_in, + MED_DATAREADY_IN => med_dataready_in, + MED_DATA_IN => med_data_in, + MED_PACKET_NUM_IN => med_packet_num_in, + MED_READ_OUT => med_read_out, + MED_STAT_OP_IN => med_stat_op, + MED_CTRL_OP_OUT => med_ctrl_op, + + --Timing trigger in + TRG_TIMING_TRG_RECEIVED_IN => TRIGGER_LEFT, + --LVL1 trigger to FEE + LVL1_TRG_DATA_VALID_OUT => readout_rx.data_valid, + LVL1_VALID_TIMING_TRG_OUT => readout_rx.valid_timing_trg, + LVL1_VALID_NOTIMING_TRG_OUT => readout_rx.valid_notiming_trg, + LVL1_INVALID_TRG_OUT => readout_rx.invalid_trg, + + LVL1_TRG_TYPE_OUT => readout_rx.trg_type, + LVL1_TRG_NUMBER_OUT => readout_rx.trg_number, + LVL1_TRG_CODE_OUT => readout_rx.trg_code, + LVL1_TRG_INFORMATION_OUT => readout_rx.trg_information, + LVL1_INT_TRG_NUMBER_OUT => readout_rx.trg_int_number, + + --Information about trigger handler errors + TRG_MULTIPLE_TRG_OUT => readout_rx.trg_multiple, + TRG_TIMEOUT_DETECTED_OUT => readout_rx.trg_timeout, + TRG_SPURIOUS_TRG_OUT => readout_rx.trg_spurious, + TRG_MISSING_TMG_TRG_OUT => readout_rx.trg_missing, + TRG_SPIKE_DETECTED_OUT => readout_rx.trg_spike, + + --Response from FEE + FEE_TRG_RELEASE_IN(0) => readout_tx.busy_release, + FEE_TRG_STATUSBITS_IN => readout_tx.statusbits, + FEE_DATA_IN => readout_tx.data, + FEE_DATA_WRITE_IN(0) => readout_tx.data_write, + FEE_DATA_FINISHED_IN(0) => readout_tx.data_finished, + FEE_DATA_ALMOST_FULL_OUT(0) => readout_rx.buffer_almost_full, + + -- Slow Control Data Port + REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00 + REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 + REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe, + REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe, + REGIO_STAT_REG_IN => (others => '0'), + REGIO_CTRL_REG_OUT => open, + REGIO_STAT_STROBE_OUT => open, + REGIO_CTRL_STROBE_OUT => open, + REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE, + REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'), + + BUS_RX => regio_rx, + BUS_TX => regio_tx, + + ONEWIRE_INOUT => TEMPSENS, + ONEWIRE_MONITOR_OUT => open, + + TIME_GLOBAL_OUT => global_time, + TIME_LOCAL_OUT => local_time, + TIME_SINCE_LAST_TRG_OUT => time_since_last_trg, + TIME_TICKS_OUT => timer_ticks + + ); + + readout_tx.busy_release <= '1'; + readout_tx.statusbits <= (others => '0'); + readout_tx.data <= (others => '0'); + readout_tx.data_write <= '0'; + readout_tx.data_finished <= '1'; + +--------------------------------------------------------------------------- +-- AddOn +--------------------------------------------------------------------------- + DQLL <= (others => '0'); + DQUL <= (others => '0'); + DQLR <= (others => '0'); + DQUR <= (others => '0'); + +gen_power : if POWER_TEST = 1 generate + gen_chains : for i in 0 to 33 generate + process begin + wait until rising_edge(clk_200_i); + c(i)(1000 downto 1) <= c(i)(999 downto 0); + c(i)(0) <= not c(i)(0) or DQUL(i); + DQUR(i) <= c(i)(1000); + if reset_i = '1' then + c(i)(1000 downto 0) <= (others => '0'); + end if; + end process; + + end generate; +end generate; + +gen_cdt : if CDT_TEST = 1 generate + MY_TEST : entity work.cdt_test + port map( + CLK_200 => clk_200_i, + CLK_100 => clk_100_i, + BUS_RX => bustest_rx, + BUS_TX => bustest_tx, + DEBUG => test_debug(31 downto 0) + ); +end generate; + + +--------------------------------------------------------------------------- +-- Bus Handler +--------------------------------------------------------------------------- + THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record + generic map( + PORT_NUMBER => 3, + PORT_ADDRESSES => (0 => x"d000", 1 => x"d500", 2 => x"a000", others => x"0000"), + PORT_ADDR_MASK => (0 => 9, 1 => 2, 2 => 8, others => 0), + PORT_MASK_ENABLE => 1 + ) + port map( + CLK => clk_100_i, + RESET => reset_i, + + REGIO_RX => regio_rx, + REGIO_TX => regio_tx, + + BUS_RX(0) => busmem_rx, --Flash + BUS_RX(1) => bussed_rx, --SED + BUS_RX(2) => bustest_rx, + BUS_TX(0) => busmem_tx, + BUS_TX(1) => bussed_tx, + BUS_TX(2) => bustest_tx, + + STAT_DEBUG => open + ); + + +--------------------------------------------------------------------------- +-- SPI / Flash +--------------------------------------------------------------------------- + +THE_SPI_RELOAD : entity work.spi_flash_and_fpga_reload + port map( + CLK_IN => clk_100_i, + RESET_IN => reset_i, + + BUS_ADDR_IN => busmem_rx.addr(8 downto 0), + BUS_READ_IN => busmem_rx.read, + BUS_WRITE_IN => busmem_rx.write, + BUS_DATAREADY_OUT => busmem_tx.rack, + BUS_WRITE_ACK_OUT => busmem_tx.wack, + BUS_UNKNOWN_ADDR_OUT => busmem_tx.unknown, + BUS_NO_MORE_DATA_OUT => busmem_tx.nack, + BUS_DATA_IN => busmem_rx.data, + BUS_DATA_OUT => busmem_tx.data, + + DO_REBOOT_IN => common_ctrl_reg(15), + PROGRAMN => PROGRAMN, + + SPI_CS_OUT => FLASH_CS, + SPI_SCK_OUT => FLASH_CLK, + SPI_SDO_OUT => FLASH_DIN, + SPI_SDI_IN => FLASH_DOUT + ); + +--------------------------------------------------------------------------- +-- SED Detection +--------------------------------------------------------------------------- + THE_SED : entity work.sedcheck + port map( + CLK => clk_100_i, + ERROR_OUT => open, + BUS_RX => bussed_rx, + BUS_TX => bussed_tx, + DEBUG => sed_debug + ); + +--------------------------------------------------------------------------- +-- LED +--------------------------------------------------------------------------- + LED_GREEN <= not med_stat_op(9); + LED_ORANGE <= not med_stat_op(10); + LED_RED <= not time_counter(26); + LED_YELLOW <= not test_debug(31); + + +--------------------------------------------------------------------------- +-- Test Connector +--------------------------------------------------------------------------- + + TEST_LINE(15 downto 0) <= test_debug(31 downto 28) & test_debug(21 downto 16) & test_debug(5 downto 0); + + +--------------------------------------------------------------------------- +-- Test Circuits +--------------------------------------------------------------------------- + process + begin + wait until rising_edge(clk_100_i); + time_counter <= time_counter + 1; + end process; + +end architecture; \ No newline at end of file diff --git a/fpgatest/trb3_periph_test_constraints.lpf b/fpgatest/trb3_periph_test_constraints.lpf new file mode 100644 index 0000000..1601a00 --- /dev/null +++ b/fpgatest/trb3_periph_test_constraints.lpf @@ -0,0 +1,32 @@ +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +BLOCK RD_DURING_WR_PATHS ; + +################################################################# +# Basic Settings +################################################################# + +SYSCONFIG MCCLK_FREQ = 20; + +FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; +#FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; +#FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz; +#FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; + +################################################################# +# Reset Nets +################################################################# +GSR_NET NET "GSR_N"; + +MULTICYCLE TO CELL "THE_RESET_HANDLER/final_reset*" 20 ns; + +################################################################# +# Locate Serdes and media interfaces +################################################################# + +LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ; +REGION "MEDIA_UPLINK" "R102C95D" 13 25; +LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ; + +MULTICYCLE TO CELL "THE_SPI_RELOAD_THE_SPI_MASTER_THE_SPI_SLIM_tx_sreg_oregio*" 20 ns; + -- 2.43.0