From c588ea68f8d667ffde0eb032645e6067ff6b29bf Mon Sep 17 00:00:00 2001 From: Cahit Date: Mon, 10 Mar 2014 15:51:35 +0100 Subject: [PATCH] Project for ADA_Addon --- ADA_Addon/compile_constraints.pl | 13 + ADA_Addon/compile_periph_frankfurt.pl | 155 +++++ ADA_Addon/compile_periph_gsi.pl | 325 ++++++++++ ADA_Addon/config.vhd | 69 +++ ADA_Addon/trb3_periph_ADA.p2t | 20 + ADA_Addon/trb3_periph_ADA.prj | 168 +++++ ADA_Addon/trb3_periph_ADA.vhd | 842 ++++++++++++++++++++++++++ base/trb3_periph_ADA.lpf | 218 +++++++ 8 files changed, 1810 insertions(+) create mode 100755 ADA_Addon/compile_constraints.pl create mode 100755 ADA_Addon/compile_periph_frankfurt.pl create mode 100755 ADA_Addon/compile_periph_gsi.pl create mode 100644 ADA_Addon/config.vhd create mode 100644 ADA_Addon/trb3_periph_ADA.p2t create mode 100644 ADA_Addon/trb3_periph_ADA.prj create mode 100644 ADA_Addon/trb3_periph_ADA.vhd create mode 100644 base/trb3_periph_ADA.lpf diff --git a/ADA_Addon/compile_constraints.pl b/ADA_Addon/compile_constraints.pl new file mode 100755 index 0000000..9b30454 --- /dev/null +++ b/ADA_Addon/compile_constraints.pl @@ -0,0 +1,13 @@ +#!/usr/bin/perl +use Data::Dumper; +use warnings; +use strict; + +my $TOPNAME = "trb3_periph_ADA"; #Name of top-level entity + + +#create full lpf file +system("cp ../base/trb3_periph_ADA.lpf diamond/$TOPNAME.lpf"); +system("cat currentRelease/trbnet_constraints.lpf >> diamond/$TOPNAME.lpf"); +system("cat currentRelease/tdc_constraints_64.lpf >> diamond/$TOPNAME.lpf"); + diff --git a/ADA_Addon/compile_periph_frankfurt.pl b/ADA_Addon/compile_periph_frankfurt.pl new file mode 100755 index 0000000..aa15bf6 --- /dev/null +++ b/ADA_Addon/compile_periph_frankfurt.pl @@ -0,0 +1,155 @@ +#!/usr/bin/perl +use Data::Dumper; +use warnings; +use strict; + + + + +################################################################################### +#Settings for this project +my $TOPNAME = "trb3_periph_ADA"; #Name of top-level entity +my $BasePath = "../base/"; #path to "base" directory +my $lattice_path = '/d/jspc29/lattice/diamond/1.4.2.105'; +my $synplify_path = '/d/jspc29/lattice/synplify/F-2012.03-SP1/'; +my $lm_license_file_for_synplify = "27000\@localhost"; +my $lm_license_file_for_par = "1710\@cronos.e12.physik.tu-muenchen.de"; +################################################################################### + + + + + + + + +use FileHandle; + +$ENV{'SYNPLIFY'}=$synplify_path; +$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1; +$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify; + + + + +my $FAMILYNAME="LatticeECP3"; +my $DEVICENAME="LFE3-150EA"; +my $PACKAGE="FPBGA672"; +my $SPEEDGRADE="8"; + +#create full lpf file +system("cp ../base/$TOPNAME.lpf $WORKDIR/$TOPNAME.lpf"); +system("cat currentRelease/trbnet_constraints.lpf >> $WORKDIR/$TOPNAME.lpf"); +system("cat currentRelease/tdc_constraints_64.lpf >> $WORKDIR/$TOPNAME.lpf"); + + +#set -e +#set -o errexit + +#generate timestamp +my $t=time; +my $fh = new FileHandle(">version.vhd"); +die "could not open file" if (! defined $fh); +print $fh <close; + +system("env| grep LM_"); +my $r = ""; + +my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj"; +$r=execute($c, "do_not_exit" ); + + +chdir "workdir"; +$fh = new FileHandle("<$TOPNAME".".srr"); +my @a = <$fh>; +$fh -> close; + + + +foreach (@a) +{ + if(/\@E:/) + { + print "\n"; + $c="cat $TOPNAME.srr | grep \"\@E\""; + system($c); + print "\n\n"; + exit 129; + } +} + + +$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par; + +$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |; +execute($c); + +$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|; +execute($c); + +$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|; +execute($c); + +my $tpmap = $TOPNAME . "_map" ; +system("mv $TOPNAME.ncd guidefile.ncd"); + +#-g guidefile.ncd +$c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|; +execute($c); + + +$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|; +execute($c); + +## IOR IO Timing Report +#$c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; +#execute($c); + +# TWR Timing Report +$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); + +$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); + +$c=qq|$lattice_path/ispfpga/bin/lin/ltxt2ptxt $TOPNAME.ncd|; +execute($c); + +$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); + +chdir ".."; + +exit; + +sub execute { + my ($c, $op) = @_; + #print "option: $op \n"; + $op = "" if(!$op); + print "\n\ncommand to execute: $c \n"; + $r=system($c); + if($r) { + print "$!"; + if($op ne "do_not_exit") { + exit; + } + } + + return $r; + +} diff --git a/ADA_Addon/compile_periph_gsi.pl b/ADA_Addon/compile_periph_gsi.pl new file mode 100755 index 0000000..b6ced65 --- /dev/null +++ b/ADA_Addon/compile_periph_gsi.pl @@ -0,0 +1,325 @@ +#!/usr/bin/perl +use Data::Dumper; +use warnings; +use strict; +use FileHandle; +use Getopt::Long; + +################################################################################### +#Settings for this project +my $TOPNAME = "trb3_periph_ADA"; #Name of top-level entity +#my $lattice_path = '/opt/lattice/diamond/3.0_x64/'; +#my $lattice_bin_path = "$lattice_path/bin/lin64"; # note the lin/lin64 at the end, no isfgpa needed +#my $synplify_path = '/opt/synplicity/I-2013.09-SP1'; +my $lattice_path = '/opt/lattice/diamond/2.01/'; +my $lattice_bin_path = "$lattice_path/bin/lin"; # note the lin/lin64 at the end, no isfgpa needed +my $synplify_path = '/opt/synplicity/F-2012.03-SP1'; +my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de"; +my $lm_license_file_for_par = "1702\@hadeb05.gsi.de"; +################################################################################### + +################################################################################### +#Options for the script +my $help = ""; +my $isMultiPar = 0; # set it to zero for single par run on the local machine +my $nrNodes = 0; # set it to one for single par run on the local machine +my $all = 1; +my $syn = 0; +my $map = 0; +my $par = 0; +my $timing = 0; +my $bitgen = 0; + +my $result = GetOptions ( + "h|help" => \$help, + "m|mpar=i" => \$nrNodes, + "a|all" => \$all, + "s|syn" => \$syn, + "mp|map" => \$map, + "p|par" => \$par, + "t|timing" => \$timing, + "b|bitgen" => \$bitgen, + ); + +if($help) { + print "Usage: compile_priph_gsi.de \n\n"; + print "-h --help\tPrints the usage manual.\n"; + print "-a --all\tRun all compile script. By default the script is going to rung the whole process.\n"; + print "-s --syn\tRun synthesis part of the compile script.\n"; + print "-mp --map\tRun map part of the compile script.\n"; + print "-p --par\tRun par part of the compile script.\n"; + print "-t --timing\tRun timing analysis part of the compile script.\n"; + print "-b --bitgen\tRun bit generation part of the compile script.\n"; + print "-m --mpar\tSwitch for multi par. \"-m \" (Default = off)\n"; + print "\t\tThe node list file name has to be edited in the script. (Default = nodes_lxhadeb07.txt)\n"; + print "\n"; + exit; +} + +if ($nrNodes!=0){ + $isMultiPar=1; +} +if ($syn!=0 || $map!=0 || $par!=0 || $timing!=0 || $bitgen!=0){ + $all=0; +} +################################################################################### + + + +# source the standard lattice environment +$ENV{bindir}="$lattice_bin_path"; +open my $SOURCE, "bash -c '. $lattice_bin_path/diamond_env >& /dev/null; env'|" or + die "Can't fork: $!"; +while (<$SOURCE>) { + if (/^(.*)=(.*)/) { + $ENV{$1} = ${2} ; + } +} +close $SOURCE; + + +$ENV{'PAR_DESIGN_NAME'}=$TOPNAME; +$ENV{'SYNPLIFY'}=$synplify_path; +$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1; +$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify; + + +my $FAMILYNAME="LatticeECP3"; +my $DEVICENAME="LFE3-150EA"; +my $PACKAGE="FPBGA672"; +my $SPEEDGRADE="8"; + +my $WORKDIR = "workdir"; +unless(-d $WORKDIR) { + mkdir $WORKDIR or die "can't create workdir '$WORKDIR': $!"; +} + +system("ln -sfT $lattice_path $WORKDIR/lattice-diamond"); + +#create full lpf file +system("cp ../base/$TOPNAME.lpf $WORKDIR/$TOPNAME.lpf"); +system("cat currentRelease/trbnet_constraints.lpf >> $WORKDIR/$TOPNAME.lpf"); +system("cat currentRelease/tdc_constraints_64.lpf >> $WORKDIR/$TOPNAME.lpf"); + +#generate timestamp +my $t=time; +my $fh = new FileHandle(">version.vhd"); +die "could not open file" if (! defined $fh); +print $fh <close; + +system("env| grep LM_"); +my $r = ""; +my $c = ""; +my @a = (); +my $tpmap = $TOPNAME . "_map" ; + +if($syn==1 || $all==1){ + $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj"; + $r=execute($c, "do_not_exit" ); +} + +chdir $WORKDIR; + +if($syn==1 || $all==1){ + $fh = new FileHandle("<$TOPNAME".".srr"); + @a = <$fh>; + $fh -> close; + + foreach (@a) + { + if(/\@E:/) + { + print "\n"; + $c="cat $TOPNAME.srr | grep \"\@E\""; + system($c); + print "\n\n"; + exit 129; + } + } +} + +$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par; + +if($map==1 || $all==1){ + $c=qq| edif2ngd -path "../" -path "." -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |; + execute($c); + + $c=qq|edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|; + execute($c); + + $c=qq|ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|; + execute($c); + + $c=qq|map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|; + execute($c); + + $fh = new FileHandle("$TOPNAME.mrp"); + @a = <$fh>; + $fh -> close; + my $fileSize = @a; + my $isParError = 0; + + open (DEBUG, '>par.log'); + for (my $i=0; $i<$fileSize; ) + { + my @line = split(' ', $a[$i]); + if (@line && ($line[0] =~ /WARNING/)) + { + my $warning = $a[$i]; + chomp $warning; + my $k = 1; + my @nextLine = split(' ', $a[$i+$k]); + if(!@nextLine) + { + $k+=10; + @nextLine = split(' ', $a[$i+$k]); + } + while (!($nextLine[0] =~ /WARNING/)) + { + my $b = $a[$i+$k]; + chomp $b; + $b =~ s/^\s+//; + $warning = join (' ', $warning, $b); + $k++; + @nextLine = split(' ', $a[$i+$k]); + if(!@nextLine) + { + $k+=10; + @nextLine = split(' ', $a[$i+$k]); + } + if ($k>20) + { + last; + } + } + #open my $keywords, '<', '../keywords.txt' or die "Can't open keywords: $!"; + if ($warning =~ /FC_|HitInvert|ff_en_/) + { + print DEBUG $warning."\n\n"; + $isParError = 1; + } + } + $i++; + } + close (DEBUG); + + if ($isParError) + { + print "\n\n"; + print "#################################################\n"; + print "# !!!Possible Placement Errors!!! #\n"; + print "#################################################\n\n"; + + my $c="egrep \"FC_|HitInvert|ff_en_\" par.log"; + system($c); + } +} + + +if($par==1 || $all==1){ + system("rm $TOPNAME.ncd"); + #$c=qq|mpartrce -p "../$TOPNAME.p2t" -log "$TOPNAME.log" -o "$TOPNAME.rpt" -pr "$TOPNAME.prf" -tf "$TOPNAME.pt" "|.$TOPNAME.qq|_map.ncd" "$TOPNAME.ncd"|; + #$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|; + if ($isMultiPar) + { + $c=qq|par -m ../nodes_lxhadeb07.txt -n $nrNodes -stopzero -w -l 5 -i 6 -t 1 -c 0 -e 0 -exp parDisablePgroup=0:parUseNBR=1:parCDP=0:parCDR=0:parPathBased=ON $tpmap.ncd $TOPNAME.dir $TOPNAME.prf|; + execute($c); + # find and copy the .ncd file which has met the timing constraints + $fh = new FileHandle("<$TOPNAME".".par"); + my @a = <$fh>; + my $isSuccess = 0; + $fh -> close; + foreach (@a) + { + my @line = split(' ', $_); + if(@line && ($line[2] =~ m/^[0-9]+$/) && ($line[3] =~ m/^[0-9]+$/)) + { + if(($line[2] == 0) && ($line[3] == 0)) + { + print "Copying $line[0].ncd file to workdir\n"; + my $c="cp $TOPNAME.dir/$line[0].ncd $TOPNAME.ncd"; + system($c); + print "\n\n"; + $isSuccess = 1; + last; + } + } + } + + if (!$isSuccess){ + print "\n\n"; + print "#################################################\n"; + print "# !!!PAR not succesfull!!! #\n"; + print "#################################################\n\n"; + exit 129; + } + } + else + { + $c=qq|par -w -l 5 -i 6 -t 1 -c 0 -e 0 -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=ON $tpmap.ncd $TOPNAME.dir $TOPNAME.prf|; + execute($c); + my $c="cp trb3_periph_32PinAddOn.dir/5_1.ncd trb3_periph_32PinAddOn.ncd"; + system($c); + } + my $c="cat trb3_periph_32PinAddOn.par"; + system($c); +} + + +if($timing==1 || $all==1){ + # IOR IO Timing Report + $c=qq|iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; + execute($c); + + # TWR Timing Report + $c=qq|trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|; + execute($c); + + $c=qq|trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|; + execute($c); + + $c=qq|ltxt2ptxt $TOPNAME.ncd|; + execute($c); + + my $c="cat trb3_periph_32PinAddOn.par"; + system($c); +} + +if($bitgen==1 || $all==1){ + $c=qq|bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No $TOPNAME.ncd $TOPNAME.bit $TOPNAME.prf|; + # $c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|; + execute($c); +} + +chdir ".."; +exit; + +sub execute { + my ($c, $op) = @_; + #print "option: $op \n"; + $op = "" if(!$op); + print "\n\ncommand to execute: $c \n"; + $r=system($c); + if($r) { + print "$!"; + if($op ne "do_not_exit") { + exit; + } + } + return $r; +} diff --git a/ADA_Addon/config.vhd b/ADA_Addon/config.vhd new file mode 100644 index 0000000..5987129 --- /dev/null +++ b/ADA_Addon/config.vhd @@ -0,0 +1,69 @@ +library ieee; +USE IEEE.std_logic_1164.ALL; +use ieee.numeric_std.all; +use work.trb_net_std.all; + +package config is + + +------------------------------------------------------------------------------ +--Begin of design configuration +------------------------------------------------------------------------------ + +--Include GbE logic + constant NUM_TDC_CHANNELS : integer range 1 to 65 := 65; + constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 6; --the nearest power of two, for convenience reasons + constant USE_DOUBLE_EDGE : integer := c_YES; + +--Include SPI on AddOn connector + constant INCLUDE_SPI : integer := c_YES; + +--Add logic to generate configurable trigger signal from input signals. + constant INCLUDE_TRIGGER_LOGIC : integer := c_YES; + +--Run wih 125 MHz instead of 100 MHz + constant USE_125_MHZ : integer := c_NO; --not implemented yet! + +--Use sync mode, RX clock for all parts of the FPGA + constant USE_RXCLOCK : integer := c_NO; --not implemented yet! + + +--Address settings + constant INIT_ADDRESS : std_logic_vector := x"F305"; + constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"48"; + +------------------------------------------------------------------------------ +--End of design configuration +------------------------------------------------------------------------------ + + +------------------------------------------------------------------------------ +--Select settings by configuration +------------------------------------------------------------------------------ + type intlist_t is array(0 to 7) of integer; + type hw_info_t is array(0 to 7) of unsigned(31 downto 0); + constant HW_INFO_BASE : unsigned(31 downto 0) := x"91001000"; + constant HW_INFO_SPI : hw_info_t := (x"00000000",x"00000400", others => x"00000000"); + constant HW_INFO_DOUBLE_EDGE : hw_info_t := (x"00000000",x"00000800", others => x"00000000"); + constant HW_INFO_NUM_CHANS : hw_info_t := (x"00000000",x"00000010",x"00000020",x"00000030", + x"00000040",x"00000050",x"00000060",x"00000070", others => x"00000000"); + constant CLOCK_FREQUENCY_ARR : intlist_t := (100,125, others => 0); + constant MEDIA_FREQUENCY_ARR : intlist_t := (200,125, others => 0); + + --declare constants, filled in body + constant HARDWARE_INFO : std_logic_vector(31 downto 0); + constant CLOCK_FREQUENCY : integer; + constant MEDIA_FREQUENCY : integer; + +end; + +package body config is +--compute correct configuration mode + + constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector( + HW_INFO_BASE + HW_INFO_SPI(INCLUDE_SPI) + HW_INFO_DOUBLE_EDGE(USE_DOUBLE_EDGE) + + HW_INFO_NUM_CHANS(NUM_TDC_CHANNELS_POWER2)); + constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_125_MHZ); + constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_125_MHZ); + +end package body; diff --git a/ADA_Addon/trb3_periph_ADA.p2t b/ADA_Addon/trb3_periph_ADA.p2t new file mode 100644 index 0000000..c037b03 --- /dev/null +++ b/ADA_Addon/trb3_periph_ADA.p2t @@ -0,0 +1,20 @@ +-w +-i 15 +-l 5 +-n 1 +-y +-s 12 +-t 12 +-c 1 +-e 2 +-m nodelist.txt +# -w +# -i 6 +# -l 5 +# -n 1 +# -t 1 +# -s 1 +# -c 0 +# -e 0 +# +-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1: diff --git a/ADA_Addon/trb3_periph_ADA.prj b/ADA_Addon/trb3_periph_ADA.prj new file mode 100644 index 0000000..6304f52 --- /dev/null +++ b/ADA_Addon/trb3_periph_ADA.prj @@ -0,0 +1,168 @@ + + +# implementation: "workdir" +impl -add workdir -type fpga + +# device options +set_option -technology LATTICE-ECP3 +set_option -part LFE3_150EA +set_option -package FN672C +set_option -speed_grade -8 +set_option -part_companion "" + +# compilation/mapping options +set_option -default_enum_encoding sequential +set_option -symbolic_fsm_compiler 1 +set_option -top_module "trb3_periph_ADA" +set_option -resource_sharing true + +# map options +set_option -frequency 200 +set_option -fanout_limit 100 +set_option -disable_io_insertion 0 +set_option -retiming 0 +set_option -pipe 0 +#set_option -force_gsr +set_option -force_gsr false +set_option -fixgatedclocks 3 +set_option -fixgeneratedclocks 3 +set_option -compiler_compatible true + + +# simulation options +set_option -write_verilog 0 +set_option -write_vhdl 1 + +# automatic place and route (vendor) options +set_option -write_apr_constraint 0 + +# set result format/file last +project -result_format "edif" +project -result_file "workdir/trb3_periph_ADA.edf" + +#implementation attributes + +set_option -vlog_std v2001 +set_option -project_relative_includes 1 +impl -active "workdir" + +#################### + + + +#add_file options + +add_file -vhdl -lib work "version.vhd" +add_file -vhdl -lib work "config.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" +add_file -vhdl -lib "work" "../base/trb3_components.vhd" + +add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd" +add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd" +add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd" + +add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd" +add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" + +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" + +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" + +add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" +add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd" + +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" + +add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd" + +############### +#Change path to tdc release also in compile script! +############### +#add_file -vhdl -lib "work" "currentRelease/Adder_304.vhd" +add_file -vhdl -lib "work" "currentRelease/bit_sync.vhd" +add_file -vhdl -lib "work" "currentRelease/BusHandler.vhd" +add_file -vhdl -lib "work" "currentRelease/Channel.vhd" +add_file -vhdl -lib "work" "currentRelease/Channel_200.vhd" +add_file -vhdl -lib "work" "currentRelease/Encoder_304_Bit.vhd" +add_file -vhdl -lib "work" "currentRelease/LogicAnalyser.vhd" +add_file -vhdl -lib "work" "currentRelease/Readout.vhd" +add_file -vhdl -lib "work" "currentRelease/ROM4_Encoder.vhd" +add_file -vhdl -lib "work" "currentRelease/ROM_encoder_3.vhd" +add_file -vhdl -lib "work" "currentRelease/ShiftRegisterSISO.vhd" +add_file -vhdl -lib "work" "currentRelease/TDC.vhd" +add_file -vhdl -lib "work" "currentRelease/TriggerHandler.vhd" +add_file -vhdl -lib "work" "currentRelease/up_counter.vhd" +add_file -vhdl -lib "work" "currentRelease/fallingEdgeDetect.vhd" +add_file -vhdl -lib "work" "currentRelease/risingEdgeDetect.vhd" +add_file -vhdl -lib "work" "currentRelease/hit_inv.vhd" +add_file -vhdl -lib "work" "../base/cores/FIFO_36x128_OutReg.vhd" +add_file -vhdl -lib "work" "../base/cores/FIFO_DC_36x128_OutReg.vhd" +add_file -vhdl -lib "work" "../base/code/input_to_trigger_logic.vhd" + +add_file -vhdl -lib "work" "trb3_periph_ADA.vhd" diff --git a/ADA_Addon/trb3_periph_ADA.vhd b/ADA_Addon/trb3_periph_ADA.vhd new file mode 100644 index 0000000..0bef5c3 --- /dev/null +++ b/ADA_Addon/trb3_periph_ADA.vhd @@ -0,0 +1,842 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.config.all; +use work.version.all; + + +entity trb3_periph_ADA is + port( + --Clocks + CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz + CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA + CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right! + CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right! + --Trigger + TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out + TRIGGER_RIGHT : in std_logic; --right side trigger input from fan-out + --Serdes + CLK_SERDES_INT_LEFT : in std_logic; --Clock Manager 1/(1357), off, 125 MHz possible + CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 2/(1357), 200 MHz, only in case of problems + SERDES_INT_TX : out std_logic_vector(3 downto 0); + SERDES_INT_RX : in std_logic_vector(3 downto 0); + SERDES_ADDON_TX : out std_logic_vector(11 downto 0); + SERDES_ADDON_RX : in std_logic_vector(11 downto 0); + --Inter-FPGA Communication + FPGA5_COMM : inout std_logic_vector(11 downto 0); + --Bit 0/1 input, serial link RX active + --Bit 2/3 output, serial link TX active + --Connection to ADA AddOn + SPARE_LINE : inout std_logic_vector(3 downto 0); --inputs only + INP : in std_logic_vector(63 downto 0); + --DAC + DAC_SDO : in std_logic; + DAC_SDI : out std_logic; + DAC_SCK : out std_logic; + DAC_CS : out std_logic_vector(4 downto 1); + --Flash ROM & Reboot + FLASH_CLK : out std_logic; + FLASH_CS : out std_logic; + FLASH_DIN : out std_logic; + FLASH_DOUT : in std_logic; + PROGRAMN : out std_logic; --reboot FPGA + --Misc + TEMPSENS : inout std_logic; --Temperature Sensor + CODE_LINE : in std_logic_vector(1 downto 0); + LED_GREEN : out std_logic; + LED_ORANGE : out std_logic; + LED_RED : out std_logic; + LED_YELLOW : out std_logic; + SUPPL : in std_logic; --terminated diff pair, PCLK, Pads + --Test Connectors + TEST_LINE : out std_logic_vector(15 downto 0) + ); + attribute syn_useioff : boolean; + --no IO-FF for LEDs relaxes timing constraints + attribute syn_useioff of LED_GREEN : signal is false; + attribute syn_useioff of LED_ORANGE : signal is false; + attribute syn_useioff of LED_RED : signal is false; + attribute syn_useioff of LED_YELLOW : signal is false; + attribute syn_useioff of TEMPSENS : signal is false; + attribute syn_useioff of PROGRAMN : signal is false; + attribute syn_useioff of CODE_LINE : signal is false; + attribute syn_useioff of TRIGGER_LEFT : signal is false; + attribute syn_useioff of TRIGGER_RIGHT : signal is false; + --important signals + attribute syn_useioff of FLASH_CLK : signal is true; + attribute syn_useioff of FLASH_CS : signal is true; + attribute syn_useioff of FLASH_DIN : signal is true; + attribute syn_useioff of FLASH_DOUT : signal is true; + attribute syn_useioff of FPGA5_COMM : signal is true; + attribute syn_useioff of TEST_LINE : signal is true; + attribute syn_useioff of INP : signal is false; + attribute syn_useioff of SPARE_LINE : signal is true; + attribute syn_useioff of DAC_SDI : signal is true; + attribute syn_useioff of DAC_SDO : signal is true; + attribute syn_useioff of DAC_SCK : signal is true; + attribute syn_useioff of DAC_CS : signal is true; + +end entity; + + +architecture trb3_periph_ADA_arch of trb3_periph_ADA is + --Constants + constant REGIO_NUM_STAT_REGS : integer := 3; + constant REGIO_NUM_CTRL_REGS : integer := 3; + + attribute syn_keep : boolean; + attribute syn_preserve : boolean; + + --Clock / Reset + signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL + signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL + signal osc_int : std_logic; -- clock for calibrating the tdc, 2.5 MHz, via internal osscilator + signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic. + signal clear_i : std_logic; + signal reset_i : std_logic; + signal GSR_N : std_logic; + attribute syn_keep of GSR_N : signal is true; + attribute syn_preserve of GSR_N : signal is true; + + --Media Interface + signal med_stat_op : std_logic_vector (1*16-1 downto 0); + signal med_ctrl_op : std_logic_vector (1*16-1 downto 0); + signal med_stat_debug : std_logic_vector (1*64-1 downto 0); + signal med_data_out : std_logic_vector (1*16-1 downto 0); + signal med_packet_num_out : std_logic_vector (1*3-1 downto 0); + signal med_dataready_out : std_logic; + signal med_read_out : std_logic; + signal med_data_in : std_logic_vector (1*16-1 downto 0); + signal med_packet_num_in : std_logic_vector (1*3-1 downto 0); + signal med_dataready_in : std_logic; + signal med_read_in : std_logic; + + --LVL1 channel + signal timing_trg_received_i : std_logic; + signal trg_data_valid_i : std_logic; + signal trg_timing_valid_i : std_logic; + signal trg_notiming_valid_i : std_logic; + signal trg_invalid_i : std_logic; + signal trg_type_i : std_logic_vector(3 downto 0); + signal trg_number_i : std_logic_vector(15 downto 0); + signal trg_code_i : std_logic_vector(7 downto 0); + signal trg_information_i : std_logic_vector(23 downto 0); + signal trg_int_number_i : std_logic_vector(15 downto 0); + signal trg_multiple_trg_i : std_logic; + signal trg_timeout_detected_i : std_logic; + signal trg_spurious_trg_i : std_logic; + signal trg_missing_tmg_trg_i : std_logic; + signal trg_spike_detected_i : std_logic; + + --Data channel + signal fee_trg_release_i : std_logic; + signal fee_trg_statusbits_i : std_logic_vector(31 downto 0); + signal fee_data_i : std_logic_vector(31 downto 0); + signal fee_data_write_i : std_logic; + signal fee_data_finished_i : std_logic; + signal fee_almost_full_i : std_logic; + + --Slow Control channel + signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0); + signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); + signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0); + signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0); + signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0); + signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0); + signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0); + signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0); + + --RegIO + signal regio_addr_out : std_logic_vector (15 downto 0); + signal regio_read_enable_out : std_logic; + signal regio_write_enable_out : std_logic; + signal regio_data_out : std_logic_vector (31 downto 0); + signal regio_data_in : std_logic_vector (31 downto 0); + signal regio_dataready_in : std_logic; + signal regio_no_more_data_in : std_logic; + signal regio_write_ack_in : std_logic; + signal regio_unknown_addr_in : std_logic; + signal regio_timeout_out : std_logic; + + --Timer + signal global_time : std_logic_vector(31 downto 0); + signal local_time : std_logic_vector(7 downto 0); + signal time_since_last_trg : std_logic_vector(31 downto 0); + signal timer_ticks : std_logic_vector(1 downto 0); + + --Flash + signal spictrl_read_en : std_logic; + signal spictrl_write_en : std_logic; + signal spictrl_data_in : std_logic_vector(31 downto 0); + signal spictrl_addr : std_logic; + signal spictrl_data_out : std_logic_vector(31 downto 0); + signal spictrl_ack : std_logic; + signal spictrl_busy : std_logic; + signal spimem_read_en : std_logic; + signal spimem_write_en : std_logic; + signal spimem_data_in : std_logic_vector(31 downto 0); + signal spimem_addr : std_logic_vector(5 downto 0); + signal spimem_data_out : std_logic_vector(31 downto 0); + signal spimem_ack : std_logic; + signal spidac_read_en : std_logic; + signal spidac_write_en : std_logic; + signal spidac_data_in : std_logic_vector(31 downto 0); + signal spidac_addr : std_logic_vector(4 downto 0); + signal spidac_data_out : std_logic_vector(31 downto 0); + signal spidac_ack : std_logic; + signal spidac_busy : std_logic; + + signal hitreg_read_en : std_logic; + signal hitreg_write_en : std_logic; + signal hitreg_addr : std_logic_vector(6 downto 0); + signal hitreg_data_out : std_logic_vector(31 downto 0); + signal hitreg_data_ready : std_logic; + signal hitreg_invalid : std_logic; + + signal srb_read_en : std_logic; + signal srb_write_en : std_logic; + signal srb_addr : std_logic_vector(6 downto 0); + signal srb_data_out : std_logic_vector(31 downto 0); + signal srb_data_ready : std_logic; + signal srb_invalid : std_logic; + + signal lhb_read_en : std_logic; + signal lhb_write_en : std_logic; + signal lhb_addr : std_logic_vector(6 downto 0); + signal lhb_data_out : std_logic_vector(31 downto 0); + signal lhb_data_ready : std_logic; + signal lhb_invalid : std_logic; + + signal esb_read_en : std_logic; + signal esb_write_en : std_logic; + signal esb_addr : std_logic_vector(6 downto 0); + signal esb_data_out : std_logic_vector(31 downto 0); + signal esb_data_ready : std_logic; + signal esb_invalid : std_logic; + + signal efb_read_en : std_logic; + signal efb_write_en : std_logic; + signal efb_addr : std_logic_vector(6 downto 0); + signal efb_data_out : std_logic_vector(31 downto 0); + signal efb_data_ready : std_logic; + signal efb_invalid : std_logic; + + signal tdc_ctrl_read : std_logic; + signal last_tdc_ctrl_read : std_logic; + signal tdc_ctrl_write : std_logic; + signal tdc_ctrl_addr : std_logic_vector(2 downto 0); + signal tdc_ctrl_data_in : std_logic_vector(31 downto 0); + signal tdc_ctrl_data_out : std_logic_vector(31 downto 0); + signal tdc_ctrl_reg : std_logic_vector(5*32-1 downto 0); + + signal spi_bram_addr : std_logic_vector(7 downto 0); + signal spi_bram_wr_d : std_logic_vector(7 downto 0); + signal spi_bram_rd_d : std_logic_vector(7 downto 0); + signal spi_bram_we : std_logic; + + signal trig_out : std_logic_vector(3 downto 0); + signal trig_din : std_logic_vector(31 downto 0); + signal trig_dout : std_logic_vector(31 downto 0); + signal trig_write : std_logic := '0'; + signal trig_read : std_logic := '0'; + signal trig_ack : std_logic := '0'; + signal trig_nack : std_logic := '0'; + signal trig_addr : std_logic_vector(15 downto 0) := (others => '0'); + + --TDC + signal hit_in_i : std_logic_vector(64 downto 1); + signal logic_analyser_i : std_logic_vector(15 downto 0); + +begin +--------------------------------------------------------------------------- +-- Reset Generation +--------------------------------------------------------------------------- + + GSR_N <= pll_lock; + + THE_RESET_HANDLER : trb_net_reset_handler + generic map( + RESET_DELAY => x"FEEE" + ) + port map( + CLEAR_IN => '0', -- reset input (high active, async) + CLEAR_N_IN => '1', -- reset input (low active, async) + CLK_IN => clk_200_i, -- raw master clock, NOT from PLL/DLL! + SYSCLK_IN => clk_100_i, -- PLL/DLL remastered clock + PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async) + RESET_IN => '0', -- general reset signal (SYSCLK) + TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK) + CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE! + RESET_OUT => reset_i, -- synchronous reset out (SYSCLK) + DEBUG_OUT => open + ); + + +--------------------------------------------------------------------------- +-- Clock Handling +--------------------------------------------------------------------------- + THE_MAIN_PLL : pll_in200_out100 + port map( + CLK => CLK_GPLL_RIGHT, + CLKOP => clk_100_i, + CLKOK => clk_200_i, + LOCK => pll_lock + ); + + -- internal oscillator with frequency of 2.5MHz for tdc calibration + OSCInst0 : OSCF + port map ( + OSC => osc_int); + +--------------------------------------------------------------------------- +-- The TrbNet media interface (to other FPGA) +--------------------------------------------------------------------------- + THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp + generic map( + SERDES_NUM => 1, --number of serdes in quad + EXT_CLOCK => c_NO, --use internal clock + USE_200_MHZ => c_YES, --run on 200 MHz clock + USE_125_MHZ => c_NO, + USE_CTC => c_NO + ) + port map( + CLK => clk_200_i, + SYSCLK => clk_100_i, + RESET => reset_i, + CLEAR => clear_i, + CLK_EN => '1', + --Internal Connection + MED_DATA_IN => med_data_out, + MED_PACKET_NUM_IN => med_packet_num_out, + MED_DATAREADY_IN => med_dataready_out, + MED_READ_OUT => med_read_in, + MED_DATA_OUT => med_data_in, + MED_PACKET_NUM_OUT => med_packet_num_in, + MED_DATAREADY_OUT => med_dataready_in, + MED_READ_IN => med_read_out, + REFCLK2CORE_OUT => open, + --SFP Connection + SD_RXD_P_IN => SERDES_INT_RX(2), + SD_RXD_N_IN => SERDES_INT_RX(3), + SD_TXD_P_OUT => SERDES_INT_TX(2), + SD_TXD_N_OUT => SERDES_INT_TX(3), + SD_REFCLK_P_IN => open, + SD_REFCLK_N_IN => open, + SD_PRSNT_N_IN => FPGA5_COMM(0), + SD_LOS_IN => FPGA5_COMM(0), + SD_TXDIS_OUT => FPGA5_COMM(2), + -- Status and control port + STAT_OP => med_stat_op, + CTRL_OP => med_ctrl_op, + STAT_DEBUG => med_stat_debug, + CTRL_DEBUG => (others => '0') + ); + +--------------------------------------------------------------------------- +-- Endpoint +--------------------------------------------------------------------------- + + THE_ENDPOINT : trb_net16_endpoint_hades_full_handler + generic map( + REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS, + REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, + ADDRESS_MASK => x"FFFF", + BROADCAST_BITMASK => x"FF", + BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR, + REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)), + REGIO_HARDWARE_VERSION => HARDWARE_INFO, + REGIO_INIT_ADDRESS => INIT_ADDRESS, + REGIO_USE_VAR_ENDPOINT_ID => c_YES, + CLOCK_FREQUENCY => CLOCK_FREQUENCY, + TIMING_TRIGGER_RAW => c_YES, + --Configure data handler + DATA_INTERFACE_NUMBER => 1, + DATA_BUFFER_DEPTH => 13, --13 + DATA_BUFFER_WIDTH => 32, + DATA_BUFFER_FULL_THRESH => 2**13-800, --2**13-(maximal 2**12) + TRG_RELEASE_AFTER_DATA => c_YES, + HEADER_BUFFER_DEPTH => 9, + HEADER_BUFFER_FULL_THRESH => 2**9-16 + ) + port map( + CLK => clk_100_i, + RESET => reset_i, + CLK_EN => '1', + MED_DATAREADY_OUT => med_dataready_out, -- open, -- + MED_DATA_OUT => med_data_out, -- open, -- + MED_PACKET_NUM_OUT => med_packet_num_out, -- open, -- + MED_READ_IN => med_read_in, + MED_DATAREADY_IN => med_dataready_in, + MED_DATA_IN => med_data_in, + MED_PACKET_NUM_IN => med_packet_num_in, + MED_READ_OUT => med_read_out, -- open, -- + MED_STAT_OP_IN => med_stat_op, + MED_CTRL_OP_OUT => med_ctrl_op, + + --Timing trigger in + TRG_TIMING_TRG_RECEIVED_IN => timing_trg_received_i, + --LVL1 trigger to FEE + LVL1_TRG_DATA_VALID_OUT => trg_data_valid_i, + LVL1_VALID_TIMING_TRG_OUT => trg_timing_valid_i, + LVL1_VALID_NOTIMING_TRG_OUT => trg_notiming_valid_i, + LVL1_INVALID_TRG_OUT => trg_invalid_i, + + LVL1_TRG_TYPE_OUT => trg_type_i, + LVL1_TRG_NUMBER_OUT => trg_number_i, + LVL1_TRG_CODE_OUT => trg_code_i, + LVL1_TRG_INFORMATION_OUT => trg_information_i, + LVL1_INT_TRG_NUMBER_OUT => trg_int_number_i, + + --Information about trigger handler errors + TRG_MULTIPLE_TRG_OUT => trg_multiple_trg_i, + TRG_TIMEOUT_DETECTED_OUT => trg_timeout_detected_i, + TRG_SPURIOUS_TRG_OUT => trg_spurious_trg_i, + TRG_MISSING_TMG_TRG_OUT => trg_missing_tmg_trg_i, + TRG_SPIKE_DETECTED_OUT => trg_spike_detected_i, + + --Response from FEE + FEE_TRG_RELEASE_IN(0) => fee_trg_release_i, + FEE_TRG_STATUSBITS_IN => fee_trg_statusbits_i, + FEE_DATA_IN => fee_data_i, + FEE_DATA_WRITE_IN(0) => fee_data_write_i, + FEE_DATA_FINISHED_IN(0) => fee_data_finished_i, + FEE_DATA_ALMOST_FULL_OUT(0) => fee_almost_full_i, + + -- Slow Control Data Port + REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00 + REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 + REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe, + REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe, + REGIO_STAT_REG_IN => stat_reg, --start 0x80 + REGIO_CTRL_REG_OUT => ctrl_reg, --start 0xc0 + REGIO_STAT_STROBE_OUT => stat_reg_strobe, + REGIO_CTRL_STROBE_OUT => ctrl_reg_strobe, + REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE, + REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'), + + BUS_ADDR_OUT => regio_addr_out, + BUS_READ_ENABLE_OUT => regio_read_enable_out, + BUS_WRITE_ENABLE_OUT => regio_write_enable_out, + BUS_DATA_OUT => regio_data_out, + BUS_DATA_IN => regio_data_in, + BUS_DATAREADY_IN => regio_dataready_in, + BUS_NO_MORE_DATA_IN => regio_no_more_data_in, + BUS_WRITE_ACK_IN => regio_write_ack_in, + BUS_UNKNOWN_ADDR_IN => regio_unknown_addr_in, + BUS_TIMEOUT_OUT => regio_timeout_out, + ONEWIRE_INOUT => TEMPSENS, + ONEWIRE_MONITOR_OUT => open, + + TIME_GLOBAL_OUT => global_time, + TIME_LOCAL_OUT => local_time, + TIME_SINCE_LAST_TRG_OUT => time_since_last_trg, + TIME_TICKS_OUT => timer_ticks, + + STAT_DEBUG_IPU => open, + STAT_DEBUG_1 => open, + STAT_DEBUG_2 => open, + STAT_DEBUG_DATA_HANDLER_OUT => open, + STAT_DEBUG_IPU_HANDLER_OUT => open, + STAT_TRIGGER_OUT => open, + CTRL_MPLEX => (others => '0'), + IOBUF_CTRL_GEN => (others => '0'), + STAT_ONEWIRE => open, + STAT_ADDR_DEBUG => open, + DEBUG_LVL1_HANDLER_OUT => open + ); + + timing_trg_received_i <= TRIGGER_LEFT; --TRIGGER_RIGHT; -- + common_stat_reg <= (others => '0'); + stat_reg <= (others => '0'); + +--------------------------------------------------------------------------- +-- AddOn +--------------------------------------------------------------------------- + +--------------------------------------------------------------------------- +-- Bus Handler +--------------------------------------------------------------------------- + THE_BUS_HANDLER : trb_net16_regio_bus_handler + generic map( + PORT_NUMBER => 10, + PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"d400", 3 => x"c000", 4 => x"c100", 5 => x"c200", 6 => x"c300", 7 => x"c400", 8 => x"c800", 9 => x"cf00", others => x"0000"), + PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 5, 3 => 7, 4 => 5, 5 => 7, 6 => 7, 7 => 7, 8 => 3, 9 => 6, others => 0) + ) + port map( + CLK => clk_100_i, + RESET => reset_i, + + DAT_ADDR_IN => regio_addr_out, + DAT_DATA_IN => regio_data_out, + DAT_DATA_OUT => regio_data_in, + DAT_READ_ENABLE_IN => regio_read_enable_out, + DAT_WRITE_ENABLE_IN => regio_write_enable_out, + DAT_TIMEOUT_IN => regio_timeout_out, + DAT_DATAREADY_OUT => regio_dataready_in, + DAT_WRITE_ACK_OUT => regio_write_ack_in, + DAT_NO_MORE_DATA_OUT => regio_no_more_data_in, + DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in, + + --Bus Handler (SPI CTRL) + BUS_READ_ENABLE_OUT(0) => spictrl_read_en, + BUS_WRITE_ENABLE_OUT(0) => spictrl_write_en, + BUS_DATA_OUT(0*32+31 downto 0*32) => spictrl_data_in, + BUS_ADDR_OUT(0*16) => spictrl_addr, + BUS_ADDR_OUT(0*16+15 downto 0*16+1) => open, + BUS_TIMEOUT_OUT(0) => open, + BUS_DATA_IN(0*32+31 downto 0*32) => spictrl_data_out, + BUS_DATAREADY_IN(0) => spictrl_ack, + BUS_WRITE_ACK_IN(0) => spictrl_ack, + BUS_NO_MORE_DATA_IN(0) => spictrl_busy, + BUS_UNKNOWN_ADDR_IN(0) => '0', + --Bus Handler (SPI Memory) + BUS_READ_ENABLE_OUT(1) => spimem_read_en, + BUS_WRITE_ENABLE_OUT(1) => spimem_write_en, + BUS_DATA_OUT(1*32+31 downto 1*32) => spimem_data_in, + BUS_ADDR_OUT(1*16+5 downto 1*16) => spimem_addr, + BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open, + BUS_TIMEOUT_OUT(1) => open, + BUS_DATA_IN(1*32+31 downto 1*32) => spimem_data_out, + BUS_DATAREADY_IN(1) => spimem_ack, + BUS_WRITE_ACK_IN(1) => spimem_ack, + BUS_NO_MORE_DATA_IN(1) => '0', + BUS_UNKNOWN_ADDR_IN(1) => '0', + --Bus Handler (SPI DAC) + BUS_READ_ENABLE_OUT(2) => spidac_read_en, + BUS_WRITE_ENABLE_OUT(2) => spidac_write_en, + BUS_DATA_OUT(2*32+31 downto 2*32) => spidac_data_in, + BUS_ADDR_OUT(2*16+4 downto 2*16) => spidac_addr, + BUS_ADDR_OUT(2*16+15 downto 2*16+5) => open, + BUS_TIMEOUT_OUT(2) => open, + BUS_DATA_IN(2*32+31 downto 2*32) => spidac_data_out, + BUS_DATAREADY_IN(2) => spidac_ack, + BUS_WRITE_ACK_IN(2) => spidac_ack, + BUS_NO_MORE_DATA_IN(2) => spidac_busy, + BUS_UNKNOWN_ADDR_IN(2) => '0', + --HitRegisters + BUS_READ_ENABLE_OUT(3) => hitreg_read_en, + BUS_WRITE_ENABLE_OUT(3) => hitreg_write_en, + BUS_DATA_OUT(3*32+31 downto 3*32) => open, + BUS_ADDR_OUT(3*16+6 downto 3*16) => hitreg_addr, + BUS_ADDR_OUT(3*16+15 downto 3*16+7) => open, + BUS_TIMEOUT_OUT(3) => open, + BUS_DATA_IN(3*32+31 downto 3*32) => hitreg_data_out, + BUS_DATAREADY_IN(3) => hitreg_data_ready, + BUS_WRITE_ACK_IN(3) => '0', + BUS_NO_MORE_DATA_IN(3) => '0', + BUS_UNKNOWN_ADDR_IN(3) => hitreg_invalid, + --Status Registers + BUS_READ_ENABLE_OUT(4) => srb_read_en, + BUS_WRITE_ENABLE_OUT(4) => srb_write_en, + BUS_DATA_OUT(4*32+31 downto 4*32) => open, + BUS_ADDR_OUT(4*16+6 downto 4*16) => srb_addr, + BUS_ADDR_OUT(4*16+15 downto 4*16+7) => open, + BUS_TIMEOUT_OUT(4) => open, + BUS_DATA_IN(4*32+31 downto 4*32) => srb_data_out, + BUS_DATAREADY_IN(4) => srb_data_ready, + BUS_WRITE_ACK_IN(4) => '0', + BUS_NO_MORE_DATA_IN(4) => '0', + BUS_UNKNOWN_ADDR_IN(4) => srb_invalid, + --Encoder Start Registers + BUS_READ_ENABLE_OUT(5) => esb_read_en, + BUS_WRITE_ENABLE_OUT(5) => esb_write_en, + BUS_DATA_OUT(5*32+31 downto 5*32) => open, + BUS_ADDR_OUT(5*16+6 downto 5*16) => esb_addr, + BUS_ADDR_OUT(5*16+15 downto 5*16+7) => open, + BUS_TIMEOUT_OUT(5) => open, + BUS_DATA_IN(5*32+31 downto 5*32) => esb_data_out, + BUS_DATAREADY_IN(5) => esb_data_ready, + BUS_WRITE_ACK_IN(5) => '0', + BUS_NO_MORE_DATA_IN(5) => '0', + BUS_UNKNOWN_ADDR_IN(5) => esb_invalid, + --Fifo Write Registers + BUS_READ_ENABLE_OUT(6) => efb_read_en, + BUS_WRITE_ENABLE_OUT(6) => efb_write_en, + BUS_DATA_OUT(6*32+31 downto 6*32) => open, + BUS_ADDR_OUT(6*16+6 downto 6*16) => efb_addr, + BUS_ADDR_OUT(6*16+15 downto 6*16+7) => open, + BUS_TIMEOUT_OUT(6) => open, + BUS_DATA_IN(6*32+31 downto 6*32) => efb_data_out, + BUS_DATAREADY_IN(6) => efb_data_ready, + BUS_WRITE_ACK_IN(6) => '0', + BUS_NO_MORE_DATA_IN(6) => '0', + BUS_UNKNOWN_ADDR_IN(6) => efb_invalid, + --Lost Hit Registers + BUS_READ_ENABLE_OUT(7) => lhb_read_en, + BUS_WRITE_ENABLE_OUT(7) => lhb_write_en, + BUS_DATA_OUT(7*32+31 downto 7*32) => open, + BUS_ADDR_OUT(7*16+6 downto 7*16) => lhb_addr, + BUS_ADDR_OUT(7*16+15 downto 7*16+7) => open, + BUS_TIMEOUT_OUT(7) => open, + BUS_DATA_IN(7*32+31 downto 7*32) => lhb_data_out, + BUS_DATAREADY_IN(7) => lhb_data_ready, + BUS_WRITE_ACK_IN(7) => '0', + BUS_NO_MORE_DATA_IN(7) => '0', + BUS_UNKNOWN_ADDR_IN(7) => lhb_invalid, + --TDC config registers + BUS_READ_ENABLE_OUT(8) => tdc_ctrl_read, + BUS_WRITE_ENABLE_OUT(8) => tdc_ctrl_write, + BUS_DATA_OUT(8*32+31 downto 8*32) => tdc_ctrl_data_in, + BUS_ADDR_OUT(8*16+2 downto 8*16) => tdc_ctrl_addr, + BUS_ADDR_OUT(8*16+15 downto 8*16+3) => open, + BUS_TIMEOUT_OUT(8) => open, + BUS_DATA_IN(8*32+31 downto 8*32) => tdc_ctrl_data_out, + BUS_DATAREADY_IN(8) => last_tdc_ctrl_read, + BUS_WRITE_ACK_IN(8) => tdc_ctrl_write, + BUS_NO_MORE_DATA_IN(8) => '0', + BUS_UNKNOWN_ADDR_IN(8) => '0', + --Trigger logic registers + BUS_READ_ENABLE_OUT(9) => trig_read, + BUS_WRITE_ENABLE_OUT(9) => trig_write, + BUS_DATA_OUT(9*32+31 downto 9*32) => trig_din, + BUS_ADDR_OUT(9*16+15 downto 9*16) => trig_addr, + BUS_TIMEOUT_OUT(9) => open, + BUS_DATA_IN(9*32+31 downto 9*32) => trig_dout, + BUS_DATAREADY_IN(9) => trig_ack, + BUS_WRITE_ACK_IN(9) => trig_ack, + BUS_NO_MORE_DATA_IN(9) => '0', + BUS_UNKNOWN_ADDR_IN(9) => trig_nack, + + STAT_DEBUG => open + ); + + PROC_TDC_CTRL_REG : process + variable pos : integer; + begin + wait until rising_edge(clk_100_i); + pos := to_integer(unsigned(tdc_ctrl_addr))*32; + tdc_ctrl_data_out <= tdc_ctrl_reg(pos+31 downto pos); + last_tdc_ctrl_read <= tdc_ctrl_read; + if tdc_ctrl_write = '1' then + tdc_ctrl_reg(pos+31 downto pos) <= tdc_ctrl_data_in; + end if; + end process; + +--------------------------------------------------------------------------- +-- SPI / Flash +--------------------------------------------------------------------------- + + THE_SPI_MASTER : spi_master + port map( + CLK_IN => clk_100_i, + RESET_IN => reset_i, + -- Slave bus + BUS_READ_IN => spictrl_read_en, + BUS_WRITE_IN => spictrl_write_en, + BUS_BUSY_OUT => spictrl_busy, + BUS_ACK_OUT => spictrl_ack, + BUS_ADDR_IN(0) => spictrl_addr, + BUS_DATA_IN => spictrl_data_in, + BUS_DATA_OUT => spictrl_data_out, + -- SPI connections + SPI_CS_OUT => FLASH_CS, + SPI_SDI_IN => FLASH_DOUT, + SPI_SDO_OUT => FLASH_DIN, + SPI_SCK_OUT => FLASH_CLK, + -- BRAM for read/write data + BRAM_A_OUT => spi_bram_addr, + BRAM_WR_D_IN => spi_bram_wr_d, + BRAM_RD_D_OUT => spi_bram_rd_d, + BRAM_WE_OUT => spi_bram_we, + -- Status lines + STAT => open + ); + + -- data memory for SPI accesses + THE_SPI_MEMORY : spi_databus_memory + port map( + CLK_IN => clk_100_i, + RESET_IN => reset_i, + -- Slave bus + BUS_ADDR_IN => spimem_addr, + BUS_READ_IN => spimem_read_en, + BUS_WRITE_IN => spimem_write_en, + BUS_ACK_OUT => spimem_ack, + BUS_DATA_IN => spimem_data_in, + BUS_DATA_OUT => spimem_data_out, + -- state machine connections + BRAM_ADDR_IN => spi_bram_addr, + BRAM_WR_D_OUT => spi_bram_wr_d, + BRAM_RD_D_IN => spi_bram_rd_d, + BRAM_WE_IN => spi_bram_we, + -- Status lines + STAT => open + ); + +------------------------------------------------------------------------------- +-- SPI +------------------------------------------------------------------------------- + gen_SPI : if INCLUDE_SPI = 1 generate + DAC_SPI : spi_ltc2600 + port map ( + CLK_IN => clk_100_i, + RESET_IN => reset_i, + -- Slave bus + BUS_READ_IN => spidac_read_en, + BUS_WRITE_IN => spidac_write_en, + BUS_BUSY_OUT => spidac_busy, + BUS_ACK_OUT => spidac_ack, + BUS_ADDR_IN => spidac_addr, + BUS_DATA_IN => spidac_data_in, + BUS_DATA_OUT => spidac_data_out, + -- SPI connections + SPI_CS_OUT(3 downto 0) => DAC_CS, + SPI_SDI_IN => '0', + SPI_SDO_OUT => DAC_SDI, + SPI_SCK_OUT => DAC_SCK, + SPI_CLR_OUT => open); + end generate; + +--------------------------------------------------------------------------- +-- Trigger logic +--------------------------------------------------------------------------- + gen_TRIGGER_LOGIC : if INCLUDE_TRIGGER_LOGIC = 1 generate + THE_TRIG_LOGIC : input_to_trigger_logic + generic map( + INPUTS => 32, + OUTPUTS => 4 + ) + port map( + CLK => clk_100_i, + + INPUT => INP(32 downto 1), + OUTPUT => trig_out, + + DATA_IN => trig_din, + DATA_OUT => trig_dout, + WRITE_IN => trig_write, + READ_IN => trig_read, + ACK_OUT => trig_ack, + NACK_OUT => trig_nack, + ADDR_IN => trig_addr + ); + FPGA5_COMM(10 downto 7) <= trig_out; + end generate; + +--------------------------------------------------------------------------- +-- Reboot FPGA +--------------------------------------------------------------------------- + THE_FPGA_REBOOT : fpga_reboot + port map( + CLK => clk_100_i, + RESET => reset_i, + DO_REBOOT => common_ctrl_reg(15), + PROGRAMN => PROGRAMN + ); + +--------------------------------------------------------------------------- +-- LED +--------------------------------------------------------------------------- + LED_GREEN <= not med_stat_op(9); + LED_ORANGE <= not med_stat_op(10); + LED_RED <= not INP(0); + LED_YELLOW <= not med_stat_op(11); + +--------------------------------------------------------------------------- +-- Test Connector - Logic Analyser +--------------------------------------------------------------------------- + + TEST_LINE <= logic_analyser_i; + +------------------------------------------------------------------------------- +-- TDC +------------------------------------------------------------------------------- + + THE_TDC : TDC + generic map ( + CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels + STATUS_REG_NR => 20, -- Number of status regs + CONTROL_REG_NR => 5, -- Number of control regs - higher than 8 check tdc_ctrl_addr + TDC_VERSION => x"160", -- TDC version number + DEBUG => c_YES, + SIMULATION => c_NO) + port map ( + RESET => reset_i, + CLK_TDC => CLK_PCLK_LEFT, -- Clock used for the time measurement + CLK_READOUT => clk_100_i, -- Clock for the readout + REFERENCE_TIME => timing_trg_received_i, -- Reference time input + HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals + HIT_CALIBRATION => osc_int, -- Hits for calibrating the TDC + TRG_WIN_PRE => tdc_ctrl_reg(42 downto 32), -- Pre-Trigger window width + TRG_WIN_POST => tdc_ctrl_reg(58 downto 48), -- Post-Trigger window width + -- + -- Trigger signals from handler + TRG_DATA_VALID_IN => trg_data_valid_i, -- trig data valid signal from trbnet + VALID_TIMING_TRG_IN => trg_timing_valid_i, -- valid timing trigger signal from trbnet + VALID_NOTIMING_TRG_IN => trg_notiming_valid_i, -- valid notiming signal from trbnet + INVALID_TRG_IN => trg_invalid_i, -- invalid trigger signal from trbnet + TMGTRG_TIMEOUT_IN => trg_timeout_detected_i, -- timing trigger timeout signal from trbnet + SPIKE_DETECTED_IN => trg_spike_detected_i, + MULTI_TMG_TRG_IN => trg_multiple_trg_i, + SPURIOUS_TRG_IN => trg_spurious_trg_i, + -- + TRG_NUMBER_IN => trg_number_i, -- LVL1 trigger information package + TRG_CODE_IN => trg_code_i, -- + TRG_INFORMATION_IN => trg_information_i, -- + TRG_TYPE_IN => trg_type_i, -- LVL1 trigger information package + -- + --Response to handler + TRG_RELEASE_OUT => fee_trg_release_i, -- trigger release signal + TRG_STATUSBIT_OUT => fee_trg_statusbits_i, -- status information of the tdc + DATA_OUT => fee_data_i, -- tdc data + DATA_WRITE_OUT => fee_data_write_i, -- data valid signal + DATA_FINISHED_OUT => fee_data_finished_i, -- readout finished signal + -- + --Hit Counter Bus + HCB_READ_EN_IN => hitreg_read_en, -- bus read en strobe + HCB_WRITE_EN_IN => hitreg_write_en, -- bus write en strobe + HCB_ADDR_IN => hitreg_addr, -- bus address + HCB_DATA_OUT => hitreg_data_out, -- bus data + HCB_DATAREADY_OUT => hitreg_data_ready, -- bus data ready strobe + HCB_UNKNOWN_ADDR_OUT => hitreg_invalid, -- bus invalid addr + --Status Registers Bus + SRB_READ_EN_IN => srb_read_en, -- bus read en strobe + SRB_WRITE_EN_IN => srb_write_en, -- bus write en strobe + SRB_ADDR_IN => srb_addr, -- bus address + SRB_DATA_OUT => srb_data_out, -- bus data + SRB_DATAREADY_OUT => srb_data_ready, -- bus data ready strobe + SRB_UNKNOWN_ADDR_OUT => srb_invalid, -- bus invalid addr + --Encoder Start Registers Bus + ESB_READ_EN_IN => esb_read_en, -- bus read en strobe + ESB_WRITE_EN_IN => esb_write_en, -- bus write en strobe + ESB_ADDR_IN => esb_addr, -- bus address + ESB_DATA_OUT => esb_data_out, -- bus data + ESB_DATAREADY_OUT => esb_data_ready, -- bus data ready strobe + ESB_UNKNOWN_ADDR_OUT => esb_invalid, -- bus invalid addr + --Fifo Write Registers Bus + EFB_READ_EN_IN => efb_read_en, -- bus read en strobe + EFB_WRITE_EN_IN => efb_write_en, -- bus write en strobe + EFB_ADDR_IN => efb_addr, -- bus address + EFB_DATA_OUT => efb_data_out, -- bus data + EFB_DATAREADY_OUT => efb_data_ready, -- bus data ready strobe + EFB_UNKNOWN_ADDR_OUT => efb_invalid, -- bus invalid addr + --Lost Hit Registers Bus + LHB_READ_EN_IN => lhb_read_en, -- bus read en strobe + LHB_WRITE_EN_IN => lhb_write_en, -- bus write en strobe + LHB_ADDR_IN => lhb_addr, -- bus address + LHB_DATA_OUT => lhb_data_out, -- bus data + LHB_DATAREADY_OUT => lhb_data_ready, -- bus data ready strobe + LHB_UNKNOWN_ADDR_OUT => lhb_invalid, -- bus invalid addr + -- + LOGIC_ANALYSER_OUT => logic_analyser_i, + CONTROL_REG_IN => tdc_ctrl_reg); + + -- For single edge measurements + gen_single : if USE_DOUBLE_EDGE = 0 generate + hit_in_i <= INP; + end generate; + + -- For ToT Measurements + gen_double : if USE_DOUBLE_EDGE = 1 generate + Gen_Hit_In_Signals : for i in 1 to 32 generate + hit_in_i(i*2-1) <= INP(i-1); + hit_in_i(i*2) <= not INP(i-1); + end generate Gen_Hit_In_Signals; + end generate; + +end architecture; diff --git a/base/trb3_periph_ADA.lpf b/base/trb3_periph_ADA.lpf new file mode 100644 index 0000000..56c8eac --- /dev/null +++ b/base/trb3_periph_ADA.lpf @@ -0,0 +1,218 @@ +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +BLOCK RD_DURING_WR_PATHS ; + + +################################################################# +# Basic Settings +################################################################# + +SYSCONFIG MCCLK_FREQ = 20; + +FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; +FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; +FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; +FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz; + +################################################################# +# Clock I/O +################################################################# +LOCATE COMP "CLK_GPLL_LEFT" SITE "U25"; +LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1"; +LOCATE COMP "CLK_PCLK_LEFT" SITE "M4"; +LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20"; +LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10"; +LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18"; + +DEFINE PORT GROUP "CLK_group" "CLK*" ; +IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ; + +################################################################# +# Trigger I/O +################################################################# + +#Trigger from fan-out +LOCATE COMP "TRIGGER_RIGHT" SITE "N24"; +IOBUF PORT "TRIGGER_RIGHT" IO_TYPE=LVDS25; + +LOCATE COMP "TRIGGER_LEFT" SITE "V3"; +IOBUF PORT "TRIGGER_LEFT" IO_TYPE=LVDS25; + +################################################################# +# To central FPGA +################################################################# + +LOCATE COMP "FPGA5_COMM_0" SITE "AD4"; +LOCATE COMP "FPGA5_COMM_1" SITE "AE3"; +LOCATE COMP "FPGA5_COMM_2" SITE "AA7"; +LOCATE COMP "FPGA5_COMM_3" SITE "AB7"; +LOCATE COMP "FPGA5_COMM_4" SITE "AD3"; +LOCATE COMP "FPGA5_COMM_5" SITE "AC4"; +LOCATE COMP "FPGA5_COMM_6" SITE "AE2"; +LOCATE COMP "FPGA5_COMM_7" SITE "AF3"; +LOCATE COMP "FPGA5_COMM_8" SITE "AE4"; +LOCATE COMP "FPGA5_COMM_9" SITE "AF4"; +LOCATE COMP "FPGA5_COMM_10" SITE "V10"; +LOCATE COMP "FPGA5_COMM_11" SITE "W10"; +DEFINE PORT GROUP "FPGA_group" "FPGA*" ; +IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ; + +LOCATE COMP "TEST_LINE_0" SITE "A5"; +LOCATE COMP "TEST_LINE_1" SITE "A6"; +LOCATE COMP "TEST_LINE_2" SITE "G8"; +LOCATE COMP "TEST_LINE_3" SITE "F9"; +LOCATE COMP "TEST_LINE_4" SITE "D9"; +LOCATE COMP "TEST_LINE_5" SITE "D10"; +LOCATE COMP "TEST_LINE_6" SITE "F10"; +LOCATE COMP "TEST_LINE_7" SITE "E10"; +LOCATE COMP "TEST_LINE_8" SITE "A8"; +LOCATE COMP "TEST_LINE_9" SITE "B8"; +LOCATE COMP "TEST_LINE_10" SITE "G10"; +LOCATE COMP "TEST_LINE_11" SITE "G9"; +LOCATE COMP "TEST_LINE_12" SITE "C9"; +LOCATE COMP "TEST_LINE_13" SITE "C10"; +LOCATE COMP "TEST_LINE_14" SITE "H10"; +LOCATE COMP "TEST_LINE_15" SITE "H11"; +DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ; +IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12; + +################################################################# +# TDC INPUTS +################################################################# + +LOCATE COMP "INP_0" SITE "P1"; +LOCATE COMP "INP_1" SITE "T2"; +LOCATE COMP "INP_2" SITE "R1"; +LOCATE COMP "INP_3" SITE "N3"; +LOCATE COMP "INP_4" SITE "P5"; +LOCATE COMP "INP_5" SITE "N5"; +LOCATE COMP "INP_6" SITE "AC2"; +LOCATE COMP "INP_7" SITE "AB1"; +LOCATE COMP "INP_8" SITE "AA1"; +LOCATE COMP "INP_9" SITE "W7"; +LOCATE COMP "INP_10" SITE "Y5"; +LOCATE COMP "INP_11" SITE "V6"; +LOCATE COMP "INP_12" SITE "H2"; +LOCATE COMP "INP_13" SITE "K3"; +LOCATE COMP "INP_14" SITE "H1"; +LOCATE COMP "INP_15" SITE "M5"; +LOCATE COMP "INP_16" SITE "AD1"; +LOCATE COMP "INP_17" SITE "AB5"; +LOCATE COMP "INP_18" SITE "AB3"; +LOCATE COMP "INP_19" SITE "Y6"; +LOCATE COMP "INP_20" SITE "AA3"; +LOCATE COMP "INP_21" SITE "W8"; +LOCATE COMP "INP_22" SITE "V1"; +LOCATE COMP "INP_23" SITE "T1"; +LOCATE COMP "INP_24" SITE "P4"; +LOCATE COMP "INP_25" SITE "T3"; +LOCATE COMP "INP_26" SITE "R5"; +LOCATE COMP "INP_27" SITE "T7"; +LOCATE COMP "INP_28" SITE "K2"; +LOCATE COMP "INP_29" SITE "J4"; +LOCATE COMP "INP_30" SITE "D1"; +LOCATE COMP "INP_31" SITE "K4"; +LOCATE COMP "INP_32" SITE "J23"; +LOCATE COMP "INP_33" SITE "G26"; +LOCATE COMP "INP_34" SITE "F24"; +LOCATE COMP "INP_35" SITE "H26"; +LOCATE COMP "INP_36" SITE "K23"; +LOCATE COMP "INP_37" SITE "F25"; +LOCATE COMP "INP_38" SITE "AC26"; +LOCATE COMP "INP_39" SITE "Y19"; +LOCATE COMP "INP_40" SITE "AB24"; +LOCATE COMP "INP_41" SITE "Y22"; +LOCATE COMP "INP_42" SITE "AD24"; +LOCATE COMP "INP_43" SITE "AE25"; +LOCATE COMP "INP_44" SITE "W23"; +LOCATE COMP "INP_45" SITE "AA25"; +LOCATE COMP "INP_46" SITE "AA26"; +LOCATE COMP "INP_47" SITE "W21"; +LOCATE COMP "INP_48" SITE "H24"; +LOCATE COMP "INP_49" SITE "L20"; +LOCATE COMP "INP_50" SITE "K24"; +LOCATE COMP "INP_51" SITE "M23"; +LOCATE COMP "INP_52" SITE "L24"; +LOCATE COMP "INP_53" SITE "M22"; +LOCATE COMP "INP_54" SITE "J26"; +LOCATE COMP "INP_55" SITE "N23"; +LOCATE COMP "INP_56" SITE "K19"; +LOCATE COMP "INP_57" SITE "P23"; +LOCATE COMP "INP_58" SITE "L25"; +LOCATE COMP "INP_59" SITE "P21"; +LOCATE COMP "INP_60" SITE "R25"; +LOCATE COMP "INP_61" SITE "T25"; +LOCATE COMP "INP_62" SITE "T26"; +LOCATE COMP "INP_63" SITE "V21"; + +DEFINE PORT GROUP "INP_group" "INP*" ; +IOBUF GROUP "INP_group" IO_TYPE=LVDS25 DIFFRESISTOR=100; + + +################################################################# +# Additional Lines to AddOn +################################################################# + +#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3 +#all lines are input only +#line 4/5 go to PLL input +#LOCATE COMP "SPARE_LINE_0" SITE "M25"; #194 +#LOCATE COMP "SPARE_LINE_1" SITE "M26"; #196 +#LOCATE COMP "SPARE_LINE_2" SITE "W4"; #198 +#LOCATE COMP "SPARE_LINE_3" SITE "W5"; #200 + +LOCATE COMP "DAC_SDI" SITE "D4"; #"DQUL_2" DQUL0_2 #78 +LOCATE COMP "DAC_SCK" SITE "C3"; #"DQUL_4" DQUL0_4 #82 +LOCATE COMP "DAC_CS_1" SITE "H6"; #"DQUL_10" DQUL0_8 #94 +LOCATE COMP "DAC_CS_2" SITE "AA24"; #"DQUL_10" DQUL0_8 #94 +LOCATE COMP "DAC_CS_3" SITE "U24"; #"DQUL_10" DQUL0_8 #94 +LOCATE COMP "DAC_CS_4" SITE "U23"; #"DQUL_10" DQUL0_8 #94 +LOCATE COMP "DAC_SDO" SITE "G5"; #"DQUL_6" DQSUL0_T #86 + +DEFINE PORT GROUP "DAC_group" "DAC_*" ; +IOBUF GROUP "DAC_group" IO_TYPE=LVDS25; + +#IOBUF PORT "DAC_SDO" IO_TYPE=LVDS25 DIFFRESISTOR=100; + +################################################################# +# DAC SPI & Flash ROM & Reboot +################################################################# + +LOCATE COMP "FLASH_CLK" SITE "B12"; +LOCATE COMP "FLASH_CS" SITE "E11"; +LOCATE COMP "FLASH_DIN" SITE "E12"; +LOCATE COMP "FLASH_DOUT" SITE "A12"; + +DEFINE PORT GROUP "FLASH_group" "FLASH*" ; +IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE; + +LOCATE COMP "PROGRAMN" SITE "B11"; +IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; + + +################################################################# +# Misc +################################################################# +LOCATE COMP "TEMPSENS" SITE "A13"; +IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; + +#coding of FPGA number +LOCATE COMP "CODE_LINE_1" SITE "AA20"; +LOCATE COMP "CODE_LINE_0" SITE "Y21"; +IOBUF PORT "CODE_LINE_1" IO_TYPE=LVCMOS25 PULLMODE=UP ; +IOBUF PORT "CODE_LINE_0" IO_TYPE=LVCMOS25 PULLMODE=UP ; + +#terminated differential pair to pads +LOCATE COMP "SUPPL" SITE "C14"; +IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ; + + +################################################################# +# LED +################################################################# +LOCATE COMP "LED_GREEN" SITE "F12"; +LOCATE COMP "LED_ORANGE" SITE "G13"; +LOCATE COMP "LED_RED" SITE "A15"; +LOCATE COMP "LED_YELLOW" SITE "A16"; +DEFINE PORT GROUP "LED_group" "LED*" ; +IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12; -- 2.43.0