From c5a0b860d238f6d87a0ccb844c18c071233d8ba6 Mon Sep 17 00:00:00 2001
From: hadeshyp <hadeshyp>
Date: Mon, 4 Oct 2010 11:59:53 +0000
Subject: [PATCH] *** empty log message ***

---
 testbenches/error_generator.vhd | 202 ++++++++++++++++++++++++++++++++
 1 file changed, 202 insertions(+)
 create mode 100644 testbenches/error_generator.vhd

diff --git a/testbenches/error_generator.vhd b/testbenches/error_generator.vhd
new file mode 100644
index 0000000..0af128f
--- /dev/null
+++ b/testbenches/error_generator.vhd
@@ -0,0 +1,202 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+USE ieee.math_real.all;
+
+library work;
+
+entity error_generator is
+port(
+	RXCLK_IN             : in  std_logic;
+	RESET_IN             : in  std_logic;
+
+	RX1_DATA_IN          : in  std_logic_vector(7 downto 0);
+	RX1_DATA_OUT         : out std_logic_vector(7 downto 0);
+	
+	RX2_DATA_IN          : in  std_logic_vector(7 downto 0);
+	RX2_DATA_OUT         : out std_logic_vector(7 downto 0);
+
+	RX1_K_IN             : in  std_logic;
+	RX1_K_OUT            : out std_logic;
+
+	RX2_K_IN             : in  std_logic;
+	RX2_K_OUT            : out std_logic;
+
+	RX1_CV_IN            : in  std_logic;
+	RX1_CV_OUT           : out std_logic;
+
+	RX2_CV_IN            : in  std_logic;
+	RX2_CV_OUT           : out std_logic
+  );
+end entity;
+
+architecture arch of error_generator is
+
+begin
+
+CV1_PROC : process
+variable seed1    : positive;
+variable seed2    : positive := 1;
+variable rand     : real;
+variable int_rand : integer;
+begin
+
+	wait until rising_edge(RXCLK_IN);
+
+	UNIFORM(seed1, seed2, rand);
+	int_rand := INTEGER(TRUNC(rand * 256.0));
+
+	if( (int_rand MOD 40) = 0 ) then
+		RX1_CV_OUT <= not RX1_CV_IN;
+		assert false report "RX1_CV" severity note;
+		wait for 40 ns;
+		RX1_CV_OUT <= RX1_CV_IN;
+	else
+		RX1_CV_OUT <= RX1_CV_IN;
+	end if;
+
+	wait for 400 ns;
+
+end process;
+
+CV2_PROC : process
+variable seed1    : positive;
+variable seed2    : positive := 2;
+variable rand     : real;
+variable int_rand : integer;
+begin
+
+	wait until rising_edge(RXCLK_IN);
+
+	UNIFORM(seed1, seed2, rand);
+	int_rand := INTEGER(TRUNC(rand * 256.0));
+
+	if( (int_rand MOD 40) = 0 ) then
+		RX2_CV_OUT <= not RX2_CV_IN;
+		assert false report "RX2_CV" severity note;
+		wait for 40 ns;
+		RX2_CV_OUT <= RX2_CV_IN;
+	else
+		RX2_CV_OUT <= RX2_CV_IN;
+	end if;
+
+	wait for 400 ns;
+
+end process;
+
+RD1_DATA_proc : process
+variable seed1    : positive;
+variable seed2    : positive := 3;
+variable rand     : real;
+variable int_rand : integer;
+begin
+
+	wait until rising_edge(RXCLK_IN);
+
+	UNIFORM(seed1, seed2, rand);
+	int_rand := INTEGER(TRUNC(rand * 256.0));
+
+	if( (int_rand MOD 40) = 0 ) then
+
+		UNIFORM(seed1, seed2, rand);
+		int_rand := INTEGER(TRUNC(rand * 256.0));
+
+		RX1_DATA_OUT(int_rand mod 8) <= not RX1_DATA_IN(int_rand mod 8);
+
+		assert false report "RX1_DATA" severity note;
+
+		wait for 40 ns;
+		RX1_DATA_OUT <= RX1_DATA_IN;
+	else
+		RX1_DATA_OUT <= RX1_DATA_IN;
+	end if;
+
+	wait for 400 ns;
+
+end process;
+
+RD2_DATA_proc : process
+variable seed1    : positive;
+variable seed2    : positive := 4;
+variable rand     : real;
+variable int_rand : integer;
+begin
+
+	wait until rising_edge(RXCLK_IN);
+
+	UNIFORM(seed1, seed2, rand);
+	int_rand := INTEGER(TRUNC(rand * 256.0));
+
+	if( (int_rand MOD 40) = 0 ) then
+
+		UNIFORM(seed1, seed2, rand);
+		int_rand := INTEGER(TRUNC(rand * 256.0));
+
+		RX2_DATA_OUT(int_rand mod 8) <= not RX2_DATA_IN(int_rand mod 8);
+
+		assert false report "RX2_DATA" severity note;
+
+		wait for 40 ns;
+		RX2_DATA_OUT <= RX2_DATA_IN;
+	else
+		RX2_DATA_OUT <= RX2_DATA_IN;
+	end if;
+
+	wait for 400 ns;
+
+end process;
+
+K1_PROC : process
+variable seed1    : positive;
+variable seed2    : positive := 5;
+variable rand     : real;
+variable int_rand : integer;
+begin
+
+	wait until rising_edge(RXCLK_IN);
+
+	UNIFORM(seed1, seed2, rand);
+	int_rand := INTEGER(TRUNC(rand * 256.0));
+
+	if( (int_rand MOD 40) = 0 ) then
+		RX1_K_OUT <= not RX1_K_IN;
+		assert false report "RX1_K" severity note;
+		wait for 40 ns;
+		RX1_K_OUT <= RX1_K_IN;
+	else
+		RX1_K_OUT <= RX1_K_IN;
+	end if;
+
+	wait for 400 ns;
+
+end process;
+
+K2_PROC : process
+variable seed1    : positive;
+variable seed2    : positive := 6;
+variable rand     : real;
+variable int_rand : integer;
+begin
+
+	wait until rising_edge(RXCLK_IN);
+
+	UNIFORM(seed1, seed2, rand);
+	int_rand := INTEGER(TRUNC(rand * 256.0));
+
+	if( (int_rand MOD 40) = 0 ) then
+		RX2_K_OUT <= not RX2_K_IN;
+		assert false report "RX2_K" severity note;
+		wait for 40 ns;
+		RX2_K_OUT <= RX2_K_IN;
+	else
+		RX2_K_OUT <= RX2_K_IN;
+	end if;
+
+	wait for 400 ns;
+
+end process;
+
+end architecture;
+
+
+
-- 
2.43.0