From c5aceb1f71e38e2716301c316fbdf963dcbd91e9 Mon Sep 17 00:00:00 2001 From: Ingo Froehlich Date: Thu, 17 Jan 2019 10:06:06 +0100 Subject: [PATCH] dirich working in Lab --- media_interfaces/med_ecp3_sfp_sync.vhd | 51 +++++++++++++++++++++- media_interfaces/med_ecp3_sfp_sync_4.vhd | 12 ++++- media_interfaces/sync/med_sync_control.vhd | 4 +- media_interfaces/sync/rx_control.vhd | 4 +- 4 files changed, 65 insertions(+), 6 deletions(-) diff --git a/media_interfaces/med_ecp3_sfp_sync.vhd b/media_interfaces/med_ecp3_sfp_sync.vhd index c4433c4..fce92c8 100644 --- a/media_interfaces/med_ecp3_sfp_sync.vhd +++ b/media_interfaces/med_ecp3_sfp_sync.vhd @@ -100,6 +100,12 @@ signal hdinp, hdinn, hdoutp, hdoutn : std_logic; attribute nopad : string; attribute nopad of hdinp, hdinn, hdoutp, hdoutn : signal is "true"; +signal mii_tx_i : CTRLBUS_TX; +signal mii_rx_i : CTRLBUS_RX; + +signal loc_bus_rx : CTRLBUS_RX; +signal loc_bus_tx : CTRLBUS_TX; + begin @@ -268,7 +274,11 @@ THE_MED_CONTROL : entity work.med_sync_control STAT_RX_CONTROL => stat_rx_control_i, DEBUG_TX_CONTROL => debug_tx_control_i, DEBUG_RX_CONTROL => debug_rx_control_i, - STAT_RESET => stat_fsm_reset_i + STAT_RESET => stat_fsm_reset_i, + + BUS_RX => mii_rx_i, + BUS_TX => mii_tx_i + ); THE_SCI_READER : entity work.sci_reader @@ -289,6 +299,9 @@ THE_SCI_READER : entity work.sci_reader --Slowcontrol BUS_RX => BUS_RX, BUS_TX => BUS_TX, + + LOC_BUS_RX => loc_BUS_RX, + LOC_BUS_TX => loc_BUS_TX, --MEDIA_STATUS_REG_IN(31 downto 0) => stat_rx_control_i, --MEDIA_STATUS_REG_IN(63 downto 32) => stat_tx_control_i, @@ -297,6 +310,42 @@ THE_SCI_READER : entity work.sci_reader DEBUG_OUT => open ); + +BUS_WRITER : process + begin + wait until rising_edge(SYSCLK); + loc_BUS_TX.unknown <= '0'; + loc_BUS_TX.rack <= '0'; + loc_BUS_TX.wack <= '0'; + loc_BUS_TX.data <= x"00000000"; + loc_BUS_TX.ack <= '0'; + + mii_rx_i.data <= loc_BUS_RX.data; + mii_rx_i.addr <= loc_BUS_RX.addr; + mii_rx_i.read <= '0'; + mii_rx_i.write <= '0'; + + if loc_BUS_RX.addr(2) = '0' then + if loc_BUS_RX.read = '1' then + loc_BUS_TX.ack <= '1'; + case loc_BUS_RX.addr(4 downto 0) is + when "00000" => loc_BUS_TX.data <= stat_rx_control_i(31 downto 0); + when "00001" => loc_BUS_TX.data <= stat_tx_control_i(31 downto 0); + when "00010" => loc_BUS_TX.data <= stat_fsm_reset_i(31 downto 0); + end case; + end if; + else + if mii_tx_i.ack = '1' then + loc_BUS_TX.data <= mii_tx_i.data; + loc_BUS_TX.ack <= '1'; + loc_BUS_TX.unknown <= mii_tx_i.unknown; + end if; + mii_rx_i.read <= loc_BUS_RX.read; + mii_rx_i.write <= loc_BUS_RX.write; + end if; +end process; + + -- STAT_DEBUG(4 downto 0) <= debug_rx_control_i(4 downto 0); -- STAT_DEBUG(6 downto 5) <= stat_fsm_reset_i(9 downto 8); -- STAT_DEBUG(7) <= '0'; diff --git a/media_interfaces/med_ecp3_sfp_sync_4.vhd b/media_interfaces/med_ecp3_sfp_sync_4.vhd index 16b6831..094ee3e 100644 --- a/media_interfaces/med_ecp3_sfp_sync_4.vhd +++ b/media_interfaces/med_ecp3_sfp_sync_4.vhd @@ -14,7 +14,7 @@ use work.med_sync_define.all; entity med_ecp3_sfp_sync_4 is generic( IS_SYNC_SLAVE : int_array_t(0 to 3) := (c_NO, c_NO, c_NO, c_NO); --select slave mode - IS_USED : int_array_t(0 to 3) := (c_YES,c_YES,c_YES,c_YES); + IS_USED : int_array_t(0 to 3) := (c_YES,c_YES,c_YES,c_YES) ); port( CLK_REF_FULL : in std_logic; -- 200 MHz reference clock @@ -417,7 +417,15 @@ BUS_WRITER : process case loc_BUS_RX.addr(4 downto 0) is when "00000" => loc_BUS_TX.data <= stat_rx_control_i(31 downto 0); when "00001" => loc_BUS_TX.data <= stat_tx_control_i(31 downto 0); - when "00010" => loc_BUS_TX.data <= stat_fsm_reset_i(31 downto 0); + when "01000" => loc_BUS_TX.data <= stat_rx_control_i(63 downto 32); + when "01001" => loc_BUS_TX.data <= stat_tx_control_i(63 downto 32); + when "10000" => loc_BUS_TX.data <= stat_rx_control_i(95 downto 64); + when "10001" => loc_BUS_TX.data <= stat_tx_control_i(95 downto 64); + when "11000" => loc_BUS_TX.data <= stat_rx_control_i(127 downto 96); + when "11001" => loc_BUS_TX.data <= stat_tx_control_i(127 downto 96); + + --when "00010" => loc_BUS_TX.data <= stat_fsm_reset_i(31 downto 0); + when "00010" => loc_BUS_TX.data <= x"affeaffe"; when "00011" => loc_BUS_TX.data <= x"000000" & std_logic_vector(cv_cnt_sys(0)); when "01011" => loc_BUS_TX.data <= x"000000" & std_logic_vector(cv_cnt_sys(1)); when "10011" => loc_BUS_TX.data <= x"000000" & std_logic_vector(cv_cnt_sys(2)); diff --git a/media_interfaces/sync/med_sync_control.vhd b/media_interfaces/sync/med_sync_control.vhd index a327759..7fa35ea 100644 --- a/media_interfaces/sync/med_sync_control.vhd +++ b/media_interfaces/sync/med_sync_control.vhd @@ -348,8 +348,8 @@ THE_RX_CONTROL : rx_control FORCE_CRC_ERROR => force_crc_error, CRC_ERROR_DELAY => crc_error_delay, - --RESET_RETRANSMIT_IN => MEDIA_INT2MED.ctrl_op(15), - RESET_RETRANSMIT_IN => '0', + RESET_RETRANSMIT_IN => MEDIA_INT2MED.ctrl_op(15), + --RESET_RETRANSMIT_IN => '0', --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM RX_DLM => rx_dlm_i, diff --git a/media_interfaces/sync/rx_control.vhd b/media_interfaces/sync/rx_control.vhd index cbac893..eaa38bd 100644 --- a/media_interfaces/sync/rx_control.vhd +++ b/media_interfaces/sync/rx_control.vhd @@ -574,7 +574,9 @@ STAT_REG_OUT(7) <= ct_fifo_write; STAT_REG_OUT(15 downto 8) <= reg_rx_data_in when rising_edge(clk_100); --rx_data(7 downto 0); STAT_REG_OUT(16) <= rx_data(16); STAT_REG_OUT(17) <= use_crc; -STAT_REG_OUT(31 downto 18) <= (others => '0'); +--STAT_REG_OUT(31 downto 18) <= (others => '0'); +STAT_REG_OUT(23 downto 18) <= (others => '0'); +STAT_REG_OUT(31 downto 24) <= good_pos_counter; DEBUG_OUT(3 downto 0) <= rx_state_bits; -- 2.43.0