From c62726209be69123b0133770164eeb81fd302512 Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Mon, 17 Jan 2022 15:31:51 +0100 Subject: [PATCH] RST distribution to be done --- backplanemaster/trb3sc_master.vhd | 24 ++- cts/trb3sc_cts.vhd | 65 ++++-- hub/config_compile_gsi.pl | 2 +- hub/trb3sc_hub.vhd | 340 ++++++++++++++++-------------- 4 files changed, 237 insertions(+), 194 deletions(-) diff --git a/backplanemaster/trb3sc_master.vhd b/backplanemaster/trb3sc_master.vhd index 07b27de..c30262e 100644 --- a/backplanemaster/trb3sc_master.vhd +++ b/backplanemaster/trb3sc_master.vhd @@ -196,6 +196,10 @@ architecture trb3sc_arch of trb3sc_master is signal tx_reset_state : std_logic_vector(3 downto 0); signal debug_i : std_logic_vector(31 downto 0); + signal send_rst_i : std_logic; + signal send_rst_word_i : std_logic_vector(7 downto 0); + signal send_dlm_word_i : std_logic_vector(7 downto 0); + begin --------------------------------------------------------------------------- @@ -252,11 +256,13 @@ THE_MEDIA_INT_MIXED : entity work.med_ecp3_sfp_sync_all_RS --PCSB RX_DLM_OUT(1) => open, RX_DLM_OUT(2) => open, RX_DLM_OUT(3) => rx_dlm_i, - RX_DLM_WORD_OUT => open, +-- RX_DLM_WORD_OUT => open, + RX_DLM_WORD_OUT(23 downto 0) => open, + RX_DLM_WORD_OUT(31 downto 24) => send_dlm_word_i, TX_DLM_IN => rx_dlm_i, - TX_DLM_WORD_IN => x"00", - RX_RST_OUT => open, - RX_RST_WORD_OUT => open, + TX_DLM_WORD_IN => send_dlm_word_i, --x"00", + RX_RST_OUT => send_rst_i, --open, + RX_RST_WORD_OUT => send_rst_word_i, --open, TX_RST_IN => '0', TX_RST_WORD_IN => x"00", -- sync operation @@ -364,11 +370,11 @@ THE_MEDIA_4_DOWN : entity work.med_ecp3_sfp_sync_all_RS --PCSA RX_DLM_OUT => open, RX_DLM_WORD_OUT => open, TX_DLM_IN => rx_dlm_i, - TX_DLM_WORD_IN => x"00", + TX_DLM_WORD_IN => send_dlm_word_i, --x"00", RX_RST_OUT => open, RX_RST_WORD_OUT => open, - TX_RST_IN => '0', - TX_RST_WORD_IN => x"00", + TX_RST_IN => send_rst_i, --'0', + TX_RST_WORD_IN => send_rst_word_i, --x"00", -- sync operation WORD_SYNC_IN => word_sync_i, WORD_SYNC_OUT => open, @@ -793,7 +799,9 @@ end generate; LED_ORANGE <= not debug_i(24 + 2); -- LHD --debug_clock_reset(1); LED_RED <= not debug_i(24 + 1); -- LRR --not sed_error_i; LED_YELLOW <= not debug_i(24 + 0); -- LTR --debug_clock_reset(2); - LED_WHITE <= led; +-- LED_WHITE <= led; + LED_WHITE(0) <= not send_rst_word_i(0); + LED_WHITE(1) <= not send_rst_word_i(1); LED_SFP_GREEN(1) <= not med2int(4).stat_op(9); --SFP Link Status LED_SFP_RED(1) <= not (med2int(4).stat_op(10) or med2int(4).stat_op(11)); --SFP RX/TX gen_led_nogbe : if INCLUDE_GBE = c_NO generate diff --git a/cts/trb3sc_cts.vhd b/cts/trb3sc_cts.vhd index fd703ee..d2ba907 100644 --- a/cts/trb3sc_cts.vhd +++ b/cts/trb3sc_cts.vhd @@ -243,12 +243,18 @@ architecture trb3sc_arch of trb3sc_cts is signal dlm_send_q : std_logic; signal dlm_send_qq : std_logic; - attribute syn_keep : boolean; - attribute syn_preserve : boolean; - attribute syn_keep of tx_dlm_i : signal is true; - attribute syn_preserve of tx_dlm_i : signal is true; - attribute syn_keep of rx_dlm_i : signal is true; - attribute syn_preserve of rx_dlm_i : signal is true; + signal test_reg : std_logic_vector(31 downto 0); + signal pulse_detect : std_logic_vector(7 downto 0); + signal pulse_raising_egde_x : std_logic; + signal pulse_raising_edge : std_logic; + signal send_rst_i : std_logic; + +-- attribute syn_keep : boolean; +-- attribute syn_preserve : boolean; +-- attribute syn_keep of tx_dlm_i : signal is true; +-- attribute syn_preserve of tx_dlm_i : signal is true; +-- attribute syn_keep of rx_dlm_i : signal is true; +-- attribute syn_preserve of rx_dlm_i : signal is true; begin @@ -346,16 +352,16 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate RX_DLM_OUT(3) => rx_dlm_i, RX_DLM_WORD_OUT => open, TX_DLM_IN => tx_dlm_i, - TX_DLM_WORD_IN => x"aa", + TX_DLM_WORD_IN => test_reg(15 downto 8), --x"aa", RX_RST_OUT => open, RX_RST_WORD_OUT => open, - TX_RST_IN => '0', - TX_RST_WORD_IN => x"00", + TX_RST_IN => pulse_raising_edge, --'0', + TX_RST_WORD_IN => test_reg(7 downto 0), --x"00", -- sync operation WORD_SYNC_IN => '1', -- CTS MASTER WORD_SYNC_OUT => word_sync_i, - MASTER_CLK_IN => clk_full_osc, -- CTS MASTER - MASTER_CLK_OUT => master_clk_i, + MASTER_CLK_IN => master_clk_i, -- CTS MASTER + MASTER_CLK_OUT => open, QUAD_RST_IN => '0', -- check GLOBAL_RESET_OUT => open, SLAVE_ACTIVE_OUT => open, @@ -391,6 +397,8 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate CTRL_DEBUG => open, DEBUG_OUT => debug_i ); + + master_clk_i <= clk_full_osc; THE_MAIN_TX_RST: main_tx_reset_RS port map ( @@ -410,6 +418,12 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate PCSSW <= "01001110"; --SFP2 on B3, AddOn on D1 + -- just for testing + destroy_link_i <= test_reg(24); --common_ctrl_reg(88); + send_rst_i <= test_reg(30); + enable_dlm_i <= test_reg(31); --common_ctrl_reg(89); + + -- DLM generator THE_DLM_SEND_PROC: process( master_clk_i ) begin if( rising_edge(master_clk_i) ) then @@ -429,11 +443,18 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate -- HDR_IO(10 downto 1) <= (others => '0'); -- TEST_LINE(15 downto 0) <= (others => '0'); - - -- just for testing - destroy_link_i <= common_ctrl_reg(88); - enable_dlm_i <= common_ctrl_reg(89); + -- RST generator + THE_RST_SEND_PROC: process( master_clk_i ) + begin + if( rising_edge(master_clk_i) ) then + pulse_detect(7 downto 0) <= pulse_detect(6 downto 0) & send_rst_i; + pulse_raising_edge <= pulse_raising_egde_x; + end if; + end process THE_RST_SEND_PROC; + + pulse_raising_egde_x <= not pulse_detect(7) and pulse_detect(6); + end generate; --------------------------------------------------------------------------- @@ -465,12 +486,12 @@ end generate; NUMBER_OF_GBE_LINKS => 4, LINKS_ACTIVE => "0001", - LINK_HAS_READOUT => "0001", - LINK_HAS_SLOWCTRL => "0001", - LINK_HAS_DHCP => "0001", - LINK_HAS_ARP => "0001", - LINK_HAS_PING => "0001", - LINK_HAS_FWD => "0000" + LINK_HAS_READOUT => "0001", + LINK_HAS_SLOWCTRL => "0001", + LINK_HAS_DHCP => "0001", + LINK_HAS_ARP => "0001", + LINK_HAS_PING => "0001", + LINK_HAS_FWD => "0000" ) port map( CLK_SYS_IN => clk_sys, @@ -868,6 +889,8 @@ end generate; HEADER_IO => open, --HDR_IO, -- needed for debug --LCD LCD_DATA_IN => open, + -- additional register for testing + ADDITIONAL_REG => test_reg, --ADC ADC_CS => ADC_CS, ADC_MOSI => ADC_DIN, diff --git a/hub/config_compile_gsi.pl b/hub/config_compile_gsi.pl index 5bb3137..89c8e9a 100644 --- a/hub/config_compile_gsi.pl +++ b/hub/config_compile_gsi.pl @@ -8,7 +8,7 @@ synplify_command => "/opt/synplicity/R-2020.09-SP1/bin/synplify_prem nodelist_file => 'nodelist.txt', #pinout_file => '', par_options => '../par.p2t', -#mapper_options => '-u -retime -split_node', +mapper_options => '-u -retime -split_node', include_TDC => 0, include_GBE => 0, diff --git a/hub/trb3sc_hub.vhd b/hub/trb3sc_hub.vhd index 6d176fa..8ecfd01 100644 --- a/hub/trb3sc_hub.vhd +++ b/hub/trb3sc_hub.vhd @@ -133,10 +133,10 @@ architecture trb3sc_arch of trb3sc_hub is signal gsc_init_read, gsc_reply_read : std_logic; signal gsc_init_dataready, gsc_reply_dataready : std_logic; signal gsc_init_packet_num, gsc_reply_packet_num : std_logic_vector(2 downto 0); - signal gsc_busy : std_logic; - signal my_address : std_logic_vector(15 downto 0); - signal mc_unique_id : std_logic_vector(63 downto 0); - signal reset_via_gbe : std_logic := '0'; + signal gsc_busy : std_logic; + signal my_address : std_logic_vector(15 downto 0); + signal mc_unique_id : std_logic_vector(63 downto 0); + signal reset_via_gbe : std_logic := '0'; signal med_dataready_out : std_logic_vector (11-1 downto 0); signal med_data_out : std_logic_vector (11*c_DATA_WIDTH-1 downto 0); @@ -150,8 +150,8 @@ architecture trb3sc_arch of trb3sc_hub is signal med_ctrl_op : std_logic_vector (11*16-1 downto 0); signal rdack, wrack : std_logic; - signal trig_gen_out_i : std_logic_vector(3 downto 0); - signal monitor_inputs_i : std_logic_vector(17 downto 0); + signal trig_gen_out_i : std_logic_vector(3 downto 0); + signal monitor_inputs_i : std_logic_vector(17 downto 0); attribute syn_keep of GSR_N : signal is true; attribute syn_preserve of GSR_N : signal is true; @@ -179,6 +179,10 @@ architecture trb3sc_arch of trb3sc_hub is signal tx_reset_state : std_logic_vector(3 downto 0); signal debug_i : std_logic_vector(31 downto 0); + signal send_rst_i : std_logic; + signal send_rst_word_i : std_logic_vector(7 downto 0); + signal send_dlm_word_i : std_logic_vector(7 downto 0); + begin --------------------------------------------------------------------------- -- Clock & Reset Handling @@ -234,13 +238,17 @@ gen_PCSA : if USE_BACKPLANE = c_YES generate RX_DLM_OUT(1) => open, RX_DLM_OUT(2) => open, RX_DLM_OUT(3) => open, - RX_DLM_WORD_OUT => open, +-- RX_DLM_WORD_OUT => open, + RX_DLM_WORD_OUT(7 downto 0) => send_dlm_word_i, + RX_DLM_WORD_OUT(15 downto 8) => open, + RX_DLM_WORD_OUT(23 downto 16) => open, + RX_DLM_WORD_OUT(31 downto 24) => open, TX_DLM_IN => rx_dlm_i, - TX_DLM_WORD_IN => x"00", - RX_RST_OUT => open, - RX_RST_WORD_OUT => open, - TX_RST_IN => '0', - TX_RST_WORD_IN => x"00", + TX_DLM_WORD_IN => send_dlm_word_i, --x"00", + RX_RST_OUT => send_rst_i, --open, + RX_RST_WORD_OUT => send_rst_word_i, --open, + TX_RST_IN => send_rst_i, --'0', + TX_RST_WORD_IN => send_rst_word_i, --"00", -- sync operation WORD_SYNC_IN => word_sync_i, WORD_SYNC_OUT => word_sync_i, @@ -310,11 +318,11 @@ gen_PCSB_BKPL : if USE_BACKPLANE = c_YES generate RX_DLM_OUT(3) => open, RX_DLM_WORD_OUT => open, TX_DLM_IN => rx_dlm_i, - TX_DLM_WORD_IN => x"00", + TX_DLM_WORD_IN => send_dlm_word_i, --x"00", RX_RST_OUT => open, RX_RST_WORD_OUT => open, - TX_RST_IN => '0', - TX_RST_WORD_IN => x"00", + TX_RST_IN => send_rst_i, --'0', + TX_RST_WORD_IN => send_rst_word_i, --x"00", -- sync operation WORD_SYNC_IN => word_sync_i, WORD_SYNC_OUT => open, @@ -379,13 +387,17 @@ gen_PCSB_noBKPL : if USE_BACKPLANE = c_NO generate RX_DLM_OUT(1) => open, RX_DLM_OUT(2) => open, RX_DLM_OUT(3) => rx_dlm_i, - RX_DLM_WORD_OUT => open, +-- RX_DLM_WORD_OUT => open, + RX_DLM_WORD_OUT(7 downto 0) => open, + RX_DLM_WORD_OUT(15 downto 8) => open, + RX_DLM_WORD_OUT(23 downto 16) => open, + RX_DLM_WORD_OUT(31 downto 24) => send_dlm_word_i, TX_DLM_IN => rx_dlm_i, - TX_DLM_WORD_IN => x"00", - RX_RST_OUT => open, - RX_RST_WORD_OUT => open, - TX_RST_IN => '0', - TX_RST_WORD_IN => x"00", + TX_DLM_WORD_IN => send_dlm_word_i, --x"00", + RX_RST_OUT => send_rst_i, --open, + RX_RST_WORD_OUT => send_rst_word_i, --open, + TX_RST_IN => send_rst_i, --'0', + TX_RST_WORD_IN => send_rst_word_i, --x"00", -- sync operation WORD_SYNC_IN => word_sync_i, WORD_SYNC_OUT => word_sync_i, @@ -472,11 +484,11 @@ end generate; RX_DLM_OUT => open, RX_DLM_WORD_OUT => open, TX_DLM_IN => rx_dlm_i, - TX_DLM_WORD_IN => x"00", + TX_DLM_WORD_IN => send_dlm_word_i, --x"00", RX_RST_OUT => open, RX_RST_WORD_OUT => open, - TX_RST_IN => '0', - TX_RST_WORD_IN => x"00", + TX_RST_IN => send_rst_i, --'0', + TX_RST_WORD_IN => send_rst_word_i, --x"00", -- sync operation WORD_SYNC_IN => word_sync_i, WORD_SYNC_OUT => open, @@ -542,11 +554,11 @@ gen_PCSD : if INCLUDE_GBE = c_NO generate RX_DLM_OUT => open, RX_DLM_WORD_OUT => open, TX_DLM_IN => rx_dlm_i, - TX_DLM_WORD_IN => x"00", + TX_DLM_WORD_IN => send_dlm_word_i, --x"00", RX_RST_OUT => open, RX_RST_WORD_OUT => open, - TX_RST_IN => '0', - TX_RST_WORD_IN => x"00", + TX_RST_IN => send_rst_i, --'0', + TX_RST_WORD_IN => send_rst_word_i, --x"00", -- sync operation WORD_SYNC_IN => word_sync_i, WORD_SYNC_OUT => open, @@ -615,69 +627,68 @@ gen_GBE : if INCLUDE_GBE = c_YES generate NUMBER_OF_GBE_LINKS => 4, LINKS_ACTIVE => "0001", - LINK_HAS_READOUT => "0001", - LINK_HAS_SLOWCTRL => "0001", - LINK_HAS_DHCP => "0001", - LINK_HAS_ARP => "0001", - LINK_HAS_PING => "0001" - ) - + LINK_HAS_READOUT => "0001", + LINK_HAS_SLOWCTRL => "0001", + LINK_HAS_DHCP => "0001", + LINK_HAS_ARP => "0001", + LINK_HAS_PING => "0001" + ) port map( - CLK_SYS_IN => clk_sys, - CLK_125_IN => CLK_SUPPL_PCLK, - RESET => reset_i, - GSR_N => GSR_N, + CLK_SYS_IN => clk_sys, + CLK_125_IN => CLK_SUPPL_PCLK, + RESET => reset_i, + GSR_N => GSR_N, - TRIGGER_IN => '0', + TRIGGER_IN => '0', - SD_PRSNT_N_IN(0) => SFP_MOD0(0), - SD_PRSNT_N_IN(3 downto 1)=> "111", - SD_LOS_IN(0) => SFP_LOS(0), - SD_LOS_IN(3 downto 1) => "111", - SD_TXDIS_OUT(0) => SFP_TX_DIS(0), - - CTS_NUMBER_IN => cts_number, - CTS_CODE_IN => cts_code, - CTS_INFORMATION_IN => cts_information, - CTS_READOUT_TYPE_IN => cts_readout_type, - CTS_START_READOUT_IN => cts_start_readout, - CTS_DATA_OUT => cts_data, - CTS_DATAREADY_OUT => cts_dataready, - CTS_READOUT_FINISHED_OUT => cts_readout_finished, - CTS_READ_IN => cts_read, - CTS_LENGTH_OUT => cts_length, - CTS_ERROR_PATTERN_OUT => cts_status_bits, + SD_PRSNT_N_IN(0) => SFP_MOD0(0), + SD_PRSNT_N_IN(3 downto 1) => "111", + SD_LOS_IN(0) => SFP_LOS(0), + SD_LOS_IN(3 downto 1) => "111", + SD_TXDIS_OUT(0) => SFP_TX_DIS(0), + + CTS_NUMBER_IN => cts_number, + CTS_CODE_IN => cts_code, + CTS_INFORMATION_IN => cts_information, + CTS_READOUT_TYPE_IN => cts_readout_type, + CTS_START_READOUT_IN => cts_start_readout, + CTS_DATA_OUT => cts_data, + CTS_DATAREADY_OUT => cts_dataready, + CTS_READOUT_FINISHED_OUT => cts_readout_finished, + CTS_READ_IN => cts_read, + CTS_LENGTH_OUT => cts_length, + CTS_ERROR_PATTERN_OUT => cts_status_bits, + + FEE_DATA_IN => fee_data, + FEE_DATAREADY_IN => fee_dataready, + FEE_READ_OUT => fee_read, + FEE_STATUS_BITS_IN => fee_status_bits, + FEE_BUSY_IN => fee_busy, + + MC_UNIQUE_ID_IN => mc_unique_id, + MY_TRBNET_ADDRESS_IN => my_address, + ISSUE_REBOOT_OUT => reboot_from_gbe, - FEE_DATA_IN => fee_data, - FEE_DATAREADY_IN => fee_dataready, - FEE_READ_OUT => fee_read, - FEE_STATUS_BITS_IN => fee_status_bits, - FEE_BUSY_IN => fee_busy, + GSC_CLK_IN => clk_sys, + GSC_INIT_DATAREADY_OUT => gsc_init_dataready, + GSC_INIT_DATA_OUT => gsc_init_data, + GSC_INIT_PACKET_NUM_OUT => gsc_init_packet_num, + GSC_INIT_READ_IN => gsc_init_read, + GSC_REPLY_DATAREADY_IN => gsc_reply_dataready, + GSC_REPLY_DATA_IN => gsc_reply_data, + GSC_REPLY_PACKET_NUM_IN => gsc_reply_packet_num, + GSC_REPLY_READ_OUT => gsc_reply_read, + GSC_BUSY_IN => gsc_busy, - MC_UNIQUE_ID_IN => mc_unique_id, - MY_TRBNET_ADDRESS_IN => my_address, - ISSUE_REBOOT_OUT => reboot_from_gbe, - - GSC_CLK_IN => clk_sys, - GSC_INIT_DATAREADY_OUT => gsc_init_dataready, - GSC_INIT_DATA_OUT => gsc_init_data, - GSC_INIT_PACKET_NUM_OUT => gsc_init_packet_num, - GSC_INIT_READ_IN => gsc_init_read, - GSC_REPLY_DATAREADY_IN => gsc_reply_dataready, - GSC_REPLY_DATA_IN => gsc_reply_data, - GSC_REPLY_PACKET_NUM_IN => gsc_reply_packet_num, - GSC_REPLY_READ_OUT => gsc_reply_read, - GSC_BUSY_IN => gsc_busy, - - BUS_IP_RX => busgbeip_rx, - BUS_IP_TX => busgbeip_tx, - BUS_REG_RX => busgbereg_rx, - BUS_REG_TX => busgbereg_tx, + BUS_IP_RX => busgbeip_rx, + BUS_IP_TX => busgbeip_tx, + BUS_REG_RX => busgbereg_rx, + BUS_REG_TX => busgbereg_tx, - MAKE_RESET_OUT => reset_via_gbe, + MAKE_RESET_OUT => reset_via_gbe, - DEBUG_OUT => open - ); + DEBUG_OUT => open + ); end generate; --------------------------------------------------------------------------- @@ -686,82 +697,80 @@ end generate; gen_hub_with_gbe : if INCLUDE_GBE = c_YES generate THE_HUB: entity work.trb_net16_hub_streaming_port_sctrl_record generic map( - HUB_USED_CHANNELS => (1,1,0,1), - INIT_ADDRESS => INIT_ADDRESS, - MII_NUMBER => INTERFACE_NUM, - MII_IS_UPLINK => IS_UPLINK, - MII_IS_DOWNLINK => IS_DOWNLINK, - MII_IS_UPLINK_ONLY => IS_UPLINK_ONLY, - USE_ONEWIRE => c_YES, - HARDWARE_VERSION => HARDWARE_INFO, - INCLUDED_FEATURES => INCLUDED_FEATURES, - INIT_ENDPOINT_ID => x"0001", - CLOCK_FREQUENCY => CLOCK_FREQUENCY, - BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR + HUB_USED_CHANNELS => (1,1,0,1), + INIT_ADDRESS => INIT_ADDRESS, + MII_NUMBER => INTERFACE_NUM, + MII_IS_UPLINK => IS_UPLINK, + MII_IS_DOWNLINK => IS_DOWNLINK, + MII_IS_UPLINK_ONLY => IS_UPLINK_ONLY, + USE_ONEWIRE => c_YES, + HARDWARE_VERSION => HARDWARE_INFO, + INCLUDED_FEATURES => INCLUDED_FEATURES, + INIT_ENDPOINT_ID => x"0001", + CLOCK_FREQUENCY => CLOCK_FREQUENCY, + BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR ) port map( - CLK => clk_sys, - RESET => reset_i, - CLK_EN => '1', - + CLK => clk_sys, + RESET => reset_i, + CLK_EN => '1', --Media interfacces - MEDIA_MED2INT => med2int(0 to INTERFACE_NUM-1), - MEDIA_INT2MED => int2med(0 to INTERFACE_NUM-1), - + MEDIA_MED2INT => med2int(0 to INTERFACE_NUM-1), + MEDIA_INT2MED => int2med(0 to INTERFACE_NUM-1), --Event information coming from CTSCTS_READOUT_TYPE_OUT - CTS_NUMBER_OUT => cts_number, - CTS_CODE_OUT => cts_code, - CTS_INFORMATION_OUT => cts_information, - CTS_READOUT_TYPE_OUT => cts_readout_type, - CTS_START_READOUT_OUT => cts_start_readout, + CTS_NUMBER_OUT => cts_number, + CTS_CODE_OUT => cts_code, + CTS_INFORMATION_OUT => cts_information, + CTS_READOUT_TYPE_OUT => cts_readout_type, + CTS_START_READOUT_OUT => cts_start_readout, --Information sent to CTS --status data, equipped with DHDR - CTS_DATA_IN => cts_data, - CTS_DATAREADY_IN => cts_dataready, - CTS_READOUT_FINISHED_IN => cts_readout_finished, - CTS_READ_OUT => cts_read, - CTS_LENGTH_IN => cts_length, - CTS_STATUS_BITS_IN => cts_status_bits, + CTS_DATA_IN => cts_data, + CTS_DATAREADY_IN => cts_dataready, + CTS_READOUT_FINISHED_IN => cts_readout_finished, + CTS_READ_OUT => cts_read, + CTS_LENGTH_IN => cts_length, + CTS_STATUS_BITS_IN => cts_status_bits, -- Data from Frontends - FEE_DATA_OUT => fee_data, - FEE_DATAREADY_OUT => fee_dataready, - FEE_READ_IN => fee_read, - FEE_STATUS_BITS_OUT => fee_status_bits, - FEE_BUSY_OUT => fee_busy, - MY_ADDRESS_IN => my_address, - COMMON_STAT_REGS => common_stat_reg, --open, - COMMON_CTRL_REGS => common_ctrl_reg, --open, - ONEWIRE => TEMPSENS, - MY_ADDRESS_OUT => my_address, - UNIQUE_ID_OUT => mc_unique_id, - EXTERNAL_SEND_RESET => external_reset_i, + FEE_DATA_OUT => fee_data, + FEE_DATAREADY_OUT => fee_dataready, + FEE_READ_IN => fee_read, + FEE_STATUS_BITS_OUT => fee_status_bits, + FEE_BUSY_OUT => fee_busy, + MY_ADDRESS_IN => my_address, + COMMON_STAT_REGS => common_stat_reg, --open, + COMMON_CTRL_REGS => common_ctrl_reg, --open, + ONEWIRE => TEMPSENS, + MY_ADDRESS_OUT => my_address, + UNIQUE_ID_OUT => mc_unique_id, + EXTERNAL_SEND_RESET => external_reset_i, - BUS_RX => ctrlbus_rx, - BUS_TX => ctrlbus_tx, - TIMER => timer, + BUS_RX => ctrlbus_rx, + BUS_TX => ctrlbus_tx, + TIMER => timer, --Gbe Sctrl Input - GSC_INIT_DATAREADY_IN => gsc_init_dataready, - GSC_INIT_DATA_IN => gsc_init_data, - GSC_INIT_PACKET_NUM_IN => gsc_init_packet_num, - GSC_INIT_READ_OUT => gsc_init_read, - GSC_REPLY_DATAREADY_OUT => gsc_reply_dataready, - GSC_REPLY_DATA_OUT => gsc_reply_data, - GSC_REPLY_PACKET_NUM_OUT => gsc_reply_packet_num, - GSC_REPLY_READ_IN => gsc_reply_read, - GSC_BUSY_OUT => gsc_busy, + GSC_INIT_DATAREADY_IN => gsc_init_dataready, + GSC_INIT_DATA_IN => gsc_init_data, + GSC_INIT_PACKET_NUM_IN => gsc_init_packet_num, + GSC_INIT_READ_OUT => gsc_init_read, + GSC_REPLY_DATAREADY_OUT => gsc_reply_dataready, + GSC_REPLY_DATA_OUT => gsc_reply_data, + GSC_REPLY_PACKET_NUM_OUT => gsc_reply_packet_num, + GSC_REPLY_READ_IN => gsc_reply_read, + GSC_BUSY_OUT => gsc_busy, --status and control ports - HUB_STAT_CHANNEL => open, - HUB_STAT_GEN => open, - MPLEX_CTRL => (others => '0'), - MPLEX_STAT => open, - STAT_REGS => open, - STAT_CTRL_REGS => open, + HUB_STAT_CHANNEL => open, + HUB_STAT_GEN => open, + MPLEX_CTRL => (others => '0'), + MPLEX_STAT => open, + STAT_REGS => open, + STAT_CTRL_REGS => open, --Fixed status and control ports - STAT_DEBUG => open, - CTRL_DEBUG => (others => '0') + STAT_DEBUG => open, + CTRL_DEBUG => (others => '0') ); external_reset_i <= reset_via_gbe; -- or med2int(INTERFACE_NUM-1).stat_op(15); end generate; @@ -770,19 +779,19 @@ end generate; gen_hub_no_gbe : if INCLUDE_GBE = c_NO generate THE_HUB : trb_net16_hub_base generic map( - HUB_USED_CHANNELS => (1,1,0,1), - INIT_ADDRESS => INIT_ADDRESS, - MII_NUMBER => INTERFACE_NUM, - MII_IS_UPLINK => IS_UPLINK, - MII_IS_DOWNLINK => IS_DOWNLINK, - MII_IS_UPLINK_ONLY => IS_UPLINK_ONLY, - USE_ONEWIRE => c_YES, - HARDWARE_VERSION => HARDWARE_INFO, - INCLUDED_FEATURES => INCLUDED_FEATURES, - INIT_ENDPOINT_ID => x"0001", - CLOCK_FREQUENCY => CLOCK_FREQUENCY, + HUB_USED_CHANNELS => (1,1,0,1), + INIT_ADDRESS => INIT_ADDRESS, + MII_NUMBER => INTERFACE_NUM, + MII_IS_UPLINK => IS_UPLINK, + MII_IS_DOWNLINK => IS_DOWNLINK, + MII_IS_UPLINK_ONLY => IS_UPLINK_ONLY, + USE_ONEWIRE => c_YES, + HARDWARE_VERSION => HARDWARE_INFO, + INCLUDED_FEATURES => INCLUDED_FEATURES, + INIT_ENDPOINT_ID => x"0001", + CLOCK_FREQUENCY => CLOCK_FREQUENCY, BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR, - COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)) + COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)) ) port map ( CLK => clk_sys, @@ -972,13 +981,16 @@ end generate; not med2int(7).stat_op(9); LED_SFP_RED(1) <= not (med2int(9).stat_op(10) or med2int(9).stat_op(11) or not med2int(9).stat_op(9)) when INCLUDE_GBE = c_NO else not (med2int(7).stat_op(10) or med2int(7).stat_op(11) or not med2int(7).stat_op(9)); - - LED_WHITE(0) <= not med2int(10).stat_op(9) when INCLUDE_GBE = c_NO and USE_BACKPLANE = c_YES else - not med2int(8).stat_op(9) when INCLUDE_GBE = c_YES and USE_BACKPLANE = c_YES else - '1'; - LED_WHITE(1) <= not (med2int(10).stat_op(10) or med2int(10).stat_op(11) or not med2int(10).stat_op(9)) when INCLUDE_GBE = c_NO and USE_BACKPLANE = c_YES else - not (med2int(8).stat_op(10) or med2int(8).stat_op(11) or not med2int(8).stat_op(9)) when INCLUDE_GBE = c_YES and USE_BACKPLANE = c_YES else - '1'; + + LED_WHITE(0) <= not send_rst_word_i(0); + LED_WHITE(1) <= not send_rst_word_i(1); + +-- LED_WHITE(0) <= not med2int(10).stat_op(9) when INCLUDE_GBE = c_NO and USE_BACKPLANE = c_YES else +-- not med2int(8).stat_op(9) when INCLUDE_GBE = c_YES and USE_BACKPLANE = c_YES else +-- '1'; +-- LED_WHITE(1) <= not (med2int(10).stat_op(10) or med2int(10).stat_op(11) or not med2int(10).stat_op(9)) when INCLUDE_GBE = c_NO and USE_BACKPLANE = c_YES else +-- not (med2int(8).stat_op(10) or med2int(8).stat_op(11) or not med2int(8).stat_op(9)) when INCLUDE_GBE = c_YES and USE_BACKPLANE = c_YES else +-- '1'; end architecture; -- 2.43.0