From c6292abdcabfcdeab2e8bdb64664df90c6d0ce3a Mon Sep 17 00:00:00 2001 From: Your Name Date: Thu, 29 Jun 2017 17:20:53 +0200 Subject: [PATCH] update --- gbe_trb/base/gbe_logic_wrapper.vhd | 5 +- gbe_trb/base/gbe_wrapper.vhd | 104 +++++++++--------- gbe_trb/base/trb_net16_gbe_frame_receiver.vhd | 22 +++- gbe_trb/base/trb_net_gbe_components.vhd | 2 + 4 files changed, 80 insertions(+), 53 deletions(-) diff --git a/gbe_trb/base/gbe_logic_wrapper.vhd b/gbe_trb/base/gbe_logic_wrapper.vhd index 82cb444..5fb1f3a 100644 --- a/gbe_trb/base/gbe_logic_wrapper.vhd +++ b/gbe_trb/base/gbe_logic_wrapper.vhd @@ -291,7 +291,7 @@ begin MC_DHCP_DONE_OUT => dhcp_done, MC_MY_MAC_IN => MY_MAC_IN, MY_TRBNET_ADDRESS_IN => MY_TRBNET_ADDRESS_IN, - ISSUE_REBOOT_OUT => ISSUE_REBOOT_OUT, + ISSUE_REBOOT_OUT => open, --ISSUE_REBOOT_OUT, -- signals to/from receive controller RC_FRAME_WAITING_IN => rc_frame_ready, @@ -807,6 +807,9 @@ begin RX_MAC_CLK => CLK_RX_125_IN, MY_MAC_IN => MY_MAC_IN, + MY_TRBNET_ADDRESS_IN => MY_TRBNET_ADDRESS_IN, + ISSUE_REBOOT_OUT => ISSUE_REBOOT_OUT, + -- input signals from TS_MAC MAC_RX_EOF_IN => MAC_RX_EOF_IN, MAC_RX_ER_IN => MAC_RX_ERROR_IN, diff --git a/gbe_trb/base/gbe_wrapper.vhd b/gbe_trb/base/gbe_wrapper.vhd index a36d12a..636e835 100644 --- a/gbe_trb/base/gbe_wrapper.vhd +++ b/gbe_trb/base/gbe_wrapper.vhd @@ -1016,6 +1016,8 @@ begin cfg_max_queue <= x"fff0"; cfg_max_subs_in_queue <= x"0001"; cfg_max_single_sub <= x"fff0"; + cfg_throttle_pause <= x"0000"; + end generate; NOSCTRL_MAP_GEN : if (LINK_HAS_SLOWCTRL = "0000") generate @@ -1594,57 +1596,57 @@ begin -- ETHERNET PAUSE FRAME - wait until rising_edge(clk_125_rx_from_pcs(0)); - mac_rx_write(0) <= '1'; - -- dest mac - mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"01"; - wait until rising_edge(clk_125_rx_from_pcs(0)); - mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"80"; - wait until rising_edge(clk_125_rx_from_pcs(0)); - mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"c2"; - wait until rising_edge(clk_125_rx_from_pcs(0)); - mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; - wait until rising_edge(clk_125_rx_from_pcs(0)); - mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; - wait until rising_edge(clk_125_rx_from_pcs(0)); - mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"01"; - wait until rising_edge(clk_125_rx_from_pcs(0)); - -- src mac - mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; - wait until rising_edge(clk_125_rx_from_pcs(0)); - mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"aa"; - wait until rising_edge(clk_125_rx_from_pcs(0)); - mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"bb"; - wait until rising_edge(clk_125_rx_from_pcs(0)); - mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"cc"; - wait until rising_edge(clk_125_rx_from_pcs(0)); - mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"dd"; - wait until rising_edge(clk_125_rx_from_pcs(0)); - mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ee"; - wait until rising_edge(clk_125_rx_from_pcs(0)); - -- frame type - mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"88"; - wait until rising_edge(clk_125_rx_from_pcs(0)); - mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"08"; - wait until rising_edge(clk_125_rx_from_pcs(0)); - mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; - wait until rising_edge(clk_125_rx_from_pcs(0)); - mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"01"; - wait until rising_edge(clk_125_rx_from_pcs(0)); - mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff"; - wait until rising_edge(clk_125_rx_from_pcs(0)); - mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff"; - wait until rising_edge(clk_125_rx_from_pcs(0)); - - for empty_b_ctr in 0 to 40 loop - mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; - wait until rising_edge(clk_125_rx_from_pcs(0)); - end loop; - mac_rx_eof(0) <= '1'; - mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; - wait until rising_edge(clk_125_rx_from_pcs(0)); - mac_rx_write(0) <='0'; - mac_rx_eof(0) <= '0'; +-- wait until rising_edge(clk_125_rx_from_pcs(0)); +-- mac_rx_write(0) <= '1'; +-- -- dest mac +-- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"01"; +-- wait until rising_edge(clk_125_rx_from_pcs(0)); +-- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"80"; +-- wait until rising_edge(clk_125_rx_from_pcs(0)); +-- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"c2"; +-- wait until rising_edge(clk_125_rx_from_pcs(0)); +-- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; +-- wait until rising_edge(clk_125_rx_from_pcs(0)); +-- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; +-- wait until rising_edge(clk_125_rx_from_pcs(0)); +-- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"01"; +-- wait until rising_edge(clk_125_rx_from_pcs(0)); +-- -- src mac +-- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; +-- wait until rising_edge(clk_125_rx_from_pcs(0)); +-- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"aa"; +-- wait until rising_edge(clk_125_rx_from_pcs(0)); +-- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"bb"; +-- wait until rising_edge(clk_125_rx_from_pcs(0)); +-- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"cc"; +-- wait until rising_edge(clk_125_rx_from_pcs(0)); +-- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"dd"; +-- wait until rising_edge(clk_125_rx_from_pcs(0)); +-- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ee"; +-- wait until rising_edge(clk_125_rx_from_pcs(0)); +-- -- frame type +-- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"88"; +-- wait until rising_edge(clk_125_rx_from_pcs(0)); +-- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"08"; +-- wait until rising_edge(clk_125_rx_from_pcs(0)); +-- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; +-- wait until rising_edge(clk_125_rx_from_pcs(0)); +-- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"01"; +-- wait until rising_edge(clk_125_rx_from_pcs(0)); +-- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff"; +-- wait until rising_edge(clk_125_rx_from_pcs(0)); +-- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff"; +-- wait until rising_edge(clk_125_rx_from_pcs(0)); +-- +-- for empty_b_ctr in 0 to 40 loop +-- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; +-- wait until rising_edge(clk_125_rx_from_pcs(0)); +-- end loop; +-- mac_rx_eof(0) <= '1'; +-- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; +-- wait until rising_edge(clk_125_rx_from_pcs(0)); +-- mac_rx_write(0) <='0'; +-- mac_rx_eof(0) <= '0'; wait; diff --git a/gbe_trb/base/trb_net16_gbe_frame_receiver.vhd b/gbe_trb/base/trb_net16_gbe_frame_receiver.vhd index bc7ee97..f46381e 100644 --- a/gbe_trb/base/trb_net16_gbe_frame_receiver.vhd +++ b/gbe_trb/base/trb_net16_gbe_frame_receiver.vhd @@ -25,6 +25,9 @@ port ( RX_MAC_CLK : in std_logic; -- receiver serdes clock MY_MAC_IN : in std_logic_vector(47 downto 0); + MY_TRBNET_ADDRESS_IN : in std_logic_vector(15 downto 0); + ISSUE_REBOOT_OUT : out std_logic; + -- input signals from TS_MAC MAC_RX_EOF_IN : in std_logic; MAC_RX_ER_IN : in std_logic; @@ -107,7 +110,7 @@ signal dbg_rec_frames : std_logic_vector(31 downto 0); signal dbg_drp_frames : std_logic_vector(31 downto 0); signal state : std_logic_vector(3 downto 0); -signal rx_data, fr_q : std_logic_vector(8 downto 0); +signal rx_data, fr_q : std_logic_vector(8 downto 0); signal fr_src_ip, fr_dest_ip : std_logic_vector(31 downto 0); signal fr_dest_udp, fr_src_udp, fr_frame_size, fr_frame_proto : std_logic_vector(15 downto 0); @@ -494,6 +497,23 @@ port map( Full => rec_fifo_full ); + +-- killer ping +process(RX_MAC_CLK) +begin + if rising_edge(RX_MAC_CLK) then + + if (filter_current_state = SAVE_FRAME and saved_proto = x"01" and saved_frame_type = x"0800" and rx_bytes_ctr = x"001A" and rx_data(7 downto 0) = MY_TRBNET_ADDRESS_IN(7 downto 0) and MAC_RXD_IN = MY_TRBNET_ADDRESS_IN(15 downto 8)) then + ISSUE_REBOOT_OUT <= '1'; + else + ISSUE_REBOOT_OUT <= '0'; + end if; + + end if; +end process; + + + -- BUG HERE, probably more lost bytes in the fifo in other conditions --fifo_wr_en <= '1' when (MAC_RX_EN_IN = '1') and ((filter_current_state = SAVE_FRAME) or -- --( (filter_current_state = REMOVE_TYPE and remove_ctr = x"b" and saved_frame_type /= x"8100" and saved_frame_type /= x"0800") or diff --git a/gbe_trb/base/trb_net_gbe_components.vhd b/gbe_trb/base/trb_net_gbe_components.vhd index 8eb9686..a57352c 100644 --- a/gbe_trb/base/trb_net_gbe_components.vhd +++ b/gbe_trb/base/trb_net_gbe_components.vhd @@ -722,6 +722,8 @@ port ( ALLOW_RX_IN : in std_logic; RX_MAC_CLK : in std_logic; -- receiver serdes clock MY_MAC_IN : in std_logic_vector(47 downto 0); + MY_TRBNET_ADDRESS_IN : in std_logic_vector(15 downto 0); + ISSUE_REBOOT_OUT : out std_logic; -- input signals from TS_MAC MAC_RX_EOF_IN : in std_logic; -- 2.43.0