From c76b272ad170c2d31c112d399f406f94963a185d Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Mon, 14 Jan 2013 15:30:34 +0000 Subject: [PATCH] *** empty log message *** --- base/panda_dirc_wasa1.lpf | 30 +++- base/trb3_central.lpf | 7 +- cts/trb3_central.vhd | 105 +++++++------ cts/trb3_central_constraints.lpf | 2 + hub/compile_periph_frankfurt.pl | 4 +- hub/trb3_periph_hub.vhd | 123 ++++++++++------ hub/trb3_periph_hub_constraints.lpf | 12 +- tdc_releases/tdc_v1.1.1/Encoder_304_Bit.vhd | 14 ++ trb3_gbe/compile_central_frankfurt.pl | 2 +- trb3_gbe/trb3_central.prj | 2 + trb3_gbe/trb3_central.vhd | 154 +++++++++++++++----- trb3_gbe/trb3_central_constraints.lpf | 3 + wasa/panda_dirc_wasa.p2t | 20 +++ wasa/panda_dirc_wasa.vhd | 57 ++++---- 14 files changed, 366 insertions(+), 169 deletions(-) create mode 100644 wasa/panda_dirc_wasa.p2t diff --git a/base/panda_dirc_wasa1.lpf b/base/panda_dirc_wasa1.lpf index f34ac0f..177666a 100644 --- a/base/panda_dirc_wasa1.lpf +++ b/base/panda_dirc_wasa1.lpf @@ -21,17 +21,15 @@ MULTICYCLE TO PORT "SPI_*" 20.000000 ns ; ################################################################# # I/O ################################################################# - - LOCATE COMP "CON_1" SITE "A4"; LOCATE COMP "CON_2" SITE "A5"; LOCATE COMP "CON_3" SITE "A3"; LOCATE COMP "CON_4" SITE "D6"; LOCATE COMP "CON_5" SITE "B7"; -LOCATE COMP "CON_6" SITE "F7"; -LOCATE COMP "CON_7" SITE "C8"; -LOCATE COMP "CON_8" SITE "D8"; -LOCATE COMP "CON_9" SITE "F8"; +LOCATE COMP "CON_6" SITE "F7"; +LOCATE COMP "CON_7" SITE "C8"; +LOCATE COMP "CON_8" SITE "D8"; +LOCATE COMP "CON_9" SITE "F8"; LOCATE COMP "CON_10" SITE "B9"; LOCATE COMP "CON_11" SITE "F9"; LOCATE COMP "CON_12" SITE "D10"; @@ -42,6 +40,26 @@ LOCATE COMP "CON_16" SITE "C12"; DEFINE PORT GROUP "CON_group" "CON*" ; IOBUF GROUP "CON_group" IO_TYPE=LVDS25; + +# LOCATE COMP "CON_1" SITE "A4"; +# LOCATE COMP "CON_2" SITE "A5"; +# LOCATE COMP "CON_3" SITE "A3"; +# LOCATE COMP "CON_4" SITE "D6"; +# LOCATE COMP "CON_5" SITE "B7"; +# LOCATE COMP "CON_6" SITE "F7"; +# LOCATE COMP "CON_7" SITE "C8"; +# LOCATE COMP "CON_8" SITE "D8"; +# LOCATE COMP "CON_9" SITE "F8"; +# LOCATE COMP "CON_10" SITE "B9"; +# LOCATE COMP "CON_11" SITE "F9"; +# LOCATE COMP "CON_12" SITE "D10"; +# LOCATE COMP "CON_13" SITE "A11"; +# LOCATE COMP "CON_14" SITE "B11"; +# LOCATE COMP "CON_15" SITE "B13"; +# LOCATE COMP "CON_16" SITE "C12"; +# DEFINE PORT GROUP "CON_group" "CON*" ; +# IOBUF GROUP "CON_group" IO_TYPE=LVDS25; + LOCATE COMP "INP_1" SITE "T2"; LOCATE COMP "INP_2" SITE "T3"; diff --git a/base/trb3_central.lpf b/base/trb3_central.lpf index 7edfa4f..ec8db6c 100644 --- a/base/trb3_central.lpf +++ b/base/trb3_central.lpf @@ -61,7 +61,12 @@ LOCATE COMP "TRIGGER_EXT_3" SITE "W4"; #was EXT_TRIG_2 DEFINE PORT GROUP "TRIGGER_EXT_group" "TRIGGER_EXT*" ; IOBUF GROUP "TRIGGER_EXT_group" IO_TYPE=LVDS25; - +LOCATE COMP "CLK_TEST_OUT_2" SITE "Y34"; +IOBUF PORT "CLK_TEST_OUT_2" IO_TYPE=LVDS25 ; +LOCATE COMP "CLK_TEST_OUT_1" SITE "W4"; +IOBUF PORT "CLK_TEST_OUT_1" IO_TYPE=LVDS25 ; +LOCATE COMP "CLK_TEST_OUT_0" SITE "U9"; +IOBUF PORT "CLK_TEST_OUT_0" IO_TYPE=LVDS25 ; ################################################################# diff --git a/cts/trb3_central.vhd b/cts/trb3_central.vhd index a0d158a..19119fd 100644 --- a/cts/trb3_central.vhd +++ b/cts/trb3_central.vhd @@ -64,9 +64,10 @@ entity trb3_central is --Trigger TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out TRIGGER_RIGHT : in std_logic; --right side trigger input from fan-out - TRIGGER_EXT : in std_logic_vector(4 downto 2); --additional trigger from RJ45 + TRIGGER_EXT : in std_logic_vector(2 downto 2); --additional trigger from RJ45 TRIGGER_OUT : out std_logic; --trigger to second input of fan-out TRIGGER_OUT2 : out std_logic; + RXCLK_OUT : out std_logic; --Serdes CLK_SERDES_INT_LEFT : in std_logic; --Clock Manager 2/0, 200 MHz, only in case of problems @@ -190,7 +191,7 @@ architecture trb3_central_arch of trb3_central is --FPGA Test signal time_counter, time_counter2 : unsigned(31 downto 0); - + signal rx_clock : std_logic; --Media Interface signal med_stat_op : std_logic_vector (5*16-1 downto 0); signal med_ctrl_op : std_logic_vector (5*16-1 downto 0); @@ -302,8 +303,7 @@ architecture trb3_central_arch of trb3_central is signal cts_rdo_invalid_trg : std_logic; signal cts_rdo_trg_status_bits, - cts_rdo_trg_status_bits_cts, - cts_rdo_trg_status_bits_additional: std_logic_vector(31 downto 0) := (others => '0'); + cts_rdo_trg_status_bits_cts : std_logic_vector(31 downto 0) := (others => '0'); signal cts_rdo_data : std_logic_vector(31 downto 0); signal cts_rdo_write : std_logic; signal cts_rdo_finished : std_logic; @@ -313,10 +313,17 @@ architecture trb3_central_arch of trb3_central is signal cts_ext_control : std_logic_vector(31 downto 0); signal cts_ext_debug : std_logic_vector(31 downto 0); - signal cts_rdo_additional_data : std_logic_vector(31 downto 0); - signal cts_rdo_additional_write : std_logic := '0'; - signal cts_rdo_additional_finished : std_logic := '0'; - + signal cts_rdo_additional_data : std_logic_vector(63 downto 0); + signal cts_rdo_additional_write : std_logic_vector(1 downto 0) := "00"; + signal cts_rdo_additional_finished : std_logic_vector(1 downto 0) := "00"; + signal cts_rdo_trg_status_bits_additional : std_logic_vector(63 downto 0) := (others => '0'); + signal cts_rdo_trg_type : std_logic_vector(3 downto 0); + signal cts_rdo_trg_code : std_logic_vector(7 downto 0); + signal cts_rdo_trg_information : std_logic_vector(23 downto 0); + signal cts_rdo_trg_number : std_logic_vector(15 downto 0); + + + signal cts_trg_send : std_logic; signal cts_trg_type : std_logic_vector(3 downto 0); signal cts_trg_number : std_logic_vector(15 downto 0); @@ -446,10 +453,10 @@ begin TRG_SYNC_OUT => cts_ext_trigger, TRIGGER_IN => cts_rdo_trg_data_valid, - DATA_OUT => cts_rdo_additional_data, - WRITE_OUT => cts_rdo_additional_write, - STATUSBIT_OUT => cts_rdo_trg_status_bits_additional, - FINISHED_OUT => cts_rdo_additional_finished, + DATA_OUT => cts_rdo_additional_data(31 downto 0), + WRITE_OUT => cts_rdo_additional_write(0), + STATUSBIT_OUT => cts_rdo_trg_status_bits_additional(31 downto 0), + FINISHED_OUT => cts_rdo_additional_finished(0), CONTROL_REG_IN => cts_ext_control, STATUS_REG_OUT => cts_ext_status, @@ -458,7 +465,8 @@ begin ); trigger_in_buf_i(1 downto 0) <= CLK_EXT; - trigger_in_buf_i(3 downto 2) <= TRIGGER_EXT(3 downto 2); + trigger_in_buf_i(2 downto 2) <= TRIGGER_EXT(2 downto 2); + trigger_in_buf_i(3) <= '0'; THE_CTS: CTS generic map ( @@ -611,7 +619,7 @@ THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp MED_PACKET_NUM_OUT => med_packet_num_in(14 downto 12), MED_DATAREADY_OUT => med_dataready_in(4), MED_READ_IN => med_read_out(4), - REFCLK2CORE_OUT => open, + REFCLK2CORE_OUT => rx_clock, --SFP Connection SD_RXD_P_IN => SFP_RX_P(1), SD_RXD_N_IN => SFP_RX_N(1), @@ -703,18 +711,18 @@ THE_MEDIA_ONBOARD : trb_net16_med_ecp3_sfp_4_onboard CLOCK_FREQUENCY => 100, USE_ONEWIRE => c_YES, BROADCAST_SPECIAL_ADDR => x"35", - RDO_ADDITIONAL_PORT => c_YES, + RDO_ADDITIONAL_PORT => 2, RDO_DATA_BUFFER_DEPTH => 9, RDO_DATA_BUFFER_FULL_THRESH => 2**9-128, RDO_HEADER_BUFFER_DEPTH => 9, - RDO_HEADER_BUFFER_FULL_THRESH => 2**9-128 + RDO_HEADER_BUFFER_FULL_THRESH => 2**9-16 ) port map( CLK => clk_100_i, RESET => reset_i, CLK_EN => '1', - --Media interfacces +-- Media interfacces --------------------------------------------------------------- MED_DATAREADY_OUT(5*1-1 downto 0) => med_dataready_out, MED_DATA_OUT(5*16-1 downto 0) => med_data_out, MED_PACKET_NUM_OUT(5*3-1 downto 0) => med_packet_num_out, @@ -763,23 +771,29 @@ THE_MEDIA_ONBOARD : trb_net16_med_ecp3_sfp_4_onboard CTS_IPU_BUSY_OUT => cts_ipu_busy, -- CTS Data Readout ---------------------------------------------------------------- - --Trigger In + --Trigger to CTS out RDO_TRIGGER_IN => cts_rdo_trigger, RDO_TRG_DATA_VALID_OUT => cts_rdo_trg_data_valid, RDO_VALID_TIMING_TRG_OUT => cts_rdo_valid_timing_trg, RDO_VALID_NOTIMING_TRG_OUT => cts_rdo_valid_notiming_trg, RDO_INVALID_TRG_OUT => cts_rdo_invalid_trg, - --Data out + RDO_TRG_TYPE_OUT => cts_rdo_trg_type, + RDO_TRG_CODE_OUT => cts_rdo_trg_code, + RDO_TRG_INFORMATION_OUT => cts_rdo_trg_information, + RDO_TRG_NUMBER_OUT => cts_rdo_trg_number, + + --Data from CTS in RDO_TRG_STATUSBITS_IN => cts_rdo_trg_status_bits_cts, RDO_DATA_IN => cts_rdo_data, RDO_DATA_WRITE_IN => cts_rdo_write, RDO_DATA_FINISHED_IN => cts_rdo_finished, - + --Data from additional modules RDO_ADDITIONAL_STATUSBITS_IN => cts_rdo_trg_status_bits_additional, RDO_ADDITIONAL_DATA => cts_rdo_additional_data, RDO_ADDITIONAL_WRITE => cts_rdo_additional_write, RDO_ADDITIONAL_FINISHED => cts_rdo_additional_finished, +-- Slow Control -------------------------------------------------------------------- COMMON_STAT_REGS => common_stat_regs, --open, COMMON_CTRL_REGS => common_ctrl_regs, --open, ONEWIRE => TEMPSENS, @@ -1091,12 +1105,15 @@ THE_BUS_HANDLER : trb_net16_regio_bus_handler ); -PROC_TDC_CTRL_REG : process begin +PROC_TDC_CTRL_REG : process + variable pos : integer; +begin wait until rising_edge(clk_100_i); - tdc_ctrl_data_out <= tdc_ctrl_reg(to_integer(unsigned(tdc_ctrl_addr))*32+31 downto to_integer(unsigned(tdc_ctrl_addr))*32); + pos := to_integer(unsigned(tdc_ctrl_addr))*32; + tdc_ctrl_data_out <= tdc_ctrl_reg(pos+31 downto pos); last_tdc_ctrl_read <= tdc_ctrl_read; - if tdc_ctrl_read = '1' then - tdc_ctrl_reg(to_integer(unsigned(tdc_ctrl_addr))*32+31 downto to_integer(unsigned(tdc_ctrl_addr))*32) <= tdc_ctrl_data_in; + if tdc_ctrl_write = '1' then + tdc_ctrl_reg(pos+31 downto pos) <= tdc_ctrl_data_in; end if; end process; @@ -1180,27 +1197,27 @@ THE_FPGA_REBOOT : fpga_reboot TRG_WIN_PRE => tdc_ctrl_reg(42 downto 32), -- Pre-Trigger window width TRG_WIN_POST => tdc_ctrl_reg(58 downto 48), -- Post-Trigger window width -- + -- Trigger signals from handler --- TRG_DATA_VALID_IN => trg_data_valid_i, -- trig data valid signal from trbnet --- VALID_TIMING_TRG_IN => trg_timing_valid_i, -- valid timing trigger signal from trbnet --- VALID_NOTIMING_TRG_IN => trg_notiming_valid_i, -- valid notiming signal from trbnet --- INVALID_TRG_IN => trg_invalid_i, -- invalid trigger signal from trbnet --- TMGTRG_TIMEOUT_IN => trg_timeout_detected_i, -- timing trigger timeout signal from trbnet --- SPIKE_DETECTED_IN => trg_spike_detected_i, --- MULTI_TMG_TRG_IN => trg_multiple_trg_i, --- SPURIOUS_TRG_IN => trg_spurious_trg_i, --- -- --- TRG_NUMBER_IN => trg_number_i, -- LVL1 trigger information package --- TRG_CODE_IN => trg_code_i, -- --- TRG_INFORMATION_IN => trg_information_i, -- --- TRG_TYPE_IN => trg_type_i, -- LVL1 trigger information package --- -- + TRG_DATA_VALID_IN => cts_rdo_trg_data_valid, -- trig data valid signal from trbnet + VALID_TIMING_TRG_IN => cts_rdo_valid_timing_trg, -- valid timing trigger signal from trbnet + VALID_NOTIMING_TRG_IN => cts_rdo_valid_notiming_trg, -- valid notiming signal from trbnet + INVALID_TRG_IN => cts_rdo_invalid_trg, -- invalid trigger signal from trbnet + TMGTRG_TIMEOUT_IN => '0', -- timing trigger timeout signal from trbnet + SPIKE_DETECTED_IN => '0', + MULTI_TMG_TRG_IN => '0', + SPURIOUS_TRG_IN => '0', + -- + TRG_NUMBER_IN => cts_rdo_trg_number, -- LVL1 trigger information package + TRG_CODE_IN => cts_rdo_trg_code, -- + TRG_INFORMATION_IN => cts_rdo_trg_information, -- + TRG_TYPE_IN => cts_rdo_trg_type, -- LVL1 trigger information package --Response to handler -- TRG_RELEASE_OUT => fee_trg_release_i, -- trigger release signal --- TRG_STATUSBIT_OUT => fee_trg_statusbits_i, -- status information of the tdc --- DATA_OUT => fee_data_i, -- tdc data --- DATA_WRITE_OUT => fee_data_write_i, -- data valid signal --- DATA_FINISHED_OUT => fee_data_finished_i, -- readout finished signal + TRG_STATUSBIT_OUT => cts_rdo_trg_status_bits_additional(63 downto 32), -- status information of the tdc + DATA_OUT => cts_rdo_additional_data(63 downto 32), -- tdc data + DATA_WRITE_OUT => cts_rdo_additional_write(1), -- data valid signal + DATA_FINISHED_OUT => cts_rdo_additional_finished(1), -- readout finished signal -- --Hit Counter Bus HCB_READ_EN_IN => hitreg_read_en, -- bus read en strobe @@ -1264,7 +1281,7 @@ end process; TRIGGER_OUT <= cts_trigger_out; TRIGGER_OUT2 <= cts_trigger_out; - + cts_rdo_trigger <= cts_trigger_out; --------------------------------------------------------------------------- -- FPGA communication --------------------------------------------------------------------------- @@ -1312,7 +1329,7 @@ LED_ORANGE <= debug(1); LED_RED <= debug(2); LED_YELLOW <= link_ok; --debug(3); - +RXCLK_OUT <= rx_clock; --------------------------------------------------------------------------- -- Test Connector --------------------------------------------------------------------------- diff --git a/cts/trb3_central_constraints.lpf b/cts/trb3_central_constraints.lpf index 9ee3327..56f8b3e 100644 --- a/cts/trb3_central_constraints.lpf +++ b/cts/trb3_central_constraints.lpf @@ -39,6 +39,8 @@ LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ; REGION "MEDIA_ONBOARD" "R90C122" 20 40; LOCATE UGROUP "THE_MEDIA_ONBOARD/media_interface_group" REGION "MEDIA_ONBOARD" ; +MULTICYCLE TO CELL "THE_MEDIA_DOWNLINK/SCI_DATA_OUT*" 50 ns; +MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns; #SPI Interface REGION "REGION_SPI" "R13C150D" 12 16 DEVSIZE; diff --git a/hub/compile_periph_frankfurt.pl b/hub/compile_periph_frankfurt.pl index d60e808..50dcdda 100755 --- a/hub/compile_periph_frankfurt.pl +++ b/hub/compile_periph_frankfurt.pl @@ -9,14 +9,14 @@ use strict; ################################################################################### #Settings for this project my $TOPNAME = "trb3_periph_hub"; #Name of top-level entity -my $lattice_path = '/d/jspc29/lattice/diamond/1.4.2.105'; +my $lattice_path = '/d/jspc29/lattice/diamond/2.01'; my $synplify_path = '/d/jspc29/lattice/synplify/F-2012.03-SP1/'; my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de"; my $lm_license_file_for_par = "1702\@hadeb05.gsi.de"; ################################################################################### - +$ENV{'PAR_DESIGN_NAME'}=$TOPNAME; diff --git a/hub/trb3_periph_hub.vhd b/hub/trb3_periph_hub.vhd index c9c67ef..75ac24b 100644 --- a/hub/trb3_periph_hub.vhd +++ b/hub/trb3_periph_hub.vhd @@ -12,6 +12,9 @@ use work.version.all; entity trb3_periph_hub is + generic( + SYNC_MODE : integer range 0 to 1 := c_NO --use the RX clock for internal logic and transmission. 4 SFP links only. + ); port( --Clocks CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz @@ -121,6 +124,10 @@ architecture trb3_periph_hub_arch of trb3_periph_hub is signal GSR_N : std_logic; attribute syn_keep of GSR_N : signal is true; attribute syn_preserve of GSR_N : signal is true; + signal clk_100_internal : std_logic; + signal clk_200_internal : std_logic; + signal rx_clock_100 : std_logic; + signal rx_clock_200 : std_logic; --Media Interface signal med_stat_op : std_logic_vector (7*16-1 downto 0); @@ -218,7 +225,7 @@ begin port map( CLEAR_IN => '0', -- reset input (high active, async) CLEAR_N_IN => '1', -- reset input (low active, async) - CLK_IN => clk_200_i, -- raw master clock, NOT from PLL/DLL! + CLK_IN => clk_200_internal, -- raw master clock, NOT from PLL/DLL! SYSCLK_IN => clk_100_i, -- PLL/DLL remastered clock PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async) RESET_IN => '0', -- general reset signal (SYSCLK) @@ -236,15 +243,26 @@ begin THE_MAIN_PLL : pll_in200_out100 port map( CLK => CLK_GPLL_RIGHT, - CLKOP => clk_100_i, - CLKOK => clk_200_i, + CLKOP => clk_100_internal, + CLKOK => clk_200_internal, LOCK => pll_lock ); + +gen_sync_clocks : if SYNC_MODE = c_YES generate + clk_100_i <= rx_clock_100; + clk_200_i <= rx_clock_200; +end generate; + +gen_local_clocks : if SYNC_MODE = c_NO generate + clk_100_i <= clk_100_internal; + clk_200_i <= clk_200_internal; +end generate; --------------------------------------------------------------------------- -- The TrbNet media interface (to other FPGA) --------------------------------------------------------------------------- +gen_full_media : if SYNC_MODE = c_NO generate THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp_4 generic map( REVERSE_ORDER => c_NO, --order of ports @@ -339,48 +357,62 @@ begin STAT_DEBUG => open, CTRL_DEBUG => (others => '0') ); +end generate; + +gen_sync_media : if SYNC_MODE = c_YES generate + med_stat_op(3*16+15 downto 3*16) <= x"0007"; + med_stat_op(5*16+15 downto 5*16) <= x"0007"; - - --- trb_net16_med_ecp3_sfp --- generic map( --- SERDES_NUM => 1, --number of serdes in quad --- EXT_CLOCK => c_NO, --use internal clock --- USE_200_MHZ => c_YES --run on 200 MHz clock --- ) --- port map( --- CLK => clk_200_i, --- SYSCLK => clk_100_i, --- RESET => reset_i, --- CLEAR => clear_i, --- CLK_EN => '1', --- --Internal Connection --- MED_DATA_IN => med_data_out(15 downto 0), --- MED_PACKET_NUM_IN => med_packet_num_out(2 downto 0), --- MED_DATAREADY_IN => med_dataready_out(0), --- MED_READ_OUT => med_read_in(0), --- MED_DATA_OUT => med_data_in(15 downto 0), --- MED_PACKET_NUM_OUT => med_packet_num_in(2 downto 0), --- MED_DATAREADY_OUT => med_dataready_in(0), --- MED_READ_IN => med_read_out(0), --- REFCLK2CORE_OUT => open, --- --SFP Connection --- SD_RXD_P_IN => SERDES_INT_RX(2), --- SD_RXD_N_IN => SERDES_INT_RX(3), --- SD_TXD_P_OUT => SERDES_INT_TX(2), --- SD_TXD_N_OUT => SERDES_INT_TX(3), --- SD_REFCLK_P_IN => open, --- SD_REFCLK_N_IN => open, --- SD_PRSNT_N_IN => FPGA5_COMM(0), --- SD_LOS_IN => FPGA5_COMM(0), --- SD_TXDIS_OUT => FPGA5_COMM(2), --- -- Status and control port --- STAT_OP => med_stat_op(15 downto 0), --- CTRL_OP => med_ctrl_op(15 downto 0), --- STAT_DEBUG => med_stat_debug(63 downto 0), --- CTRL_DEBUG => (others => '0') --- ); - + THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp + generic map( + SERDES_NUM => 1, --number of serdes in quad + EXT_CLOCK => c_NO, --use internal clock + USE_200_MHZ => c_YES, --run on 200 MHz clock + USE_CTC => c_NO, + USE_SLAVE => c_YES + ) + port map( + CLK => clk_200_internal, + SYSCLK => clk_100_i, + RESET => reset_i, + CLEAR => clear_i, + CLK_EN => '1', + --Internal Connection + MED_DATA_IN => med_data_out(15 downto 0), + MED_PACKET_NUM_IN => med_packet_num_out(2 downto 0), + MED_DATAREADY_IN => med_dataready_out(0), + MED_READ_OUT => med_read_in(0), + MED_DATA_OUT => med_data_in(15 downto 0), + MED_PACKET_NUM_OUT => med_packet_num_in(2 downto 0), + MED_DATAREADY_OUT => med_dataready_in(0), + MED_READ_IN => med_read_out(0), + REFCLK2CORE_OUT => open, + CLK_RX_HALF_OUT => rx_clock_100, + CLK_RX_FULL_OUT => rx_clock_200, + --SFP Connection + SD_RXD_P_IN => SERDES_ADDON_RX(8), + SD_RXD_N_IN => SERDES_ADDON_RX(9), + SD_TXD_P_OUT => SERDES_ADDON_TX(8), + SD_TXD_N_OUT => SERDES_ADDON_TX(9), + SD_REFCLK_P_IN => open, + SD_REFCLK_N_IN => open, + SD_PRSNT_N_IN => FPGA5_COMM(0), + SD_LOS_IN => FPGA5_COMM(0), + SD_TXDIS_OUT => FPGA5_COMM(2), + + SCI_DATA_IN => sci1_data_in, + SCI_DATA_OUT => sci1_data_out, + SCI_ADDR => sci1_addr, + SCI_READ => sci1_read, + SCI_WRITE => sci1_write, + SCI_ACK => sci1_ack, + -- Status and control port + STAT_OP => med_stat_op(15 downto 0), + CTRL_OP => med_ctrl_op(15 downto 0), + STAT_DEBUG => med_stat_debug(63 downto 0), + CTRL_DEBUG => (others => '0') + ); +end generate; THE_MEDIA_DOWNLINK : trb_net16_med_ecp3_sfp_4 generic map( @@ -477,8 +509,7 @@ THE_MEDIA_DOWNLINK : trb_net16_med_ecp3_sfp_4 CTRL_DEBUG => (others => '0') ); --- med_stat_op(3*16+15 downto 3*16) <= x"0007"; --- med_stat_op(5*16+15 downto 5*16) <= x"0007"; + --------------------------------------------------------------------------- -- Hub diff --git a/hub/trb3_periph_hub_constraints.lpf b/hub/trb3_periph_hub_constraints.lpf index 2665b6c..1c2deb0 100644 --- a/hub/trb3_periph_hub_constraints.lpf +++ b/hub/trb3_periph_hub_constraints.lpf @@ -24,8 +24,10 @@ GSR_NET NET "GSR_N"; ################################################################# # Locate Serdes and media interfaces ################################################################# -LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ; -LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_200/PCSD_INST" SITE "PCSA" ; +LOCATE COMP "gen_sync_media_THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ; +LOCATE COMP "gen_sync_media_THE_MEDIA_UPLINK/gen_serdes_1_200_ctc_THE_SERDES/PCSD_INST" SITE "PCSA" ; +LOCATE COMP "gen_full_media_THE_MEDIA_UPLINK/gen_serdes_200/PCSD_INST" SITE "PCSA" ; + LOCATE COMP "THE_MEDIA_DOWNLINK/gen_serdes_200/PCSD_INST" SITE "PCSB" ; @@ -37,7 +39,8 @@ REGION "REGION_IOBUF" "R10C43D" 88 86 DEVSIZE; LOCATE UGROUP "THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ; LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ; -LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ; +LOCATE UGROUP "gen_sync_media_THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ; +LOCATE UGROUP "gen_full_media_THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ; LOCATE UGROUP "THE_MEDIA_DOWNLINK/media_interface_group" REGION "MEDIA_DOWNLINK" ; #LOCATE UGROUP "THE_HUB/gen_muxes_0_MPLEX/MUX_group" REGION "REGION_IOBUF" ; @@ -126,5 +129,6 @@ LOCATE UGROUP "THE_HUB/gen_bufs_0_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF2_gen_ MULTICYCLE TO CELL "THE_MEDIA_DOWNLINK/SCI_DATA_OUT*" 50 ns; -MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns; +MULTICYCLE TO CELL "gen_full_media_THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns; +MULTICYCLE TO CELL "gen_sync_media_THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns; diff --git a/tdc_releases/tdc_v1.1.1/Encoder_304_Bit.vhd b/tdc_releases/tdc_v1.1.1/Encoder_304_Bit.vhd index df471dd..79de25d 100644 --- a/tdc_releases/tdc_v1.1.1/Encoder_304_Bit.vhd +++ b/tdc_releases/tdc_v1.1.1/Encoder_304_Bit.vhd @@ -99,6 +99,7 @@ architecture behavioral of Encoder_304_Bit is signal proc_finished_3 : std_logic; signal proc_finished_4 : std_logic; signal conv_finished_i : std_logic; + signal thermocode_i : std_logic_vector(303 downto -1); attribute syn_keep : boolean; attribute syn_keep of mux_control : signal is true; @@ -109,6 +110,11 @@ architecture behavioral of Encoder_304_Bit is ------------------------------------------------------------------------------- begin + + thermocode_i(303 downto 0) <= THERMOCODE_IN; + thermocode_i(-1) <= '1'; + + --purpose : Register signals Register_Signals : process (CLK, RESET) begin @@ -201,11 +207,19 @@ begin end process Interval_Number_to_Binary; Interval_Selection : process (CLK, RESET) + variable tmp : std_logic_vector(8 downto 0); begin -- The interval with the 0-1 transition is selected. if rising_edge(CLK) then if RESET = '1' then interval_reg <= (others => '0'); else +-- tmp := (others => '0'); +-- make_mux : for i in 0 to 37 loop +-- make_mux_2 : for j in 0 to 8 loop +-- tmp(j) := tmp(j) or (thermocode_i(i*8-1+j) and P_one(j)); +-- end loop; +-- end loop; +-- interval_reg <= tmp; case mux_control is when "000001" => interval_reg <= THERMOCODE_IN(7 downto 0) & '1'; when "000010" => interval_reg <= THERMOCODE_IN(15 downto 7); diff --git a/trb3_gbe/compile_central_frankfurt.pl b/trb3_gbe/compile_central_frankfurt.pl index 463cc7e..475f7a3 100755 --- a/trb3_gbe/compile_central_frankfurt.pl +++ b/trb3_gbe/compile_central_frankfurt.pl @@ -9,7 +9,7 @@ use strict; ################################################################################### #Settings for this project my $TOPNAME = "trb3_central"; #Name of top-level entity -my $lattice_path = '/d/jspc29/lattice/diamond/1.4.2.105'; +my $lattice_path = '/d/jspc29/lattice/diamond/2.01'; # my $synplify_path = '/d/jspc29/lattice/synplify/fpga_e201103/'; my $synplify_path = '/d/jspc29/lattice/synplify/F-2012.03-SP1/'; my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de"; diff --git a/trb3_gbe/trb3_central.prj b/trb3_gbe/trb3_central.prj index bb54e25..950d079 100644 --- a/trb3_gbe/trb3_central.prj +++ b/trb3_gbe/trb3_central.prj @@ -196,12 +196,14 @@ add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_onboard_full.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_full_ctc.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_0_200_ctc.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_0_200_int.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp_4_onboard.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp_4.vhd" add_file -vhdl -lib work "../base/cores/pll_in200_out100.vhd" add_file -vhdl -lib work "./trb3_central.vhd" diff --git a/trb3_gbe/trb3_central.vhd b/trb3_gbe/trb3_central.vhd index c03699d..db5345b 100644 --- a/trb3_gbe/trb3_central.vhd +++ b/trb3_gbe/trb3_central.vhd @@ -15,22 +15,23 @@ use work.trb_net_gbe_components.all; entity trb3_central is generic ( - USE_ETHERNET : integer range c_NO to c_YES := c_NO + USE_ETHERNET : integer range c_NO to c_YES := c_NO; + SYNC_MODE : integer range c_NO to c_YES := c_NO ); port( --Clocks - CLK_EXT : in std_logic_vector(4 downto 3); --from RJ45 +-- CLK_EXT : in std_logic_vector(4 downto 3); --from RJ45 CLK_GPLL_LEFT : in std_logic; --Clock Manager 2/9, 200 MHz <-- MAIN CLOCK CLK_GPLL_RIGHT : in std_logic; --Clock Manager 1/9, 125 MHz <-- for GbE CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz + CLK_TEST_OUT : out std_logic_vector(2 downto 0); --Trigger TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out TRIGGER_RIGHT : in std_logic; --right side trigger input from fan-out - TRIGGER_EXT : in std_logic_vector(4 downto 2); --additional trigger from RJ45 +-- TRIGGER_EXT : in std_logic_vector(4 downto 2); --additional trigger from RJ45 TRIGGER_OUT : out std_logic; --trigger to second input of fan-out - --Serdes CLK_SERDES_INT_LEFT : in std_logic; --Clock Manager 2/0, 200 MHz, only in case of problems CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 1/0, off, 125 MHz possible @@ -151,6 +152,11 @@ architecture trb3_central_arch of trb3_central is --FPGA Test signal time_counter, time_counter2 : unsigned(31 downto 0); + signal rx_clock : std_logic; + signal rx_clock_100 : std_logic; + signal rx_clock_200 : std_logic; + signal clk_100_internal : std_logic; + signal clk_200_internal : std_logic; --Media Interface signal med_stat_op : std_logic_vector (5*16-1 downto 0); @@ -194,7 +200,20 @@ architecture trb3_central_arch of trb3_central is signal spimem_addr : std_logic_vector(5 downto 0); signal spimem_data_out : std_logic_vector(31 downto 0); signal spimem_ack : std_logic; - + signal sci1_ack : std_logic; + signal sci1_write : std_logic; + signal sci1_read : std_logic; + signal sci1_data_in : std_logic_vector(7 downto 0); + signal sci1_data_out : std_logic_vector(7 downto 0); + signal sci1_addr : std_logic_vector(8 downto 0); + + signal sci2_ack : std_logic; + signal sci2_write : std_logic; + signal sci2_read : std_logic; + signal sci2_data_in : std_logic_vector(7 downto 0); + signal sci2_data_out : std_logic_vector(7 downto 0); + signal sci2_addr : std_logic_vector(8 downto 0); + signal spi_bram_addr : std_logic_vector(7 downto 0); signal spi_bram_wr_d : std_logic_vector(7 downto 0); signal spi_bram_rd_d : std_logic_vector(7 downto 0); @@ -275,7 +294,7 @@ THE_RESET_HANDLER : trb_net_reset_handler port map( CLEAR_IN => '0', -- reset input (high active, async) CLEAR_N_IN => '1', -- reset input (low active, async) - CLK_IN => clk_200_i, -- raw master clock, NOT from PLL/DLL! + CLK_IN => clk_200_internal,-- raw master clock, NOT from PLL/DLL! SYSCLK_IN => clk_100_i, -- PLL/DLL remastered clock PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async) RESET_IN => '0', -- general reset signal (SYSCLK) @@ -303,11 +322,20 @@ process begin THE_MAIN_PLL : pll_in200_out100 port map( CLK => CLK_GPLL_LEFT, - CLKOP => clk_100_i, - CLKOK => clk_200_i, + CLKOP => clk_100_internal,--clk_100_i + CLKOK => clk_200_internal, --clk_200_i LOCK => pll_lock ); +gen_sync_clocks : if SYNC_MODE = c_YES generate + clk_100_i <= rx_clock_100; + clk_200_i <= rx_clock_200; +end generate; + +gen_local_clocks : if SYNC_MODE = c_NO generate + clk_100_i <= clk_100_internal; + clk_200_i <= clk_200_internal; +end generate; --------------------------------------------------------------------------- -- The TrbNet media interface (Uplink) @@ -317,10 +345,11 @@ THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp SERDES_NUM => 0, --number of serdes in quad EXT_CLOCK => c_NO, --use internal clock USE_200_MHZ => c_YES, --run on 200 MHz clock - USE_CTC => c_YES + USE_CTC => c_NO, + USE_SLAVE => SYNC_MODE ) port map( - CLK => clk_200_i, + CLK => clk_200_internal, --clk_200_i, SYSCLK => clk_100_i, RESET => reset_i, CLEAR => clear_i, @@ -335,6 +364,8 @@ THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp MED_DATAREADY_OUT => med_dataready_in(4), MED_READ_IN => med_read_out(4), REFCLK2CORE_OUT => open, + CLK_RX_HALF_OUT => rx_clock_100, + CLK_RX_FULL_OUT => rx_clock_200, --SFP Connection SD_RXD_P_IN => SFP_RX_P(1), SD_RXD_N_IN => SFP_RX_N(1), @@ -345,6 +376,13 @@ THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp SD_PRSNT_N_IN => SFP_MOD0(1), SD_LOS_IN => SFP_LOS(1), SD_TXDIS_OUT => SFP_TXDIS(1), + + SCI_DATA_IN => sci1_data_in, + SCI_DATA_OUT => sci1_data_out, + SCI_ADDR => sci1_addr, + SCI_READ => sci1_read, + SCI_WRITE => sci1_write, + SCI_ACK => sci1_ack, -- Status and control port STAT_OP => med_stat_op(79 downto 64), CTRL_OP => med_ctrl_op(79 downto 64), @@ -360,7 +398,7 @@ SFP_TXDIS(7 downto 2) <= (others => '1'); --------------------------------------------------------------------------- -- The TrbNet media interface (to other FPGA) --------------------------------------------------------------------------- -THE_MEDIA_ONBOARD : trb_net16_med_ecp3_sfp_4_onboard +THE_MEDIA_ONBOARD : trb_net16_med_ecp3_sfp_4 port map( CLK => clk_200_i, SYSCLK => clk_100_i, @@ -396,6 +434,13 @@ THE_MEDIA_ONBOARD : trb_net16_med_ecp3_sfp_4_onboard SD_TXDIS_OUT(1) => FPGA2_COMM(0), SD_TXDIS_OUT(2) => FPGA3_COMM(0), SD_TXDIS_OUT(3) => FPGA4_COMM(0), + + SCI_DATA_IN => sci2_data_in, + SCI_DATA_OUT => sci2_data_out, + SCI_ADDR => sci2_addr, + SCI_READ => sci2_read, + SCI_WRITE => sci2_write, + SCI_ACK => sci2_ack, -- Status and control port STAT_OP => med_stat_op(63 downto 0), CTRL_OP => med_ctrl_op(63 downto 0), @@ -695,9 +740,9 @@ end generate; --------------------------------------------------------------------------- THE_BUS_HANDLER : trb_net16_regio_bus_handler generic map( - PORT_NUMBER => 4, - PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"8100", 3 => x"8300", others => x"0000"), - PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 8, 3 => 8, others => 0) + PORT_NUMBER => 6, + PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"8100", 3 => x"8300", 4 => x"b000", 5 => x"b200", others => x"0000"), + PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 8, 3 => 8, 4 => 9, 5 => 9, others => 0) ) port map( CLK => clk_100_i, @@ -739,31 +784,58 @@ THE_BUS_HANDLER : trb_net16_regio_bus_handler BUS_NO_MORE_DATA_IN(1) => '0', BUS_UNKNOWN_ADDR_IN(1) => '0', - -- third one - IP config memory - BUS_ADDR_OUT(3*16-1 downto 2*16) => mb_ip_mem_addr, - BUS_DATA_OUT(3*32-1 downto 2*32) => mb_ip_mem_data_wr, - BUS_READ_ENABLE_OUT(2) => mb_ip_mem_read, - BUS_WRITE_ENABLE_OUT(2) => mb_ip_mem_write, - BUS_TIMEOUT_OUT(2) => open, - BUS_DATA_IN(3*32-1 downto 2*32) => mb_ip_mem_data_rd, - BUS_DATAREADY_IN(2) => mb_ip_mem_ack, - BUS_WRITE_ACK_IN(2) => mb_ip_mem_ack, - BUS_NO_MORE_DATA_IN(2) => '0', - BUS_UNKNOWN_ADDR_IN(2) => '0', - - -- gk 22.04.10 - -- gbe setup - BUS_ADDR_OUT(4*16-1 downto 3*16) => gbe_stp_reg_addr, - BUS_DATA_OUT(4*32-1 downto 3*32) => gbe_stp_reg_data_wr, - BUS_READ_ENABLE_OUT(3) => gbe_stp_reg_read, - BUS_WRITE_ENABLE_OUT(3) => gbe_stp_reg_write, - BUS_TIMEOUT_OUT(3) => open, - BUS_DATA_IN(4*32-1 downto 3*32) => gbe_stp_reg_data_rd, - BUS_DATAREADY_IN(3) => gbe_stp_reg_ack, - BUS_WRITE_ACK_IN(3) => gbe_stp_reg_ack, - BUS_NO_MORE_DATA_IN(3) => '0', - BUS_UNKNOWN_ADDR_IN(3) => '0', - + -- third one - IP config memory + BUS_ADDR_OUT(3*16-1 downto 2*16) => mb_ip_mem_addr, + BUS_DATA_OUT(3*32-1 downto 2*32) => mb_ip_mem_data_wr, + BUS_READ_ENABLE_OUT(2) => mb_ip_mem_read, + BUS_WRITE_ENABLE_OUT(2) => mb_ip_mem_write, + BUS_TIMEOUT_OUT(2) => open, + BUS_DATA_IN(3*32-1 downto 2*32) => mb_ip_mem_data_rd, + BUS_DATAREADY_IN(2) => mb_ip_mem_ack, + BUS_WRITE_ACK_IN(2) => mb_ip_mem_ack, + BUS_NO_MORE_DATA_IN(2) => '0', + BUS_UNKNOWN_ADDR_IN(2) => '0', + + -- gk 22.04.10 + -- gbe setup + BUS_ADDR_OUT(4*16-1 downto 3*16) => gbe_stp_reg_addr, + BUS_DATA_OUT(4*32-1 downto 3*32) => gbe_stp_reg_data_wr, + BUS_READ_ENABLE_OUT(3) => gbe_stp_reg_read, + BUS_WRITE_ENABLE_OUT(3) => gbe_stp_reg_write, + BUS_TIMEOUT_OUT(3) => open, + BUS_DATA_IN(4*32-1 downto 3*32) => gbe_stp_reg_data_rd, + BUS_DATAREADY_IN(3) => gbe_stp_reg_ack, + BUS_WRITE_ACK_IN(3) => gbe_stp_reg_ack, + BUS_NO_MORE_DATA_IN(3) => '0', + BUS_UNKNOWN_ADDR_IN(3) => '0', + + --SCI first Media Interface + BUS_READ_ENABLE_OUT(4) => sci1_read, + BUS_WRITE_ENABLE_OUT(4) => sci1_write, + BUS_DATA_OUT(4*32+7 downto 4*32) => sci1_data_in, + BUS_DATA_OUT(4*32+31 downto 4*32+8) => open, + BUS_ADDR_OUT(4*16+8 downto 4*16) => sci1_addr, + BUS_ADDR_OUT(4*16+15 downto 4*16+9) => open, + BUS_TIMEOUT_OUT(4) => open, + BUS_DATA_IN(4*32+7 downto 4*32) => sci1_data_out, + BUS_DATAREADY_IN(4) => sci1_ack, + BUS_WRITE_ACK_IN(4) => sci1_ack, + BUS_NO_MORE_DATA_IN(4) => '0', + BUS_UNKNOWN_ADDR_IN(4) => '0', + --SCI second Media Interface + BUS_READ_ENABLE_OUT(5) => sci2_read, + BUS_WRITE_ENABLE_OUT(5) => sci2_write, + BUS_DATA_OUT(5*32+7 downto 5*32) => sci2_data_in, + BUS_DATA_OUT(5*32+31 downto 5*32+8) => open, + BUS_ADDR_OUT(5*16+8 downto 5*16) => sci2_addr, + BUS_ADDR_OUT(5*16+15 downto 5*16+9) => open, + BUS_TIMEOUT_OUT(5) => open, + BUS_DATA_IN(5*32+7 downto 5*32) => sci2_data_out, + BUS_DATAREADY_IN(5) => sci2_ack, + BUS_WRITE_ACK_IN(5) => sci2_ack, + BUS_NO_MORE_DATA_IN(5) => '0', + BUS_UNKNOWN_ADDR_IN(5) => '0', + STAT_DEBUG => open ); @@ -904,6 +976,8 @@ LED_YELLOW <= link_ok; --debug(3); TEST_LINE(31 downto 10) <= (others => '0'); + CLK_TEST_OUT <= clk_200_i & rx_clock & clk_100_i; + -- FPGA1_CONNECTOR(0) <= '0'; FPGA2_CONNECTOR(0) <= '0'; @@ -916,7 +990,7 @@ LED_YELLOW <= link_ok; --debug(3); --------------------------------------------------------------------------- process begin - wait until rising_edge(clk_100_i); + wait until rising_edge(clk_100_internal); time_counter <= time_counter + 1; end process; diff --git a/trb3_gbe/trb3_central_constraints.lpf b/trb3_gbe/trb3_central_constraints.lpf index c5d55e7..5d3b54e 100644 --- a/trb3_gbe/trb3_central_constraints.lpf +++ b/trb3_gbe/trb3_central_constraints.lpf @@ -26,6 +26,7 @@ GSR_NET NET "GSR_N"; ################################################################# LOCATE COMP "gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/clk_int_SERDES_GBE/PCSD_INST" SITE "PCSB"; LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_0_200_ctc_THE_SERDES/PCSD_INST" SITE "PCSA" ; +LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_0_200_THE_SERDES/PCSD_INST" SITE "PCSA" ; LOCATE COMP "THE_MEDIA_ONBOARD/gen_serdes_200_THE_SERDES/PCSD_INST" SITE "PCSC" ; LOCATE COMP "THE_MEDIA_ONBOARD/gen_serdes_125_THE_SERDES/PCSD_INST" SITE "PCSC" ; @@ -36,6 +37,8 @@ LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ; REGION "MEDIA_ONBOARD" "R90C122" 20 40; LOCATE UGROUP "THE_MEDIA_ONBOARD/media_interface_group" REGION "MEDIA_ONBOARD" ; +MULTICYCLE TO CELL "THE_MEDIA_ONBOARD/SCI_DATA_OUT*" 50 ns; +MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns; #SPI Interface REGION "REGION_SPI" "R13C150D" 12 16 DEVSIZE; diff --git a/wasa/panda_dirc_wasa.p2t b/wasa/panda_dirc_wasa.p2t new file mode 100644 index 0000000..995161f --- /dev/null +++ b/wasa/panda_dirc_wasa.p2t @@ -0,0 +1,20 @@ +-w +-i 15 +-l 5 +-n 1 +-y +-s 12 +-t 11 +-c 1 +-e 2 +-m nodelist.txt +# -w +# -i 6 +# -l 5 +# -n 1 +# -t 1 +# -s 1 +# -c 0 +# -e 0 +# +-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1: diff --git a/wasa/panda_dirc_wasa.vhd b/wasa/panda_dirc_wasa.vhd index 1fc24af..6c65f84 100644 --- a/wasa/panda_dirc_wasa.vhd +++ b/wasa/panda_dirc_wasa.vhd @@ -14,7 +14,7 @@ use machxo2.all; entity panda_dirc_wasa is generic( - SAME_ORDER : integer := 0 + NORMAL_ORDER : integer := 1 ); port( CON : out std_logic_vector(16 downto 1); @@ -164,7 +164,7 @@ type ram_t is array(0 to 15) of std_logic_vector(15 downto 0); signal ram : ram_t; signal pwm_i : std_logic_vector(31 downto 0); -signal tmp_con : std_logic_vector(15 downto 0); +signal INP_i : std_logic_vector(15 downto 0); signal spi_reg00_i : std_logic_vector(15 downto 0); signal spi_reg10_i : std_logic_vector(15 downto 0); signal spi_reg20_i : std_logic_vector(15 downto 0); @@ -258,7 +258,24 @@ clk_source: OSCH SEDSTDBY => open ); +--------------------------------------------------------------------------- +-- Input re-ordering +--------------------------------------------------------------------------- +gen_outputs_1 : if NORMAL_ORDER = 1 generate + INP_i <= INP; + PWM <= pwm_i(15 downto 0); +end generate; +gen_outputs_2 : if NORMAL_ORDER = 0 generate + INP_i <= INP(15) & INP(7) & INP(14) & INP(6) & INP(13) & INP(5) & INP(12) & INP(4) & + INP(11) & INP(3) & INP(10) & INP(2) & INP(9) & INP(1) & INP(8) & INP(0); + PWM <= pwm_i(15) & pwm_i(7) & pwm_i(14) & pwm_i(6) & pwm_i(13) & pwm_i(5) & pwm_i(12) & pwm_i(4) & + pwm_i(11) & pwm_i(3) & pwm_i(10) & pwm_i(2) & pwm_i(9) & pwm_i(1) & pwm_i(8) & pwm_i(0); +end generate; + + + + --------------------------------------------------------------------------- -- SPI Interface --------------------------------------------------------------------------- @@ -281,13 +298,14 @@ THE_SPI_SLAVE : spi_slave ); SPI_OUT <= buf_SPI_OUT; ---------------------------------------------------------------------------- --- RAM Interface ---------------------------------------------------------------------------- - +spi_reg00_i <= pwm_data_o; +spi_reg10_i <= idram(to_integer(unsigned(spi_channel_i(2 downto 0)))); spi_reg40_i <= flash_busy & flash_err & "000000" & ram_data_o; +--------------------------------------------------------------------------- +-- RAM Interface +--------------------------------------------------------------------------- PROC_CTRL_FLASH : process begin @@ -404,9 +422,7 @@ THE_PWM_GEN : pwm_generator PWM => pwm_i ); - PWM <= pwm_i(15 downto 0); -spi_reg00_i <= pwm_data_o; PROC_PWM_DATA_MUX : process(fsm_copydat, spi_data_i, spi_write_i, spi_channel_i, pwm_fsm_addr, pwm_fsm_data_i, pwm_fsm_write, @@ -463,7 +479,6 @@ PROC_IDMEM : process begin else idram(4) <= "0000" & temperature_i; end if; - spi_reg10_i <= idram(to_integer(unsigned(spi_channel_i(2 downto 0)))); if spi_write_i(1) = '1' then onewire_reset <= spi_data_i(0); @@ -511,7 +526,7 @@ THE_IO_REG_WRITE : process begin end if; end process; -inp_status <= INP when rising_edge(clk_i); +inp_status <= INP_i when rising_edge(clk_i); last_inp <= inp_status(3 downto 0) when rising_edge(clk_i); @@ -533,15 +548,8 @@ end process; -- Rest of the I/O --------------------------------------------------------------------------- -inp_gated <= (INP xor inp_invert) and not input_enable; -tmp_con <= inp_gated or (inp_stretched and inp_stretch); - -gen_outputs_1 : if SAME_ORDER = 1 generate - CON <= tmp_con; -end generate; -gen_outputs_2 : if SAME_ORDER = 0 generate - CON <= tmp_con; -end generate; +inp_gated <= (INP_i xor inp_invert) and not input_enable; +CON <= inp_gated or (inp_stretched and inp_stretch); @@ -560,10 +568,10 @@ inp_stretched <= inp_hold_reg or last_inp_hold_reg or inp_hold; -SPARE_OUTPUT : process(INP, inp_select, inp_or, inp_long_or, inp_long_reg, last_inp_long_reg) +SPARE_OUTPUT : process(INP_i, inp_select, inp_or, inp_long_or, inp_long_reg, last_inp_long_reg) begin if inp_select < 16 then - SPARE_LVDS <= INP(inp_select+1); + SPARE_LVDS <= INP_i(inp_select); elsif inp_select < 24 then SPARE_LVDS <= inp_or; else @@ -571,12 +579,11 @@ SPARE_OUTPUT : process(INP, inp_select, inp_or, inp_long_or, inp_long_reg, last_ end if; end process; -inp_or <= or_all((INP xor inp_invert) and not input_enable); - +inp_or <= or_all((INP_i xor inp_invert) and not input_enable); inp_long_or <= (inp_or or inp_long_or) and not inp_long_reg; - inp_long_reg <= inp_long_or when rising_edge(clk_i); last_inp_long_reg <= inp_long_reg when rising_edge(clk_i); + -- ll_inp_long_reg <= last_inp_long_reg when rising_edge(clk_i); @@ -595,7 +602,7 @@ last_inp_long_reg <= inp_long_reg when rising_edge(clk_i); -- TEST_LINE(15) <= '1' when fsm_copydat = PWM_WRITE_GET_2 or fsm_copydat = PWM_WRITE else '0'; -TEST_LINE <= spi_debug_i; +TEST_LINE <= (others => '0'); LED_GREEN <= not leds(0) when led_status(4) = '0' else not led_status(0); -- 2.43.0