From c7808ee61a29b805fcf172dc04d0b22bbf8d5952 Mon Sep 17 00:00:00 2001 From: hadaq Date: Thu, 10 Jun 2010 12:56:55 +0000 Subject: [PATCH] *** empty log message *** --- slowcontrol.tex | 260 ++++++++++++++++++++++++++++++------------------ 1 file changed, 162 insertions(+), 98 deletions(-) diff --git a/slowcontrol.tex b/slowcontrol.tex index 841a517..5cef927 100755 --- a/slowcontrol.tex +++ b/slowcontrol.tex @@ -1,15 +1,18 @@ \label{RegIO} -The RegIO component handles all data received on the slow control channel. Its structure is depicted in figure \ref{fig:regio}. It provides status registers that are common for all boards, user defineable -status and control registers, and stores information about the hardware. As already mentioned, these common registers are needed to provide a universal monitoring tool for all parts of the detector. +The RegIO component handles all data received on the slow control channel. Its structure +is depicted in figure~\ref{fig:regio}. It provides status registers that are common for +all boards, user defineable status and control registers, and stores information about +the hardware. As already mentioned, these common registers are needed to provide a +universal monitoring tool for all parts of the detector. -Each register has one 16Bit address assigned as shown in Table~\ref{regioaddressmap}. -Each address corresponds to one 32 Bit register or data word. +Each register has one 16bit address assigned as shown in Table~\ref{regioaddressmap}. +Each address corresponds to one 32bit register or data word. To access all registers and other information, a simple command structure is -defined. The protocol is quite simple: For each access a 64 bit data word +defined. The protocol is quite simple: For each access a 64bit data word is sent as shown in Table~\ref{RegIO:protocol}. The \netname{dtype} of the -packets carries the desired operation, followed by the first 16 bit word with -the register address and, in case of a write access, 32 bits of data. +packets carries the desired operation, followed by the first 16~bit word with +the register address and, in case of a write access, 32bit of data. Altogether there are four different operations implemented: Single and multiple reads and writes from or to the same (or ascending) address. The multiple access is only supported on the internal data port and can be used to read data from a FIFO. @@ -41,31 +44,34 @@ addresses and the board ID.} section about addresses} \\ \hline \end{tabular} - \caption{[Register read/write protocol]Register read/write protocol. The config word for multiple accesses has the highest bit selecting between fixed (0) addresses and ascending (1) addresses. The lower 15 bit on the read operation select the maximum number of read accesses to be made. A multiple write always consists of one starting word containing address and mode followed by an arbitrary number of data packets.} + \caption{[Register read/write protocol]Register read/write protocol. The config word for +multiple accesses has the highest bit selecting between fixed (0) addresses and ascending +(1) addresses. The lower 15bit on the read operation select the maximum number of read +accesses to be made. A multiple write always consists of one starting word containing +address and mode followed by an arbitrary number of data packets.} \label{RegIO:protocol} \end{center} \end{table} -Internally it also has logic to readout the 1-wire temperature logic and to assign network addresses. Other features include a global timer and configurable easy-to-use status and control registers. Additional, more complex logic can be connected to the internal data bus. - - - - - - - - - +Internally it also has logic to readout the 1-wire temperature logic and to assign network +addresses. Other features include a global timer and configurable easy-to-use status and +control registers. Additional, more complex logic can be connected to the internal data bus. \subsection{User Interface} The ports on the user interface can be divided into several sets: \paragraph{Registers} \label{RegIORegisters} -There are four types of registers provided by RegIO: Common registers that are defined for all boards in the same way and user specific resgisters. These two sets are further divided into status registers that can be written by the internal logic and control registers that can be written over the network. The registers have a size of 32 bits each. The number of user registers in each of the four groups can be set using generics (see \ref{regiogenerics}). +There are four types of registers provided by RegIO: Common registers that are defined for all +boards in the same way and user specific resgisters. These two sets are further divided into +status registers that can be written by the internal logic and control registers that can be +written over the network. The registers have a size of 32bit each. The number of user registers +in each of the four groups can be set using generics (see \ref{regiogenerics}). -For each register there is a strobe signal that shows read access (in case of status register) or write access (in case of control registers) from the network side. The following listing shows the name of all ports: +For each register there is a strobe signal that shows read access (in case of status register) or +write access (in case of control registers) from the network side. The following listing shows +the name of all ports: \lstset { caption ={Register Ports on RegIO}} \begin{lstlisting} @@ -82,58 +88,96 @@ Regio_Ctrl_Strobe(2**(num_ctrl_regs)-1 downto 0) \paragraph{Onewire} -The temperature sensor on each board is connected to the following ports. In case no temperature sensor is connected directly, the generic setting \genericname{Regio\_\-Use\_\-1wire\_\-Interface} has to be set accordingly. +The temperature sensor on each board is connected to the following ports. In case no temperature +sensor is connected directly, the generic setting \genericname{Regio\_\-Use\_\-1wire\_\-Interface} +has to be set accordingly. \begin{description} \item[\portname{Regio\_Onewire\_Inout}] Direct connection to a 1-wire temperature sensor - \item[\portname{Regio\_Onewire\_Monitor\_Out}] Outputs a copy of the signals on the 1-wire bus. Used to transport information to another FPGA. - \item[\portname{Regio\_Onewire\_Monitor\_In}] The corresponding input to monitor traffic on a 1-wire bus if no sensor is connected directly to the fpga. + \item[\portname{Regio\_Onewire\_Monitor\_Out}] Outputs a copy of the signals on the 1-wire bus. +Used to transport information to another FPGA. + \item[\portname{Regio\_Onewire\_Monitor\_In}] The corresponding input to monitor traffic on a +1-wire bus if no sensor is connected directly to the fpga. \end{description} \paragraph{Timers} -The timers give a rough information on the current time. The global time can be set using normal slow control accesses. That means, it has an inherent ambiguity of about 200 ns plus a drift of up to 20ppm compared to other boards. The additional timer ticks can be used to simplify other parts of the logic, e.g. as clock enable signal for slowly running parts of the design. +The timers give a rough information on the current time. The global time can be set using normal +slow control accesses. That means, it has an inherent ambiguity of about 200ns plus a drift of up +to 20ppm compared to other boards. The additional timer ticks can be used to simplify other parts +of the logic, e.g. as clock enable signal for slowly running parts of the design. \begin{description} - \item[\portname{Global\_Time\_Out}] The global time measured in microseconds. This time will be synchronized on all boards from time to time to keep descrepancies between the boards low. E.g. used for marking debugging and status information. - \item[\portname{Local\_Time\_Out}] The local time is used to measure in the sub-microsecond range. It counts with the internal clock frequency (standard: 100 MHz) and is reset each microsecond. - \item[\portname{Time\_Since\_Last\_Trg\_Out}] The time since the last timing trigger has been received, measured in clock cycles. - \item[\portname{Timer\_Us\_Tick\_Out}] A tickmark that is set every microsecond for one clock cycle. Can be used to clock internal slow running logic. - \item[\portname{Timer\_Ms\_Tick\_Out}] A tickmark that is set every 1024 us for one clock cycle. Can be used to clock internal slow running logic. + \item[\portname{Global\_Time\_Out}] The global time measured in microseconds. This time will be +synchronized on all boards from time to time to keep descrepancies between the boards low. E.g. +used for marking debugging and status information. + \item[\portname{Local\_Time\_Out}] The local time is used to measure in the sub-microsecond range. +It counts with the internal clock frequency (standard: 100 MHz) and is reset each microsecond. + \item[\portname{Time\_Since\_Last\_Trg\_Out}] The time since the last timing trigger has been received, +measured in clock cycles. + \item[\portname{Timer\_Us\_Tick\_Out}] A tickmark that is set every microsecond for one clock cycle. +Can be used to clock internal slow running logic. + \item[\portname{Timer\_Ms\_Tick\_Out}] A tickmark that is set every 1024 us for one clock cycle. +Can be used to clock internal slow running logic. \end{description} \paragraph{Internal Data Bus} -An access cycle on the internal data bus consists of two actions: First, RegIO sends a read or a write strobe. At the same time \portname{address} and \portname{data\_out} are valid. Afterwards it waits up to 32 clock cycles for a reaction of the connected logic. This can be either of \portname{dataready}, \portname{no\_more\_data}, \portname{write\_ack} or \portname{unknown\_addr} as described below. If the logic fails to answer, an automatic timeout is generated. +An access cycle on the internal data bus consists of two actions: First, RegIO sends a read or a +write strobe. At the same time \portname{address} and \portname{data\_out} are valid. Afterwards +it waits up to 32 clock cycles for a reaction of the connected logic. This can be either of +\portname{dataready}, \portname{no\_more\_data}, \portname{write\_ack} or \portname{unknown\_addr} +as described below. If the logic fails to answer, an automatic timeout is generated. \begin{description} - \item[\portname{Regio\_Addr\_Out}] (16 bit) address port. Address is valid when either of \portname{read\_enable} and \portname{write\_enable} is high. + \item[\portname{Regio\_Addr\_Out}] (16 bit) address port. Address is valid when either of +\portname{read\_enable} and \portname{write\_enable} is high. \item[\portname{Regio\_Read\_Enable\_Out}] Read enable strobe. \item[\portname{Regio\_Write\_Enable\_Out}] Write enable strobe. - \item[\portname{Regio\_Data\_Out}] (32 bit) Data output of regIO, input to the user. Valid when \portname{write\_\-enable} is high. - \item[\portname{Regio\_Data\_In}] (32 bit) Data input to regIO, output from the user. Valid when \portname{dataready\_\-in} is high. - \item[\portname{Regio\_Dataready\_In}] User signal to show that \portname{data\_in} is valid. May only be used after a strobe on \portname{read\_enable}. - \item[\portname{Regio\_No\_More\_Data\_In}] User signal. After a read strobe: User has no more data to read from this address. After a write strobe: User is not able to handle more data on this address now. - \item[\portname{Regio\_Write\_Ack\_In}] User signal. Acknowledge after a strobe on \portname{write\_enable} and writing was successful. - \item[\portname{Regio\_Unknown\_Addr\_In}] User signal. After either read or write strobe: The given address is not in use. - \item[\portname{Regio\_Timeout\_Out}] About 24 to 32 clock cycles after a read or write strobe RegIO terminates the access assuming the user logic does not react. + \item[\portname{Regio\_Data\_Out}] (32 bit) Data output of regIO, input to the user. Valid when +\portname{write\_\-enable} is high. + \item[\portname{Regio\_Data\_In}] (32 bit) Data input to regIO, output from the user. Valid when +\portname{dataready\_\-in} is high. + \item[\portname{Regio\_Dataready\_In}] User signal to show that \portname{data\_in} is valid. May +only be used after a strobe on \portname{read\_enable}. + \item[\portname{Regio\_No\_More\_Data\_In}] User signal. After a read strobe: User has no more data +to read from this address. After a write strobe: User is not able to handle more data on this address now. + \item[\portname{Regio\_Write\_Ack\_In}] User signal. Acknowledge after a strobe on \portname{write\_enable} +and writing was successful. + \item[\portname{Regio\_Unknown\_Addr\_In}] User signal. After either read or write strobe: The given +address is not in use. + \item[\portname{Regio\_Timeout\_Out}] About 24 to 32 clock cycles after a read or write strobe RegIO +terminates the access assuming the user logic does not react. \end{description} \paragraph{Generic Settings} \label{regiogenerics} \begin{description} - \item[\portname{Regio\_Num\_Stat\_Regs}] The number of status registers (addr. 0x80 ff). This value is log2 of the desired number of 32bit registers - \item[\portname{Regio\_Num\_Ctrl\_Regs}] The number of control registers (addr. 0xc0 ff). This value is log2 of the desired number of 32bit registers - \item[\portname{Regio\_Init\_Ctrl\_Regs}] The initial value of all control registers. This generic has a fixed size of 8x32 bits - \item[\portname{Regio\_Use\_Dat\_Port}] Selects to have an internal data port to connect own registers to in the address space above 0x0100 - \item[\portname{Regio\_Use\_1wire\_Interface}] Set to \constname{c\_Yes} means a temperature sensor is connected, \constname{c\_\-Mon\-itor} means there is a 1-wire data stream sent by another FPGA, \constname{c\_No} means temperature and unique id are written using some user supplied logic. - \item[\portname{Use\_Dat\_Port}] The internal data port can be switched off if not in use. Hence, all accesses to addresses above 0x100 will be automatically answered by RegIO. - \item[\portname{Init\_Address}] The network address the board is given initially. (note: does not work using Synplify under Linux) - \item[\portname{Init\_Endpoint\_Id}] The endpoint ID. On boards with two or more FPGAs this is usually the FPGA number according to the boards schematics. Boards with only one FPGA use 1 here. Basic Rule: Each FPGA connected to the same temperature sensore has to have a different endpoint ID to be indentifieable. - \item[\portname{Compile\_Time}] The UNIX timestamp when the design has been compiled. Must be set by hand or using our standard compile script. - \item[\portname{Hardware\_Version}] These 32bit give information about the type of hardware. The upper 16 bit are defined in table \ref{HardwareInformation}, the lower 16 bits are free to use. + \item[\portname{Regio\_Num\_Stat\_Regs}] The number of status registers (addr. 0x80 ff). +This value is log2 of the desired number of 32bit registers + \item[\portname{Regio\_Num\_Ctrl\_Regs}] The number of control registers (addr. 0xc0 ff). +This value is log2 of the desired number of 32bit registers + \item[\portname{Regio\_Init\_Ctrl\_Regs}] The initial value of all control registers. +This generic has a fixed size of 8x32 bits + \item[\portname{Regio\_Use\_Dat\_Port}] Selects to have an internal data port to connect +own registers to in the address space above 0x0100 + \item[\portname{Regio\_Use\_1wire\_Interface}] Set to \constname{c\_Yes} means a temperature +sensor is connected, \constname{c\_\-Mon\-itor} means there is a 1-wire data stream sent by +another FPGA, \constname{c\_No} means temperature and unique id are written using some user supplied logic. + \item[\portname{Use\_Dat\_Port}] The internal data port can be switched off if not in use. +Hence, all accesses to addresses above 0x100 will be automatically answered by RegIO. + \item[\portname{Init\_Address}] The network address the board is given initially. (note: +may not work using Synplify under Linux, depending on the compiler version) + \item[\portname{Init\_Endpoint\_Id}] The endpoint ID. On boards with two or more FPGAs +this is usually the FPGA number according to the boards schematics. Boards with only one FPGA +use 1 here. Basic Rule: Each FPGA connected to the same temperature sensore has to have a different +endpoint ID to be indentifieable. + \item[\portname{Compile\_Time}] The UNIX timestamp when the design has been compiled. Must be set +by hand or using our standard compile script. + \item[\portname{Hardware\_Version}] These 32bit give information about the type of hardware. The + upper 16~bit are defined in table \ref{HardwareInformation}, the lower 16~bits are free to use. \end{description} @@ -141,9 +185,15 @@ An access cycle on the internal data bus consists of two actions: First, RegIO s \subsection{RegIo Bus Handler} -If you want to connect several registers or function blocks to the internal data bus, you can use the RegIO Bus Handler. This special entity (\filename{trb\_net16\_regio\_bus\_handler}) simplifies to generate several address sub-spaces on the internal data bus. It is configured using three generic values as shown in the listing below. These settings introduce two address spaces: One starting at 0xA000 with a size of 2**8 addresses, i.e. from 0xA000 to 0xA0FF, and one starting at 0x8000 with 2**6 addresses, i.e. from 0x8000 to 0x803F. +If you want to connect several registers or function blocks to the internal data bus, you can use the +RegIO Bus Handler. This special entity (\filename{trb\_net16\_regio\_bus\_handler}) simplifies to +generate several address sub-spaces on the internal data bus. It is configured using three generic +values as shown in the listing below. These settings introduce two address spaces: One starting at +0xA000 with a size of 2**8 addresses, i.e. from 0xA000 to 0xA0FF, and one starting at 0x8000 with +2**6 addresses, i.e. from 0x8000 to 0x803F. -The behaviour on the data busses is identical to the original RegIO interface. Connecting to the different address spaces can be done in a convenient form as shown in the following piece of code: +The behaviour on the data busses is identical to the original RegIO interface. Connecting to the +different address spaces can be done in a convenient form as shown in the following piece of code: \lstset { caption ={Excerpt from the regio\_bus\_handler used in MDC OEP.}} \begin{lstlisting} @@ -199,34 +249,31 @@ port map( \end{lstlisting} - - - - \subsection{Register Map} -Table \ref{regioaddressmap} shows a list of most defined registers within the slow control endpoint. The common status and control registers are further explained in the next section. +Table \ref{regioaddressmap} shows a list of most defined registers within the slow control endpoint. +The common status and control registers are further explained in the next section. \begin{table}[htbp] \begin{center} -\begin{tabularx}{\textwidth}{|c|c|C|} +\begin{tabularx}{\textwidth}{|c|c|c|C|} \hline -\textbf{Address} & \textbf{Name} & \textbf{Description} \\ +\textbf{Address} & \textbf{Mnemonics} & \textbf{Name} & \textbf{Description} \\ \hline\hline -00 & common status register 0 (CSR0) & Basic Error Flags and Temperature (see below) (r) \\ -01 & common status register 1 (CSR1) & LVL1 trigger number (Bits 15..0), timing Trigger number (Bits 31..16) (r) \\ -20 & common control register 0 (CCR0) & Strobes for board resets and test triggers (see below) (w)\\ -21 & common control register 1 (CCR1) & Sets LVL1 trigger number (Bits 15..0) (r/w)\\ -22 & common control register 2 (CCR2) & frontend enable, trigger enable, debug enable (r/w)\\ -40 & information ROM 0 & Compile Time (set by generic) (r)\\ -41 & information ROM 1 & Design Version (set by generic) (r) \\ -42 & information ROM 2 & Hardware Information (set by generic) (r)\\ -50 & global time & Global Time (r/w)\\ -51 & time since trigger & Time since last timing trigger (r)\\ -80 -- BF & user status registers & User status registers \\ -C0 -- FF & user control registers & User control registers \\ -0100 -- 6FFF & reserved & Reserved addresses on internal data port (e.g. for monitoring and other features)\\ -7000 -- 7FFF & endpoint monitoring & Monitoring Registers for Endpoint\\ -8000 -- FFFF & user defined & User defined address space on the internal data bus \\ +00 & common status register 0 & CSR0 & Basic Error Flags and Temperature (see below) (r) \\ +01 & common status register 1 & CSR1 & LVL1 trigger number (Bits 15..0), timing Trigger number (Bits 31..16) (r) \\ +20 & common control register 0 & CCR0 & Strobes for board resets and test triggers (see below) (w)\\ +21 & common control register 1 & CCR1 & Sets LVL1 trigger number (Bits 15..0) (r/w)\\ +22 & common control register 2 & CCR2 & frontend enable, trigger enable, debug enable (r/w)\\ +40 & information ROM 0 & ROM0 & Compile Time (set by generic) (r)\\ +41 & information ROM 1 & ROM1 & Design Version (set by generic) (r) \\ +42 & information ROM 2 & ROM2 & Hardware Information (set by generic) (r)\\ +50 & global time & TIME & Global Time (r/w)\\ +51 & time since trigger & TSTR & Time since last timing trigger (r)\\ +80 -- BF & user status registers & --- & User status registers \\ +C0 -- FF & user control registers & --- & User control registers \\ +0100 -- 6FFF & reserved & --- & Reserved addresses on internal data port (e.g. for monitoring and other features)\\ +7000 -- 7FFF & endpoint monitoring & --- & Monitoring Registers for Endpoint\\ +8000 -- FFFF & user defined & --- & User defined address space on the internal data bus \\ \hline \end{tabularx} \caption{Register Map of the Slow Control Endpoint.} @@ -275,21 +322,21 @@ A detailed bit definition can be found in table~\ref{CommonCtrlReg2}. \hline \textbf{Bits} & \textbf{Description} \\ \hline\hline -0 & serious error flag \\ -1 & error flag \\ -2 & warning flag \\ -3 & note flag\\ -4 & LVL1 trigger counter mismatch \\ -5 & IPU channel counter mismatch \\ -6 & Frontend not configured\\ -7 & Frontend error\\ -8 & Timing trigger missing\\ -9 & IPU Event not found\\ -10 & IPU requested event partially not found / data missing\\ -11 & Severe problem in event data buffer / IPU request handler\\ +31 -- 20 & temperature \\ +19 -- 13 & reserved \\ 12 & Last event sent on IPU is broken\\ -13 -- 19 & reserved \\ -20 -- 31 & temperature \\ +11 & Severe problem in event data buffer / IPU request handler\\ +10 & IPU requested event partially not found / data missing\\ +9 & IPU Event not found\\ +8 & Timing trigger missing\\ +7 & Frontend error\\ +6 & Frontend not configured\\ +5 & IPU channel counter mismatch \\ +4 & LVL1 trigger counter mismatch \\ +3 & note flag\\ +2 & warning flag \\ +1 & error flag \\ +0 & serious error flag \\ \hline \end{tabular} \caption{Common Status Register 0} @@ -304,17 +351,19 @@ A detailed bit definition can be found in table~\ref{CommonCtrlReg2}. \hline \textbf{Bits} & \textbf{Description} \\ \hline\hline -0 & reset frontends \\ -1 & reset trigger logic \\ -2 & empty IPU chain / reset IPU logic \\ -3 & master reset \\ -10 & reset sequence counter \\ -15 & reboot FPGA \\ -16 -- 19 & dummy timing triggers \\ -20 -- 21 & reserved \\ -22 & Begin Run trigger \\ +31 -- 24 & user defined \\ 23 & End Run trigger \\ -24 -- 31 & user defined \\ +22 & Begin Run trigger \\ +21 -- 20 & reserved \\ +19 -- 16 & dummy timing triggers \\ +15 & reboot FPGA \\ +14 -- 11 & reserved \\ +10 & reset sequence counter \\ +9 -- 4 & reserved \\ +3 & master reset \\ +2 & empty IPU chain / reset IPU logic \\ +1 & reset trigger logic \\ +0 & reset frontends \\ \hline \end{tabular} \caption{Common Control Register 0 (CCR1). All bits are strobe signals.} @@ -329,12 +378,21 @@ A detailed bit definition can be found in table~\ref{CommonCtrlReg2}. \hline \textbf{Bits} & \textbf{Description} \\ \hline\hline +<<<<<<< slowcontrol.tex +31 & enable trigger \\ +30 & enable debug \\ +29 -- 24 & reserved \\ +23 -- 20 & data format \\ +19 -- 16 & reserved \\ +15 -- 0 & enable frontends \\ +======= 0 -- 15 & front-end enable \\ 16 -- 19 & reserved \\ 20 -- 23 & data format select \\ 24 -- 29 & reserved \\ 30 & enable debug output \\ 31 & enable trigger \\ +>>>>>>> 1.11 \hline \end{tabular} \caption{Common Control Register 2 (CCR2)} @@ -344,7 +402,11 @@ A detailed bit definition can be found in table~\ref{CommonCtrlReg2}. \paragraph{Hardware Information (0x42)} -This register holds information about the type of hardware. The upper 16 bit define the hardware type, the lower 16 bit are kept free to mark minor differences in the hardware setup such as optional patch wires used in the design. Design variants can also be marked using these bits. Their definition is given in the section dealing with detector specific features. The upper 16 bit are defined in table \ref{HardwareInformation} +This register holds information about the type of hardware. The upper 16 bit define the hardware type, +the lower 16 bit are kept free to mark minor differences in the hardware setup such as optional patch +wires used in the design. Design variants can also be marked using these bits. Their definition is +given in the section dealing with detector specific features. The upper 16 bit are defined in +table~\ref{HardwareInformation} \begin{table}[htbp] \begin{center} @@ -383,7 +445,9 @@ This register holds information about the type of hardware. The upper 16 bit def 8800 & Other TRB \\ \hline \end{tabularx} -\caption{Upper 16 bit in register 0x42 marking the hardware the design is belonging to. The value can be set by a generic value (\genericname{Regio\_Hardware\_Version}) of the TrbNet endpoint. The lower 16bit are not globally defined.} +\caption{Upper 16 bit in register 0x42 marking the hardware the design is belonging to. The value +can be set by a generic value (\genericname{Regio\_Hardware\_Version}) of the TrbNet endpoint. The +lower 16bit are not globally defined.} \label{HardwareInformation} \end{center} \end{table} -- 2.43.0