From c79a3a6859dbdc000f3920b7b99ce5caa77ee2e5 Mon Sep 17 00:00:00 2001
From: hadeshyp <hadeshyp>
Date: Fri, 26 Aug 2011 08:39:47 +0000
Subject: [PATCH] Ready for first test

---
 base/trb3.xcf                      | 234 +++++++++++++++++++++++++++++
 fpgatest/projects/trb3_central.pty |   3 +
 fpgatest/projects/trb3_periph.ldf  |  32 ++++
 fpgatest/projects/trb3_periph.pty  |   3 +
 4 files changed, 272 insertions(+)
 create mode 100644 base/trb3.xcf
 create mode 100644 fpgatest/projects/trb3_central.pty
 create mode 100644 fpgatest/projects/trb3_periph.ldf
 create mode 100644 fpgatest/projects/trb3_periph.pty

diff --git a/base/trb3.xcf b/base/trb3.xcf
new file mode 100644
index 0000000..ec4bc63
--- /dev/null
+++ b/base/trb3.xcf
@@ -0,0 +1,234 @@
+<?xml version='1.0' encoding='utf-8' ?>
+<!DOCTYPE		ispXCF	SYSTEM	"IspXCF.dtd" >
+<ispXCF version="17.8 Linux">
+	<Comment></Comment>
+	<Chain>
+		<Comm>JTAG</Comm>
+		<Device>
+			<Pos>1</Pos>
+			<Ref>FPGA5</Ref>
+			<Vendor>Lattice</Vendor>
+			<Family>LatticeECP3EA</Family>
+			<Name>LFE3-150EA</Name>
+			<IDCode>0x01015043</IDCode>
+			<Package>1156-ball fpBGA</Package>
+			<PON>LFE3-150EA-XXFN1156</PON>
+			<Bypass>
+				<InstrLen>8</InstrLen>
+				<InstrVal>11111111</InstrVal>
+				<BScanLen>1</BScanLen>
+				<BScanVal>0</BScanVal>
+			</Bypass>
+			<File>/d/jspc22/trb/cvs/trb3/fpgatest/workdir/trb3_central.bit</File>
+			<MaskFile>/home/hadaq/.isplever_lin/ispvmsystem/Database/xpga/ecp3/ecp3-150.msk</MaskFile>
+			<FileTime>8/24/2011 18:40:0</FileTime>
+			<Operation>Fast Program</Operation>
+			<Option>
+				<SVFVendor>JTAG STANDARD</SVFVendor>
+				<IOState>HighZ</IOState>
+				<PreloadLength>1326</PreloadLength>
+				<IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
+				<OverideUES value="TRUE"/>
+				<TCKFrequency>1.000000 MHz</TCKFrequency>
+				<SVFProcessor>SVF Processor</SVFProcessor>
+				<Usercode>0x00000000</Usercode>
+				<AccessMode>JTAG</AccessMode>
+			</Option>
+		</Device>
+		<Device>
+			<Pos>2</Pos>
+			<Ref>FPGA1</Ref>
+			<Vendor>Lattice</Vendor>
+			<Family>LatticeECP3EA</Family>
+			<Name>LFE3-150EA</Name>
+			<IDCode>0x01015043</IDCode>
+			<Package>672-ball fpBGA</Package>
+			<PON>LFE3-150EA-XXFN672</PON>
+			<Bypass>
+				<InstrLen>8</InstrLen>
+				<InstrVal>11111111</InstrVal>
+				<BScanLen>1</BScanLen>
+				<BScanVal>0</BScanVal>
+			</Bypass>
+			<File>/d/jspc22/trb/cvs/trb3/fpgatest/workdir/trb3_periph.bit</File>
+			<MaskFile>/home/hadaq/.isplever_lin/ispvmsystem/Database/xpga/ecp3/ecp3-150.msk</MaskFile>
+			<FileTime>8/25/2011 14:55:0</FileTime>
+			<Operation>Fast Program</Operation>
+			<Option>
+				<SVFVendor>JTAG STANDARD</SVFVendor>
+				<IOState>HighZ</IOState>
+				<PreloadLength>1326</PreloadLength>
+				<IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
+				<OverideUES value="TRUE"/>
+				<TCKFrequency>1.000000 MHz</TCKFrequency>
+				<SVFProcessor>SVF Processor</SVFProcessor>
+				<Usercode>0x00000000</Usercode>
+				<AccessMode>JTAG</AccessMode>
+			</Option>
+		</Device>
+		<Device>
+			<Pos>3</Pos>
+			<Ref>FPGA2</Ref>
+			<Vendor>Lattice</Vendor>
+			<Family>LatticeECP3EA</Family>
+			<Name>LFE3-150EA</Name>
+			<IDCode>0x01015043</IDCode>
+			<Package>672-ball fpBGA</Package>
+			<PON>LFE3-150EA-XXFN672</PON>
+			<Bypass>
+				<InstrLen>8</InstrLen>
+				<InstrVal>11111111</InstrVal>
+				<BScanLen>1</BScanLen>
+				<BScanVal>0</BScanVal>
+			</Bypass>
+			<File>/d/jspc22/trb/cvs/trb3/fpgatest/workdir/trb3_periph.bit</File>
+			<MaskFile>/home/hadaq/.isplever_lin/ispvmsystem/Database/xpga/ecp3/ecp3-150.msk</MaskFile>
+			<FileTime>8/25/2011 14:55:0</FileTime>
+			<Operation>Fast Program</Operation>
+			<Option>
+				<SVFVendor>JTAG STANDARD</SVFVendor>
+				<IOState>HighZ</IOState>
+				<PreloadLength>1326</PreloadLength>
+				<IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
+				<OverideUES value="TRUE"/>
+				<TCKFrequency>1.000000 MHz</TCKFrequency>
+				<SVFProcessor>SVF Processor</SVFProcessor>
+				<Usercode>0x00000000</Usercode>
+				<AccessMode>JTAG</AccessMode>
+			</Option>
+		</Device>
+		<Device>
+			<Pos>4</Pos>
+			<Vendor>Lattice</Vendor>
+			<Family>LatticeECP3EA</Family>
+			<Name>LFE3-150EA</Name>
+			<IDCode>0x01015043</IDCode>
+			<Package>672-ball fpBGA</Package>
+			<PON>LFE3-150EA-XXFN672</PON>
+			<Bypass>
+				<InstrLen>8</InstrLen>
+				<InstrVal>11111111</InstrVal>
+				<BScanLen>1</BScanLen>
+				<BScanVal>0</BScanVal>
+			</Bypass>
+			<File>/d/jspc22/trb/cvs/trb3/fpgatest/workdir/trb3_periph.bit</File>
+			<MaskFile>/home/hadaq/.isplever_lin/ispvmsystem/Database/xpga/ecp3/ecp3-150.msk</MaskFile>
+			<FileTime>8/25/2011 14:55:0</FileTime>
+			<Operation>Fast Program</Operation>
+			<Option>
+				<SVFVendor>JTAG STANDARD</SVFVendor>
+				<IOState>HighZ</IOState>
+				<PreloadLength>1326</PreloadLength>
+				<IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
+				<OverideUES value="TRUE"/>
+				<TCKFrequency>1.000000 MHz</TCKFrequency>
+				<SVFProcessor>SVF Processor</SVFProcessor>
+				<Usercode>0x00000000</Usercode>
+				<AccessMode>JTAG</AccessMode>
+			</Option>
+		</Device>
+		<Device>
+			<Pos>5</Pos>
+			<Vendor>Lattice</Vendor>
+			<Family>LatticeECP3EA</Family>
+			<Name>LFE3-150EA</Name>
+			<IDCode>0x01015043</IDCode>
+			<Package>672-ball fpBGA</Package>
+			<PON>LFE3-150EA-XXFN672</PON>
+			<Bypass>
+				<InstrLen>8</InstrLen>
+				<InstrVal>11111111</InstrVal>
+				<BScanLen>1</BScanLen>
+				<BScanVal>0</BScanVal>
+			</Bypass>
+			<File>/d/jspc22/trb/cvs/trb3/fpgatest/workdir/trb3_periph.bit</File>
+			<MaskFile>/home/hadaq/.isplever_lin/ispvmsystem/Database/xpga/ecp3/ecp3-150.msk</MaskFile>
+			<FileTime>8/25/2011 14:55:0</FileTime>
+			<Operation>Fast Program</Operation>
+			<Option>
+				<SVFVendor>JTAG STANDARD</SVFVendor>
+				<IOState>HighZ</IOState>
+				<PreloadLength>1326</PreloadLength>
+				<IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
+				<OverideUES value="TRUE"/>
+				<TCKFrequency>1.000000 MHz</TCKFrequency>
+				<SVFProcessor>SVF Processor</SVFProcessor>
+				<Usercode>0x00000000</Usercode>
+				<AccessMode>JTAG</AccessMode>
+			</Option>
+		</Device>
+		<Device>
+			<Pos>6</Pos>
+			<Ref>CM1</Ref>
+			<Vendor>Lattice</Vendor>
+			<Family>ispCLOCK</Family>
+			<Name>ispPAC-CLK5410D</Name>
+			<IDCode>0x00190043</IDCode>
+			<Package>64-pin QFNS</Package>
+			<PON>ispPAC-CLK5410D-XXSN64C</PON>
+			<Bypass>
+				<InstrLen>8</InstrLen>
+				<InstrVal>11111111</InstrVal>
+				<BScanLen>1</BScanLen>
+				<BScanVal>0</BScanVal>
+			</Bypass>
+			<File>/d/jspc22/trb/cvs/trb3/base/clockmanager/CM1.jed</File>
+			<FileTime>8/24/2011 15:39:12</FileTime>
+			<JedecChecksum>0x1C8C</JedecChecksum>
+			<Operation>Erase,Program,Verify</Operation>
+			<Option>
+				<SVFVendor>JTAG STANDARD</SVFVendor>
+				<IOState>HighZ</IOState>
+				<IOVectorData>0x00000000</IOVectorData>
+				<OverideUES value="TRUE"/>
+				<TCKFrequency>1.000000 MHz</TCKFrequency>
+				<SVFProcessor>SVF Processor</SVFProcessor>
+				<Usercode>0xFFFFFFFF</Usercode>
+			</Option>
+		</Device>
+		<Device>
+			<Pos>7</Pos>
+			<Vendor>Lattice</Vendor>
+			<Family>ispCLOCK</Family>
+			<Name>ispPAC-CLK5410D</Name>
+			<IDCode>0x00190043</IDCode>
+			<Package>64-pin QFNS</Package>
+			<PON>ispPAC-CLK5410D-XXSN64C</PON>
+			<Bypass>
+				<InstrLen>8</InstrLen>
+				<InstrVal>11111111</InstrVal>
+				<BScanLen>1</BScanLen>
+				<BScanVal>0</BScanVal>
+			</Bypass>
+			<File>/d/jspc22/trb/cvs/trb3/base/clockmanager/CM2.jed</File>
+			<FileTime>8/24/2011 15:39:12</FileTime>
+			<JedecChecksum>0x18EE</JedecChecksum>
+			<Operation>Erase,Program,Verify</Operation>
+			<Option>
+				<SVFVendor>JTAG STANDARD</SVFVendor>
+				<IOState>HighZ</IOState>
+				<IOVectorData>0x00000000</IOVectorData>
+				<OverideUES value="TRUE"/>
+				<TCKFrequency>1.000000 MHz</TCKFrequency>
+				<SVFProcessor>SVF Processor</SVFProcessor>
+				<Usercode>0xFFFFFFFF</Usercode>
+			</Option>
+		</Device>
+	</Chain>
+	<ProjectOptions>
+		<Program>SEQUENTIAL</Program>
+		<Process>ENTIRED CHAIN</Process>
+		<OperationOverride>No Override</OperationOverride>
+		<StartTAP>TLR</StartTAP>
+		<EndTAP>TLR</EndTAP>
+		<DeGlitch value="TRUE"/>
+		<VerifyUsercode value="TRUE"/>
+		<PinSetting>
+			TMS	LOW;
+			TCK	LOW;
+			TDI	LOW;
+			TDO	LOW;
+			CableEN	HIGH;
+		</PinSetting>
+	</ProjectOptions>
+</ispXCF>
diff --git a/fpgatest/projects/trb3_central.pty b/fpgatest/projects/trb3_central.pty
new file mode 100644
index 0000000..537921f
--- /dev/null
+++ b/fpgatest/projects/trb3_central.pty
@@ -0,0 +1,3 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE strategy>
+<Strategy version="1.0" predefined="0" description="" label=""/>
diff --git a/fpgatest/projects/trb3_periph.ldf b/fpgatest/projects/trb3_periph.ldf
new file mode 100644
index 0000000..768b5a1
--- /dev/null
+++ b/fpgatest/projects/trb3_periph.ldf
@@ -0,0 +1,32 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<BaliProject version="1.3" title="trb3_periph" device="LFE3-150EA-7FN672" default_implementation="trb3_periph">
+    <Options/>
+    <Implementation title="trb3_periph" dir="trb3_periph" description="trb3_periph" default_strategy="Strategy1">
+        <Options/>
+        <Source name="../../base/trb3_periph.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../base/trb3_components.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../base/cores/pll_in200_out100.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../base/cores/pll_in200_out100.lpc" type="LPC_Module" type_short="LPC">
+            <Options/>
+        </Source>
+        <Source name="../../base/cores/pll_in200_out100.ipx" type="IPX_Module" type_short="IPX">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/trb_net_components.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/trb_net_std.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../base/trb3_central.lpf" type="Logic Preference" type_short="LPF">
+            <Options/>
+        </Source>
+    </Implementation>
+    <Strategy name="Strategy1" file="Strategy1.sty"/>
+</BaliProject>
diff --git a/fpgatest/projects/trb3_periph.pty b/fpgatest/projects/trb3_periph.pty
new file mode 100644
index 0000000..537921f
--- /dev/null
+++ b/fpgatest/projects/trb3_periph.pty
@@ -0,0 +1,3 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE strategy>
+<Strategy version="1.0" predefined="0" description="" label=""/>
-- 
2.43.0