From c7ab8a827b3531b64096f72e639b0afb2f334c6f Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Fri, 21 Oct 2022 11:25:23 +0200 Subject: [PATCH] reset changes, better behaviour --- gbe_trb/base/gbe_lsm.vhd | 20 +++++++++----------- gbe_trb/base/inserter.vhd | 2 +- gbe_trb/base/parser.vhd | 10 ++++------ gbe_trb/base/remover.vhd | 2 +- gbe_trb/base/trb_net16_gbe_mac_control.vhd | 12 +++++------- gbe_trb_ecp3/media/gbe_med_fifo.vhd | 4 ++-- media_interfaces/sync/sci_reader_RS.vhd | 2 +- 7 files changed, 23 insertions(+), 29 deletions(-) diff --git a/gbe_trb/base/gbe_lsm.vhd b/gbe_trb/base/gbe_lsm.vhd index 1c9dead..81ab5d5 100644 --- a/gbe_trb/base/gbe_lsm.vhd +++ b/gbe_trb/base/gbe_lsm.vhd @@ -42,10 +42,10 @@ begin THE_DLY_CTR: process( CLK ) begin - if( rising_edge(CLK) ) then - if ( RESET = '1' ) then - dly_ctr <= (others => '0'); - elsif( rst_dly_ctr = '1' ) then + if ( RESET = '1' ) then + dly_ctr <= (others => '0'); + elsif( rising_edge(CLK) ) then + if( rst_dly_ctr = '1' ) then dly_ctr <= (others => '0'); elsif( ce_dly_ctr = '1' ) then dly_ctr <= dly_ctr + 1; @@ -58,14 +58,12 @@ begin ----------------------------------------------------------- -- statemachine: clocked process ----------------------------------------------------------- - THE_FSM: process( CLK ) + THE_FSM: process( CLK, RESET ) begin - if( rising_edge(CLK) ) then - if( RESET = '1' ) then - STATE <= INACTIVE; - else - STATE <= NEXT_STATE; - end if; + if ( RESET = '1' ) then + STATE <= INACTIVE; + elsif( rising_edge(CLK) ) then + STATE <= NEXT_STATE; end if; end process THE_FSM; diff --git a/gbe_trb/base/inserter.vhd b/gbe_trb/base/inserter.vhd index 727afea..c93874d 100644 --- a/gbe_trb/base/inserter.vhd +++ b/gbe_trb/base/inserter.vhd @@ -7,7 +7,7 @@ library work; entity inserter is port( CLK : in std_logic; - CLEAR : in std_logic; + CLEAR : in std_logic; -- not used ACTIVE_IN : in std_logic; -- PHY output PHY_D_IN : in std_logic_vector(7 downto 0); diff --git a/gbe_trb/base/parser.vhd b/gbe_trb/base/parser.vhd index 5f993c5..9767d37 100644 --- a/gbe_trb/base/parser.vhd +++ b/gbe_trb/base/parser.vhd @@ -49,14 +49,12 @@ begin ----------------------------------------------------------- -- statemachine: clocked process ----------------------------------------------------------- - THE_FSM: process( CLK ) + THE_FSM: process( CLK, RESET ) begin - if( rising_edge(CLK) ) then - if( RESET = '1' ) then - STATE <= ST0; - else + if( RESET = '1' ) then + STATE <= ST0; + elsif( rising_edge(CLK) ) then STATE <= NEXT_STATE; - end if; end if; end process THE_FSM; diff --git a/gbe_trb/base/remover.vhd b/gbe_trb/base/remover.vhd index 4c12082..3fc1678 100644 --- a/gbe_trb/base/remover.vhd +++ b/gbe_trb/base/remover.vhd @@ -7,7 +7,7 @@ library work; entity remover is port( CLK : in std_logic; - CLEAR : in std_logic; + CLEAR : in std_logic; -- not used ACTIVE_IN : in std_logic; -- SerDes output RX_D_IN : in std_logic_vector(7 downto 0); diff --git a/gbe_trb/base/trb_net16_gbe_mac_control.vhd b/gbe_trb/base/trb_net16_gbe_mac_control.vhd index 130c151..978387f 100644 --- a/gbe_trb/base/trb_net16_gbe_mac_control.vhd +++ b/gbe_trb/base/trb_net16_gbe_mac_control.vhd @@ -82,14 +82,12 @@ reg_tx_rx_ctrl1(1) <= '1'; -- receive discard FCS and padding reg_tx_rx_ctrl1(0) <= MC_PROMISC_IN; -- promiscuous mode -MAC_CONF_MACHINE_PROC : process(CLK) +MAC_CONF_MACHINE_PROC : process( CLK, RESET ) begin - if( rising_edge(CLK) ) then - if( RESET = '1' ) then - mac_conf_current_state <= IDLE; - else - mac_conf_current_state <= mac_conf_next_state; - end if; + if ( RESET = '1' ) then + mac_conf_current_state <= IDLE; + elsif( rising_edge(CLK) ) then + mac_conf_current_state <= mac_conf_next_state; end if; end process MAC_CONF_MACHINE_PROC; diff --git a/gbe_trb_ecp3/media/gbe_med_fifo.vhd b/gbe_trb_ecp3/media/gbe_med_fifo.vhd index 943104d..2b78765 100644 --- a/gbe_trb_ecp3/media/gbe_med_fifo.vhd +++ b/gbe_trb_ecp3/media/gbe_med_fifo.vhd @@ -694,7 +694,7 @@ begin SGMII_GBE_PCS : sgmii_gbe_pcs42 port map( rst_n => RESET_N, --CLEAR_N, - signal_detect => link_rx_ready(i), --serdes_active(i), + signal_detect => serdes_active(i), --link_rx_ready(i), gbe_mode => '1', sgmii_mode => '0', operational_rate => b"10", @@ -738,7 +738,7 @@ begin mr_page_rx => mr_page_rx_i(i), --open, mr_lp_adv_ability => open, mr_main_reset => RESET, --CLEAR, - mr_an_enable => link_rx_ready(i), --'1', + mr_an_enable => serdes_active(i), --link_rx_ready(i), --'1', mr_restart_an => '0', mr_adv_ability => x"0020" ); diff --git a/media_interfaces/sync/sci_reader_RS.vhd b/media_interfaces/sync/sci_reader_RS.vhd index de4ad43..efce108 100644 --- a/media_interfaces/sync/sci_reader_RS.vhd +++ b/media_interfaces/sync/sci_reader_RS.vhd @@ -12,7 +12,7 @@ entity sci_reader_RS is port( CLK : in std_logic; - RESET : in std_logic; + RESET : in std_logic; -- not used --SCI SCI_WRDATA : out std_logic_vector(7 downto 0); SCI_RDDATA : in std_logic_vector(7 downto 0); -- 2.43.0