From c82de83316469d3d1aefed45b0dfd1ced89e3eb1 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Wed, 7 Mar 2018 13:49:00 +0100 Subject: [PATCH] add input to reset after send_reset ends --- code/clock_reset_handler.vhd | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/code/clock_reset_handler.vhd b/code/clock_reset_handler.vhd index 8068456..d23748b 100644 --- a/code/clock_reset_handler.vhd +++ b/code/clock_reset_handler.vhd @@ -14,7 +14,8 @@ entity clock_reset_handler is EXT_CLK_IN : in std_logic; -- external clock input NET_CLK_FULL_IN : in std_logic; -- recovered clock NET_CLK_HALF_IN : in std_logic; - RESET_FROM_NET : in std_logic; + RESET_FROM_NET : in std_logic := '0'; + SEND_RESET_IN : in std_logic := '0'; BUS_RX : in CTRLBUS_RX; BUS_TX : out CTRLBUS_TX; @@ -51,7 +52,7 @@ signal timer : unsigned(27 downto 0) := (others => '0'); signal clear_n_i : std_logic := '0'; signal reset_i : std_logic; signal debug_reset_handler : std_logic_vector(15 downto 0); - +signal send_reset_detect, trb_reset_i : std_logic := '0'; attribute syn_keep of clear_n_i : signal is true; attribute syn_preserve of clear_n_i : signal is true; @@ -230,14 +231,15 @@ THE_RESET_HANDLER : trb_net_reset_handler SYSCLK_IN => clk_selected_half, -- PLL/DLL remastered clock PLL_LOCKED_IN => pll_int_lock, -- master PLL lock signal (async) RESET_IN => '0', -- general reset signal (SYSCLK) - TRB_RESET_IN => RESET_FROM_NET, -- TRBnet reset signal (SYSCLK) + TRB_RESET_IN => trb_reset_i, -- TRBnet reset signal (SYSCLK) CLEAR_OUT => CLEAR_OUT, -- async reset out, USE WITH CARE! RESET_OUT => reset_i, -- synchronous reset out (SYSCLK) DEBUG_OUT => debug_reset_handler ); RESET_OUT <= reset_i; - +send_reset_detect <= SEND_RESET_IN when rising_edge(INT_CLK_IN); +trb_reset_i <= RESET_FROM_NET or (send_reset_detect and not SEND_RESET_IN); --------------------------------------------------------------------------- -- Slow clock for DCDC converters -- 2.43.0