From c8e2c975518b7c56590a9118c90de2d740abc84c Mon Sep 17 00:00:00 2001 From: Maier Date: Sun, 21 Feb 2016 18:23:22 +0100 Subject: [PATCH] scaler update --- scaler/cores/counter_45bit.vhd | 674 +++++++++++++++++++++++ scaler/cores/fifo_6to6_dc.vhd | 580 +++++++++++++++++++ scaler/cores/pll_clk400.vhd | 99 ++++ scaler/cores/pll_quadruple.vhd | 99 ++++ scaler/cores_raw/counter_45bit.ipx | 9 + scaler/cores_raw/counter_45bit.lpc | 39 ++ scaler/cores_raw/counter_45bit.vhd | 674 +++++++++++++++++++++++ scaler/cores_raw/counter_48bit.ipx | 9 + scaler/cores_raw/counter_48bit.lpc | 39 ++ scaler/cores_raw/counter_48bit.vhd | 585 ++++++++++++++++++++ scaler/cores_raw/fifo_3to3_dc.ipx | 9 + scaler/cores_raw/fifo_3to3_dc.lpc | 50 ++ scaler/cores_raw/fifo_3to3_dc.vhd | 580 +++++++++++++++++++ scaler/cores_raw/fifo_4to4_dc.ipx | 9 + scaler/cores_raw/fifo_4to4_dc.lpc | 50 ++ scaler/cores_raw/fifo_4to4_dc.vhd | 580 +++++++++++++++++++ scaler/cores_raw/fifo_5to5_dc.ipx | 9 + scaler/cores_raw/fifo_5to5_dc.lpc | 50 ++ scaler/cores_raw/fifo_5to5_dc.vhd | 580 +++++++++++++++++++ scaler/cores_raw/fifo_6to6_dc.ipx | 9 + scaler/cores_raw/fifo_6to6_dc.lpc | 50 ++ scaler/cores_raw/fifo_6to6_dc.vhd | 580 +++++++++++++++++++ scaler/cores_raw/fifo_data_48to48_dc.ipx | 9 + scaler/cores_raw/fifo_data_48to48_dc.lpc | 50 ++ scaler/cores_raw/fifo_data_48to48_dc.vhd | 606 ++++++++++++++++++++ scaler/cores_raw/pll_clk400.ipx | 8 + scaler/cores_raw/pll_clk400.lpc | 69 +++ scaler/cores_raw/pll_clk400.vhd | 99 ++++ scaler/cores_raw/pll_clk500.ipx | 8 + scaler/cores_raw/pll_clk500.lpc | 69 +++ scaler/cores_raw/pll_clk500.vhd | 99 ++++ scaler/cores_raw/pll_clk_scaler.ipx | 8 + scaler/cores_raw/pll_clk_scaler.lpc | 69 +++ scaler/cores_raw/pll_clk_scaler.vhd | 102 ++++ scaler/cores_raw/pll_quadruple.ipx | 8 + scaler/cores_raw/pll_quadruple.lpc | 69 +++ scaler/cores_raw/pll_quadruple.vhd | 99 ++++ scaler/source/scaler_channel.vhd | 2 +- 38 files changed, 6736 insertions(+), 1 deletion(-) create mode 100644 scaler/cores/counter_45bit.vhd create mode 100644 scaler/cores/fifo_6to6_dc.vhd create mode 100644 scaler/cores/pll_clk400.vhd create mode 100644 scaler/cores/pll_quadruple.vhd create mode 100644 scaler/cores_raw/counter_45bit.ipx create mode 100644 scaler/cores_raw/counter_45bit.lpc create mode 100644 scaler/cores_raw/counter_45bit.vhd create mode 100644 scaler/cores_raw/counter_48bit.ipx create mode 100644 scaler/cores_raw/counter_48bit.lpc create mode 100644 scaler/cores_raw/counter_48bit.vhd create mode 100644 scaler/cores_raw/fifo_3to3_dc.ipx create mode 100644 scaler/cores_raw/fifo_3to3_dc.lpc create mode 100644 scaler/cores_raw/fifo_3to3_dc.vhd create mode 100644 scaler/cores_raw/fifo_4to4_dc.ipx create mode 100644 scaler/cores_raw/fifo_4to4_dc.lpc create mode 100644 scaler/cores_raw/fifo_4to4_dc.vhd create mode 100644 scaler/cores_raw/fifo_5to5_dc.ipx create mode 100644 scaler/cores_raw/fifo_5to5_dc.lpc create mode 100644 scaler/cores_raw/fifo_5to5_dc.vhd create mode 100644 scaler/cores_raw/fifo_6to6_dc.ipx create mode 100644 scaler/cores_raw/fifo_6to6_dc.lpc create mode 100644 scaler/cores_raw/fifo_6to6_dc.vhd create mode 100644 scaler/cores_raw/fifo_data_48to48_dc.ipx create mode 100644 scaler/cores_raw/fifo_data_48to48_dc.lpc create mode 100644 scaler/cores_raw/fifo_data_48to48_dc.vhd create mode 100644 scaler/cores_raw/pll_clk400.ipx create mode 100644 scaler/cores_raw/pll_clk400.lpc create mode 100644 scaler/cores_raw/pll_clk400.vhd create mode 100644 scaler/cores_raw/pll_clk500.ipx create mode 100644 scaler/cores_raw/pll_clk500.lpc create mode 100644 scaler/cores_raw/pll_clk500.vhd create mode 100644 scaler/cores_raw/pll_clk_scaler.ipx create mode 100644 scaler/cores_raw/pll_clk_scaler.lpc create mode 100644 scaler/cores_raw/pll_clk_scaler.vhd create mode 100644 scaler/cores_raw/pll_quadruple.ipx create mode 100644 scaler/cores_raw/pll_quadruple.lpc create mode 100644 scaler/cores_raw/pll_quadruple.vhd diff --git a/scaler/cores/counter_45bit.vhd b/scaler/cores/counter_45bit.vhd new file mode 100644 index 0000000..96cd92d --- /dev/null +++ b/scaler/cores/counter_45bit.vhd @@ -0,0 +1,674 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80 +-- Module Version: 4.5 +--/usr/local/opt/lattice_diamond/diamond/3.4/ispfpga/bin/lin64/scuba -w -n counter_45bit -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type counter -up -width 45 -group 16 + +-- Mon Jun 8 02:11:09 2015 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity counter_45bit is + port ( + Clock: in std_logic; + Clk_En: in std_logic; + Aclr: in std_logic; + Q: out std_logic_vector(44 downto 0)); +end counter_45bit; + +architecture Structure of counter_45bit is + + -- internal signal declarations + signal tdataout1_inv: std_logic; + signal func_and_inet_3: std_logic; + signal func_and_inet_2: std_logic; + signal func_and_inet_1: std_logic; + signal func_and_inet: std_logic; + signal func_and_inet_7: std_logic; + signal func_and_inet_6: std_logic; + signal func_and_inet_5: std_logic; + signal func_and_inet_4: std_logic; + signal group_cout_pre: std_logic; + signal group_cout0: std_logic; + signal group_cout1: std_logic; + signal group_cout_pre_1: std_logic; + signal group_cin_pre_1: std_logic; + signal scuba_vhi: std_logic; + signal idataout0: std_logic; + signal idataout1: std_logic; + signal cnt_ci: std_logic; + signal tdataout0: std_logic; + signal tdataout1: std_logic; + signal idataout2: std_logic; + signal idataout3: std_logic; + signal co0: std_logic; + signal tdataout2: std_logic; + signal tdataout3: std_logic; + signal idataout4: std_logic; + signal idataout5: std_logic; + signal co1: std_logic; + signal tdataout4: std_logic; + signal tdataout5: std_logic; + signal idataout6: std_logic; + signal idataout7: std_logic; + signal co2: std_logic; + signal tdataout6: std_logic; + signal tdataout7: std_logic; + signal idataout8: std_logic; + signal idataout9: std_logic; + signal co3: std_logic; + signal tdataout8: std_logic; + signal tdataout9: std_logic; + signal idataout10: std_logic; + signal idataout11: std_logic; + signal co4: std_logic; + signal tdataout10: std_logic; + signal tdataout11: std_logic; + signal idataout12: std_logic; + signal idataout13: std_logic; + signal co5: std_logic; + signal tdataout12: std_logic; + signal tdataout13: std_logic; + signal idataout14: std_logic; + signal idataout15: std_logic; + signal co7: std_logic; + signal co6: std_logic; + signal tdataout14: std_logic; + signal tdataout15: std_logic; + signal group_cin0: std_logic; + signal idataout16: std_logic; + signal idataout17: std_logic; + signal cntGrpCinNet_1: std_logic; + signal tdataout16: std_logic; + signal tdataout17: std_logic; + signal idataout18: std_logic; + signal idataout19: std_logic; + signal co8: std_logic; + signal tdataout18: std_logic; + signal tdataout19: std_logic; + signal idataout20: std_logic; + signal idataout21: std_logic; + signal co9: std_logic; + signal tdataout20: std_logic; + signal tdataout21: std_logic; + signal idataout22: std_logic; + signal idataout23: std_logic; + signal co10: std_logic; + signal tdataout22: std_logic; + signal tdataout23: std_logic; + signal idataout24: std_logic; + signal idataout25: std_logic; + signal co11: std_logic; + signal tdataout24: std_logic; + signal tdataout25: std_logic; + signal idataout26: std_logic; + signal idataout27: std_logic; + signal co12: std_logic; + signal tdataout26: std_logic; + signal tdataout27: std_logic; + signal idataout28: std_logic; + signal idataout29: std_logic; + signal co13: std_logic; + signal tdataout28: std_logic; + signal tdataout29: std_logic; + signal idataout30: std_logic; + signal idataout31: std_logic; + signal co15: std_logic; + signal co14: std_logic; + signal tdataout30: std_logic; + signal tdataout31: std_logic; + signal group_cin1: std_logic; + signal idataout32: std_logic; + signal idataout33: std_logic; + signal cntGrpCinNet_2: std_logic; + signal tdataout32: std_logic; + signal tdataout33: std_logic; + signal idataout34: std_logic; + signal idataout35: std_logic; + signal co16: std_logic; + signal tdataout34: std_logic; + signal tdataout35: std_logic; + signal idataout36: std_logic; + signal idataout37: std_logic; + signal co17: std_logic; + signal tdataout36: std_logic; + signal tdataout37: std_logic; + signal idataout38: std_logic; + signal idataout39: std_logic; + signal co18: std_logic; + signal tdataout38: std_logic; + signal tdataout39: std_logic; + signal idataout40: std_logic; + signal idataout41: std_logic; + signal co19: std_logic; + signal tdataout40: std_logic; + signal tdataout41: std_logic; + signal idataout42: std_logic; + signal idataout43: std_logic; + signal co20: std_logic; + signal tdataout42: std_logic; + signal tdataout43: std_logic; + signal idataout44: std_logic; + signal co22: std_logic; + signal co21: std_logic; + signal tdataout44: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + attribute GSR : string; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + INV_0: INV + port map (A=>tdataout1, Z=>tdataout1_inv); + + LUT4_10: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>tdataout0, AD2=>tdataout1_inv, AD1=>tdataout2, + AD0=>tdataout3, DO0=>func_and_inet); + + LUT4_9: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>tdataout4, AD2=>tdataout5, AD1=>tdataout6, + AD0=>tdataout7, DO0=>func_and_inet_1); + + LUT4_8: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>tdataout8, AD2=>tdataout9, AD1=>tdataout10, + AD0=>tdataout11, DO0=>func_and_inet_2); + + LUT4_7: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>tdataout12, AD2=>tdataout13, AD1=>tdataout14, + AD0=>tdataout15, DO0=>func_and_inet_3); + + LUT4_6: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet, AD2=>func_and_inet_1, + AD1=>func_and_inet_2, AD0=>func_and_inet_3, + DO0=>group_cout_pre); + + LUT4_5: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>tdataout16, AD2=>tdataout17, AD1=>tdataout18, + AD0=>tdataout19, DO0=>func_and_inet_4); + + LUT4_4: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>tdataout20, AD2=>tdataout21, AD1=>tdataout22, + AD0=>tdataout23, DO0=>func_and_inet_5); + + LUT4_3: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>tdataout24, AD2=>tdataout25, AD1=>tdataout26, + AD0=>tdataout27, DO0=>func_and_inet_6); + + LUT4_2: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>tdataout28, AD2=>tdataout29, AD1=>tdataout30, + AD0=>tdataout31, DO0=>func_and_inet_7); + + LUT4_1: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_4, AD2=>func_and_inet_5, + AD1=>func_and_inet_6, AD0=>func_and_inet_7, + DO0=>group_cout_pre_1); + + LUT4_0: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>group_cout0, AD2=>group_cout1, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>group_cin_pre_1); + + FF_48: FD1P3DX + port map (D=>idataout0, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout0); + + FF_47: FD1P3DX + port map (D=>idataout1, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout1); + + FF_46: FD1P3DX + port map (D=>idataout2, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout2); + + FF_45: FD1P3DX + port map (D=>idataout3, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout3); + + FF_44: FD1P3DX + port map (D=>idataout4, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout4); + + FF_43: FD1P3DX + port map (D=>idataout5, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout5); + + FF_42: FD1P3DX + port map (D=>idataout6, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout6); + + FF_41: FD1P3DX + port map (D=>idataout7, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout7); + + FF_40: FD1P3DX + port map (D=>idataout8, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout8); + + FF_39: FD1P3DX + port map (D=>idataout9, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout9); + + FF_38: FD1P3DX + port map (D=>idataout10, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout10); + + FF_37: FD1P3DX + port map (D=>idataout11, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout11); + + FF_36: FD1P3DX + port map (D=>idataout12, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout12); + + FF_35: FD1P3DX + port map (D=>idataout13, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout13); + + FF_34: FD1P3DX + port map (D=>idataout14, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout14); + + FF_33: FD1P3DX + port map (D=>idataout15, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout15); + + FF_32: FD1P3DX + port map (D=>idataout16, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout16); + + FF_31: FD1P3DX + port map (D=>idataout17, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout17); + + FF_30: FD1P3DX + port map (D=>idataout18, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout18); + + FF_29: FD1P3DX + port map (D=>idataout19, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout19); + + FF_28: FD1P3DX + port map (D=>idataout20, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout20); + + FF_27: FD1P3DX + port map (D=>idataout21, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout21); + + FF_26: FD1P3DX + port map (D=>idataout22, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout22); + + FF_25: FD1P3DX + port map (D=>idataout23, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout23); + + FF_24: FD1P3DX + port map (D=>idataout24, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout24); + + FF_23: FD1P3DX + port map (D=>idataout25, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout25); + + FF_22: FD1P3DX + port map (D=>idataout26, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout26); + + FF_21: FD1P3DX + port map (D=>idataout27, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout27); + + FF_20: FD1P3DX + port map (D=>idataout28, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout28); + + FF_19: FD1P3DX + port map (D=>idataout29, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout29); + + FF_18: FD1P3DX + port map (D=>idataout30, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout30); + + FF_17: FD1P3DX + port map (D=>idataout31, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout31); + + FF_16: FD1P3DX + port map (D=>idataout32, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout32); + + FF_15: FD1P3DX + port map (D=>idataout33, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout33); + + FF_14: FD1P3DX + port map (D=>idataout34, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout34); + + FF_13: FD1P3DX + port map (D=>idataout35, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout35); + + FF_12: FD1P3DX + port map (D=>idataout36, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout36); + + FF_11: FD1P3DX + port map (D=>idataout37, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout37); + + FF_10: FD1P3DX + port map (D=>idataout38, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout38); + + FF_9: FD1P3DX + port map (D=>idataout39, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout39); + + FF_8: FD1P3DX + port map (D=>idataout40, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout40); + + FF_7: FD1P3DX + port map (D=>idataout41, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout41); + + FF_6: FD1P3DX + port map (D=>idataout42, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout42); + + FF_5: FD1P3DX + port map (D=>idataout43, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout43); + + FF_4: FD1P3DX + port map (D=>idataout44, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout44); + + FF_3: FD1P3DX + port map (D=>group_cout_pre, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>group_cout0); + + FF_2: FD1P3DX + port map (D=>group_cout0, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>group_cin0); + + FF_1: FD1P3DX + port map (D=>group_cout_pre_1, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>group_cout1); + + FF_0: FD1P3DX + port map (D=>group_cin_pre_1, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>group_cin1); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + cnt_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cnt_ci, S0=>open, + S1=>open); + + cnt_0: CU2 + port map (CI=>cnt_ci, PC0=>tdataout0, PC1=>tdataout1, CO=>co0, + NC0=>idataout0, NC1=>idataout1); + + cnt_1: CU2 + port map (CI=>co0, PC0=>tdataout2, PC1=>tdataout3, CO=>co1, + NC0=>idataout2, NC1=>idataout3); + + cnt_2: CU2 + port map (CI=>co1, PC0=>tdataout4, PC1=>tdataout5, CO=>co2, + NC0=>idataout4, NC1=>idataout5); + + cnt_3: CU2 + port map (CI=>co2, PC0=>tdataout6, PC1=>tdataout7, CO=>co3, + NC0=>idataout6, NC1=>idataout7); + + cnt_4: CU2 + port map (CI=>co3, PC0=>tdataout8, PC1=>tdataout9, CO=>co4, + NC0=>idataout8, NC1=>idataout9); + + cnt_5: CU2 + port map (CI=>co4, PC0=>tdataout10, PC1=>tdataout11, CO=>co5, + NC0=>idataout10, NC1=>idataout11); + + cnt_6: CU2 + port map (CI=>co5, PC0=>tdataout12, PC1=>tdataout13, CO=>co6, + NC0=>idataout12, NC1=>idataout13); + + cnt_7: CU2 + port map (CI=>co6, PC0=>tdataout14, PC1=>tdataout15, CO=>co7, + NC0=>idataout14, NC1=>idataout15); + + cntGrpCinInst_1: FADD2B + port map (A0=>scuba_vlo, A1=>group_cin0, B0=>scuba_vlo, + B1=>group_cin0, CI=>scuba_vlo, COUT=>cntGrpCinNet_1, + S0=>open, S1=>open); + + cnt_8: CU2 + port map (CI=>cntGrpCinNet_1, PC0=>tdataout16, PC1=>tdataout17, + CO=>co8, NC0=>idataout16, NC1=>idataout17); + + cnt_9: CU2 + port map (CI=>co8, PC0=>tdataout18, PC1=>tdataout19, CO=>co9, + NC0=>idataout18, NC1=>idataout19); + + cnt_10: CU2 + port map (CI=>co9, PC0=>tdataout20, PC1=>tdataout21, CO=>co10, + NC0=>idataout20, NC1=>idataout21); + + cnt_11: CU2 + port map (CI=>co10, PC0=>tdataout22, PC1=>tdataout23, CO=>co11, + NC0=>idataout22, NC1=>idataout23); + + cnt_12: CU2 + port map (CI=>co11, PC0=>tdataout24, PC1=>tdataout25, CO=>co12, + NC0=>idataout24, NC1=>idataout25); + + cnt_13: CU2 + port map (CI=>co12, PC0=>tdataout26, PC1=>tdataout27, CO=>co13, + NC0=>idataout26, NC1=>idataout27); + + cnt_14: CU2 + port map (CI=>co13, PC0=>tdataout28, PC1=>tdataout29, CO=>co14, + NC0=>idataout28, NC1=>idataout29); + + cnt_15: CU2 + port map (CI=>co14, PC0=>tdataout30, PC1=>tdataout31, CO=>co15, + NC0=>idataout30, NC1=>idataout31); + + cntGrpCinInst_2: FADD2B + port map (A0=>scuba_vlo, A1=>group_cin1, B0=>scuba_vlo, + B1=>group_cin1, CI=>scuba_vlo, COUT=>cntGrpCinNet_2, + S0=>open, S1=>open); + + cnt_16: CU2 + port map (CI=>cntGrpCinNet_2, PC0=>tdataout32, PC1=>tdataout33, + CO=>co16, NC0=>idataout32, NC1=>idataout33); + + cnt_17: CU2 + port map (CI=>co16, PC0=>tdataout34, PC1=>tdataout35, CO=>co17, + NC0=>idataout34, NC1=>idataout35); + + cnt_18: CU2 + port map (CI=>co17, PC0=>tdataout36, PC1=>tdataout37, CO=>co18, + NC0=>idataout36, NC1=>idataout37); + + cnt_19: CU2 + port map (CI=>co18, PC0=>tdataout38, PC1=>tdataout39, CO=>co19, + NC0=>idataout38, NC1=>idataout39); + + cnt_20: CU2 + port map (CI=>co19, PC0=>tdataout40, PC1=>tdataout41, CO=>co20, + NC0=>idataout40, NC1=>idataout41); + + cnt_21: CU2 + port map (CI=>co20, PC0=>tdataout42, PC1=>tdataout43, CO=>co21, + NC0=>idataout42, NC1=>idataout43); + + cnt_22: CU2 + port map (CI=>co21, PC0=>tdataout44, PC1=>scuba_vlo, CO=>co22, + NC0=>idataout44, NC1=>open); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + Q(0) <= tdataout0; + Q(1) <= tdataout1; + Q(2) <= tdataout2; + Q(3) <= tdataout3; + Q(4) <= tdataout4; + Q(5) <= tdataout5; + Q(6) <= tdataout6; + Q(7) <= tdataout7; + Q(8) <= tdataout8; + Q(9) <= tdataout9; + Q(10) <= tdataout10; + Q(11) <= tdataout11; + Q(12) <= tdataout12; + Q(13) <= tdataout13; + Q(14) <= tdataout14; + Q(15) <= tdataout15; + Q(16) <= tdataout16; + Q(17) <= tdataout17; + Q(18) <= tdataout18; + Q(19) <= tdataout19; + Q(20) <= tdataout20; + Q(21) <= tdataout21; + Q(22) <= tdataout22; + Q(23) <= tdataout23; + Q(24) <= tdataout24; + Q(25) <= tdataout25; + Q(26) <= tdataout26; + Q(27) <= tdataout27; + Q(28) <= tdataout28; + Q(29) <= tdataout29; + Q(30) <= tdataout30; + Q(31) <= tdataout31; + Q(32) <= tdataout32; + Q(33) <= tdataout33; + Q(34) <= tdataout34; + Q(35) <= tdataout35; + Q(36) <= tdataout36; + Q(37) <= tdataout37; + Q(38) <= tdataout38; + Q(39) <= tdataout39; + Q(40) <= tdataout40; + Q(41) <= tdataout41; + Q(42) <= tdataout42; + Q(43) <= tdataout43; + Q(44) <= tdataout44; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of counter_45bit is + for Structure + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/scaler/cores/fifo_6to6_dc.vhd b/scaler/cores/fifo_6to6_dc.vhd new file mode 100644 index 0000000..5bb8402 --- /dev/null +++ b/scaler/cores/fifo_6to6_dc.vhd @@ -0,0 +1,580 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80 +-- Module Version: 5.7 +--/usr/local/opt/lattice_diamond/diamond/3.4/ispfpga/bin/lin64/scuba -w -n fifo_6to6_dc -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 4 -width 6 -depth 4 -rdata_width 6 -regout -no_enable -pe -1 -pf -1 + +-- Mon Jun 15 23:21:51 2015 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity fifo_6to6_dc is + port ( + Data: in std_logic_vector(5 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(5 downto 0); + Empty: out std_logic; + Full: out std_logic); +end fifo_6to6_dc; + +architecture Structure of fifo_6to6_dc is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal co1: std_logic; + signal co0: std_logic; + signal wcount_2: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal co1_1: std_logic; + signal co0_1: std_logic; + signal rcount_2: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal wcount_r1: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal empty_cmp_clr: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w0: std_logic; + signal rcount_w1: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal full_cmp_clr: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component DP16KC + generic (GSR : in String; WRITEMODE_B : in String; + WRITEMODE_A : in String; CSDECODE_B : in String; + CSDECODE_A : in String; REGMODE_B : in String; + REGMODE_A : in String; DATA_WIDTH_B : in Integer; + DATA_WIDTH_A : in Integer); + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; + WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; + WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_6to6_dc.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; + attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t6: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t5: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t4: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t3: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t2: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t1: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t0: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + LUT4_7: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r1); + + LUT4_6: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>scuba_vlo, DO0=>wcount_r0); + + LUT4_5: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w1); + + LUT4_4: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, + AD1=>r_gcount_w22, AD0=>scuba_vlo, DO0=>rcount_w0); + + LUT4_3: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_2, AD2=>rcount_2, AD1=>w_gcount_r22, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_2, AD2=>rcount_2, AD1=>w_gcount_r22, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_2, AD2=>wcount_2, AD1=>r_gcount_w22, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_2, AD2=>wcount_2, AD1=>r_gcount_w22, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + pdp_ram_0_0_0: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>scuba_vlo, + DIA7=>scuba_vlo, DIA8=>scuba_vlo, DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>scuba_vlo, ADA6=>scuba_vlo, ADA7=>scuba_vlo, + ADA8=>scuba_vlo, ADA9=>scuba_vlo, ADA10=>scuba_vlo, + ADA11=>scuba_vlo, ADA12=>scuba_vlo, ADA13=>scuba_vlo, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>scuba_vlo, + ADB6=>scuba_vlo, ADB7=>scuba_vlo, ADB8=>scuba_vlo, + ADB9=>scuba_vlo, ADB10=>scuba_vlo, ADB11=>scuba_vlo, + ADB12=>scuba_vlo, ADB13=>scuba_vlo, CEB=>rden_i, + CLKB=>RdClock, OCEB=>scuba_vhi, WEB=>scuba_vlo, + CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>Q(0), DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), + DOB4=>Q(4), DOB5=>Q(5), DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + FF_31: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_30: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_29: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_28: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_27: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_26: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_25: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_24: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_23: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_22: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_21: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_20: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_19: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_18: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_17: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_16: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_15: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_14: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_13: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_12: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_11: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_10: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_9: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_8: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_7: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_6: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_5: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_4: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_3: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_2: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_1: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_0: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>scuba_vlo, CO=>co1, + NC0=>iwcount_2, NC1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>scuba_vlo, CO=>co1_1, + NC0=>ircount_2, NC1=>open); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); + + empty_cmp_1: AGEB2 + port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, + B1=>scuba_vlo, CI=>co0_2, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); + + full_cmp_1: AGEB2 + port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, + B1=>scuba_vlo, CI=>co0_3, GE=>full_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of fifo_6to6_dc is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:OR2 use entity ecp3.OR2(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:DP16KC use entity ecp3.DP16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/scaler/cores/pll_clk400.vhd b/scaler/cores/pll_clk400.vhd new file mode 100644 index 0000000..19bb577 --- /dev/null +++ b/scaler/cores/pll_clk400.vhd @@ -0,0 +1,99 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.2.0.134 +-- Module Version: 5.6 +--/usr/local/opt/lattice_diamond/diamond/3.2/ispfpga/bin/lin64/scuba -w -n pll_clk400 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 400 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -use_rst -noclkok2 -bw + +-- Fri Jun 5 16:41:32 2015 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity pll_clk400 is + port ( + CLK: in std_logic; + RESET: in std_logic; + CLKOP: out std_logic; + LOCK: out std_logic); + attribute dont_touch : boolean; + attribute dont_touch of pll_clk400 : entity is true; +end pll_clk400; + +architecture Structure of pll_clk400 is + + -- internal signal declarations + signal CLKOP_t: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component EHXPLLF + generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String; + DELAY_PWD : in String; DELAY_VAL : in Integer; + CLKOS_TRIM_DELAY : in Integer; + CLKOS_TRIM_POL : in String; + CLKOP_TRIM_DELAY : in Integer; + CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String; + CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; + PHASE_DELAY_CNTL : in String; DUTY : in Integer; + PHASEADJ : in String; CLKOK_DIV : in Integer; + CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; + CLKI_DIV : in Integer; FIN : in String); + port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; + RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic; + DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; + DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; + DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic; + FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic; + CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic; + LOCK: out std_logic; CLKINTFB: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + attribute FREQUENCY_PIN_CLKOP : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "400.000000"; + attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000"; + attribute syn_keep : boolean; + attribute syn_noprune : boolean; + attribute syn_noprune of Structure : architecture is true; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLInst_0: EHXPLLF + generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED", + CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED", + CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=> 0, + CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING", + CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING", + PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0", + CLKOK_DIV=> 2, CLKOP_DIV=> 2, CLKFB_DIV=> 2, CLKI_DIV=> 1, + FIN=> "200.000000") + port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>RESET, RSTK=>scuba_vlo, + WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, DRPAI2=>scuba_vlo, + DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, DFPAI3=>scuba_vlo, + DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, DFPAI0=>scuba_vlo, + FDA3=>scuba_vlo, FDA2=>scuba_vlo, FDA1=>scuba_vlo, + FDA0=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>open, CLKOK=>open, + CLKOK2=>open, LOCK=>LOCK, CLKINTFB=>open); + + CLKOP <= CLKOP_t; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of pll_clk400 is + for Structure + for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/scaler/cores/pll_quadruple.vhd b/scaler/cores/pll_quadruple.vhd new file mode 100644 index 0000000..83ebbaf --- /dev/null +++ b/scaler/cores/pll_quadruple.vhd @@ -0,0 +1,99 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80 +-- Module Version: 5.7 +--/usr/local/opt/lattice_diamond/diamond/3.4/ispfpga/bin/lin64/scuba -w -n pll_quadruple -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 25 -phase_cntl STATIC -mdiv 1 -ndiv 4 -vdiv 8 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw + +-- Wed Aug 12 16:45:01 2015 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity pll_quadruple is + port ( + CLK: in std_logic; + CLKOP: out std_logic; + LOCK: out std_logic); + attribute dont_touch : boolean; + attribute dont_touch of pll_quadruple : entity is true; +end pll_quadruple; + +architecture Structure of pll_quadruple is + + -- internal signal declarations + signal CLKOP_t: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component EHXPLLF + generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String; + DELAY_PWD : in String; DELAY_VAL : in Integer; + CLKOS_TRIM_DELAY : in Integer; + CLKOS_TRIM_POL : in String; + CLKOP_TRIM_DELAY : in Integer; + CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String; + CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; + PHASE_DELAY_CNTL : in String; DUTY : in Integer; + PHASEADJ : in String; CLKOK_DIV : in Integer; + CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; + CLKI_DIV : in Integer; FIN : in String); + port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; + RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic; + DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; + DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; + DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic; + FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic; + CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic; + LOCK: out std_logic; CLKINTFB: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + attribute FREQUENCY_PIN_CLKOP : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "100.000000"; + attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "25.000000"; + attribute syn_keep : boolean; + attribute syn_noprune : boolean; + attribute syn_noprune of Structure : architecture is true; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLInst_0: EHXPLLF + generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED", + CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED", + CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=> 0, + CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING", + CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING", + PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0", + CLKOK_DIV=> 2, CLKOP_DIV=> 8, CLKFB_DIV=> 4, CLKI_DIV=> 1, + FIN=> "25.000000") + port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo, + RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, + DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, + DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, + DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo, + FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t, + CLKOS=>open, CLKOK=>open, CLKOK2=>open, LOCK=>LOCK, + CLKINTFB=>open); + + CLKOP <= CLKOP_t; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of pll_quadruple is + for Structure + for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/scaler/cores_raw/counter_45bit.ipx b/scaler/cores_raw/counter_45bit.ipx new file mode 100644 index 0000000..2770849 --- /dev/null +++ b/scaler/cores_raw/counter_45bit.ipx @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/scaler/cores_raw/counter_45bit.lpc b/scaler/cores_raw/counter_45bit.lpc new file mode 100644 index 0000000..69e9b30 --- /dev/null +++ b/scaler/cores_raw/counter_45bit.lpc @@ -0,0 +1,39 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN672C +SpeedGrade=8 +Package=FPBGA672 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=Counter +CoreRevision=4.5 +ModuleName=counter_45bit +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=06/08/2015 +Time=02:11:09 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +InputWidth=45 +CountType=Synchronous +CountDirection=Up +OptimizeSpeed=1 +Lower=0 +Upper=255 +Load=0 + +[Command] +cmd_line= -w -n counter_45bit -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type mgcounter -width 45 -cnt_direction up -aclear -clken -group 16 diff --git a/scaler/cores_raw/counter_45bit.vhd b/scaler/cores_raw/counter_45bit.vhd new file mode 100644 index 0000000..96cd92d --- /dev/null +++ b/scaler/cores_raw/counter_45bit.vhd @@ -0,0 +1,674 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80 +-- Module Version: 4.5 +--/usr/local/opt/lattice_diamond/diamond/3.4/ispfpga/bin/lin64/scuba -w -n counter_45bit -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type counter -up -width 45 -group 16 + +-- Mon Jun 8 02:11:09 2015 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity counter_45bit is + port ( + Clock: in std_logic; + Clk_En: in std_logic; + Aclr: in std_logic; + Q: out std_logic_vector(44 downto 0)); +end counter_45bit; + +architecture Structure of counter_45bit is + + -- internal signal declarations + signal tdataout1_inv: std_logic; + signal func_and_inet_3: std_logic; + signal func_and_inet_2: std_logic; + signal func_and_inet_1: std_logic; + signal func_and_inet: std_logic; + signal func_and_inet_7: std_logic; + signal func_and_inet_6: std_logic; + signal func_and_inet_5: std_logic; + signal func_and_inet_4: std_logic; + signal group_cout_pre: std_logic; + signal group_cout0: std_logic; + signal group_cout1: std_logic; + signal group_cout_pre_1: std_logic; + signal group_cin_pre_1: std_logic; + signal scuba_vhi: std_logic; + signal idataout0: std_logic; + signal idataout1: std_logic; + signal cnt_ci: std_logic; + signal tdataout0: std_logic; + signal tdataout1: std_logic; + signal idataout2: std_logic; + signal idataout3: std_logic; + signal co0: std_logic; + signal tdataout2: std_logic; + signal tdataout3: std_logic; + signal idataout4: std_logic; + signal idataout5: std_logic; + signal co1: std_logic; + signal tdataout4: std_logic; + signal tdataout5: std_logic; + signal idataout6: std_logic; + signal idataout7: std_logic; + signal co2: std_logic; + signal tdataout6: std_logic; + signal tdataout7: std_logic; + signal idataout8: std_logic; + signal idataout9: std_logic; + signal co3: std_logic; + signal tdataout8: std_logic; + signal tdataout9: std_logic; + signal idataout10: std_logic; + signal idataout11: std_logic; + signal co4: std_logic; + signal tdataout10: std_logic; + signal tdataout11: std_logic; + signal idataout12: std_logic; + signal idataout13: std_logic; + signal co5: std_logic; + signal tdataout12: std_logic; + signal tdataout13: std_logic; + signal idataout14: std_logic; + signal idataout15: std_logic; + signal co7: std_logic; + signal co6: std_logic; + signal tdataout14: std_logic; + signal tdataout15: std_logic; + signal group_cin0: std_logic; + signal idataout16: std_logic; + signal idataout17: std_logic; + signal cntGrpCinNet_1: std_logic; + signal tdataout16: std_logic; + signal tdataout17: std_logic; + signal idataout18: std_logic; + signal idataout19: std_logic; + signal co8: std_logic; + signal tdataout18: std_logic; + signal tdataout19: std_logic; + signal idataout20: std_logic; + signal idataout21: std_logic; + signal co9: std_logic; + signal tdataout20: std_logic; + signal tdataout21: std_logic; + signal idataout22: std_logic; + signal idataout23: std_logic; + signal co10: std_logic; + signal tdataout22: std_logic; + signal tdataout23: std_logic; + signal idataout24: std_logic; + signal idataout25: std_logic; + signal co11: std_logic; + signal tdataout24: std_logic; + signal tdataout25: std_logic; + signal idataout26: std_logic; + signal idataout27: std_logic; + signal co12: std_logic; + signal tdataout26: std_logic; + signal tdataout27: std_logic; + signal idataout28: std_logic; + signal idataout29: std_logic; + signal co13: std_logic; + signal tdataout28: std_logic; + signal tdataout29: std_logic; + signal idataout30: std_logic; + signal idataout31: std_logic; + signal co15: std_logic; + signal co14: std_logic; + signal tdataout30: std_logic; + signal tdataout31: std_logic; + signal group_cin1: std_logic; + signal idataout32: std_logic; + signal idataout33: std_logic; + signal cntGrpCinNet_2: std_logic; + signal tdataout32: std_logic; + signal tdataout33: std_logic; + signal idataout34: std_logic; + signal idataout35: std_logic; + signal co16: std_logic; + signal tdataout34: std_logic; + signal tdataout35: std_logic; + signal idataout36: std_logic; + signal idataout37: std_logic; + signal co17: std_logic; + signal tdataout36: std_logic; + signal tdataout37: std_logic; + signal idataout38: std_logic; + signal idataout39: std_logic; + signal co18: std_logic; + signal tdataout38: std_logic; + signal tdataout39: std_logic; + signal idataout40: std_logic; + signal idataout41: std_logic; + signal co19: std_logic; + signal tdataout40: std_logic; + signal tdataout41: std_logic; + signal idataout42: std_logic; + signal idataout43: std_logic; + signal co20: std_logic; + signal tdataout42: std_logic; + signal tdataout43: std_logic; + signal idataout44: std_logic; + signal co22: std_logic; + signal co21: std_logic; + signal tdataout44: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + attribute GSR : string; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + INV_0: INV + port map (A=>tdataout1, Z=>tdataout1_inv); + + LUT4_10: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>tdataout0, AD2=>tdataout1_inv, AD1=>tdataout2, + AD0=>tdataout3, DO0=>func_and_inet); + + LUT4_9: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>tdataout4, AD2=>tdataout5, AD1=>tdataout6, + AD0=>tdataout7, DO0=>func_and_inet_1); + + LUT4_8: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>tdataout8, AD2=>tdataout9, AD1=>tdataout10, + AD0=>tdataout11, DO0=>func_and_inet_2); + + LUT4_7: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>tdataout12, AD2=>tdataout13, AD1=>tdataout14, + AD0=>tdataout15, DO0=>func_and_inet_3); + + LUT4_6: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet, AD2=>func_and_inet_1, + AD1=>func_and_inet_2, AD0=>func_and_inet_3, + DO0=>group_cout_pre); + + LUT4_5: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>tdataout16, AD2=>tdataout17, AD1=>tdataout18, + AD0=>tdataout19, DO0=>func_and_inet_4); + + LUT4_4: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>tdataout20, AD2=>tdataout21, AD1=>tdataout22, + AD0=>tdataout23, DO0=>func_and_inet_5); + + LUT4_3: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>tdataout24, AD2=>tdataout25, AD1=>tdataout26, + AD0=>tdataout27, DO0=>func_and_inet_6); + + LUT4_2: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>tdataout28, AD2=>tdataout29, AD1=>tdataout30, + AD0=>tdataout31, DO0=>func_and_inet_7); + + LUT4_1: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_4, AD2=>func_and_inet_5, + AD1=>func_and_inet_6, AD0=>func_and_inet_7, + DO0=>group_cout_pre_1); + + LUT4_0: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>group_cout0, AD2=>group_cout1, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>group_cin_pre_1); + + FF_48: FD1P3DX + port map (D=>idataout0, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout0); + + FF_47: FD1P3DX + port map (D=>idataout1, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout1); + + FF_46: FD1P3DX + port map (D=>idataout2, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout2); + + FF_45: FD1P3DX + port map (D=>idataout3, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout3); + + FF_44: FD1P3DX + port map (D=>idataout4, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout4); + + FF_43: FD1P3DX + port map (D=>idataout5, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout5); + + FF_42: FD1P3DX + port map (D=>idataout6, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout6); + + FF_41: FD1P3DX + port map (D=>idataout7, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout7); + + FF_40: FD1P3DX + port map (D=>idataout8, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout8); + + FF_39: FD1P3DX + port map (D=>idataout9, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout9); + + FF_38: FD1P3DX + port map (D=>idataout10, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout10); + + FF_37: FD1P3DX + port map (D=>idataout11, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout11); + + FF_36: FD1P3DX + port map (D=>idataout12, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout12); + + FF_35: FD1P3DX + port map (D=>idataout13, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout13); + + FF_34: FD1P3DX + port map (D=>idataout14, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout14); + + FF_33: FD1P3DX + port map (D=>idataout15, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout15); + + FF_32: FD1P3DX + port map (D=>idataout16, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout16); + + FF_31: FD1P3DX + port map (D=>idataout17, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout17); + + FF_30: FD1P3DX + port map (D=>idataout18, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout18); + + FF_29: FD1P3DX + port map (D=>idataout19, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout19); + + FF_28: FD1P3DX + port map (D=>idataout20, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout20); + + FF_27: FD1P3DX + port map (D=>idataout21, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout21); + + FF_26: FD1P3DX + port map (D=>idataout22, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout22); + + FF_25: FD1P3DX + port map (D=>idataout23, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout23); + + FF_24: FD1P3DX + port map (D=>idataout24, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout24); + + FF_23: FD1P3DX + port map (D=>idataout25, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout25); + + FF_22: FD1P3DX + port map (D=>idataout26, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout26); + + FF_21: FD1P3DX + port map (D=>idataout27, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout27); + + FF_20: FD1P3DX + port map (D=>idataout28, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout28); + + FF_19: FD1P3DX + port map (D=>idataout29, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout29); + + FF_18: FD1P3DX + port map (D=>idataout30, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout30); + + FF_17: FD1P3DX + port map (D=>idataout31, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout31); + + FF_16: FD1P3DX + port map (D=>idataout32, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout32); + + FF_15: FD1P3DX + port map (D=>idataout33, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout33); + + FF_14: FD1P3DX + port map (D=>idataout34, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout34); + + FF_13: FD1P3DX + port map (D=>idataout35, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout35); + + FF_12: FD1P3DX + port map (D=>idataout36, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout36); + + FF_11: FD1P3DX + port map (D=>idataout37, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout37); + + FF_10: FD1P3DX + port map (D=>idataout38, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout38); + + FF_9: FD1P3DX + port map (D=>idataout39, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout39); + + FF_8: FD1P3DX + port map (D=>idataout40, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout40); + + FF_7: FD1P3DX + port map (D=>idataout41, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout41); + + FF_6: FD1P3DX + port map (D=>idataout42, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout42); + + FF_5: FD1P3DX + port map (D=>idataout43, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout43); + + FF_4: FD1P3DX + port map (D=>idataout44, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout44); + + FF_3: FD1P3DX + port map (D=>group_cout_pre, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>group_cout0); + + FF_2: FD1P3DX + port map (D=>group_cout0, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>group_cin0); + + FF_1: FD1P3DX + port map (D=>group_cout_pre_1, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>group_cout1); + + FF_0: FD1P3DX + port map (D=>group_cin_pre_1, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>group_cin1); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + cnt_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cnt_ci, S0=>open, + S1=>open); + + cnt_0: CU2 + port map (CI=>cnt_ci, PC0=>tdataout0, PC1=>tdataout1, CO=>co0, + NC0=>idataout0, NC1=>idataout1); + + cnt_1: CU2 + port map (CI=>co0, PC0=>tdataout2, PC1=>tdataout3, CO=>co1, + NC0=>idataout2, NC1=>idataout3); + + cnt_2: CU2 + port map (CI=>co1, PC0=>tdataout4, PC1=>tdataout5, CO=>co2, + NC0=>idataout4, NC1=>idataout5); + + cnt_3: CU2 + port map (CI=>co2, PC0=>tdataout6, PC1=>tdataout7, CO=>co3, + NC0=>idataout6, NC1=>idataout7); + + cnt_4: CU2 + port map (CI=>co3, PC0=>tdataout8, PC1=>tdataout9, CO=>co4, + NC0=>idataout8, NC1=>idataout9); + + cnt_5: CU2 + port map (CI=>co4, PC0=>tdataout10, PC1=>tdataout11, CO=>co5, + NC0=>idataout10, NC1=>idataout11); + + cnt_6: CU2 + port map (CI=>co5, PC0=>tdataout12, PC1=>tdataout13, CO=>co6, + NC0=>idataout12, NC1=>idataout13); + + cnt_7: CU2 + port map (CI=>co6, PC0=>tdataout14, PC1=>tdataout15, CO=>co7, + NC0=>idataout14, NC1=>idataout15); + + cntGrpCinInst_1: FADD2B + port map (A0=>scuba_vlo, A1=>group_cin0, B0=>scuba_vlo, + B1=>group_cin0, CI=>scuba_vlo, COUT=>cntGrpCinNet_1, + S0=>open, S1=>open); + + cnt_8: CU2 + port map (CI=>cntGrpCinNet_1, PC0=>tdataout16, PC1=>tdataout17, + CO=>co8, NC0=>idataout16, NC1=>idataout17); + + cnt_9: CU2 + port map (CI=>co8, PC0=>tdataout18, PC1=>tdataout19, CO=>co9, + NC0=>idataout18, NC1=>idataout19); + + cnt_10: CU2 + port map (CI=>co9, PC0=>tdataout20, PC1=>tdataout21, CO=>co10, + NC0=>idataout20, NC1=>idataout21); + + cnt_11: CU2 + port map (CI=>co10, PC0=>tdataout22, PC1=>tdataout23, CO=>co11, + NC0=>idataout22, NC1=>idataout23); + + cnt_12: CU2 + port map (CI=>co11, PC0=>tdataout24, PC1=>tdataout25, CO=>co12, + NC0=>idataout24, NC1=>idataout25); + + cnt_13: CU2 + port map (CI=>co12, PC0=>tdataout26, PC1=>tdataout27, CO=>co13, + NC0=>idataout26, NC1=>idataout27); + + cnt_14: CU2 + port map (CI=>co13, PC0=>tdataout28, PC1=>tdataout29, CO=>co14, + NC0=>idataout28, NC1=>idataout29); + + cnt_15: CU2 + port map (CI=>co14, PC0=>tdataout30, PC1=>tdataout31, CO=>co15, + NC0=>idataout30, NC1=>idataout31); + + cntGrpCinInst_2: FADD2B + port map (A0=>scuba_vlo, A1=>group_cin1, B0=>scuba_vlo, + B1=>group_cin1, CI=>scuba_vlo, COUT=>cntGrpCinNet_2, + S0=>open, S1=>open); + + cnt_16: CU2 + port map (CI=>cntGrpCinNet_2, PC0=>tdataout32, PC1=>tdataout33, + CO=>co16, NC0=>idataout32, NC1=>idataout33); + + cnt_17: CU2 + port map (CI=>co16, PC0=>tdataout34, PC1=>tdataout35, CO=>co17, + NC0=>idataout34, NC1=>idataout35); + + cnt_18: CU2 + port map (CI=>co17, PC0=>tdataout36, PC1=>tdataout37, CO=>co18, + NC0=>idataout36, NC1=>idataout37); + + cnt_19: CU2 + port map (CI=>co18, PC0=>tdataout38, PC1=>tdataout39, CO=>co19, + NC0=>idataout38, NC1=>idataout39); + + cnt_20: CU2 + port map (CI=>co19, PC0=>tdataout40, PC1=>tdataout41, CO=>co20, + NC0=>idataout40, NC1=>idataout41); + + cnt_21: CU2 + port map (CI=>co20, PC0=>tdataout42, PC1=>tdataout43, CO=>co21, + NC0=>idataout42, NC1=>idataout43); + + cnt_22: CU2 + port map (CI=>co21, PC0=>tdataout44, PC1=>scuba_vlo, CO=>co22, + NC0=>idataout44, NC1=>open); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + Q(0) <= tdataout0; + Q(1) <= tdataout1; + Q(2) <= tdataout2; + Q(3) <= tdataout3; + Q(4) <= tdataout4; + Q(5) <= tdataout5; + Q(6) <= tdataout6; + Q(7) <= tdataout7; + Q(8) <= tdataout8; + Q(9) <= tdataout9; + Q(10) <= tdataout10; + Q(11) <= tdataout11; + Q(12) <= tdataout12; + Q(13) <= tdataout13; + Q(14) <= tdataout14; + Q(15) <= tdataout15; + Q(16) <= tdataout16; + Q(17) <= tdataout17; + Q(18) <= tdataout18; + Q(19) <= tdataout19; + Q(20) <= tdataout20; + Q(21) <= tdataout21; + Q(22) <= tdataout22; + Q(23) <= tdataout23; + Q(24) <= tdataout24; + Q(25) <= tdataout25; + Q(26) <= tdataout26; + Q(27) <= tdataout27; + Q(28) <= tdataout28; + Q(29) <= tdataout29; + Q(30) <= tdataout30; + Q(31) <= tdataout31; + Q(32) <= tdataout32; + Q(33) <= tdataout33; + Q(34) <= tdataout34; + Q(35) <= tdataout35; + Q(36) <= tdataout36; + Q(37) <= tdataout37; + Q(38) <= tdataout38; + Q(39) <= tdataout39; + Q(40) <= tdataout40; + Q(41) <= tdataout41; + Q(42) <= tdataout42; + Q(43) <= tdataout43; + Q(44) <= tdataout44; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of counter_45bit is + for Structure + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/scaler/cores_raw/counter_48bit.ipx b/scaler/cores_raw/counter_48bit.ipx new file mode 100644 index 0000000..d17f4b8 --- /dev/null +++ b/scaler/cores_raw/counter_48bit.ipx @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/scaler/cores_raw/counter_48bit.lpc b/scaler/cores_raw/counter_48bit.lpc new file mode 100644 index 0000000..050b69c --- /dev/null +++ b/scaler/cores_raw/counter_48bit.lpc @@ -0,0 +1,39 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN672C +SpeedGrade=8 +Package=FPBGA672 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=Counter +CoreRevision=4.5 +ModuleName=counter_48bit +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=06/08/2015 +Time=00:28:14 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +InputWidth=48 +CountType=Synchronous +CountDirection=Up +OptimizeSpeed=0 +Lower=0 +Upper=255 +Load=0 + +[Command] +cmd_line= -w -n counter_48bit -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type mgcounter -width 48 -cnt_direction up -aclear -clken diff --git a/scaler/cores_raw/counter_48bit.vhd b/scaler/cores_raw/counter_48bit.vhd new file mode 100644 index 0000000..61c2df5 --- /dev/null +++ b/scaler/cores_raw/counter_48bit.vhd @@ -0,0 +1,585 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80 +-- Module Version: 4.5 +--/usr/local/opt/lattice_diamond/diamond/3.4/ispfpga/bin/lin64/scuba -w -n counter_48bit -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type counter -up -width 48 + +-- Mon Jun 8 00:28:14 2015 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity counter_48bit is + port ( + Clock: in std_logic; + Clk_En: in std_logic; + Aclr: in std_logic; + Q: out std_logic_vector(47 downto 0)); +end counter_48bit; + +architecture Structure of counter_48bit is + + -- internal signal declarations + signal scuba_vlo: std_logic; + signal scuba_vhi: std_logic; + signal idataout0: std_logic; + signal idataout1: std_logic; + signal cnt_ci: std_logic; + signal tdataout0: std_logic; + signal tdataout1: std_logic; + signal idataout2: std_logic; + signal idataout3: std_logic; + signal co0: std_logic; + signal tdataout2: std_logic; + signal tdataout3: std_logic; + signal idataout4: std_logic; + signal idataout5: std_logic; + signal co1: std_logic; + signal tdataout4: std_logic; + signal tdataout5: std_logic; + signal idataout6: std_logic; + signal idataout7: std_logic; + signal co2: std_logic; + signal tdataout6: std_logic; + signal tdataout7: std_logic; + signal idataout8: std_logic; + signal idataout9: std_logic; + signal co3: std_logic; + signal tdataout8: std_logic; + signal tdataout9: std_logic; + signal idataout10: std_logic; + signal idataout11: std_logic; + signal co4: std_logic; + signal tdataout10: std_logic; + signal tdataout11: std_logic; + signal idataout12: std_logic; + signal idataout13: std_logic; + signal co5: std_logic; + signal tdataout12: std_logic; + signal tdataout13: std_logic; + signal idataout14: std_logic; + signal idataout15: std_logic; + signal co6: std_logic; + signal tdataout14: std_logic; + signal tdataout15: std_logic; + signal idataout16: std_logic; + signal idataout17: std_logic; + signal co7: std_logic; + signal tdataout16: std_logic; + signal tdataout17: std_logic; + signal idataout18: std_logic; + signal idataout19: std_logic; + signal co8: std_logic; + signal tdataout18: std_logic; + signal tdataout19: std_logic; + signal idataout20: std_logic; + signal idataout21: std_logic; + signal co9: std_logic; + signal tdataout20: std_logic; + signal tdataout21: std_logic; + signal idataout22: std_logic; + signal idataout23: std_logic; + signal co10: std_logic; + signal tdataout22: std_logic; + signal tdataout23: std_logic; + signal idataout24: std_logic; + signal idataout25: std_logic; + signal co11: std_logic; + signal tdataout24: std_logic; + signal tdataout25: std_logic; + signal idataout26: std_logic; + signal idataout27: std_logic; + signal co12: std_logic; + signal tdataout26: std_logic; + signal tdataout27: std_logic; + signal idataout28: std_logic; + signal idataout29: std_logic; + signal co13: std_logic; + signal tdataout28: std_logic; + signal tdataout29: std_logic; + signal idataout30: std_logic; + signal idataout31: std_logic; + signal co14: std_logic; + signal tdataout30: std_logic; + signal tdataout31: std_logic; + signal idataout32: std_logic; + signal idataout33: std_logic; + signal co15: std_logic; + signal tdataout32: std_logic; + signal tdataout33: std_logic; + signal idataout34: std_logic; + signal idataout35: std_logic; + signal co16: std_logic; + signal tdataout34: std_logic; + signal tdataout35: std_logic; + signal idataout36: std_logic; + signal idataout37: std_logic; + signal co17: std_logic; + signal tdataout36: std_logic; + signal tdataout37: std_logic; + signal idataout38: std_logic; + signal idataout39: std_logic; + signal co18: std_logic; + signal tdataout38: std_logic; + signal tdataout39: std_logic; + signal idataout40: std_logic; + signal idataout41: std_logic; + signal co19: std_logic; + signal tdataout40: std_logic; + signal tdataout41: std_logic; + signal idataout42: std_logic; + signal idataout43: std_logic; + signal co20: std_logic; + signal tdataout42: std_logic; + signal tdataout43: std_logic; + signal idataout44: std_logic; + signal idataout45: std_logic; + signal co21: std_logic; + signal tdataout44: std_logic; + signal tdataout45: std_logic; + signal idataout46: std_logic; + signal idataout47: std_logic; + signal co23: std_logic; + signal co22: std_logic; + signal tdataout46: std_logic; + signal tdataout47: std_logic; + + -- local component declarations + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + attribute GSR : string; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + FF_47: FD1P3DX + port map (D=>idataout0, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout0); + + FF_46: FD1P3DX + port map (D=>idataout1, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout1); + + FF_45: FD1P3DX + port map (D=>idataout2, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout2); + + FF_44: FD1P3DX + port map (D=>idataout3, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout3); + + FF_43: FD1P3DX + port map (D=>idataout4, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout4); + + FF_42: FD1P3DX + port map (D=>idataout5, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout5); + + FF_41: FD1P3DX + port map (D=>idataout6, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout6); + + FF_40: FD1P3DX + port map (D=>idataout7, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout7); + + FF_39: FD1P3DX + port map (D=>idataout8, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout8); + + FF_38: FD1P3DX + port map (D=>idataout9, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout9); + + FF_37: FD1P3DX + port map (D=>idataout10, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout10); + + FF_36: FD1P3DX + port map (D=>idataout11, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout11); + + FF_35: FD1P3DX + port map (D=>idataout12, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout12); + + FF_34: FD1P3DX + port map (D=>idataout13, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout13); + + FF_33: FD1P3DX + port map (D=>idataout14, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout14); + + FF_32: FD1P3DX + port map (D=>idataout15, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout15); + + FF_31: FD1P3DX + port map (D=>idataout16, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout16); + + FF_30: FD1P3DX + port map (D=>idataout17, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout17); + + FF_29: FD1P3DX + port map (D=>idataout18, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout18); + + FF_28: FD1P3DX + port map (D=>idataout19, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout19); + + FF_27: FD1P3DX + port map (D=>idataout20, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout20); + + FF_26: FD1P3DX + port map (D=>idataout21, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout21); + + FF_25: FD1P3DX + port map (D=>idataout22, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout22); + + FF_24: FD1P3DX + port map (D=>idataout23, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout23); + + FF_23: FD1P3DX + port map (D=>idataout24, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout24); + + FF_22: FD1P3DX + port map (D=>idataout25, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout25); + + FF_21: FD1P3DX + port map (D=>idataout26, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout26); + + FF_20: FD1P3DX + port map (D=>idataout27, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout27); + + FF_19: FD1P3DX + port map (D=>idataout28, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout28); + + FF_18: FD1P3DX + port map (D=>idataout29, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout29); + + FF_17: FD1P3DX + port map (D=>idataout30, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout30); + + FF_16: FD1P3DX + port map (D=>idataout31, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout31); + + FF_15: FD1P3DX + port map (D=>idataout32, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout32); + + FF_14: FD1P3DX + port map (D=>idataout33, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout33); + + FF_13: FD1P3DX + port map (D=>idataout34, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout34); + + FF_12: FD1P3DX + port map (D=>idataout35, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout35); + + FF_11: FD1P3DX + port map (D=>idataout36, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout36); + + FF_10: FD1P3DX + port map (D=>idataout37, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout37); + + FF_9: FD1P3DX + port map (D=>idataout38, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout38); + + FF_8: FD1P3DX + port map (D=>idataout39, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout39); + + FF_7: FD1P3DX + port map (D=>idataout40, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout40); + + FF_6: FD1P3DX + port map (D=>idataout41, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout41); + + FF_5: FD1P3DX + port map (D=>idataout42, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout42); + + FF_4: FD1P3DX + port map (D=>idataout43, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout43); + + FF_3: FD1P3DX + port map (D=>idataout44, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout44); + + FF_2: FD1P3DX + port map (D=>idataout45, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout45); + + FF_1: FD1P3DX + port map (D=>idataout46, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout46); + + FF_0: FD1P3DX + port map (D=>idataout47, SP=>Clk_En, CK=>Clock, CD=>Aclr, + Q=>tdataout47); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + cnt_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cnt_ci, S0=>open, + S1=>open); + + cnt_0: CU2 + port map (CI=>cnt_ci, PC0=>tdataout0, PC1=>tdataout1, CO=>co0, + NC0=>idataout0, NC1=>idataout1); + + cnt_1: CU2 + port map (CI=>co0, PC0=>tdataout2, PC1=>tdataout3, CO=>co1, + NC0=>idataout2, NC1=>idataout3); + + cnt_2: CU2 + port map (CI=>co1, PC0=>tdataout4, PC1=>tdataout5, CO=>co2, + NC0=>idataout4, NC1=>idataout5); + + cnt_3: CU2 + port map (CI=>co2, PC0=>tdataout6, PC1=>tdataout7, CO=>co3, + NC0=>idataout6, NC1=>idataout7); + + cnt_4: CU2 + port map (CI=>co3, PC0=>tdataout8, PC1=>tdataout9, CO=>co4, + NC0=>idataout8, NC1=>idataout9); + + cnt_5: CU2 + port map (CI=>co4, PC0=>tdataout10, PC1=>tdataout11, CO=>co5, + NC0=>idataout10, NC1=>idataout11); + + cnt_6: CU2 + port map (CI=>co5, PC0=>tdataout12, PC1=>tdataout13, CO=>co6, + NC0=>idataout12, NC1=>idataout13); + + cnt_7: CU2 + port map (CI=>co6, PC0=>tdataout14, PC1=>tdataout15, CO=>co7, + NC0=>idataout14, NC1=>idataout15); + + cnt_8: CU2 + port map (CI=>co7, PC0=>tdataout16, PC1=>tdataout17, CO=>co8, + NC0=>idataout16, NC1=>idataout17); + + cnt_9: CU2 + port map (CI=>co8, PC0=>tdataout18, PC1=>tdataout19, CO=>co9, + NC0=>idataout18, NC1=>idataout19); + + cnt_10: CU2 + port map (CI=>co9, PC0=>tdataout20, PC1=>tdataout21, CO=>co10, + NC0=>idataout20, NC1=>idataout21); + + cnt_11: CU2 + port map (CI=>co10, PC0=>tdataout22, PC1=>tdataout23, CO=>co11, + NC0=>idataout22, NC1=>idataout23); + + cnt_12: CU2 + port map (CI=>co11, PC0=>tdataout24, PC1=>tdataout25, CO=>co12, + NC0=>idataout24, NC1=>idataout25); + + cnt_13: CU2 + port map (CI=>co12, PC0=>tdataout26, PC1=>tdataout27, CO=>co13, + NC0=>idataout26, NC1=>idataout27); + + cnt_14: CU2 + port map (CI=>co13, PC0=>tdataout28, PC1=>tdataout29, CO=>co14, + NC0=>idataout28, NC1=>idataout29); + + cnt_15: CU2 + port map (CI=>co14, PC0=>tdataout30, PC1=>tdataout31, CO=>co15, + NC0=>idataout30, NC1=>idataout31); + + cnt_16: CU2 + port map (CI=>co15, PC0=>tdataout32, PC1=>tdataout33, CO=>co16, + NC0=>idataout32, NC1=>idataout33); + + cnt_17: CU2 + port map (CI=>co16, PC0=>tdataout34, PC1=>tdataout35, CO=>co17, + NC0=>idataout34, NC1=>idataout35); + + cnt_18: CU2 + port map (CI=>co17, PC0=>tdataout36, PC1=>tdataout37, CO=>co18, + NC0=>idataout36, NC1=>idataout37); + + cnt_19: CU2 + port map (CI=>co18, PC0=>tdataout38, PC1=>tdataout39, CO=>co19, + NC0=>idataout38, NC1=>idataout39); + + cnt_20: CU2 + port map (CI=>co19, PC0=>tdataout40, PC1=>tdataout41, CO=>co20, + NC0=>idataout40, NC1=>idataout41); + + cnt_21: CU2 + port map (CI=>co20, PC0=>tdataout42, PC1=>tdataout43, CO=>co21, + NC0=>idataout42, NC1=>idataout43); + + cnt_22: CU2 + port map (CI=>co21, PC0=>tdataout44, PC1=>tdataout45, CO=>co22, + NC0=>idataout44, NC1=>idataout45); + + cnt_23: CU2 + port map (CI=>co22, PC0=>tdataout46, PC1=>tdataout47, CO=>co23, + NC0=>idataout46, NC1=>idataout47); + + Q(0) <= tdataout0; + Q(1) <= tdataout1; + Q(2) <= tdataout2; + Q(3) <= tdataout3; + Q(4) <= tdataout4; + Q(5) <= tdataout5; + Q(6) <= tdataout6; + Q(7) <= tdataout7; + Q(8) <= tdataout8; + Q(9) <= tdataout9; + Q(10) <= tdataout10; + Q(11) <= tdataout11; + Q(12) <= tdataout12; + Q(13) <= tdataout13; + Q(14) <= tdataout14; + Q(15) <= tdataout15; + Q(16) <= tdataout16; + Q(17) <= tdataout17; + Q(18) <= tdataout18; + Q(19) <= tdataout19; + Q(20) <= tdataout20; + Q(21) <= tdataout21; + Q(22) <= tdataout22; + Q(23) <= tdataout23; + Q(24) <= tdataout24; + Q(25) <= tdataout25; + Q(26) <= tdataout26; + Q(27) <= tdataout27; + Q(28) <= tdataout28; + Q(29) <= tdataout29; + Q(30) <= tdataout30; + Q(31) <= tdataout31; + Q(32) <= tdataout32; + Q(33) <= tdataout33; + Q(34) <= tdataout34; + Q(35) <= tdataout35; + Q(36) <= tdataout36; + Q(37) <= tdataout37; + Q(38) <= tdataout38; + Q(39) <= tdataout39; + Q(40) <= tdataout40; + Q(41) <= tdataout41; + Q(42) <= tdataout42; + Q(43) <= tdataout43; + Q(44) <= tdataout44; + Q(45) <= tdataout45; + Q(46) <= tdataout46; + Q(47) <= tdataout47; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of counter_48bit is + for Structure + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/scaler/cores_raw/fifo_3to3_dc.ipx b/scaler/cores_raw/fifo_3to3_dc.ipx new file mode 100644 index 0000000..12f35b1 --- /dev/null +++ b/scaler/cores_raw/fifo_3to3_dc.ipx @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/scaler/cores_raw/fifo_3to3_dc.lpc b/scaler/cores_raw/fifo_3to3_dc.lpc new file mode 100644 index 0000000..bda012d --- /dev/null +++ b/scaler/cores_raw/fifo_3to3_dc.lpc @@ -0,0 +1,50 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN672C +SpeedGrade=8 +Package=FPBGA672 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.7 +ModuleName=fifo_3to3_dc +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=06/13/2015 +Time=20:51:35 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=4 +Width=4 +RDepth=4 +RWidth=4 +regout=1 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Dual Threshold +PfAssert=508 +PfDeassert=506 +RDataCount=0 +WDataCount=0 +EnECC=0 + +[Command] +cmd_line= -w -n fifo_3to3_dc -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 2 -data_width 4 -num_words 4 -rdata_width 4 -outdata REGISTERED -no_enable -pe -1 -pf -1 diff --git a/scaler/cores_raw/fifo_3to3_dc.vhd b/scaler/cores_raw/fifo_3to3_dc.vhd new file mode 100644 index 0000000..28efb5f --- /dev/null +++ b/scaler/cores_raw/fifo_3to3_dc.vhd @@ -0,0 +1,580 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80 +-- Module Version: 5.7 +--/usr/local/opt/lattice_diamond/diamond/3.4/ispfpga/bin/lin64/scuba -w -n fifo_3to3_dc -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 4 -width 4 -depth 4 -rdata_width 4 -regout -no_enable -pe -1 -pf -1 + +-- Sat Jun 13 20:51:35 2015 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity fifo_3to3_dc is + port ( + Data: in std_logic_vector(3 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(3 downto 0); + Empty: out std_logic; + Full: out std_logic); +end fifo_3to3_dc; + +architecture Structure of fifo_3to3_dc is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal co1: std_logic; + signal co0: std_logic; + signal wcount_2: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal co1_1: std_logic; + signal co0_1: std_logic; + signal rcount_2: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal wcount_r1: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal empty_cmp_clr: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w0: std_logic; + signal rcount_w1: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal full_cmp_clr: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component DP16KC + generic (GSR : in String; WRITEMODE_B : in String; + WRITEMODE_A : in String; CSDECODE_B : in String; + CSDECODE_A : in String; REGMODE_B : in String; + REGMODE_A : in String; DATA_WIDTH_B : in Integer; + DATA_WIDTH_A : in Integer); + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; + WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; + WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_3to3_dc.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; + attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t6: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t5: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t4: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t3: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t2: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t1: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t0: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + LUT4_7: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r1); + + LUT4_6: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>scuba_vlo, DO0=>wcount_r0); + + LUT4_5: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w1); + + LUT4_4: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, + AD1=>r_gcount_w22, AD0=>scuba_vlo, DO0=>rcount_w0); + + LUT4_3: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_2, AD2=>rcount_2, AD1=>w_gcount_r22, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_2, AD2=>rcount_2, AD1=>w_gcount_r22, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_2, AD2=>wcount_2, AD1=>r_gcount_w22, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_2, AD2=>wcount_2, AD1=>r_gcount_w22, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + pdp_ram_0_0_0: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 4, + DATA_WIDTH_A=> 4) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, + ADA4=>scuba_vlo, ADA5=>scuba_vlo, ADA6=>scuba_vlo, + ADA7=>scuba_vlo, ADA8=>scuba_vlo, ADA9=>scuba_vlo, + ADA10=>scuba_vlo, ADA11=>scuba_vlo, ADA12=>scuba_vlo, + ADA13=>scuba_vlo, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, ADB4=>scuba_vlo, + ADB5=>scuba_vlo, ADB6=>scuba_vlo, ADB7=>scuba_vlo, + ADB8=>scuba_vlo, ADB9=>scuba_vlo, ADB10=>scuba_vlo, + ADB11=>scuba_vlo, ADB12=>scuba_vlo, ADB13=>scuba_vlo, + CEB=>rden_i, CLKB=>RdClock, OCEB=>scuba_vhi, WEB=>scuba_vlo, + CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>Q(0), DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + FF_31: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_30: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_29: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_28: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_27: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_26: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_25: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_24: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_23: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_22: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_21: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_20: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_19: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_18: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_17: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_16: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_15: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_14: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_13: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_12: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_11: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_10: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_9: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_8: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_7: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_6: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_5: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_4: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_3: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_2: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_1: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_0: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>scuba_vlo, CO=>co1, + NC0=>iwcount_2, NC1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>scuba_vlo, CO=>co1_1, + NC0=>ircount_2, NC1=>open); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); + + empty_cmp_1: AGEB2 + port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, + B1=>scuba_vlo, CI=>co0_2, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); + + full_cmp_1: AGEB2 + port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, + B1=>scuba_vlo, CI=>co0_3, GE=>full_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of fifo_3to3_dc is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:OR2 use entity ecp3.OR2(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:DP16KC use entity ecp3.DP16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/scaler/cores_raw/fifo_4to4_dc.ipx b/scaler/cores_raw/fifo_4to4_dc.ipx new file mode 100644 index 0000000..7259d60 --- /dev/null +++ b/scaler/cores_raw/fifo_4to4_dc.ipx @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/scaler/cores_raw/fifo_4to4_dc.lpc b/scaler/cores_raw/fifo_4to4_dc.lpc new file mode 100644 index 0000000..474ca8a --- /dev/null +++ b/scaler/cores_raw/fifo_4to4_dc.lpc @@ -0,0 +1,50 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN672C +SpeedGrade=8 +Package=FPBGA672 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.7 +ModuleName=fifo_4to4_dc +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=06/13/2015 +Time=20:54:37 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=4 +Width=4 +RDepth=4 +RWidth=4 +regout=1 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Dual Threshold +PfAssert=508 +PfDeassert=506 +RDataCount=0 +WDataCount=0 +EnECC=0 + +[Command] +cmd_line= -w -n fifo_4to4_dc -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 2 -data_width 4 -num_words 4 -rdata_width 4 -outdata REGISTERED -no_enable -pe -1 -pf -1 diff --git a/scaler/cores_raw/fifo_4to4_dc.vhd b/scaler/cores_raw/fifo_4to4_dc.vhd new file mode 100644 index 0000000..6648820 --- /dev/null +++ b/scaler/cores_raw/fifo_4to4_dc.vhd @@ -0,0 +1,580 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80 +-- Module Version: 5.7 +--/usr/local/opt/lattice_diamond/diamond/3.4/ispfpga/bin/lin64/scuba -w -n fifo_4to4_dc -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 4 -width 4 -depth 4 -rdata_width 4 -regout -no_enable -pe -1 -pf -1 + +-- Sat Jun 13 20:54:37 2015 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity fifo_4to4_dc is + port ( + Data: in std_logic_vector(3 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(3 downto 0); + Empty: out std_logic; + Full: out std_logic); +end fifo_4to4_dc; + +architecture Structure of fifo_4to4_dc is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal co1: std_logic; + signal co0: std_logic; + signal wcount_2: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal co1_1: std_logic; + signal co0_1: std_logic; + signal rcount_2: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal wcount_r1: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal empty_cmp_clr: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w0: std_logic; + signal rcount_w1: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal full_cmp_clr: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component DP16KC + generic (GSR : in String; WRITEMODE_B : in String; + WRITEMODE_A : in String; CSDECODE_B : in String; + CSDECODE_A : in String; REGMODE_B : in String; + REGMODE_A : in String; DATA_WIDTH_B : in Integer; + DATA_WIDTH_A : in Integer); + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; + WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; + WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_4to4_dc.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; + attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t6: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t5: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t4: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t3: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t2: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t1: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t0: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + LUT4_7: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r1); + + LUT4_6: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>scuba_vlo, DO0=>wcount_r0); + + LUT4_5: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w1); + + LUT4_4: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, + AD1=>r_gcount_w22, AD0=>scuba_vlo, DO0=>rcount_w0); + + LUT4_3: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_2, AD2=>rcount_2, AD1=>w_gcount_r22, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_2, AD2=>rcount_2, AD1=>w_gcount_r22, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_2, AD2=>wcount_2, AD1=>r_gcount_w22, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_2, AD2=>wcount_2, AD1=>r_gcount_w22, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + pdp_ram_0_0_0: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 4, + DATA_WIDTH_A=> 4) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, + ADA4=>scuba_vlo, ADA5=>scuba_vlo, ADA6=>scuba_vlo, + ADA7=>scuba_vlo, ADA8=>scuba_vlo, ADA9=>scuba_vlo, + ADA10=>scuba_vlo, ADA11=>scuba_vlo, ADA12=>scuba_vlo, + ADA13=>scuba_vlo, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, ADB4=>scuba_vlo, + ADB5=>scuba_vlo, ADB6=>scuba_vlo, ADB7=>scuba_vlo, + ADB8=>scuba_vlo, ADB9=>scuba_vlo, ADB10=>scuba_vlo, + ADB11=>scuba_vlo, ADB12=>scuba_vlo, ADB13=>scuba_vlo, + CEB=>rden_i, CLKB=>RdClock, OCEB=>scuba_vhi, WEB=>scuba_vlo, + CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>Q(0), DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + FF_31: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_30: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_29: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_28: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_27: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_26: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_25: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_24: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_23: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_22: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_21: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_20: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_19: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_18: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_17: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_16: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_15: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_14: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_13: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_12: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_11: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_10: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_9: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_8: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_7: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_6: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_5: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_4: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_3: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_2: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_1: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_0: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>scuba_vlo, CO=>co1, + NC0=>iwcount_2, NC1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>scuba_vlo, CO=>co1_1, + NC0=>ircount_2, NC1=>open); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); + + empty_cmp_1: AGEB2 + port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, + B1=>scuba_vlo, CI=>co0_2, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); + + full_cmp_1: AGEB2 + port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, + B1=>scuba_vlo, CI=>co0_3, GE=>full_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of fifo_4to4_dc is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:OR2 use entity ecp3.OR2(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:DP16KC use entity ecp3.DP16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/scaler/cores_raw/fifo_5to5_dc.ipx b/scaler/cores_raw/fifo_5to5_dc.ipx new file mode 100644 index 0000000..f0e941b --- /dev/null +++ b/scaler/cores_raw/fifo_5to5_dc.ipx @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/scaler/cores_raw/fifo_5to5_dc.lpc b/scaler/cores_raw/fifo_5to5_dc.lpc new file mode 100644 index 0000000..06c935a --- /dev/null +++ b/scaler/cores_raw/fifo_5to5_dc.lpc @@ -0,0 +1,50 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN672C +SpeedGrade=8 +Package=FPBGA672 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.7 +ModuleName=fifo_5to5_dc +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=08/14/2015 +Time=23:11:04 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=4 +Width=5 +RDepth=4 +RWidth=5 +regout=1 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Dual Threshold +PfAssert=508 +PfDeassert=506 +RDataCount=0 +WDataCount=0 +EnECC=0 + +[Command] +cmd_line= -w -n fifo_5to5_dc -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 2 -data_width 5 -num_words 4 -rdata_width 5 -outdata REGISTERED -no_enable -pe -1 -pf -1 diff --git a/scaler/cores_raw/fifo_5to5_dc.vhd b/scaler/cores_raw/fifo_5to5_dc.vhd new file mode 100644 index 0000000..da8f148 --- /dev/null +++ b/scaler/cores_raw/fifo_5to5_dc.vhd @@ -0,0 +1,580 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80 +-- Module Version: 5.7 +--/usr/local/opt/lattice_diamond/diamond/3.4/ispfpga/bin/lin64/scuba -w -n fifo_5to5_dc -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 4 -width 5 -depth 4 -rdata_width 5 -regout -no_enable -pe -1 -pf -1 + +-- Fri Aug 14 23:11:04 2015 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity fifo_5to5_dc is + port ( + Data: in std_logic_vector(4 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(4 downto 0); + Empty: out std_logic; + Full: out std_logic); +end fifo_5to5_dc; + +architecture Structure of fifo_5to5_dc is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal co1: std_logic; + signal co0: std_logic; + signal wcount_2: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal co1_1: std_logic; + signal co0_1: std_logic; + signal rcount_2: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal wcount_r1: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal empty_cmp_clr: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w0: std_logic; + signal rcount_w1: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal full_cmp_clr: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component DP16KC + generic (GSR : in String; WRITEMODE_B : in String; + WRITEMODE_A : in String; CSDECODE_B : in String; + CSDECODE_A : in String; REGMODE_B : in String; + REGMODE_A : in String; DATA_WIDTH_B : in Integer; + DATA_WIDTH_A : in Integer); + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; + WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; + WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_5to5_dc.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; + attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t6: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t5: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t4: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t3: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t2: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t1: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t0: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + LUT4_7: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r1); + + LUT4_6: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>scuba_vlo, DO0=>wcount_r0); + + LUT4_5: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w1); + + LUT4_4: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, + AD1=>r_gcount_w22, AD0=>scuba_vlo, DO0=>rcount_w0); + + LUT4_3: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_2, AD2=>rcount_2, AD1=>w_gcount_r22, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_2, AD2=>rcount_2, AD1=>w_gcount_r22, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_2, AD2=>wcount_2, AD1=>r_gcount_w22, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_2, AD2=>wcount_2, AD1=>r_gcount_w22, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + pdp_ram_0_0_0: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, + ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>scuba_vlo, ADA6=>scuba_vlo, + ADA7=>scuba_vlo, ADA8=>scuba_vlo, ADA9=>scuba_vlo, + ADA10=>scuba_vlo, ADA11=>scuba_vlo, ADA12=>scuba_vlo, + ADA13=>scuba_vlo, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>scuba_vlo, ADB6=>scuba_vlo, ADB7=>scuba_vlo, + ADB8=>scuba_vlo, ADB9=>scuba_vlo, ADB10=>scuba_vlo, + ADB11=>scuba_vlo, ADB12=>scuba_vlo, ADB13=>scuba_vlo, + CEB=>rden_i, CLKB=>RdClock, OCEB=>scuba_vhi, WEB=>scuba_vlo, + CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>Q(0), DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), + DOB4=>Q(4), DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + FF_31: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_30: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_29: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_28: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_27: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_26: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_25: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_24: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_23: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_22: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_21: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_20: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_19: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_18: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_17: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_16: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_15: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_14: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_13: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_12: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_11: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_10: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_9: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_8: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_7: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_6: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_5: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_4: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_3: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_2: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_1: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_0: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>scuba_vlo, CO=>co1, + NC0=>iwcount_2, NC1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>scuba_vlo, CO=>co1_1, + NC0=>ircount_2, NC1=>open); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); + + empty_cmp_1: AGEB2 + port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, + B1=>scuba_vlo, CI=>co0_2, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); + + full_cmp_1: AGEB2 + port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, + B1=>scuba_vlo, CI=>co0_3, GE=>full_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of fifo_5to5_dc is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:OR2 use entity ecp3.OR2(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:DP16KC use entity ecp3.DP16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/scaler/cores_raw/fifo_6to6_dc.ipx b/scaler/cores_raw/fifo_6to6_dc.ipx new file mode 100644 index 0000000..ffbd3de --- /dev/null +++ b/scaler/cores_raw/fifo_6to6_dc.ipx @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/scaler/cores_raw/fifo_6to6_dc.lpc b/scaler/cores_raw/fifo_6to6_dc.lpc new file mode 100644 index 0000000..cbce3df --- /dev/null +++ b/scaler/cores_raw/fifo_6to6_dc.lpc @@ -0,0 +1,50 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN672C +SpeedGrade=8 +Package=FPBGA672 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.7 +ModuleName=fifo_6to6_dc +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=06/15/2015 +Time=23:21:51 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=4 +Width=6 +RDepth=4 +RWidth=6 +regout=1 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Dual Threshold +PfAssert=508 +PfDeassert=506 +RDataCount=0 +WDataCount=0 +EnECC=0 + +[Command] +cmd_line= -w -n fifo_6to6_dc -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 2 -data_width 6 -num_words 4 -rdata_width 6 -outdata REGISTERED -no_enable -pe -1 -pf -1 diff --git a/scaler/cores_raw/fifo_6to6_dc.vhd b/scaler/cores_raw/fifo_6to6_dc.vhd new file mode 100644 index 0000000..5bb8402 --- /dev/null +++ b/scaler/cores_raw/fifo_6to6_dc.vhd @@ -0,0 +1,580 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80 +-- Module Version: 5.7 +--/usr/local/opt/lattice_diamond/diamond/3.4/ispfpga/bin/lin64/scuba -w -n fifo_6to6_dc -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 4 -width 6 -depth 4 -rdata_width 6 -regout -no_enable -pe -1 -pf -1 + +-- Mon Jun 15 23:21:51 2015 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity fifo_6to6_dc is + port ( + Data: in std_logic_vector(5 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(5 downto 0); + Empty: out std_logic; + Full: out std_logic); +end fifo_6to6_dc; + +architecture Structure of fifo_6to6_dc is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal co1: std_logic; + signal co0: std_logic; + signal wcount_2: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal co1_1: std_logic; + signal co0_1: std_logic; + signal rcount_2: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal wcount_r1: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal empty_cmp_clr: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w0: std_logic; + signal rcount_w1: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal full_cmp_clr: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component DP16KC + generic (GSR : in String; WRITEMODE_B : in String; + WRITEMODE_A : in String; CSDECODE_B : in String; + CSDECODE_A : in String; REGMODE_B : in String; + REGMODE_A : in String; DATA_WIDTH_B : in Integer; + DATA_WIDTH_A : in Integer); + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; + WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; + WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_6to6_dc.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; + attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t6: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t5: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t4: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t3: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t2: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t1: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t0: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + LUT4_7: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r1); + + LUT4_6: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>scuba_vlo, DO0=>wcount_r0); + + LUT4_5: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w1); + + LUT4_4: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, + AD1=>r_gcount_w22, AD0=>scuba_vlo, DO0=>rcount_w0); + + LUT4_3: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_2, AD2=>rcount_2, AD1=>w_gcount_r22, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_2, AD2=>rcount_2, AD1=>w_gcount_r22, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_2, AD2=>wcount_2, AD1=>r_gcount_w22, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_2, AD2=>wcount_2, AD1=>r_gcount_w22, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + pdp_ram_0_0_0: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>scuba_vlo, + DIA7=>scuba_vlo, DIA8=>scuba_vlo, DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>scuba_vlo, ADA6=>scuba_vlo, ADA7=>scuba_vlo, + ADA8=>scuba_vlo, ADA9=>scuba_vlo, ADA10=>scuba_vlo, + ADA11=>scuba_vlo, ADA12=>scuba_vlo, ADA13=>scuba_vlo, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>scuba_vlo, + ADB6=>scuba_vlo, ADB7=>scuba_vlo, ADB8=>scuba_vlo, + ADB9=>scuba_vlo, ADB10=>scuba_vlo, ADB11=>scuba_vlo, + ADB12=>scuba_vlo, ADB13=>scuba_vlo, CEB=>rden_i, + CLKB=>RdClock, OCEB=>scuba_vhi, WEB=>scuba_vlo, + CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>Q(0), DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), + DOB4=>Q(4), DOB5=>Q(5), DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + FF_31: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_30: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_29: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_28: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_27: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_26: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_25: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_24: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_23: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_22: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_21: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_20: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_19: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_18: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_17: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_16: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_15: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_14: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_13: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_12: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_11: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_10: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_9: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_8: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_7: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_6: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_5: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_4: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_3: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_2: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_1: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_0: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>scuba_vlo, CO=>co1, + NC0=>iwcount_2, NC1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>scuba_vlo, CO=>co1_1, + NC0=>ircount_2, NC1=>open); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); + + empty_cmp_1: AGEB2 + port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, + B1=>scuba_vlo, CI=>co0_2, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); + + full_cmp_1: AGEB2 + port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, + B1=>scuba_vlo, CI=>co0_3, GE=>full_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of fifo_6to6_dc is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:OR2 use entity ecp3.OR2(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:DP16KC use entity ecp3.DP16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/scaler/cores_raw/fifo_data_48to48_dc.ipx b/scaler/cores_raw/fifo_data_48to48_dc.ipx new file mode 100644 index 0000000..7c5031e --- /dev/null +++ b/scaler/cores_raw/fifo_data_48to48_dc.ipx @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/scaler/cores_raw/fifo_data_48to48_dc.lpc b/scaler/cores_raw/fifo_data_48to48_dc.lpc new file mode 100644 index 0000000..6a958ac --- /dev/null +++ b/scaler/cores_raw/fifo_data_48to48_dc.lpc @@ -0,0 +1,50 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN672C +SpeedGrade=8 +Package=FPBGA672 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.7 +ModuleName=fifo_data_48to48_dc +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=06/07/2015 +Time=15:40:01 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=4 +Width=48 +RDepth=4 +RWidth=48 +regout=1 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Dual Threshold +PfAssert=508 +PfDeassert=506 +RDataCount=0 +WDataCount=0 +EnECC=0 + +[Command] +cmd_line= -w -n fifo_data_48to48_dc -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 2 -data_width 48 -num_words 4 -rdata_width 48 -outdata REGISTERED -no_enable -pe -1 -pf -1 diff --git a/scaler/cores_raw/fifo_data_48to48_dc.vhd b/scaler/cores_raw/fifo_data_48to48_dc.vhd new file mode 100644 index 0000000..34c6d9b --- /dev/null +++ b/scaler/cores_raw/fifo_data_48to48_dc.vhd @@ -0,0 +1,606 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80 +-- Module Version: 5.7 +--/usr/local/opt/lattice_diamond/diamond/3.4/ispfpga/bin/lin64/scuba -w -n fifo_data_48to48_dc -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 4 -width 48 -depth 4 -rdata_width 48 -regout -no_enable -pe -1 -pf -1 + +-- Sun Jun 7 15:40:01 2015 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity fifo_data_48to48_dc is + port ( + Data: in std_logic_vector(47 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(47 downto 0); + Empty: out std_logic; + Full: out std_logic); +end fifo_data_48to48_dc; + +architecture Structure of fifo_data_48to48_dc is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal co1: std_logic; + signal co0: std_logic; + signal wcount_2: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal co1_1: std_logic; + signal co0_1: std_logic; + signal rcount_2: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal wcount_r1: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal empty_cmp_clr: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w0: std_logic; + signal rcount_w1: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal full_cmp_clr: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component PDPW16KC + generic (GSR : in String; CSDECODE_R : in String; + CSDECODE_W : in String; REGMODE : in String; + DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer); + port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; + DI3: in std_logic; DI4: in std_logic; DI5: in std_logic; + DI6: in std_logic; DI7: in std_logic; DI8: in std_logic; + DI9: in std_logic; DI10: in std_logic; DI11: in std_logic; + DI12: in std_logic; DI13: in std_logic; + DI14: in std_logic; DI15: in std_logic; + DI16: in std_logic; DI17: in std_logic; + DI18: in std_logic; DI19: in std_logic; + DI20: in std_logic; DI21: in std_logic; + DI22: in std_logic; DI23: in std_logic; + DI24: in std_logic; DI25: in std_logic; + DI26: in std_logic; DI27: in std_logic; + DI28: in std_logic; DI29: in std_logic; + DI30: in std_logic; DI31: in std_logic; + DI32: in std_logic; DI33: in std_logic; + DI34: in std_logic; DI35: in std_logic; + ADW0: in std_logic; ADW1: in std_logic; + ADW2: in std_logic; ADW3: in std_logic; + ADW4: in std_logic; ADW5: in std_logic; + ADW6: in std_logic; ADW7: in std_logic; + ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic; + BE2: in std_logic; BE3: in std_logic; CEW: in std_logic; + CLKW: in std_logic; CSW0: in std_logic; + CSW1: in std_logic; CSW2: in std_logic; + ADR0: in std_logic; ADR1: in std_logic; + ADR2: in std_logic; ADR3: in std_logic; + ADR4: in std_logic; ADR5: in std_logic; + ADR6: in std_logic; ADR7: in std_logic; + ADR8: in std_logic; ADR9: in std_logic; + ADR10: in std_logic; ADR11: in std_logic; + ADR12: in std_logic; ADR13: in std_logic; + CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic; + CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic; + DO0: out std_logic; DO1: out std_logic; + DO2: out std_logic; DO3: out std_logic; + DO4: out std_logic; DO5: out std_logic; + DO6: out std_logic; DO7: out std_logic; + DO8: out std_logic; DO9: out std_logic; + DO10: out std_logic; DO11: out std_logic; + DO12: out std_logic; DO13: out std_logic; + DO14: out std_logic; DO15: out std_logic; + DO16: out std_logic; DO17: out std_logic; + DO18: out std_logic; DO19: out std_logic; + DO20: out std_logic; DO21: out std_logic; + DO22: out std_logic; DO23: out std_logic; + DO24: out std_logic; DO25: out std_logic; + DO26: out std_logic; DO27: out std_logic; + DO28: out std_logic; DO29: out std_logic; + DO30: out std_logic; DO31: out std_logic; + DO32: out std_logic; DO33: out std_logic; + DO34: out std_logic; DO35: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_data_48to48_dc.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is ""; + attribute RESETMODE of pdp_ram_0_0_1 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "fifo_data_48to48_dc.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is ""; + attribute RESETMODE of pdp_ram_0_1_0 : label is "SYNC"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t6: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t5: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t4: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t3: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t2: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t1: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t0: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + LUT4_7: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r1); + + LUT4_6: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>scuba_vlo, DO0=>wcount_r0); + + LUT4_5: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w1); + + LUT4_4: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, + AD1=>r_gcount_w22, AD0=>scuba_vlo, DO0=>rcount_w0); + + LUT4_3: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_2, AD2=>rcount_2, AD1=>w_gcount_r22, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_2, AD2=>rcount_2, AD1=>w_gcount_r22, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_2, AD2=>wcount_2, AD1=>r_gcount_w22, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_2, AD2=>wcount_2, AD1=>r_gcount_w22, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + pdp_ram_0_0_1: PDPW16KC + generic map (CSDECODE_R=> "0b001", CSDECODE_W=> "0b001", GSR=> "DISABLED", + REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) + port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), + DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), + DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), + DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), + DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), + DI18=>Data(18), DI19=>Data(19), DI20=>Data(20), + DI21=>Data(21), DI22=>Data(22), DI23=>Data(23), + DI24=>Data(24), DI25=>Data(25), DI26=>Data(26), + DI27=>Data(27), DI28=>Data(28), DI29=>Data(29), + DI30=>Data(30), DI31=>Data(31), DI32=>Data(32), + DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), ADW0=>wptr_0, + ADW1=>wptr_1, ADW2=>scuba_vlo, ADW3=>scuba_vlo, + ADW4=>scuba_vlo, ADW5=>scuba_vlo, ADW6=>scuba_vlo, + ADW7=>scuba_vlo, ADW8=>scuba_vlo, BE0=>scuba_vhi, + BE1=>scuba_vhi, BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i, + CLKW=>WrClock, CSW0=>scuba_vhi, CSW1=>scuba_vlo, + CSW2=>scuba_vlo, ADR0=>scuba_vlo, ADR1=>scuba_vlo, + ADR2=>scuba_vlo, ADR3=>scuba_vlo, ADR4=>scuba_vlo, + ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>scuba_vlo, ADR8=>scuba_vlo, + ADR9=>scuba_vlo, ADR10=>scuba_vlo, ADR11=>scuba_vlo, + ADR12=>scuba_vlo, ADR13=>scuba_vlo, CER=>scuba_vhi, + CLKR=>RdClock, CSR0=>rden_i, CSR1=>scuba_vlo, + CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(18), DO1=>Q(19), + DO2=>Q(20), DO3=>Q(21), DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), + DO7=>Q(25), DO8=>Q(26), DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), + DO12=>Q(30), DO13=>Q(31), DO14=>Q(32), DO15=>Q(33), + DO16=>Q(34), DO17=>Q(35), DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), + DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), + DO26=>Q(8), DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), + DO30=>Q(12), DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), + DO34=>Q(16), DO35=>Q(17)); + + pdp_ram_0_1_0: PDPW16KC + generic map (CSDECODE_R=> "0b001", CSDECODE_W=> "0b001", GSR=> "DISABLED", + REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) + port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38), + DI3=>Data(39), DI4=>Data(40), DI5=>Data(41), DI6=>Data(42), + DI7=>Data(43), DI8=>Data(44), DI9=>Data(45), DI10=>Data(46), + DI11=>Data(47), DI12=>scuba_vlo, DI13=>scuba_vlo, + DI14=>scuba_vlo, DI15=>scuba_vlo, DI16=>scuba_vlo, + DI17=>scuba_vlo, DI18=>scuba_vlo, DI19=>scuba_vlo, + DI20=>scuba_vlo, DI21=>scuba_vlo, DI22=>scuba_vlo, + DI23=>scuba_vlo, DI24=>scuba_vlo, DI25=>scuba_vlo, + DI26=>scuba_vlo, DI27=>scuba_vlo, DI28=>scuba_vlo, + DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo, + DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo, + DI35=>scuba_vlo, ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>scuba_vlo, + ADW3=>scuba_vlo, ADW4=>scuba_vlo, ADW5=>scuba_vlo, + ADW6=>scuba_vlo, ADW7=>scuba_vlo, ADW8=>scuba_vlo, + BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi, + BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, CSW0=>scuba_vhi, + CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo, + ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo, + ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>scuba_vlo, + ADR8=>scuba_vlo, ADR9=>scuba_vlo, ADR10=>scuba_vlo, + ADR11=>scuba_vlo, ADR12=>scuba_vlo, ADR13=>scuba_vlo, + CER=>scuba_vhi, CLKR=>RdClock, CSR0=>rden_i, CSR1=>scuba_vlo, + CSR2=>scuba_vlo, RST=>Reset, DO0=>open, DO1=>open, DO2=>open, + DO3=>open, DO4=>open, DO5=>open, DO6=>open, DO7=>open, + DO8=>open, DO9=>open, DO10=>open, DO11=>open, DO12=>open, + DO13=>open, DO14=>open, DO15=>open, DO16=>open, DO17=>open, + DO18=>Q(36), DO19=>Q(37), DO20=>Q(38), DO21=>Q(39), + DO22=>Q(40), DO23=>Q(41), DO24=>Q(42), DO25=>Q(43), + DO26=>Q(44), DO27=>Q(45), DO28=>Q(46), DO29=>Q(47), + DO30=>open, DO31=>open, DO32=>open, DO33=>open, DO34=>open, + DO35=>open); + + FF_31: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_30: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_29: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_28: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_27: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_26: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_25: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_24: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_23: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_22: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_21: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_20: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_19: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_18: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_17: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_16: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_15: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_14: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_13: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_12: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_11: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_10: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_9: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_8: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_7: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_6: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_5: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_4: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_3: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_2: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_1: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_0: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>scuba_vlo, CO=>co1, + NC0=>iwcount_2, NC1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>scuba_vlo, CO=>co1_1, + NC0=>ircount_2, NC1=>open); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); + + empty_cmp_1: AGEB2 + port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, + B1=>scuba_vlo, CI=>co0_2, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); + + full_cmp_1: AGEB2 + port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, + B1=>scuba_vlo, CI=>co0_3, GE=>full_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of fifo_data_48to48_dc is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:OR2 use entity ecp3.OR2(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/scaler/cores_raw/pll_clk400.ipx b/scaler/cores_raw/pll_clk400.ipx new file mode 100644 index 0000000..241f65d --- /dev/null +++ b/scaler/cores_raw/pll_clk400.ipx @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/scaler/cores_raw/pll_clk400.lpc b/scaler/cores_raw/pll_clk400.lpc new file mode 100644 index 0000000..27ef12d --- /dev/null +++ b/scaler/cores_raw/pll_clk400.lpc @@ -0,0 +1,69 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN672C +SpeedGrade=8 +Package=FPBGA672 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PLL +CoreRevision=5.6 +ModuleName=pll_clk400 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=06/05/2015 +Time=16:41:32 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=None +Order=None +IO=0 +Type=ehxpllb +mode=normal +IFrq=200 +Div=1 +ClkOPBp=0 +Post=2 +U_OFrq=400 +OP_Tol=0.0 +OFrq=400.000000 +DutyTrimP=Rising +DelayMultP=0 +fb_mode=CLKOP +Mult=2 +Phase=0.0 +Duty=8 +DelayMultS=0 +DPD=50% Duty +DutyTrimS=Rising +DelayMultD=0 +ClkOSDelay=0 +PhaseDuty=Static +CLKOK_INPUT=CLKOP +SecD=2 +U_KFrq=125 +OK_Tol=0.0 +KFrq=125.000000 +ClkRst=0 +PCDR=1 +FINDELA=0 +VcoRate= +Bandwidth=2.970786 +;DelayControl=No +EnCLKOS=0 +ClkOSBp=0 +EnCLKOK=0 +ClkOKBp=0 +enClkOK2=0 + +[Command] +cmd_line= -w -n pll_clk400 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 400 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -use_rst -noclkok2 -bw diff --git a/scaler/cores_raw/pll_clk400.vhd b/scaler/cores_raw/pll_clk400.vhd new file mode 100644 index 0000000..19bb577 --- /dev/null +++ b/scaler/cores_raw/pll_clk400.vhd @@ -0,0 +1,99 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.2.0.134 +-- Module Version: 5.6 +--/usr/local/opt/lattice_diamond/diamond/3.2/ispfpga/bin/lin64/scuba -w -n pll_clk400 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 400 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -use_rst -noclkok2 -bw + +-- Fri Jun 5 16:41:32 2015 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity pll_clk400 is + port ( + CLK: in std_logic; + RESET: in std_logic; + CLKOP: out std_logic; + LOCK: out std_logic); + attribute dont_touch : boolean; + attribute dont_touch of pll_clk400 : entity is true; +end pll_clk400; + +architecture Structure of pll_clk400 is + + -- internal signal declarations + signal CLKOP_t: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component EHXPLLF + generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String; + DELAY_PWD : in String; DELAY_VAL : in Integer; + CLKOS_TRIM_DELAY : in Integer; + CLKOS_TRIM_POL : in String; + CLKOP_TRIM_DELAY : in Integer; + CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String; + CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; + PHASE_DELAY_CNTL : in String; DUTY : in Integer; + PHASEADJ : in String; CLKOK_DIV : in Integer; + CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; + CLKI_DIV : in Integer; FIN : in String); + port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; + RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic; + DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; + DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; + DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic; + FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic; + CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic; + LOCK: out std_logic; CLKINTFB: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + attribute FREQUENCY_PIN_CLKOP : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "400.000000"; + attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000"; + attribute syn_keep : boolean; + attribute syn_noprune : boolean; + attribute syn_noprune of Structure : architecture is true; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLInst_0: EHXPLLF + generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED", + CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED", + CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=> 0, + CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING", + CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING", + PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0", + CLKOK_DIV=> 2, CLKOP_DIV=> 2, CLKFB_DIV=> 2, CLKI_DIV=> 1, + FIN=> "200.000000") + port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>RESET, RSTK=>scuba_vlo, + WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, DRPAI2=>scuba_vlo, + DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, DFPAI3=>scuba_vlo, + DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, DFPAI0=>scuba_vlo, + FDA3=>scuba_vlo, FDA2=>scuba_vlo, FDA1=>scuba_vlo, + FDA0=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>open, CLKOK=>open, + CLKOK2=>open, LOCK=>LOCK, CLKINTFB=>open); + + CLKOP <= CLKOP_t; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of pll_clk400 is + for Structure + for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/scaler/cores_raw/pll_clk500.ipx b/scaler/cores_raw/pll_clk500.ipx new file mode 100644 index 0000000..d750ae4 --- /dev/null +++ b/scaler/cores_raw/pll_clk500.ipx @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/scaler/cores_raw/pll_clk500.lpc b/scaler/cores_raw/pll_clk500.lpc new file mode 100644 index 0000000..1e9fb3f --- /dev/null +++ b/scaler/cores_raw/pll_clk500.lpc @@ -0,0 +1,69 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN672C +SpeedGrade=8 +Package=FPBGA672 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PLL +CoreRevision=5.7 +ModuleName=pll_clk500 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=06/08/2015 +Time=20:38:29 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=None +Order=None +IO=0 +Type=ehxpllb +mode=normal +IFrq=200 +Div=2 +ClkOPBp=0 +Post=2 +U_OFrq=500 +OP_Tol=0.0 +OFrq=500.000000 +DutyTrimP=Rising +DelayMultP=0 +fb_mode=CLKOP +Mult=5 +Phase=0.0 +Duty=8 +DelayMultS=0 +DPD=50% Duty +DutyTrimS=Rising +DelayMultD=0 +ClkOSDelay=0 +PhaseDuty=Static +CLKOK_INPUT=CLKOP +SecD=2 +U_KFrq=125 +OK_Tol=0.0 +KFrq=125.000000 +ClkRst=0 +PCDR=1 +FINDELA=0 +VcoRate= +Bandwidth=3.506502 +;DelayControl=No +EnCLKOS=0 +ClkOSBp=0 +EnCLKOK=0 +ClkOKBp=0 +enClkOK2=0 + +[Command] +cmd_line= -w -n pll_clk500 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 500 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -use_rst -noclkok2 -bw diff --git a/scaler/cores_raw/pll_clk500.vhd b/scaler/cores_raw/pll_clk500.vhd new file mode 100644 index 0000000..f4d8703 --- /dev/null +++ b/scaler/cores_raw/pll_clk500.vhd @@ -0,0 +1,99 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80 +-- Module Version: 5.7 +--/usr/local/opt/lattice_diamond/diamond/3.4/ispfpga/bin/lin64/scuba -w -n pll_clk500 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 500 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -use_rst -noclkok2 -bw + +-- Mon Jun 8 20:38:29 2015 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity pll_clk500 is + port ( + CLK: in std_logic; + RESET: in std_logic; + CLKOP: out std_logic; + LOCK: out std_logic); + attribute dont_touch : boolean; + attribute dont_touch of pll_clk500 : entity is true; +end pll_clk500; + +architecture Structure of pll_clk500 is + + -- internal signal declarations + signal CLKOP_t: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component EHXPLLF + generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String; + DELAY_PWD : in String; DELAY_VAL : in Integer; + CLKOS_TRIM_DELAY : in Integer; + CLKOS_TRIM_POL : in String; + CLKOP_TRIM_DELAY : in Integer; + CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String; + CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; + PHASE_DELAY_CNTL : in String; DUTY : in Integer; + PHASEADJ : in String; CLKOK_DIV : in Integer; + CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; + CLKI_DIV : in Integer; FIN : in String); + port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; + RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic; + DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; + DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; + DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic; + FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic; + CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic; + LOCK: out std_logic; CLKINTFB: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + attribute FREQUENCY_PIN_CLKOP : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "500.000000"; + attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000"; + attribute syn_keep : boolean; + attribute syn_noprune : boolean; + attribute syn_noprune of Structure : architecture is true; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLInst_0: EHXPLLF + generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED", + CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED", + CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=> 0, + CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING", + CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING", + PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0", + CLKOK_DIV=> 2, CLKOP_DIV=> 2, CLKFB_DIV=> 5, CLKI_DIV=> 2, + FIN=> "200.000000") + port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>RESET, RSTK=>scuba_vlo, + WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, DRPAI2=>scuba_vlo, + DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, DFPAI3=>scuba_vlo, + DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, DFPAI0=>scuba_vlo, + FDA3=>scuba_vlo, FDA2=>scuba_vlo, FDA1=>scuba_vlo, + FDA0=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>open, CLKOK=>open, + CLKOK2=>open, LOCK=>LOCK, CLKINTFB=>open); + + CLKOP <= CLKOP_t; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of pll_clk500 is + for Structure + for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/scaler/cores_raw/pll_clk_scaler.ipx b/scaler/cores_raw/pll_clk_scaler.ipx new file mode 100644 index 0000000..b94ab57 --- /dev/null +++ b/scaler/cores_raw/pll_clk_scaler.ipx @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/scaler/cores_raw/pll_clk_scaler.lpc b/scaler/cores_raw/pll_clk_scaler.lpc new file mode 100644 index 0000000..8631a63 --- /dev/null +++ b/scaler/cores_raw/pll_clk_scaler.lpc @@ -0,0 +1,69 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN672C +SpeedGrade=8 +Package=FPBGA672 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PLL +CoreRevision=5.7 +ModuleName=pll_clk_scaler +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=06/12/2015 +Time=16:57:24 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=None +Order=None +IO=0 +Type=ehxpllb +mode=normal +IFrq=200 +Div=2 +ClkOPBp=0 +Post=2 +U_OFrq=500 +OP_Tol=0.0 +OFrq=500.000000 +DutyTrimP=Rising +DelayMultP=0 +fb_mode=CLKOP +Mult=5 +Phase=0.0 +Duty=8 +DelayMultS=0 +DPD=50% Duty +DutyTrimS=Rising +DelayMultD=0 +ClkOSDelay=0 +PhaseDuty=Static +CLKOK_INPUT=CLKOP +SecD=2 +U_KFrq=250 +OK_Tol=0.0 +KFrq=250.000000 +ClkRst=0 +PCDR=1 +FINDELA=0 +VcoRate= +Bandwidth=3.506502 +;DelayControl=No +EnCLKOS=0 +ClkOSBp=0 +EnCLKOK=1 +ClkOKBp=0 +enClkOK2=0 + +[Command] +cmd_line= -w -n pll_clk_scaler -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 500 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -fclkok 250 -fclkok_tol 0.0 -clkoki 0 -use_rst -noclkok2 -bw diff --git a/scaler/cores_raw/pll_clk_scaler.vhd b/scaler/cores_raw/pll_clk_scaler.vhd new file mode 100644 index 0000000..c5df328 --- /dev/null +++ b/scaler/cores_raw/pll_clk_scaler.vhd @@ -0,0 +1,102 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80 +-- Module Version: 5.7 +--/usr/local/opt/lattice_diamond/diamond/3.4/ispfpga/bin/lin64/scuba -w -n pll_clk_scaler -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 500 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -fclkok 250 -fclkok_tol 0.0 -clkoki 0 -use_rst -noclkok2 -bw + +-- Fri Jun 12 16:57:24 2015 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity pll_clk_scaler is + port ( + CLK: in std_logic; + RESET: in std_logic; + CLKOP: out std_logic; + CLKOK: out std_logic; + LOCK: out std_logic); + attribute dont_touch : boolean; + attribute dont_touch of pll_clk_scaler : entity is true; +end pll_clk_scaler; + +architecture Structure of pll_clk_scaler is + + -- internal signal declarations + signal CLKOP_t: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component EHXPLLF + generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String; + DELAY_PWD : in String; DELAY_VAL : in Integer; + CLKOS_TRIM_DELAY : in Integer; + CLKOS_TRIM_POL : in String; + CLKOP_TRIM_DELAY : in Integer; + CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String; + CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; + PHASE_DELAY_CNTL : in String; DUTY : in Integer; + PHASEADJ : in String; CLKOK_DIV : in Integer; + CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; + CLKI_DIV : in Integer; FIN : in String); + port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; + RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic; + DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; + DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; + DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic; + FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic; + CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic; + LOCK: out std_logic; CLKINTFB: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + attribute FREQUENCY_PIN_CLKOP : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute FREQUENCY_PIN_CLKOK : string; + attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "500.000000"; + attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000"; + attribute FREQUENCY_PIN_CLKOK of PLLInst_0 : label is "250.000000"; + attribute syn_keep : boolean; + attribute syn_noprune : boolean; + attribute syn_noprune of Structure : architecture is true; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLInst_0: EHXPLLF + generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED", + CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED", + CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=> 0, + CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING", + CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING", + PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0", + CLKOK_DIV=> 2, CLKOP_DIV=> 2, CLKFB_DIV=> 5, CLKI_DIV=> 2, + FIN=> "200.000000") + port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>RESET, RSTK=>scuba_vlo, + WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, DRPAI2=>scuba_vlo, + DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, DFPAI3=>scuba_vlo, + DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, DFPAI0=>scuba_vlo, + FDA3=>scuba_vlo, FDA2=>scuba_vlo, FDA1=>scuba_vlo, + FDA0=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>open, CLKOK=>CLKOK, + CLKOK2=>open, LOCK=>LOCK, CLKINTFB=>open); + + CLKOP <= CLKOP_t; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of pll_clk_scaler is + for Structure + for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/scaler/cores_raw/pll_quadruple.ipx b/scaler/cores_raw/pll_quadruple.ipx new file mode 100644 index 0000000..de7702e --- /dev/null +++ b/scaler/cores_raw/pll_quadruple.ipx @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/scaler/cores_raw/pll_quadruple.lpc b/scaler/cores_raw/pll_quadruple.lpc new file mode 100644 index 0000000..05b101e --- /dev/null +++ b/scaler/cores_raw/pll_quadruple.lpc @@ -0,0 +1,69 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN672C +SpeedGrade=8 +Package=FPBGA672 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PLL +CoreRevision=5.7 +ModuleName=pll_quadruple +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=08/12/2015 +Time=16:45:00 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=None +Order=None +IO=0 +Type=ehxpllb +mode=advanced +IFrq=25 +Div=1 +ClkOPBp=0 +Post=8 +U_OFrq=100 +OP_Tol=0.0 +OFrq=100.000000 +DutyTrimP=Rising +DelayMultP=0 +fb_mode=CLKOP +Mult=4 +Phase=0.0 +Duty=8 +DelayMultS=0 +DPD=50% Duty +DutyTrimS=Rising +DelayMultD=0 +ClkOSDelay=0 +PhaseDuty=Static +CLKOK_INPUT=CLKOP +SecD=2 +U_KFrq=50 +OK_Tol=0.0 +KFrq= +ClkRst=0 +PCDR=0 +FINDELA=0 +VcoRate= +Bandwidth=3.424318 +;DelayControl=No +EnCLKOS=0 +ClkOSBp=0 +EnCLKOK=0 +ClkOKBp=0 +enClkOK2=0 + +[Command] +cmd_line= -w -n pll_quadruple -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 25 -phase_cntl STATIC -mdiv 1 -ndiv 4 -vdiv 8 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw diff --git a/scaler/cores_raw/pll_quadruple.vhd b/scaler/cores_raw/pll_quadruple.vhd new file mode 100644 index 0000000..83ebbaf --- /dev/null +++ b/scaler/cores_raw/pll_quadruple.vhd @@ -0,0 +1,99 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80 +-- Module Version: 5.7 +--/usr/local/opt/lattice_diamond/diamond/3.4/ispfpga/bin/lin64/scuba -w -n pll_quadruple -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 25 -phase_cntl STATIC -mdiv 1 -ndiv 4 -vdiv 8 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw + +-- Wed Aug 12 16:45:01 2015 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity pll_quadruple is + port ( + CLK: in std_logic; + CLKOP: out std_logic; + LOCK: out std_logic); + attribute dont_touch : boolean; + attribute dont_touch of pll_quadruple : entity is true; +end pll_quadruple; + +architecture Structure of pll_quadruple is + + -- internal signal declarations + signal CLKOP_t: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component EHXPLLF + generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String; + DELAY_PWD : in String; DELAY_VAL : in Integer; + CLKOS_TRIM_DELAY : in Integer; + CLKOS_TRIM_POL : in String; + CLKOP_TRIM_DELAY : in Integer; + CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String; + CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; + PHASE_DELAY_CNTL : in String; DUTY : in Integer; + PHASEADJ : in String; CLKOK_DIV : in Integer; + CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; + CLKI_DIV : in Integer; FIN : in String); + port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; + RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic; + DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; + DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; + DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic; + FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic; + CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic; + LOCK: out std_logic; CLKINTFB: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + attribute FREQUENCY_PIN_CLKOP : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "100.000000"; + attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "25.000000"; + attribute syn_keep : boolean; + attribute syn_noprune : boolean; + attribute syn_noprune of Structure : architecture is true; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLInst_0: EHXPLLF + generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED", + CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED", + CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=> 0, + CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING", + CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING", + PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0", + CLKOK_DIV=> 2, CLKOP_DIV=> 8, CLKFB_DIV=> 4, CLKI_DIV=> 1, + FIN=> "25.000000") + port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo, + RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, + DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, + DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, + DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo, + FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t, + CLKOS=>open, CLKOK=>open, CLKOK2=>open, LOCK=>LOCK, + CLKINTFB=>open); + + CLKOP <= CLKOP_t; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of pll_quadruple is + for Structure + for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/scaler/source/scaler_channel.vhd b/scaler/source/scaler_channel.vhd index 4a67842..b684392 100644 --- a/scaler/source/scaler_channel.vhd +++ b/scaler/source/scaler_channel.vhd @@ -255,7 +255,7 @@ begin counter_latched_new + resize(counter_latched_offset, 47); end if; counter_latched <= std_logic_vector(counter_latched_new); - data_clk <= '1'; + data_clk <= '1'; end if; end if; end if; -- 2.43.0