From ca3468e2d7ac63f86e24f12a6ab5aad0a8f3b9b5 Mon Sep 17 00:00:00 2001
From: hadaq <hadaq>
Date: Mon, 7 Jun 2010 16:49:11 +0000
Subject: [PATCH] new

---
 cts.tex | 42 ++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 40 insertions(+), 2 deletions(-)

diff --git a/cts.tex b/cts.tex
index b10bcd1..82c102b 100644
--- a/cts.tex
+++ b/cts.tex
@@ -83,19 +83,57 @@ For all registers described in this subsection refer to the Fig.\ref{cts_logic}
    \item[Bit 4] Disable readout on Etrax
   \end{description}
 
+
+
+
 %  \item[0xA0C9] Select how many times should be sent data to the EB with current ID (which corresponds to the EB IP number), when 0 does not swith between IDs
 %  \item[0xA0CA] Tables of 8 EB IDs (each ID has four bits), the IDs are switched form CA(3 down to 0) to CA(7 down to 4) ... CB(31 down to 28)
 %  \item[0xA0CB] Tables of 8 EB IDs (each ID has four bits) 
 
 %  \end{description}
-\end{description}
 
-  
+
+For the time being "old" logic of the CTS is not removed.
+\item[0xA0C5 old CTS trigger selection] Trigger source selection
+  \begin{description}
+   \item[Bits 4 - 0] enable trigger input on LVDS(4 downto 0) - corresponds to ADO LV(9 downto 0) on the trbv2 schematics
+   \item[Bits 9 - 5]  enable trigger input on LVTTL(20 downto 16) - corresponds to ADO TTL(20 downto 16) on the trbv2 schematics
+   \item[Bit 10] trigger form fast reference trigger - corresponds to Vir Trig on the trbv2 schematics
+   \item[Bit 11] self triggering (internal generator) 
+   \item[Bit 12] enable LVDS(0) and LVDS(1) coincidence 
+   \item[Bit 13] Trigger from C5(28) register
+   \item[Bit 14] enable LVTTL(16) and LVTTL(17) coincidence 
+   \item[Bit 15] enable LVTTL(18) and LVTTL(19)
+   \item[Bits 17 - 16] Change source of LVL2 trigger: "00" - auto (defaoult, generated after LVL1 trigger),"01" - LVDS lines,"10"- local source
+   \item[Bits 27 - 20] Number of how many LVL1 trigger has to pass to send LVL2 trigger
+   \item[Bit 28] Making trigger on rising edge (0...1...0)
+   \item[bit 29] not used
+   \item[bit 30] Enable LVL1 trigger source te be trigger logic (see Fig.\ref{cts_logic})
+   \item[bit 31] Make double APV pulse (0...1...0)
+  \end{description}
+
+\item[0xA0C6] LVL1 and IPU mixed 
+  \begin{description}
+   \item[Bits 7 - 0] IPU downscale - not used in current scheme. 
+   \item[Bits 27 - 8] Frequency of self triggering : 50MHz/value
+   \item[Bit 31 - 28] Length of timing trigger : 100ns + value*10ns (when is value< 7), when value > 6 time = (value - 7) * 10ns
+  \end{description}
+\item[0xA0C7] LVL1 trigger type selection
+  \begin{description}
+   \item[Bits 4 - 0] If c7(4)=1 the lvl1 trigger type equals c7(3 downto 0) else type is defined internally or by trigger logic
+  \end{description}
+
+\item[0xA0C7] LVL1 trigger information
+  \begin{description}
+   \item[Bits 13 - 0] LVL1 trigger information 13 downto 0 
+  \end{description}
+\end{description}  
 \begin{figure}
   \centering
   \includegraphics[width=.9\textwidth]{cts_doc.pdf}
   \caption{CTS trigger box logic}
   \label{cts_logic}
+
 \end{figure}
  
 
-- 
2.43.0