From cab92729d6e6f2182ec7caaf6ca51eb01a1816df Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Thu, 28 May 2009 13:55:54 +0000 Subject: [PATCH] *** empty log message *** --- design/mdc_addon_daq_bus_0.vhd | 92 +++++----- design/mdc_oepb_pack.vhd | 325 +++++++++++++++++++++++++++++++++ mdc_oepb.vhd | 17 +- 3 files changed, 380 insertions(+), 54 deletions(-) create mode 100644 design/mdc_oepb_pack.vhd diff --git a/design/mdc_addon_daq_bus_0.vhd b/design/mdc_addon_daq_bus_0.vhd index 973786f..d2d88ec 100644 --- a/design/mdc_addon_daq_bus_0.vhd +++ b/design/mdc_addon_daq_bus_0.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------- -- Attilio Tarantola --- Create Date: 01/07/2007 +-- Create Date: 01/07/2007 -- Description: this is the main entity for all buses, it contains: -- -- 1) trigger_handle_tld: entity which loads configuration parameters and sends @@ -29,13 +29,13 @@ entity mdc_addon_daq_bus_0 is CLK : in std_logic; RESET : in std_logic; - A_ADS_0 : in std_logic; --Motherboard address - A_ADS_1 : in std_logic; --Motherboard address + A_ADS_0 : in std_logic; --Motherboard address + A_ADS_1 : in std_logic; --Motherboard address A_ADS_2 : in std_logic; --Motherboard address -- A_ACK : inout std_logic; --acknowledgment A_ACK : in std_logic; - A_CMS : out std_logic; --common stop + A_CMS : out std_logic; --common stop -- A_OR : in std_logic; --common or A_RDM : out std_logic; --ready TO first motherboard @@ -52,11 +52,11 @@ entity mdc_addon_daq_bus_0 is A_ENR_1 : out std_logic; --A_GDE enable A_ENR_2 : out std_logic; --A_CMS enable -- A_ENR_3 : out std_logic; --A_OR enable - A_FET_ENABLE : out std_logic; --it enables 2 FETs + A_FET_ENABLE : out std_logic; --it enables 2 FETs A_REN : out std_logic; --A_RESERV enable - A_MOD : out std_logic; -- TDC working mode - A_RES : out std_logic; -- TDC working mode + A_MOD : out std_logic; -- TDC working mode + A_RES : out std_logic; -- TDC working mode A_TOK : out std_logic; -- TDC working mode A_WRM : out std_logic; -- TDC working mode @@ -87,8 +87,8 @@ entity mdc_addon_daq_bus_0 is -- SIGNALS for RAM ------------------------------------------------------------------------------- RAM_ADDRESS_IN : in std_logic_vector(8 downto 0); - RAM_DATA_IN : in std_logic_vector(15 downto 0); --16 bit - RAM_DATA_OUT : out std_logic_vector(15 downto 0); --16 bit + RAM_DATA_IN : in std_logic_vector(15 downto 0); --16 bit + RAM_DATA_OUT : out std_logic_vector(15 downto 0); --16 bit RAM_READ_ENABLE_IN : in std_logic; RAM_WRITE_ENABLE_IN : in std_logic; ------------------------------------------------------------------------------- @@ -96,11 +96,11 @@ entity mdc_addon_daq_bus_0 is ------------------------------------------------------------------------------- A_ADD_CONFIGURATION_OUT : out std_logic_vector(8 downto 0); --address/data line A_DST_CONFIGURATION_OUT : out std_logic; --data strobe - A_AOD_CONFIGURATION_OUT : out std_logic; --address or data + A_AOD_CONFIGURATION_OUT : out std_logic; --address or data A_ADD_DATA_IN : in std_logic_vector(8 downto 0); --address/data line A_DST_DATA_IN : in std_logic; --data strobe - A_AOD_DATA_IN : in std_logic; --address or data + A_AOD_DATA_IN : in std_logic; --address or data ------------------------------------------------------------------------------- -- DEBUG REGISTER ------------------------------------------------------------------------------- @@ -122,7 +122,7 @@ entity mdc_addon_daq_bus_0 is LVL1_TRG_INFORMATION_IN : in std_logic_vector(7 downto 0); LVL1_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0) := x"00000000"; LVL1_TRG_RELEASE_OUT : out std_logic := '0'; - + --Data Port IPU_NUMBER_IN : in std_logic_vector (15 downto 0); IPU_INFORMATION_IN : in std_logic_vector (7 downto 0); @@ -175,21 +175,21 @@ architecture behavioral of mdc_addon_daq_bus_0 is A_DRE : out std_logic; --address/data line enable A_ENR_1 : out std_logic; --A_GDE enable - A_MOD : out std_logic; -- TDC working mode - A_RES : out std_logic; -- TDC working mode + A_MOD : out std_logic; -- TDC working mode + A_RES : out std_logic; -- TDC working mode A_TOK : out std_logic; -- TDC working mode A_WRM : out std_logic; -- TDC working mode TRIGGER_TYPE_IN : in std_logic_vector(3 downto 0); -- I use 4 bit for trigger BUS_CHAIN_IN : in std_logic_vector(3 downto 0); ------------------------------------------------------------------------------- --- SIGNALS for RAM +-- SIGNALS for RAM ------------------------------------------------------------------------------- RAM_ADDRESS_IN : in std_logic_vector(8 downto 0); - RAM_DATA_IN : in std_logic_vector(15 downto 0); --16 bit - RAM_DATA_OUT : out std_logic_vector(15 downto 0); --16 bit - RAM_READ_ENABLE_IN : in std_logic; - RAM_WRITE_ENABLE_IN : in std_logic; + RAM_DATA_IN : in std_logic_vector(15 downto 0); --16 bit + RAM_DATA_OUT : out std_logic_vector(15 downto 0); --16 bit + RAM_READ_ENABLE_IN : in std_logic; + RAM_WRITE_ENABLE_IN : in std_logic; -- test pins connected to HPLA DEBUG_REGISTER : out std_logic_vector(24 downto 0); @@ -197,11 +197,11 @@ architecture behavioral of mdc_addon_daq_bus_0 is ROC1_WRITTEN : out std_logic; CAL1_WRITTEN : out std_logic; TOKEN_BACK_OUT : out std_logic_vector(3 downto 0); - REINIT_ROC1_OUT : out std_logic; + REINIT_ROC1_OUT : out std_logic; STOP_READOUT_OUT : out std_logic; RESET : in std_logic); end component; - + component tdc_readout_and_trb_interface -- generic (width : integer := 16; -- bus_number : std_logic_vector(3 downto 0)); @@ -214,7 +214,7 @@ architecture behavioral of mdc_addon_daq_bus_0 is A_ADD : in std_logic_vector(8 downto 0); A_RESERV : in std_logic; --this is 11 bit of dataword A_AOD : in std_logic; --address or data - A_ACK : in std_logic; + A_ACK : in std_logic; A_DST : in std_logic; -- A_RDO : in std_logic; A_DRE : out std_logic; @@ -256,7 +256,7 @@ architecture behavioral of mdc_addon_daq_bus_0 is LVL1_TRG_INFORMATION_IN : in std_logic_vector(7 downto 0); LVL1_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0) := x"00000000"; LVL1_TRG_RELEASE_OUT : out std_logic := '0'; - + --Data Port IPU_NUMBER_IN : in std_logic_vector (15 downto 0); IPU_INFORMATION_IN : in std_logic_vector (7 downto 0); @@ -271,15 +271,15 @@ architecture behavioral of mdc_addon_daq_bus_0 is IPU_READ_IN : in std_logic; IPU_LENGTH_OUT : out std_logic_vector (15 downto 0); IPU_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0)); - + end component; - + component common_stop_generator generic (width : integer := 5); port( CLK : in std_logic; RESET : in std_logic; - A_CMS_OUT : out std_logic; -- common stop + A_CMS_OUT : out std_logic; -- common stop A_RDO_IN : in std_logic; --ready FROM first motherboard TRIGGER_TYPE_IN : in std_logic_vector(3 downto 0); -- I use 4 bit for trigger INIT_TDC_READOUT_OUT : out std_logic_vector(3 downto 0); @@ -289,7 +289,7 @@ architecture behavioral of mdc_addon_daq_bus_0 is ENABLE_MODE_LINE_OUT : out std_logic_vector(3 downto 0); ENABLE_A_ADD_DATA_OUT : out std_logic); end component; - + begin --behavioral u0 : trigger_handle_tld @@ -310,9 +310,9 @@ begin --behavioral TRIGGER_TYPE_IN => init_trigger_handle_tld_i, --trigger_type_out_i, BUS_CHAIN_IN => BUS_CHAIN_IN, ------------------------------------------------------------------------------- --- SIGNALS for RAM +-- SIGNALS for RAM ------------------------------------------------------------------------------- - RAM_ADDRESS_IN => RAM_ADDRESS_IN, + RAM_ADDRESS_IN => RAM_ADDRESS_IN, RAM_DATA_IN => RAM_DATA_IN, RAM_DATA_OUT => RAM_DATA_OUT, RAM_READ_ENABLE_IN => RAM_READ_ENABLE_IN, @@ -330,10 +330,10 @@ begin --behavioral A_ADD_CONFIGURATION_OUT <= a_add_configuration_i; A_DST_CONFIGURATION_OUT <= a_dst_configuration_i; A_AOD_CONFIGURATION_OUT <= a_aod_configuration_i; - + a_add_data_i <= A_ADD_DATA_IN; - a_dst_data_i <= A_DST_DATA_IN; - a_aod_data_i <= A_AOD_DATA_IN; + a_dst_data_i <= A_DST_DATA_IN; + a_aod_data_i <= A_AOD_DATA_IN; --data adress line direction DIRECTION_DATA_LINE_IN <= enable_mode_line_i; @@ -353,7 +353,7 @@ begin --behavioral ENABLE_MODE_LINE_OUT => enable_mode_line_i, --gives the direction --of lines ENABLE_A_ADD_DATA_OUT => enable_a_add_data_i); - + u3 : tdc_readout_and_trb_interface -- generic map (width => 16, bus_number => bus_number) port map ( @@ -367,13 +367,13 @@ begin --behavioral A_DST => a_dst_data_i, A_DRE => open, --enable_a_add_data_i, -- - TOKEN_IN => token_back_out_i, + TOKEN_IN => token_back_out_i, INIT_TDC_READOUT_IN => init_tdc_readout_i, BUS_NUMBER_IN => open, --BUS_NUMBER_IN, -- INIT_TRB_INTERFACE_IN => init_trb_interface_i, TOKEN_TO_TRB_OUT => token_to_trb_i, - REINIT_ROC1_IN => reinit_roc1_i, + REINIT_ROC1_IN => reinit_roc1_i, REINIT_ROC1_OUT => reinit_roc1_forwarded_i, SUCCESFUL_REINIT_ROC1 => succesful_reinit_roc1_i, STOP_READOUT_IN => stop_readout_i, @@ -383,24 +383,24 @@ begin --behavioral DEBUG_REGISTER_1 => DEBUG_REGISTER_1_BUS_0, DEBUG_REGISTER_2 => DEBUG_REGISTER_2_BUS_0, -- trb interface --- ACKNOWLEDGE_TRB_INTERFACE_IN => ACKNOWLEDGE_TRB_INTERFACE_IN, --- INIT_TRB_INTERFACE_OUT => INIT_TRB_INTERFACE_OUT, --- DATA_OUT => DATA_OUT, --- READ_FIFO_IN => READ_FIFO_IN, +-- ACKNOWLEDGE_TRB_INTERFACE_IN => ACKNOWLEDGE_TRB_INTERFACE_IN, +-- INIT_TRB_INTERFACE_OUT => INIT_TRB_INTERFACE_OUT, +-- DATA_OUT => DATA_OUT, +-- READ_FIFO_IN => READ_FIFO_IN, -- DEBUG_REGISTER_TRB_INTERFACE => DEBUG_REGISTER_TRB_INTERFACE LVL1_TRG_TYPE_IN => LVL1_TRG_TYPE_IN, LVL1_TRG_RECEIVED_IN => LVL1_TRG_RECEIVED_IN, LVL1_TRG_NUMBER_IN => LVL1_TRG_NUMBER_IN, LVL1_TRG_CODE_IN => LVL1_TRG_CODE_IN, LVL1_TRG_INFORMATION_IN => LVL1_TRG_INFORMATION_IN, - LVL1_ERROR_PATTERN_OUT => open,--x"00000000", + LVL1_ERROR_PATTERN_OUT => open, LVL1_TRG_RELEASE_OUT => LVL1_TRG_RELEASE_OUT, IPU_NUMBER_IN => IPU_NUMBER_IN, IPU_INFORMATION_IN => IPU_INFORMATION_IN, IPU_START_READOUT_IN => IPU_START_READOUT_IN, IPU_DATA_OUT => IPU_DATA_OUT, - IPU_DATAREADY_OUT => IPU_DATAREADY_OUT, + IPU_DATAREADY_OUT => IPU_DATAREADY_OUT, IPU_READOUT_FINISHED_OUT => IPU_READOUT_FINISHED_OUT, IPU_READ_IN => IPU_READ_IN, IPU_LENGTH_OUT => IPU_LENGTH_OUT, @@ -435,11 +435,11 @@ begin --behavioral -- enable signal to transceivers-only differential signlals -- here signal which do not change in the design ------------------------------------------------------------------------------- - A_DRB_1 <= '0'; --A_RDO enable - A_ENR_1 <= '1'; --A_GDE enable A_ENR_1_i <= '1'; + A_DRB_1 <= '0'; --A_RDO enable + A_ENR_1 <= '1'; --A_GDE enable A_ENR_1_i <= '1'; A_REN <= '0'; --A_RESERV(11th bit of data word) enable A_ENR_2 <= '1'; --common stop enable - A_DRB_2 <= '1'; --A_RDM enable + A_DRB_2 <= '1'; --A_RDM enable A_DRA <= '0'; --A_ACK enable ------------------------------------------------------------------------------- @@ -453,8 +453,8 @@ begin --behavioral A_RDM <= a_rdm_i; a_rdo_i <= A_RDO; --token back a_reserv_i <= A_RESERV; --this is 11 bit of dataword - - A_CMS <= a_cms_out_i; --common stop + + A_CMS <= a_cms_out_i; --common stop -- A_RDO_OUT <= token_to_trb_i; diff --git a/design/mdc_oepb_pack.vhd b/design/mdc_oepb_pack.vhd new file mode 100644 index 0000000..5556894 --- /dev/null +++ b/design/mdc_oepb_pack.vhd @@ -0,0 +1,325 @@ +library ieee; +use ieee.std_logic_1164.all; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; +library work; +use work.trb_net_std.all; + +package mdc_oepb_pack is + +component mdc_addon_daq_bus_0 + -- generic (bus_number : std_logic_vector(3 downto 0)); + port ( + CLK : in std_logic; + --A_ADD : inout std_logic_vector(8 downto 0); + RESET : in std_logic; + A_ADS_0 : in std_logic; + A_ADS_1 : in std_logic; + A_ADS_2 : in std_logic; + -- A_AOD : inout std_logic; + A_ACK : in std_logic; + A_CMS : out std_logic; + -- A_DST : inout std_logic; + A_RDM : out std_logic; + A_GDE : out std_logic; + A_RDO : in std_logic; + A_RESERV : in std_logic; + A_DRA : out std_logic; + A_DRB_1 : out std_logic; + A_DRB_2 : out std_logic; + A_DRE : out std_logic; + A_ENB_1 : out std_logic; + A_ENB_2 : out std_logic; + A_ENR_1 : out std_logic; + A_ENR_2 : out std_logic; + A_FET_ENABLE : out std_logic; + A_REN : out std_logic; + A_MOD : out std_logic; + A_RES : out std_logic; + A_TOK : out std_logic; + A_WRM : out std_logic; + TOKEN_TO_MUX_OUT : out std_logic; + TRIGGER_TYPE_IN : in std_logic_vector(3 downto 0); + LA : out std_logic_vector(31 downto 0); + D : out std_logic_vector(6 downto 0); + A_RDO_OUT : out std_logic; + ROC1_WRITTEN_OUT : out std_logic; + BUS_NUMBER_IN : in std_logic_vector(3 downto 0); + BUS_CHAIN_IN : in std_logic_vector(3 downto 0); + ACKNOWLEDGE_TRB_INTERFACE_IN : in std_logic_vector(3 downto 0); + INIT_TRB_INTERFACE_OUT : out std_logic; + DATA_OUT : out std_logic_vector(25 downto 0); + READ_FIFO_IN : in std_logic; + DEBUG_REGISTER_TRB_INTERFACE : in std_logic_vector(3 downto 0); + RAM_ADDRESS_IN : in std_logic_vector(9 downto 0); + RAM_DATA_IN : in std_logic_vector(15 downto 0); + RAM_DATA_OUT : out std_logic_vector(15 downto 0); + RAM_READ_ENABLE_IN : in std_logic; + RAM_WRITE_ENABLE_IN : in std_logic; + + A_ADD_CONFIGURATION_OUT : out std_logic_vector(8 downto 0); --address/data line + A_DST_CONFIGURATION_OUT : out std_logic; + A_AOD_CONFIGURATION_OUT : out std_logic; + + A_ADD_DATA_IN : in std_logic_vector(8 downto 0); + A_DST_DATA_IN : in std_logic; + A_AOD_DATA_IN : in std_logic; + + DEBUG_REGISTER_0_BUS_0 : out std_logic_vector(7 downto 0); + DEBUG_REGISTER_1_BUS_0 : out std_logic_vector(7 downto 0); + DEBUG_REGISTER_2_BUS_0 : out std_logic_vector(7 downto 0); + DEBUG_REGISTER_3_BUS_0 : out std_logic_vector(7 downto 0); + DEBUG_REGISTER_4_BUS_0 : out std_logic_vector(7 downto 0); + DEBUG_REGISTER_5_BUS_0 : out std_logic_vector(7 downto 0); + DEBUG_REGISTER_6_BUS_0 : out std_logic_vector(7 downto 0); + DEBUG_REGISTER_7_BUS_0 : out std_logic_vector(7 downto 0); +------------------------------------------------------------------------------- +-- TRB net connections +------------------------------------------------------------------------------- + LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0); + LVL1_TRG_RECEIVED_IN : in std_logic; + LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); + LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0); + LVL1_TRG_INFORMATION_IN : in std_logic_vector(7 downto 0); + LVL1_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0) := x"00000000"; + LVL1_TRG_RELEASE_OUT : out std_logic := '0'; + + --Data Port + IPU_NUMBER_IN : in std_logic_vector (15 downto 0); + IPU_INFORMATION_IN : in std_logic_vector (7 downto 0); + --start strobe + IPU_START_READOUT_IN: in std_logic; + --detector data, equipped with DHDR + IPU_DATA_OUT : out std_logic_vector (31 downto 0); + IPU_DATAREADY_OUT : out std_logic; + --no more data, end transfer, send TRM + IPU_READOUT_FINISHED_OUT : out std_logic; + --will be low every second cycle due to 32bit -> 16bit conversion + IPU_READ_IN : in std_logic; + IPU_LENGTH_OUT : out std_logic_vector (15 downto 0); + IPU_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0)); + end component; + + + component trigger_distributor + port ( + CLK : in std_logic; + RESET : in std_logic; + INTERNAL_RESET_IN : in std_logic; + A_RDO_IN : in std_logic; + TRIGGER_IN : in std_logic; + TRIGGER_TYPE_IN : in std_logic_vector(3 downto 0); + INIT_ALL_BUSES_OUT : out std_logic_vector(3 downto 0); + ROC1_WRITTEN_IN : in std_logic; + TOKEN_TO_TRB_OUT : out std_logic; + CAL_TRIGGER_REGISTER_IN : in std_logic_vector(15 downto 0); + -- INTERNAL_RESET : in std_logic; + DEBUG_REGISTER_OUT : out std_logic_vector(31 downto 0); + LED_CNT_1_OUT : out std_logic; + LED_CNT_2_OUT : out std_logic; + LED_ERROR_OUT : out std_logic; + LED_GOOD_OUT : out std_logic); + end component; + + component pll_in25_out100 is + port ( + CLK: in std_logic; + CLKOP: out std_logic; + LOCK: out std_logic + ); + end component; + + component trb_net16_med_ecp_fot is + port( + CLK : in std_logic; + CLK_25 : in std_logic; + CLK_EN : in std_logic; + RESET : in std_logic; + + --Internal Connection + MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_IN : in std_logic; + MED_READ_OUT : out std_logic; + MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_OUT : out std_logic; + MED_READ_IN : in std_logic; + + --SFP Connection + TXP : out std_logic; + TXN : out std_logic; + RXP : in std_logic; + RXN : in std_logic; + SD : in std_logic; + + -- Status and control port + STAT_OP : out std_logic_vector (15 downto 0); + CTRL_OP : in std_logic_vector (15 downto 0); + STAT_DEBUG : out std_logic_vector (63 downto 0); + CTRL_DEBUG : in std_logic_vector (63 downto 0) + ); + end component; + + component adc_ltc2308_readout is + generic( + CLOCK_FREQUENCY : integer := 100 --MHz + ); + port( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + ADC_SCK : out std_logic; + ADC_SDI : out std_logic; + ADC_SDO : in std_logic; + ADC_CONVST : out std_logic; + + DAT_ADDR_IN : in std_logic_vector(5 downto 0); + DAT_READ_EN_IN : in std_logic; + DAT_WRITE_EN_IN : in std_logic; + DAT_DATA_OUT : out std_logic_vector(31 downto 0); + DAT_DATA_IN : in std_logic_vector(31 downto 0); + DAT_DATAREADY_OUT : out std_logic; + DAT_NO_MORE_DATA_OUT : out std_logic; + DAT_WRITE_ACK_OUT : out std_logic; + DAT_UNKNOWN_ADDR_OUT : out std_logic; + DAT_TIMEOUT_IN : in std_logic; + + STAT_VOLTAGES_OUT : out std_logic_vector(31 downto 0) + ); + end component; + + component trb_net16_endpoint_hades_full is + generic ( + USE_CHANNEL : channel_config_t := (c_YES,c_YES,c_NO,c_YES); + IBUF_DEPTH : channel_config_t := (6,6,6,6); + FIFO_TO_INT_DEPTH : channel_config_t := (6,6,6,6); + FIFO_TO_APL_DEPTH : channel_config_t := (6,6,6,6); + IBUF_SECURE_MODE : channel_config_t := (c_YES,c_YES,c_YES,c_YES); + API_SECURE_MODE_TO_APL : channel_config_t := (c_YES,c_YES,c_YES,c_YES); + API_SECURE_MODE_TO_INT : channel_config_t := (c_YES,c_YES,c_YES,c_YES); + OBUF_DATA_COUNT_WIDTH : integer range 0 to 7 := std_DATA_COUNT_WIDTH; + INIT_CAN_SEND_DATA : channel_config_t := (c_YES,c_YES,c_YES,c_NO); + REPLY_CAN_SEND_DATA : channel_config_t := (c_YES,c_YES,c_YES,c_YES); + REPLY_CAN_RECEIVE_DATA : channel_config_t := (c_YES,c_yES,c_yeS,c_NO); + USE_CHECKSUM : channel_config_t := (c_NO,c_YES,c_YES,c_YES); + APL_WRITE_ALL_WORDS : channel_config_t := (c_NO,c_NO,c_NO,c_NO); + BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF"; + REGIO_NUM_STAT_REGS : integer range 0 to 6 := 3; --log2 of number of status registers + REGIO_NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers + --standard values for output registers + REGIO_INIT_CTRL_REGS : std_logic_vector(2**(3)*32-1 downto 0) := (others => '0'); + --set to 0 for unused ctrl registers to save resources + REGIO_USED_CTRL_REGS : std_logic_vector(2**(3)-1 downto 0) := "00000001"; + --set to 0 for each unused bit in a register + REGIO_USED_CTRL_BITMASK : std_logic_vector(2**(3)*32-1 downto 0) := (others => '1'); + REGIO_USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port + REGIO_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"F100"; + REGIO_INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876"; + REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222"; + REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; + REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; + REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; + REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; + REGIO_USE_1WIRE_INTERFACE: integer := c_YES + ); + + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + -- Media direction port + MED_DATAREADY_OUT : out std_logic; + MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_IN : in std_logic; + + MED_DATAREADY_IN : in std_logic; + MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT : out std_logic; + + MED_STAT_OP_IN : in std_logic_vector(15 downto 0); + MED_CTRL_OP_OUT : out std_logic_vector(15 downto 0); + + -- LVL1 trigger APL + LVL1_TRG_TYPE_OUT : out std_logic_vector(3 downto 0); + LVL1_TRG_RECEIVED_OUT : out std_logic; + LVL1_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); + LVL1_TRG_CODE_OUT : out std_logic_vector(7 downto 0); + LVL1_TRG_INFORMATION_OUT : out std_logic_vector(7 downto 0); + LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0) := x"00000000"; + LVL1_TRG_RELEASE_IN : in std_logic := '0'; + + + --Data Port + IPU_NUMBER_OUT : out std_logic_vector (15 downto 0); + IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0); + --start strobe + IPU_START_READOUT_OUT: out std_logic; + --detector data, equipped with DHDR + IPU_DATA_IN : in std_logic_vector (31 downto 0); + IPU_DATAREADY_IN : in std_logic; + --no more data, end transfer, send TRM + IPU_READOUT_FINISHED_IN : in std_logic; + --will be low every second cycle due to 32bit -> 16bit conversion + IPU_READ_OUT : out std_logic; + IPU_LENGTH_IN : in std_logic_vector (15 downto 0); + IPU_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); + -- Slow Control Data Port + REGIO_COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); + REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0); + REGIO_REGISTERS_IN : in std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0'); + REGIO_REGISTERS_OUT : out std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0); + --following ports only used when using internal data port + REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0); + REGIO_READ_ENABLE_OUT : out std_logic; + REGIO_WRITE_ENABLE_OUT : out std_logic; + REGIO_DATA_OUT : out std_logic_vector(32-1 downto 0); + REGIO_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0'); + REGIO_DATAREADY_IN : in std_logic := '0'; + REGIO_NO_MORE_DATA_IN : in std_logic := '0'; + REGIO_WRITE_ACK_IN : in std_logic := '0'; + REGIO_UNKNOWN_ADDR_IN : in std_logic := '0'; + REGIO_TIMEOUT_OUT : out std_logic; + --IDRAM is used if no 1-wire interface, onewire used otherwise + REGIO_IDRAM_DATA_IN : in std_logic_vector(15 downto 0) := (others => '0'); + REGIO_IDRAM_DATA_OUT : out std_logic_vector(15 downto 0); + REGIO_IDRAM_ADDR_IN : in std_logic_vector(2 downto 0) := "000"; + REGIO_IDRAM_WR_IN : in std_logic := '0'; + REGIO_ONEWIRE_INOUT : inout std_logic; + REGIO_ONEWIRE_MONITOR_IN : in std_logic; + REGIO_ONEWIRE_MONITOR_OUT : out std_logic; + + STAT_DEBUG_IPU : out std_logic_vector (31 downto 0); + STAT_DEBUG_1 : out std_logic_vector (31 downto 0); + STAT_DEBUG_2 : out std_logic_vector (31 downto 0); + MED_STAT_OP : out std_logic_vector (15 downto 0); + CTRL_MPLEX : in std_logic_vector (31 downto 0); + IOBUF_CTRL_GEN : in std_logic_vector (4*32-1 downto 0); + STAT_ONEWIRE : out std_logic_vector (31 downto 0); + STAT_ADDR_DEBUG : out std_logic_vector (15 downto 0) + ); + end component; + + component ram_dp is + generic( + depth : integer := 3; + width : integer := 16 + ); + port( + CLK : in std_logic; + wr1 : in std_logic; + a1 : in std_logic_vector(depth-1 downto 0); + dout1 : out std_logic_vector(width-1 downto 0); + din1 : in std_logic_vector(width-1 downto 0); + a2 : in std_logic_vector(depth-1 downto 0); + dout2 : out std_logic_vector(width-1 downto 0) + ); + end component; + + +end package mdc_oepb_pack; \ No newline at end of file diff --git a/mdc_oepb.vhd b/mdc_oepb.vhd index 28c4cf9..1faca36 100644 --- a/mdc_oepb.vhd +++ b/mdc_oepb.vhd @@ -66,7 +66,7 @@ architecture mdc_oepb_arch of mdc_oepb is signal MED_STAT_OP : std_logic_vector(16-1 downto 0); signal MED_CTRL_OP : std_logic_vector(16-1 downto 0); signal MED_STAT_DEBUG : std_logic_vector(63 downto 0); - signal MED_CTRL_DEBUG : std_logic_vector(15 downto 0); + signal MED_CTRL_DEBUG : std_logic_vector(63 downto 0); signal LVL1_TRG_TYPE_OUT : std_logic_vector(3 downto 0); signal LVL1_TRG_RECEIVED_OUT : std_logic; @@ -145,7 +145,7 @@ architecture mdc_oepb_arch of mdc_oepb is signal pseudo_timing_trigger : std_logic; signal cal_trigger_register_in_i : std_logic_vector(15 downto 0); signal direction_data_line_in_i : std_logic_vector(3 downto 0); - + begin --------------------------------------------------------------------- -- PLL: 100 MHz @@ -188,6 +188,7 @@ begin --------------------------------------------------------------------- API: trb_net16_endpoint_hades_full generic map( + BROADCAST_BITMASK => x"FD", REGIO_NUM_STAT_REGS => 3, REGIO_NUM_CTRL_REGS => 3, --standard values for output registers @@ -195,6 +196,7 @@ begin --set to 0 for unused ctrl registers to save resources REGIO_USED_CTRL_REGS => (others => '1'), REGIO_USED_CTRL_BITMASK => (others => '1'), + BROADCAST_BITMASK => x"FD", REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)) ) port map( @@ -236,7 +238,7 @@ begin REGIO_COMMON_CTRL_REG_OUT => REGIO_COMMON_CTRL_REG_OUT, REGIO_REGISTERS_IN => REGIO_REGISTERS_IN, REGIO_REGISTERS_OUT => REGIO_REGISTERS_OUT, - + --following ports only used when using internal data port REGIO_ADDR_OUT => REGIO_ADDR_OUT, REGIO_READ_ENABLE_OUT => REGIO_READ_ENABLE_OUT, @@ -337,9 +339,9 @@ THE_REG_DAT_ADDR : process(CLK_100) end if; reg_REGIO_READ <= REGIO_READ_ENABLE_OUT; reg_REGIO_WRITE <= REGIO_WRITE_ENABLE_OUT; - + last_reg_REGIO_READ <= reg_REGIO_READ; - very_last_reg_REGIO_READ <= last_reg_REGIO_READ; + very_last_reg_REGIO_READ <= last_reg_REGIO_READ; end if; end process; @@ -364,7 +366,7 @@ THE_ADDRESS_DEC_REG_PROC: process( CLK_100 ) thresh_mem_addr <= REGIO_ADDR_OUT(8 downto 0);--(6 downto 0); thresh_mem_write <= '0'; thresh_mem_read <= '0'; - + if reg_REGIO_ADDR(15 downto 7) = x"A0"&'0' then thresh_mem_write <= REGIO_WRITE_ENABLE_OUT;--reg_REGIO_WRITE; thresh_mem_read <= reg_REGIO_READ; @@ -623,8 +625,7 @@ THE_ADDRESS_DEC_REG_PROC: process( CLK_100 ) a_add_data_i <= (others => '0'); a_aod_data_i <= '0'; a_dst_data_i <= '0'; - - else + else --DATA TACKING a_add_data_i <= TAD; a_aod_data_i <= TAOD; -- 2.43.0