From cb04022575f160fa8fd3142ee57508913ea60c1a Mon Sep 17 00:00:00 2001 From: Thomas Gessler Date: Wed, 30 Sep 2020 00:03:31 +0200 Subject: [PATCH] hub_test: change MGT locations --- hub_test/constrs/debug.xdc | 46 +++++++------- hub_test/constrs/hub_test.xdc | 31 +++++----- hub_test/hub_test.xpr | 7 +++ hub_test/src/hub_test.vhd | 112 +++++++++++++++++++++++----------- 4 files changed, 120 insertions(+), 76 deletions(-) diff --git a/hub_test/constrs/debug.xdc b/hub_test/constrs/debug.xdc index bfa1824..e835588 100644 --- a/hub_test/constrs/debug.xdc +++ b/hub_test/constrs/debug.xdc @@ -25,31 +25,27 @@ set_property port_width 1 [get_debug_ports u_ila_0/clk] connect_debug_port u_ila_0/clk [get_nets [list THE_SYSCLK/inst/clk_out1]] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] set_property port_width 32 [get_debug_ports u_ila_0/probe0] -connect_debug_port u_ila_0/probe0 [get_nets [list {generate_parsers[4].trb_parser_i/M_AXIS_TDATA[0]} {generate_parsers[4].trb_parser_i/M_AXIS_TDATA[1]} {generate_parsers[4].trb_parser_i/M_AXIS_TDATA[2]} {generate_parsers[4].trb_parser_i/M_AXIS_TDATA[3]} {generate_parsers[4].trb_parser_i/M_AXIS_TDATA[4]} {generate_parsers[4].trb_parser_i/M_AXIS_TDATA[5]} {generate_parsers[4].trb_parser_i/M_AXIS_TDATA[6]} {generate_parsers[4].trb_parser_i/M_AXIS_TDATA[7]} {generate_parsers[4].trb_parser_i/M_AXIS_TDATA[8]} {generate_parsers[4].trb_parser_i/M_AXIS_TDATA[9]} {generate_parsers[4].trb_parser_i/M_AXIS_TDATA[10]} {generate_parsers[4].trb_parser_i/M_AXIS_TDATA[11]} {generate_parsers[4].trb_parser_i/M_AXIS_TDATA[12]} {generate_parsers[4].trb_parser_i/M_AXIS_TDATA[13]} {generate_parsers[4].trb_parser_i/M_AXIS_TDATA[14]} {generate_parsers[4].trb_parser_i/M_AXIS_TDATA[15]} {generate_parsers[4].trb_parser_i/M_AXIS_TDATA[16]} {generate_parsers[4].trb_parser_i/M_AXIS_TDATA[17]} {generate_parsers[4].trb_parser_i/M_AXIS_TDATA[18]} {generate_parsers[4].trb_parser_i/M_AXIS_TDATA[19]} {generate_parsers[4].trb_parser_i/M_AXIS_TDATA[20]} {generate_parsers[4].trb_parser_i/M_AXIS_TDATA[21]} {generate_parsers[4].trb_parser_i/M_AXIS_TDATA[22]} {generate_parsers[4].trb_parser_i/M_AXIS_TDATA[23]} {generate_parsers[4].trb_parser_i/M_AXIS_TDATA[24]} {generate_parsers[4].trb_parser_i/M_AXIS_TDATA[25]} {generate_parsers[4].trb_parser_i/M_AXIS_TDATA[26]} {generate_parsers[4].trb_parser_i/M_AXIS_TDATA[27]} {generate_parsers[4].trb_parser_i/M_AXIS_TDATA[28]} {generate_parsers[4].trb_parser_i/M_AXIS_TDATA[29]} {generate_parsers[4].trb_parser_i/M_AXIS_TDATA[30]} {generate_parsers[4].trb_parser_i/M_AXIS_TDATA[31]}]] +connect_debug_port u_ila_0/probe0 [get_nets [list {generate_parsers[0].trb_parser_i/M_AXIS_TDATA[0]} {generate_parsers[0].trb_parser_i/M_AXIS_TDATA[1]} {generate_parsers[0].trb_parser_i/M_AXIS_TDATA[2]} {generate_parsers[0].trb_parser_i/M_AXIS_TDATA[3]} {generate_parsers[0].trb_parser_i/M_AXIS_TDATA[4]} {generate_parsers[0].trb_parser_i/M_AXIS_TDATA[5]} {generate_parsers[0].trb_parser_i/M_AXIS_TDATA[6]} {generate_parsers[0].trb_parser_i/M_AXIS_TDATA[7]} {generate_parsers[0].trb_parser_i/M_AXIS_TDATA[8]} {generate_parsers[0].trb_parser_i/M_AXIS_TDATA[9]} {generate_parsers[0].trb_parser_i/M_AXIS_TDATA[10]} {generate_parsers[0].trb_parser_i/M_AXIS_TDATA[11]} {generate_parsers[0].trb_parser_i/M_AXIS_TDATA[12]} {generate_parsers[0].trb_parser_i/M_AXIS_TDATA[13]} {generate_parsers[0].trb_parser_i/M_AXIS_TDATA[14]} {generate_parsers[0].trb_parser_i/M_AXIS_TDATA[15]} {generate_parsers[0].trb_parser_i/M_AXIS_TDATA[16]} {generate_parsers[0].trb_parser_i/M_AXIS_TDATA[17]} {generate_parsers[0].trb_parser_i/M_AXIS_TDATA[18]} {generate_parsers[0].trb_parser_i/M_AXIS_TDATA[19]} {generate_parsers[0].trb_parser_i/M_AXIS_TDATA[20]} {generate_parsers[0].trb_parser_i/M_AXIS_TDATA[21]} {generate_parsers[0].trb_parser_i/M_AXIS_TDATA[22]} {generate_parsers[0].trb_parser_i/M_AXIS_TDATA[23]} {generate_parsers[0].trb_parser_i/M_AXIS_TDATA[24]} {generate_parsers[0].trb_parser_i/M_AXIS_TDATA[25]} {generate_parsers[0].trb_parser_i/M_AXIS_TDATA[26]} {generate_parsers[0].trb_parser_i/M_AXIS_TDATA[27]} {generate_parsers[0].trb_parser_i/M_AXIS_TDATA[28]} {generate_parsers[0].trb_parser_i/M_AXIS_TDATA[29]} {generate_parsers[0].trb_parser_i/M_AXIS_TDATA[30]} {generate_parsers[0].trb_parser_i/M_AXIS_TDATA[31]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] set_property port_width 32 [get_debug_ports u_ila_0/probe1] -connect_debug_port u_ila_0/probe1 [get_nets [list {generate_parsers[4].trb_parser_i/DATA_OUT[0]} {generate_parsers[4].trb_parser_i/DATA_OUT[1]} {generate_parsers[4].trb_parser_i/DATA_OUT[2]} {generate_parsers[4].trb_parser_i/DATA_OUT[3]} {generate_parsers[4].trb_parser_i/DATA_OUT[4]} {generate_parsers[4].trb_parser_i/DATA_OUT[5]} {generate_parsers[4].trb_parser_i/DATA_OUT[6]} {generate_parsers[4].trb_parser_i/DATA_OUT[7]} {generate_parsers[4].trb_parser_i/DATA_OUT[8]} {generate_parsers[4].trb_parser_i/DATA_OUT[9]} {generate_parsers[4].trb_parser_i/DATA_OUT[10]} {generate_parsers[4].trb_parser_i/DATA_OUT[11]} {generate_parsers[4].trb_parser_i/DATA_OUT[12]} {generate_parsers[4].trb_parser_i/DATA_OUT[13]} {generate_parsers[4].trb_parser_i/DATA_OUT[14]} {generate_parsers[4].trb_parser_i/DATA_OUT[15]} {generate_parsers[4].trb_parser_i/DATA_OUT[16]} {generate_parsers[4].trb_parser_i/DATA_OUT[17]} {generate_parsers[4].trb_parser_i/DATA_OUT[18]} {generate_parsers[4].trb_parser_i/DATA_OUT[19]} {generate_parsers[4].trb_parser_i/DATA_OUT[20]} {generate_parsers[4].trb_parser_i/DATA_OUT[21]} {generate_parsers[4].trb_parser_i/DATA_OUT[22]} {generate_parsers[4].trb_parser_i/DATA_OUT[23]} {generate_parsers[4].trb_parser_i/DATA_OUT[24]} {generate_parsers[4].trb_parser_i/DATA_OUT[25]} {generate_parsers[4].trb_parser_i/DATA_OUT[26]} {generate_parsers[4].trb_parser_i/DATA_OUT[27]} {generate_parsers[4].trb_parser_i/DATA_OUT[28]} {generate_parsers[4].trb_parser_i/DATA_OUT[29]} {generate_parsers[4].trb_parser_i/DATA_OUT[30]} {generate_parsers[4].trb_parser_i/DATA_OUT[31]}]] +connect_debug_port u_ila_0/probe1 [get_nets [list {generate_parsers[0].trb_parser_i/DATA_OUT[0]} {generate_parsers[0].trb_parser_i/DATA_OUT[1]} {generate_parsers[0].trb_parser_i/DATA_OUT[2]} {generate_parsers[0].trb_parser_i/DATA_OUT[3]} {generate_parsers[0].trb_parser_i/DATA_OUT[4]} {generate_parsers[0].trb_parser_i/DATA_OUT[5]} {generate_parsers[0].trb_parser_i/DATA_OUT[6]} {generate_parsers[0].trb_parser_i/DATA_OUT[7]} {generate_parsers[0].trb_parser_i/DATA_OUT[8]} {generate_parsers[0].trb_parser_i/DATA_OUT[9]} {generate_parsers[0].trb_parser_i/DATA_OUT[10]} {generate_parsers[0].trb_parser_i/DATA_OUT[11]} {generate_parsers[0].trb_parser_i/DATA_OUT[12]} {generate_parsers[0].trb_parser_i/DATA_OUT[13]} {generate_parsers[0].trb_parser_i/DATA_OUT[14]} {generate_parsers[0].trb_parser_i/DATA_OUT[15]} {generate_parsers[0].trb_parser_i/DATA_OUT[16]} {generate_parsers[0].trb_parser_i/DATA_OUT[17]} {generate_parsers[0].trb_parser_i/DATA_OUT[18]} {generate_parsers[0].trb_parser_i/DATA_OUT[19]} {generate_parsers[0].trb_parser_i/DATA_OUT[20]} {generate_parsers[0].trb_parser_i/DATA_OUT[21]} {generate_parsers[0].trb_parser_i/DATA_OUT[22]} {generate_parsers[0].trb_parser_i/DATA_OUT[23]} {generate_parsers[0].trb_parser_i/DATA_OUT[24]} {generate_parsers[0].trb_parser_i/DATA_OUT[25]} {generate_parsers[0].trb_parser_i/DATA_OUT[26]} {generate_parsers[0].trb_parser_i/DATA_OUT[27]} {generate_parsers[0].trb_parser_i/DATA_OUT[28]} {generate_parsers[0].trb_parser_i/DATA_OUT[29]} {generate_parsers[0].trb_parser_i/DATA_OUT[30]} {generate_parsers[0].trb_parser_i/DATA_OUT[31]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] set_property port_width 1 [get_debug_ports u_ila_0/probe2] -connect_debug_port u_ila_0/probe2 [get_nets [list {generate_parsers[4].trb_parser_i/DATA_ACTIVE}]] +connect_debug_port u_ila_0/probe2 [get_nets [list {generate_parsers[0].trb_parser_i/DATA_ACTIVE}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] set_property port_width 1 [get_debug_ports u_ila_0/probe3] -connect_debug_port u_ila_0/probe3 [get_nets [list {generate_parsers[4].trb_parser_i/DATA_READY}]] +connect_debug_port u_ila_0/probe3 [get_nets [list {generate_parsers[0].trb_parser_i/DATA_READY}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] set_property port_width 1 [get_debug_ports u_ila_0/probe4] -connect_debug_port u_ila_0/probe4 [get_nets [list {generate_parsers[4].trb_parser_i/M_AXIS_TLAST}]] +connect_debug_port u_ila_0/probe4 [get_nets [list {generate_parsers[0].trb_parser_i/M_AXIS_TLAST}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] set_property port_width 1 [get_debug_ports u_ila_0/probe5] -connect_debug_port u_ila_0/probe5 [get_nets [list {generate_parsers[4].trb_parser_i/M_AXIS_TREADY}]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] -set_property port_width 1 [get_debug_ports u_ila_0/probe6] -connect_debug_port u_ila_0/probe6 [get_nets [list {generate_parsers[4].trb_parser_i/M_AXIS_TVALID}]] +connect_debug_port u_ila_0/probe5 [get_nets [list {generate_parsers[0].trb_parser_i/M_AXIS_TVALID}]] create_debug_core u_ila_1 ila set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_1] set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_1] @@ -63,19 +59,19 @@ set_property port_width 1 [get_debug_ports u_ila_1/clk] connect_debug_port u_ila_1/clk [get_nets [list THE_SYSCLK/inst/clk_out2]] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe0] set_property port_width 8 [get_debug_ports u_ila_1/probe0] -connect_debug_port u_ila_1/probe0 [get_nets [list {generate_downlinks[4].THE_DOWNLINK/THE_SERDES/TXDATA[0]} {generate_downlinks[4].THE_DOWNLINK/THE_SERDES/TXDATA[1]} {generate_downlinks[4].THE_DOWNLINK/THE_SERDES/TXDATA[2]} {generate_downlinks[4].THE_DOWNLINK/THE_SERDES/TXDATA[3]} {generate_downlinks[4].THE_DOWNLINK/THE_SERDES/TXDATA[4]} {generate_downlinks[4].THE_DOWNLINK/THE_SERDES/TXDATA[5]} {generate_downlinks[4].THE_DOWNLINK/THE_SERDES/TXDATA[6]} {generate_downlinks[4].THE_DOWNLINK/THE_SERDES/TXDATA[7]}]] +connect_debug_port u_ila_1/probe0 [get_nets [list {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/TXDATA[0]} {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/TXDATA[1]} {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/TXDATA[2]} {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/TXDATA[3]} {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/TXDATA[4]} {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/TXDATA[5]} {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/TXDATA[6]} {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/TXDATA[7]}]] create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe1] set_property port_width 8 [get_debug_ports u_ila_1/probe1] -connect_debug_port u_ila_1/probe1 [get_nets [list {THE_UPLINK/THE_SERDES/RXDATA[0]} {THE_UPLINK/THE_SERDES/RXDATA[1]} {THE_UPLINK/THE_SERDES/RXDATA[2]} {THE_UPLINK/THE_SERDES/RXDATA[3]} {THE_UPLINK/THE_SERDES/RXDATA[4]} {THE_UPLINK/THE_SERDES/RXDATA[5]} {THE_UPLINK/THE_SERDES/RXDATA[6]} {THE_UPLINK/THE_SERDES/RXDATA[7]}]] +connect_debug_port u_ila_1/probe1 [get_nets [list {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/RXDATA[0]} {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/RXDATA[1]} {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/RXDATA[2]} {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/RXDATA[3]} {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/RXDATA[4]} {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/RXDATA[5]} {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/RXDATA[6]} {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/RXDATA[7]}]] create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe2] set_property port_width 8 [get_debug_ports u_ila_1/probe2] -connect_debug_port u_ila_1/probe2 [get_nets [list {THE_UPLINK/THE_SERDES/TXDATA[0]} {THE_UPLINK/THE_SERDES/TXDATA[1]} {THE_UPLINK/THE_SERDES/TXDATA[2]} {THE_UPLINK/THE_SERDES/TXDATA[3]} {THE_UPLINK/THE_SERDES/TXDATA[4]} {THE_UPLINK/THE_SERDES/TXDATA[5]} {THE_UPLINK/THE_SERDES/TXDATA[6]} {THE_UPLINK/THE_SERDES/TXDATA[7]}]] +connect_debug_port u_ila_1/probe2 [get_nets [list {THE_UPLINK/THE_SERDES/RXDATA[0]} {THE_UPLINK/THE_SERDES/RXDATA[1]} {THE_UPLINK/THE_SERDES/RXDATA[2]} {THE_UPLINK/THE_SERDES/RXDATA[3]} {THE_UPLINK/THE_SERDES/RXDATA[4]} {THE_UPLINK/THE_SERDES/RXDATA[5]} {THE_UPLINK/THE_SERDES/RXDATA[6]} {THE_UPLINK/THE_SERDES/RXDATA[7]}]] create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe3] set_property port_width 8 [get_debug_ports u_ila_1/probe3] -connect_debug_port u_ila_1/probe3 [get_nets [list {generate_downlinks[4].THE_DOWNLINK/THE_SERDES/RXDATA[0]} {generate_downlinks[4].THE_DOWNLINK/THE_SERDES/RXDATA[1]} {generate_downlinks[4].THE_DOWNLINK/THE_SERDES/RXDATA[2]} {generate_downlinks[4].THE_DOWNLINK/THE_SERDES/RXDATA[3]} {generate_downlinks[4].THE_DOWNLINK/THE_SERDES/RXDATA[4]} {generate_downlinks[4].THE_DOWNLINK/THE_SERDES/RXDATA[5]} {generate_downlinks[4].THE_DOWNLINK/THE_SERDES/RXDATA[6]} {generate_downlinks[4].THE_DOWNLINK/THE_SERDES/RXDATA[7]}]] +connect_debug_port u_ila_1/probe3 [get_nets [list {THE_UPLINK/THE_SERDES/TXDATA[0]} {THE_UPLINK/THE_SERDES/TXDATA[1]} {THE_UPLINK/THE_SERDES/TXDATA[2]} {THE_UPLINK/THE_SERDES/TXDATA[3]} {THE_UPLINK/THE_SERDES/TXDATA[4]} {THE_UPLINK/THE_SERDES/TXDATA[5]} {THE_UPLINK/THE_SERDES/TXDATA[6]} {THE_UPLINK/THE_SERDES/TXDATA[7]}]] create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe4] set_property port_width 2 [get_debug_ports u_ila_1/probe4] @@ -95,19 +91,19 @@ connect_debug_port u_ila_1/probe7 [get_nets [list reset]] create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe8] set_property port_width 1 [get_debug_ports u_ila_1/probe8] -connect_debug_port u_ila_1/probe8 [get_nets [list {generate_downlinks[4].THE_DOWNLINK/THE_SERDES/RXCHARISCOMMA}]] +connect_debug_port u_ila_1/probe8 [get_nets [list THE_UPLINK/THE_SERDES/RXCHARISCOMMA]] create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe9] set_property port_width 1 [get_debug_ports u_ila_1/probe9] -connect_debug_port u_ila_1/probe9 [get_nets [list THE_UPLINK/THE_SERDES/RXCHARISCOMMA]] +connect_debug_port u_ila_1/probe9 [get_nets [list {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/RXCHARISCOMMA}]] create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe10] set_property port_width 1 [get_debug_ports u_ila_1/probe10] -connect_debug_port u_ila_1/probe10 [get_nets [list {generate_downlinks[4].THE_DOWNLINK/THE_SERDES/RXCHARISK}]] +connect_debug_port u_ila_1/probe10 [get_nets [list THE_UPLINK/THE_SERDES/RXCHARISK]] create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe11] set_property port_width 1 [get_debug_ports u_ila_1/probe11] -connect_debug_port u_ila_1/probe11 [get_nets [list THE_UPLINK/THE_SERDES/RXCHARISK]] +connect_debug_port u_ila_1/probe11 [get_nets [list {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/RXCHARISK}]] create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe12] set_property port_width 1 [get_debug_ports u_ila_1/probe12] @@ -115,7 +111,7 @@ connect_debug_port u_ila_1/probe12 [get_nets [list THE_UPLINK/THE_SERDES/RXDISPE create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe13] set_property port_width 1 [get_debug_ports u_ila_1/probe13] -connect_debug_port u_ila_1/probe13 [get_nets [list {generate_downlinks[4].THE_DOWNLINK/THE_SERDES/RXDISPERR}]] +connect_debug_port u_ila_1/probe13 [get_nets [list {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/RXDISPERR}]] create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe14] set_property port_width 1 [get_debug_ports u_ila_1/probe14] @@ -123,7 +119,7 @@ connect_debug_port u_ila_1/probe14 [get_nets [list THE_UPLINK/THE_SERDES/RXNOTIN create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe15] set_property port_width 1 [get_debug_ports u_ila_1/probe15] -connect_debug_port u_ila_1/probe15 [get_nets [list {generate_downlinks[4].THE_DOWNLINK/THE_SERDES/RXNOTINTABLE}]] +connect_debug_port u_ila_1/probe15 [get_nets [list {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/RXNOTINTABLE}]] create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe16] set_property port_width 1 [get_debug_ports u_ila_1/probe16] @@ -135,15 +131,15 @@ connect_debug_port u_ila_1/probe17 [get_nets [list trb_reset]] create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe18] set_property port_width 1 [get_debug_ports u_ila_1/probe18] -connect_debug_port u_ila_1/probe18 [get_nets [list {generate_downlinks[4].THE_DOWNLINK/THE_SERDES/TXCHARDISPMODE}]] +connect_debug_port u_ila_1/probe18 [get_nets [list THE_UPLINK/THE_SERDES/TXCHARDISPMODE]] create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe19] set_property port_width 1 [get_debug_ports u_ila_1/probe19] -connect_debug_port u_ila_1/probe19 [get_nets [list THE_UPLINK/THE_SERDES/TXCHARDISPMODE]] +connect_debug_port u_ila_1/probe19 [get_nets [list {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/TXCHARDISPMODE}]] create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe20] set_property port_width 1 [get_debug_ports u_ila_1/probe20] -connect_debug_port u_ila_1/probe20 [get_nets [list {generate_downlinks[4].THE_DOWNLINK/THE_SERDES/TXCHARDISPVAL}]] +connect_debug_port u_ila_1/probe20 [get_nets [list {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/TXCHARDISPVAL}]] create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe21] set_property port_width 1 [get_debug_ports u_ila_1/probe21] @@ -151,11 +147,11 @@ connect_debug_port u_ila_1/probe21 [get_nets [list THE_UPLINK/THE_SERDES/TXCHARD create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe22] set_property port_width 1 [get_debug_ports u_ila_1/probe22] -connect_debug_port u_ila_1/probe22 [get_nets [list {generate_downlinks[4].THE_DOWNLINK/THE_SERDES/TXCHARISK}]] +connect_debug_port u_ila_1/probe22 [get_nets [list THE_UPLINK/THE_SERDES/TXCHARISK]] create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe23] set_property port_width 1 [get_debug_ports u_ila_1/probe23] -connect_debug_port u_ila_1/probe23 [get_nets [list THE_UPLINK/THE_SERDES/TXCHARISK]] +connect_debug_port u_ila_1/probe23 [get_nets [list {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/TXCHARISK}]] set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub] set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub] set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub] diff --git a/hub_test/constrs/hub_test.xdc b/hub_test/constrs/hub_test.xdc index e775545..3719283 100644 --- a/hub_test/constrs/hub_test.xdc +++ b/hub_test/constrs/hub_test.xdc @@ -38,8 +38,11 @@ set_property IOSTANDARD LVCMOS18 [get_ports PEX_I2C_SEL1] set_property PACKAGE_PIN B34 [get_ports UC_RESET_N] set_property IOSTANDARD LVCMOS18 [get_ports UC_RESET_N] -set_property PACKAGE_PIN AK37 [get_ports MGTREFCLK_P] -create_clock -period 10.000 -name MGTREFCLK_P [get_ports MGTREFCLK_P] +set_property PACKAGE_PIN AK37 [get_ports MGTREFCLK0P_127] +create_clock -period 10.000 -name MGTREFCLK0P_127 [get_ports MGTREFCLK0P_127] + +set_property PACKAGE_PIN R6 [get_ports MGTREFCLK0P_231] +create_clock -period 5.000 -name MGTREFCLK0P_231 [get_ports MGTREFCLK0P_231] set_property PACKAGE_PIN V13 [get_ports SCL] set_property IOSTANDARD LVTTL [get_ports SCL] @@ -59,16 +62,14 @@ set_property IOSTANDARD LVDS [get_ports TRG_OUT_2_P] set_property PACKAGE_PIN AT29 [get_ports TRG_OUT_3_P] set_property IOSTANDARD LVDS [get_ports TRG_OUT_3_P] -set_property LOC GTHE3_CHANNEL_X0Y9 [get_cells -hierarchical -filter {NAME =~ generate_downlinks[4].THE_DOWNLINK/*/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}] -set_property LOC GTHE3_CHANNEL_X0Y10 [get_cells -hierarchical -filter {NAME =~ generate_downlinks[5].THE_DOWNLINK/*/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}] -set_property LOC GTHE3_CHANNEL_X0Y11 [get_cells -hierarchical -filter {NAME =~ generate_downlinks[6].THE_DOWNLINK/*/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}] - -set_property LOC GTHE3_CHANNEL_X0Y12 [get_cells -hierarchical -filter {NAME =~ generate_downlinks[2].THE_DOWNLINK/*/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}] -set_property LOC GTHE3_CHANNEL_X0Y13 [get_cells -hierarchical -filter {NAME =~ generate_downlinks[3].THE_DOWNLINK/*/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}] -set_property LOC GTHE3_CHANNEL_X0Y14 [get_cells -hierarchical -filter {NAME =~ generate_downlinks[0].THE_DOWNLINK/*/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}] -set_property LOC GTHE3_CHANNEL_X0Y15 [get_cells -hierarchical -filter {NAME =~ generate_downlinks[1].THE_DOWNLINK/*/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}] - -set_property LOC GTHE3_CHANNEL_X0Y16 [get_cells -hierarchical -filter {NAME =~ generate_downlinks[8].THE_DOWNLINK/*/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}] -set_property LOC GTHE3_CHANNEL_X0Y17 [get_cells -hierarchical -filter {NAME =~ generate_downlinks[7].THE_DOWNLINK/*/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}] - -set_property LOC GTHE3_CHANNEL_X0Y8 [get_cells -hierarchical -filter {NAME =~ THE_UPLINK/*/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}] +set_property LOC GTHE3_CHANNEL_X0Y19 [get_cells -hierarchical -filter {NAME =~ generate_downlinks[0].THE_DOWNLINK/*/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}] +set_property LOC GTHE3_CHANNEL_X0Y16 [get_cells -hierarchical -filter {NAME =~ generate_downlinks[1].THE_DOWNLINK/*/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}] +set_property LOC GTHE3_CHANNEL_X0Y18 [get_cells -hierarchical -filter {NAME =~ generate_downlinks[2].THE_DOWNLINK/*/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}] +set_property LOC GTHE3_CHANNEL_X0Y17 [get_cells -hierarchical -filter {NAME =~ generate_downlinks[3].THE_DOWNLINK/*/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}] +set_property LOC GTHE3_CHANNEL_X0Y15 [get_cells -hierarchical -filter {NAME =~ generate_downlinks[4].THE_DOWNLINK/*/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}] +set_property LOC GTHE3_CHANNEL_X0Y14 [get_cells -hierarchical -filter {NAME =~ generate_downlinks[5].THE_DOWNLINK/*/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}] +set_property LOC GTHE3_CHANNEL_X0Y12 [get_cells -hierarchical -filter {NAME =~ generate_downlinks[6].THE_DOWNLINK/*/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}] +set_property LOC GTHE3_CHANNEL_X0Y13 [get_cells -hierarchical -filter {NAME =~ generate_downlinks[7].THE_DOWNLINK/*/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}] +set_property LOC GTHE3_CHANNEL_X0Y10 [get_cells -hierarchical -filter {NAME =~ generate_downlinks[8].THE_DOWNLINK/*/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}] + +set_property LOC GTHE3_CHANNEL_X1Y29 [get_cells -hierarchical -filter {NAME =~ THE_UPLINK/*/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}] \ No newline at end of file diff --git a/hub_test/hub_test.xpr b/hub_test/hub_test.xpr index d6f1010..6e6dee7 100644 --- a/hub_test/hub_test.xpr +++ b/hub_test/hub_test.xpr @@ -74,6 +74,13 @@ + + + + + + + diff --git a/hub_test/src/hub_test.vhd b/hub_test/src/hub_test.vhd index 29123f7..f91379b 100644 --- a/hub_test/src/hub_test.vhd +++ b/hub_test/src/hub_test.vhd @@ -33,8 +33,11 @@ entity hub_test is PEX_I2C_SEL1 : out std_logic; UC_RESET_N : out std_logic; - MGTREFCLK_P : in std_logic; -- 100 MHz, sync. with SI5345_OUT7_P - MGTREFCLK_N : in std_logic; + MGTREFCLK0P_127 : in std_logic; -- 100 MHz, sync. with SI5345_OUT7_P + MGTREFCLK0N_127 : in std_logic; + + MGTREFCLK0P_231 : in std_logic; -- 200 MHz, free-running + MGTREFCLK0N_231 : in std_logic; RXN : in std_logic_vector(INTERFACE_NUM - 1 downto 0); RXP : in std_logic_vector(INTERFACE_NUM - 1 downto 0); @@ -107,10 +110,6 @@ architecture behavioral of hub_test is ); end component; - type linknum_type is array (0 to 9) of integer; - constant mgtnum_from_linknum : linknum_type - := (5, 4, 6, 7, 11, 8, 9, 3, 1, 10); - signal clk_200_ibuf : std_logic; signal baseclk_100 : std_logic; signal baseclk_out : std_logic; @@ -121,9 +120,14 @@ architecture behavioral of hub_test is signal sysclk_200 : std_logic; signal sysclk_locked : std_logic; - signal mgtrefclk : std_logic; - signal mgtrefclk_hrow : std_logic; - signal mgtrefclk_bufg : std_logic; + signal mgtrefclk_downlink : std_logic; + signal mgtrefclk_downlink_hrow : std_logic; + signal mgtrefclk_downlink_bufg : std_logic; + + signal mgtrefclk_uplink : std_logic; + signal mgtrefclk_uplink_hrow : std_logic; + signal mgtrefclk_uplink_bufg : std_logic; + signal mgtrefclk_uplink_bufg_half : std_logic; signal initial_clear_timer : unsigned(27 downto 0) := (others => '0'); signal initial_clear_n : std_logic := '0'; @@ -281,29 +285,65 @@ begin clk_in1_n => SI5345_OUT7_N ); - THE_MGTREFCLK1_X0Y3 : IBUFDS_GTE3 + THE_MGTREFCLK0_127 : IBUFDS_GTE3 generic map ( REFCLK_EN_TX_PATH => '0', REFCLK_HROW_CK_SEL => "00", REFCLK_ICNTL_RX => "00" ) port map ( - I => MGTREFCLK_P, - IB => MGTREFCLK_N, + I => MGTREFCLK0P_127, + IB => MGTREFCLK0N_127, CEB => mb_sysclk_reset, - O => mgtrefclk, - ODIV2 => mgtrefclk_hrow + O => mgtrefclk_downlink, + ODIV2 => mgtrefclk_downlink_hrow ); - BUFG_GT_MGTREFCLK1_X0Y3 : BUFG_GT + BUFG_GT_MGTREFCLK0_127 : BUFG_GT port map ( - O => mgtrefclk_bufg, + O => mgtrefclk_downlink_bufg, CE => '1', CEMASK => '0', CLR => mb_sysclk_reset, CLRMASK => '0', DIV => "000", - I => mgtrefclk_hrow + I => mgtrefclk_downlink_hrow + ); + + THE_MGTREFCLK0_231 : IBUFDS_GTE3 + generic map ( + REFCLK_EN_TX_PATH => '0', + REFCLK_HROW_CK_SEL => "00", + REFCLK_ICNTL_RX => "00" + ) + port map ( + I => MGTREFCLK0P_231, + IB => MGTREFCLK0N_231, + CEB => '0', + O => mgtrefclk_uplink, + ODIV2 => mgtrefclk_uplink_hrow + ); + + BUFG_GT_MGTREFCLK0_231 : BUFG_GT + port map ( + O => mgtrefclk_uplink_bufg, + CE => '1', + CEMASK => '0', + CLR => '0', + CLRMASK => '0', + DIV => "000", + I => mgtrefclk_uplink_hrow + ); + + BUFG_GT_MGTREFCLK0_231_half : BUFG_GT + port map ( + O => mgtrefclk_uplink_bufg_half, + CE => '1', + CEMASK => '0', + CLR => '0', + CLRMASK => '0', + DIV => "001", + I => mgtrefclk_uplink_hrow ); THE_VIO : vio_0 @@ -355,21 +395,21 @@ begin generic map ( IS_SYNC_SLAVE => c_YES, LINE_RATE_KBPS => 2000000, - REFCLK_FREQ_HZ => 100000000 + REFCLK_FREQ_HZ => 200000000 ) port map ( SYSCLK => sysclk_100, CLK_100 => baseclk_100, - GTREFCLK => mgtrefclk, - GTREFCLK_BUFG => mgtrefclk_bufg, + GTREFCLK => mgtrefclk_uplink, + GTREFCLK_BUFG => mgtrefclk_uplink_bufg, RXOUTCLK => open, TXOUTCLK => open, - RXUSRCLK => sysclk_100, - RXUSRCLK_DOUBLE => sysclk_200, - TXUSRCLK => sysclk_100, - TXUSRCLK_DOUBLE => sysclk_200, - RXUSRCLK_ACTIVE => sysclk_locked, - TXUSRCLK_ACTIVE => sysclk_locked, + RXUSRCLK => mgtrefclk_uplink_bufg_half, + RXUSRCLK_DOUBLE => mgtrefclk_uplink_bufg, + TXUSRCLK => mgtrefclk_uplink_bufg_half, + TXUSRCLK_DOUBLE => mgtrefclk_uplink_bufg, + RXUSRCLK_ACTIVE => '1', -- TODO: should be GTPOWERGOOD? + TXUSRCLK_ACTIVE => '1', -- TODO: should be GTPOWERGOOD? RXPMARESETDONE => open, TXPMARESETDONE => open, RESET => reset, @@ -384,8 +424,8 @@ begin RX_DLM_WORD => open, TX_DLM => '0', TX_DLM_WORD => x"00", - SD_LOS_IN => mpod_a_los(mgtnum_from_linknum(INTERFACE_NUM - 1)), - SD_TXDIS_OUT => mpod_a_txdis(mgtnum_from_linknum(INTERFACE_NUM - 1)), + SD_LOS_IN => mpod_d_los(1), + SD_TXDIS_OUT => mpod_d_txdis(1), STAT_DEBUG => open, CTRL_DEBUG => (others => '0'), DRPADDR => drpaddr(8 downto 0), @@ -430,8 +470,8 @@ begin port map ( SYSCLK => sysclk_100, CLK_100 => baseclk_100, - GTREFCLK => mgtrefclk, - GTREFCLK_BUFG => mgtrefclk_bufg, + GTREFCLK => mgtrefclk_downlink, + GTREFCLK_BUFG => mgtrefclk_downlink_bufg, RXOUTCLK => open, TXOUTCLK => open, RXUSRCLK => sysclk_100, @@ -454,8 +494,8 @@ begin RX_DLM_WORD => open, TX_DLM => dlm, TX_DLM_WORD => x"00", - SD_LOS_IN => mpod_a_los(mgtnum_from_linknum(linknum)), - SD_TXDIS_OUT => mpod_a_txdis(mgtnum_from_linknum(linknum)), + SD_LOS_IN => mpod_a_los(linknum), + SD_TXDIS_OUT => mpod_a_txdis(linknum), STAT_DEBUG => open, CTRL_DEBUG => (others => '0'), DRPADDR => drpaddr_i, @@ -473,8 +513,8 @@ begin TXPRECURSOR => txprecursor_i ); - generate_downlink_4: - if linknum = 4 generate + generate_downlink_0: + if linknum = 0 generate begin drpen_i <= drpen(1); drpwe_i <= drpwe(1); @@ -489,7 +529,7 @@ begin txdiffctrl_i <= txdiffctrl(7 downto 4); txpostcursor_i <= txpostcursor(9 downto 5); txprecursor_i <= txprecursor(9 downto 5); - end generate generate_downlink_4; + end generate generate_downlink_0; end generate generate_downlinks; @@ -521,7 +561,7 @@ begin rxlpmen_i => b"1_1", drpclk_i(0) => baseclk_100, drpclk_i(1) => baseclk_100, - rxoutclk_i(0) => sysclk_100, + rxoutclk_i(0) => mgtrefclk_uplink_bufg_half, rxoutclk_i(1) => sysclk_100, clk => baseclk_100 ); -- 2.43.0