From cbc8ca16b7aa9d9c64e272d04c2e66c046792352 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Tue, 2 Jun 2020 11:55:19 +0200 Subject: [PATCH] update onewire interface for stand-alone operation with external mux --- trb_net_components.vhd | 29 ++++++++++++++++------------- trb_net_onewire.vhd | 16 ++++++++++++++-- 2 files changed, 30 insertions(+), 15 deletions(-) diff --git a/trb_net_components.vhd b/trb_net_components.vhd index 47832d0..892aa7d 100644 --- a/trb_net_components.vhd +++ b/trb_net_components.vhd @@ -2313,23 +2313,26 @@ end component; component trb_net_onewire is generic( USE_TEMPERATURE_READOUT : integer range 0 to 1 := 1; - PARASITIC_MODE : integer range 0 to 1 := c_NO; - CLK_PERIOD : integer := 10 --clk period in ns + PARASITIC_MODE : integer range 0 to 1 := c_NO; + CLK_PERIOD : integer := 10; --clk period in ns + USEINOUT : integer := c_YES ); port( - CLK : in std_logic; - RESET : in std_logic; - READOUT_ENABLE_IN : in std_logic := '1'; + CLK : in std_logic; + RESET : in std_logic; + READOUT_ENABLE_IN : in std_logic := '1'; --connection to 1-wire interface - ONEWIRE : inout std_logic; - MONITOR_OUT : out std_logic; + ONEWIRE : inout std_logic; + ONEWIRE_IN : in std_logic := '0'; + ONEWIRE_OUT : out std_logic := '0'; + MONITOR_OUT : out std_logic; --connection to id ram, according to memory map in TrbNetRegIO - DATA_OUT : out std_logic_vector(15 downto 0); - ADDR_OUT : out std_logic_vector(2 downto 0); - WRITE_OUT : out std_logic; - TEMP_OUT : out std_logic_vector(11 downto 0); - ID_OUT : out std_logic_vector(63 downto 0); - STAT : out std_logic_vector(31 downto 0) + DATA_OUT : out std_logic_vector(15 downto 0); + ADDR_OUT : out std_logic_vector(2 downto 0); + WRITE_OUT: out std_logic; + TEMP_OUT : out std_logic_vector(11 downto 0); + ID_OUT : out std_logic_vector(63 downto 0); + STAT : out std_logic_vector(31 downto 0) ); end component; diff --git a/trb_net_onewire.vhd b/trb_net_onewire.vhd index 71d0c0a..8030ee4 100644 --- a/trb_net_onewire.vhd +++ b/trb_net_onewire.vhd @@ -11,7 +11,8 @@ entity trb_net_onewire is generic( USE_TEMPERATURE_READOUT : integer range 0 to 1 := 1; PARASITIC_MODE : integer range 0 to 1 := c_NO; - CLK_PERIOD : integer := 10 --clk period in ns + CLK_PERIOD : integer := 10; --clk period in ns + USEINOUT : integer := c_YES ); port( CLK : in std_logic; @@ -19,6 +20,8 @@ entity trb_net_onewire is READOUT_ENABLE_IN : in std_logic := '1'; --connection to 1-wire interface ONEWIRE : inout std_logic; + ONEWIRE_IN : in std_logic := '0'; + ONEWIRE_OUT : out std_logic := '0'; MONITOR_OUT : out std_logic; --connection to id ram, according to memory map in TrbNetRegIO DATA_OUT : out std_logic_vector(15 downto 0); @@ -62,8 +65,17 @@ architecture trb_net_onewire_arch of trb_net_onewire is signal strong_pullup, next_strong_pullup : std_logic; begin +gen_inout : if USEINOUT = c_YES generate ONEWIRE <= '0' when output = '0' else '1' when strong_pullup = '1' else 'Z'; input <= ONEWIRE; + +end generate; +gen_separate : if USEINOUT = c_NO generate + ONEWIRE_OUT <= output; + input <= ONEWIRE_IN; + ONEWIRE <= '0'; +end generate; + reset_i <= RESET when rising_edge(CLK); @@ -406,7 +418,7 @@ begin STAT(3) <= send_rom; STAT(4) <= skip_rom; STAT(5) <= conv_temp; - STAT(6) <= reading_temp; + STAT(6) <= reading_temp; --fixed, used in stand-alone 1-wire interface STAT(7) <= buf_STAT; STAT(11 downto 8) <= bitcounter_vector(3 downto 0); STAT(15 downto 12)<= state_bits; -- 2.43.0