From cbdb1a20d47e096aa42691dd6833e29a18e0859c Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Mon, 23 Mar 2009 16:44:19 +0000 Subject: [PATCH] several updates --- lattice/ecp2m/serdes/serdes_0.lpc | 18 +- lattice/ecp2m/serdes/serdes_0.pp | 10 +- lattice/ecp2m/serdes/serdes_0.readme | 4 +- lattice/ecp2m/serdes/serdes_0.sym | Bin 1892 -> 1892 bytes lattice/ecp2m/serdes/serdes_0.txt | 4 +- lattice/ecp2m/serdes/serdes_1.lpc | 18 +- lattice/ecp2m/serdes/serdes_1.pp | 10 +- lattice/ecp2m/serdes/serdes_1.readme | 4 +- lattice/ecp2m/serdes/serdes_1.sym | Bin 1892 -> 1892 bytes lattice/ecp2m/serdes/serdes_1.txt | 4 +- lattice/ecp2m/serdes/serdes_2.lpc | 26 +- lattice/ecp2m/serdes/serdes_2.pp | 12 +- lattice/ecp2m/serdes/serdes_2.readme | 4 +- lattice/ecp2m/serdes/serdes_2.sym | Bin 1892 -> 1892 bytes lattice/ecp2m/serdes/serdes_2.txt | 6 +- lattice/ecp2m/serdes/serdes_3.lpc | 18 +- lattice/ecp2m/serdes/serdes_3.pp | 10 +- lattice/ecp2m/serdes/serdes_3.readme | 4 +- lattice/ecp2m/serdes/serdes_3.sym | Bin 1892 -> 1892 bytes lattice/ecp2m/serdes/serdes_3.txt | 4 +- testbenches/testbench_all_channels_p2p.vhd | 16 +- testbenches/testbench_hublogic_ipudata.prj | 6 +- testbenches/testbench_hublogic_ipudata.vhd | 121 +++-- testbenches/trb_net16_dummy_apl.vhd | 5 +- trb_net16_api_base.vhd | 2 +- trb_net16_endpoint_hades_full.vhd | 8 +- trb_net16_hub_base.vhd | 8 +- trb_net16_hub_func.vhd | 32 +- trb_net16_hub_logic.vhd | 4 +- trb_net16_ibuf.vhd | 39 +- trb_net16_iobuf.vhd | 2 +- trb_net16_ipudata.vhd | 58 ++- trb_net16_med_ecp_sfp.vhd | 564 +++++++++++++++------ trb_net16_obuf.vhd | 10 +- trb_net16_regIO.vhd | 2 +- trb_net_std.vhd | 2 +- xilinx/virtex2/trb_net16_fifo_arch.vhd | 12 +- 37 files changed, 713 insertions(+), 334 deletions(-) diff --git a/lattice/ecp2m/serdes/serdes_0.lpc b/lattice/ecp2m/serdes/serdes_0.lpc index 26e1169..648d7c6 100644 --- a/lattice/ecp2m/serdes/serdes_0.lpc +++ b/lattice/ecp2m/serdes/serdes_0.lpc @@ -12,12 +12,12 @@ VendorName=Lattice Semiconductor Corporation CoreType=LPM CoreStatus=Demo CoreName=PCS -CoreRevision=6.0 +CoreRevision=6.1 ModuleName=serdes_0 SourceFormat=Schematic/VHDL ParameterFileVersion=1.0 -Date=02/25/2009 -Time=17:36:51 +Date=03/05/2009 +Time=17:10:39 [Parameters] Verilog=0 @@ -40,8 +40,8 @@ Rate3=None TxRefClk=CORE_TXREFCLK RxRefClk=CORE_RXREFCLK ClkRate=2 -ClkMult=10X -CalClkRate=200 +ClkMult=20X +CalClkRate=100 DataWidth=16 FPGAClkRate=100 TxRefClkCM=REFCLK @@ -50,8 +50,8 @@ RxRefClk1CM=REFCLK RxRefClk2CM=REFCLK RxRefClk3CM=REFCLK ClkRateH=1 -ClkMultH=10XH -CalClkRateH=200 +ClkMultH=20XH +CalClkRateH=100 DataWidthH=8 FPGAClkRateH=100 VCh0=0 @@ -127,6 +127,10 @@ ELSMCh0=FALSE ELSMCh1=FALSE ELSMCh2=FALSE ELSMCh3=FALSE +_teidleCh0=FALSE +_teidleCh1=FALSE +_teidleCh2=FALSE +_teidleCh3=FALSE Ports0=FALSE rdoPorts0=Serial Loopback Ports1=TRUE diff --git a/lattice/ecp2m/serdes/serdes_0.pp b/lattice/ecp2m/serdes/serdes_0.pp index 1f6f00d..66abf6d 100644 --- a/lattice/ecp2m/serdes/serdes_0.pp +++ b/lattice/ecp2m/serdes/serdes_0.pp @@ -8,8 +8,8 @@ #define _pll_txsrc "CORE_TXREFCLK" #define _pll_rxsrc "CORE_RXREFCLK" #define _datarange "MEDHIGH" -#define _refclk_mult "10X" -#define _refclk_rate 200 +#define _refclk_mult "20X" +#define _refclk_rate 100 #define _data_width "16" #define _fpgaintclk_rate 100 #define _ch0_tdrv_amp "0" @@ -76,6 +76,10 @@ #define _ch1_elsm "FALSE" #define _ch2_elsm "FALSE" #define _ch3_elsm "FALSE" +#define _ch0_teidle "FALSE" +#define _ch1_teidle "FALSE" +#define _ch2_teidle "FALSE" +#define _ch3_teidle "FALSE" #define _loopback "FALSE" #define _lbtype "Serial Loopback" #define _refck2core "FALSE" @@ -88,4 +92,4 @@ #define _lang vhdl #include -#include +#include diff --git a/lattice/ecp2m/serdes/serdes_0.readme b/lattice/ecp2m/serdes/serdes_0.readme index 55f0eb5..4b95885 100644 --- a/lattice/ecp2m/serdes/serdes_0.readme +++ b/lattice/ecp2m/serdes/serdes_0.readme @@ -5,8 +5,8 @@ MODULE: serdes_0 DESIGN: serdes_0 FILENAME: serdes_0.readme - PROJECT: - VERSION: 1.0 + PROJECT: Unknown + VERSION: 2.0 This file is auto generated by the ispLEVER diff --git a/lattice/ecp2m/serdes/serdes_0.sym b/lattice/ecp2m/serdes/serdes_0.sym index 5192c5083d3ff55cfe70ba4ccae9568d3dd85ef0..f890a3ce155242c6f36cd62c7b852f81209592bf 100644 GIT binary patch delta 15 WcmaFD_k@paO?YVITcwR`aqIvzbOrAK delta 15 WcmaFD_k@paP57*qw=x^q;@AN;lLj#W diff --git a/lattice/ecp2m/serdes/serdes_0.txt b/lattice/ecp2m/serdes/serdes_0.txt index 0be44d3..8d2d4b4 100644 --- a/lattice/ecp2m/serdes/serdes_0.txt +++ b/lattice/ecp2m/serdes/serdes_0.txt @@ -14,8 +14,8 @@ PLL_SRC "CORE_TXREFCLK" DATARANGE "MEDHIGH" CH0_CDR_SRC "CORE_RXREFCLK" CH0_DATA_WIDTH "16" -CH0_REFCK_MULT "10X" -#REFCLK_RATE 200 +CH0_REFCK_MULT "20X" +#REFCLK_RATE 100 #FPGAINTCLK_RATE 100 CH0_TDRV_AMP "0" CH0_TX_PRE "DISABLE" diff --git a/lattice/ecp2m/serdes/serdes_1.lpc b/lattice/ecp2m/serdes/serdes_1.lpc index 1dd60ec..23f74f0 100644 --- a/lattice/ecp2m/serdes/serdes_1.lpc +++ b/lattice/ecp2m/serdes/serdes_1.lpc @@ -12,12 +12,12 @@ VendorName=Lattice Semiconductor Corporation CoreType=LPM CoreStatus=Demo CoreName=PCS -CoreRevision=6.0 +CoreRevision=6.1 ModuleName=serdes_1 SourceFormat=Schematic/VHDL ParameterFileVersion=1.0 -Date=02/25/2009 -Time=17:38:13 +Date=03/05/2009 +Time=15:10:13 [Parameters] Verilog=0 @@ -40,8 +40,8 @@ Rate3=None TxRefClk=CORE_TXREFCLK RxRefClk=CORE_RXREFCLK ClkRate=2 -ClkMult=10X -CalClkRate=200 +ClkMult=20X +CalClkRate=100 DataWidth=16 FPGAClkRate=100 TxRefClkCM=REFCLK @@ -50,8 +50,8 @@ RxRefClk1CM=REFCLK RxRefClk2CM=REFCLK RxRefClk3CM=REFCLK ClkRateH=1 -ClkMultH=10XH -CalClkRateH=200 +ClkMultH=20XH +CalClkRateH=100 DataWidthH=8 FPGAClkRateH=100 VCh0=0 @@ -127,6 +127,10 @@ ELSMCh0=FALSE ELSMCh1=FALSE ELSMCh2=FALSE ELSMCh3=FALSE +_teidleCh0=FALSE +_teidleCh1=FALSE +_teidleCh2=FALSE +_teidleCh3=FALSE Ports0=FALSE rdoPorts0=Serial Loopback Ports1=TRUE diff --git a/lattice/ecp2m/serdes/serdes_1.pp b/lattice/ecp2m/serdes/serdes_1.pp index 3077b75..683c118 100644 --- a/lattice/ecp2m/serdes/serdes_1.pp +++ b/lattice/ecp2m/serdes/serdes_1.pp @@ -8,8 +8,8 @@ #define _pll_txsrc "CORE_TXREFCLK" #define _pll_rxsrc "CORE_RXREFCLK" #define _datarange "MEDHIGH" -#define _refclk_mult "10X" -#define _refclk_rate 200 +#define _refclk_mult "20X" +#define _refclk_rate 100 #define _data_width "16" #define _fpgaintclk_rate 100 #define _ch0_tdrv_amp "0" @@ -76,6 +76,10 @@ #define _ch1_elsm "FALSE" #define _ch2_elsm "FALSE" #define _ch3_elsm "FALSE" +#define _ch0_teidle "FALSE" +#define _ch1_teidle "FALSE" +#define _ch2_teidle "FALSE" +#define _ch3_teidle "FALSE" #define _loopback "FALSE" #define _lbtype "Serial Loopback" #define _refck2core "FALSE" @@ -88,4 +92,4 @@ #define _lang vhdl #include -#include +#include diff --git a/lattice/ecp2m/serdes/serdes_1.readme b/lattice/ecp2m/serdes/serdes_1.readme index 74ba449..b9f50bb 100644 --- a/lattice/ecp2m/serdes/serdes_1.readme +++ b/lattice/ecp2m/serdes/serdes_1.readme @@ -5,8 +5,8 @@ MODULE: serdes_1 DESIGN: serdes_1 FILENAME: serdes_1.readme - PROJECT: - VERSION: 1.0 + PROJECT: Unknown + VERSION: 2.0 This file is auto generated by the ispLEVER diff --git a/lattice/ecp2m/serdes/serdes_1.sym b/lattice/ecp2m/serdes/serdes_1.sym index 96f5b73fbdb85b7b64af706e957c82872353cced..941e30360305cd8bb3aee68c8731503a41c64778 100644 GIT binary patch delta 15 WcmaFD_k@paO}IzlTcwR`aqIvyoCVSV delta 15 WcmaFD_k@paP5AMaw=x^q;@AN<`vzVB diff --git a/lattice/ecp2m/serdes/serdes_1.txt b/lattice/ecp2m/serdes/serdes_1.txt index 396d538..774bd75 100644 --- a/lattice/ecp2m/serdes/serdes_1.txt +++ b/lattice/ecp2m/serdes/serdes_1.txt @@ -14,8 +14,8 @@ PLL_SRC "CORE_TXREFCLK" DATARANGE "MEDHIGH" CH1_CDR_SRC "CORE_RXREFCLK" CH1_DATA_WIDTH "16" -CH1_REFCK_MULT "10X" -#REFCLK_RATE 200 +CH1_REFCK_MULT "20X" +#REFCLK_RATE 100 #FPGAINTCLK_RATE 100 CH1_TDRV_AMP "0" CH1_TX_PRE "DISABLE" diff --git a/lattice/ecp2m/serdes/serdes_2.lpc b/lattice/ecp2m/serdes/serdes_2.lpc index f09a30a..baf0deb 100644 --- a/lattice/ecp2m/serdes/serdes_2.lpc +++ b/lattice/ecp2m/serdes/serdes_2.lpc @@ -1,10 +1,10 @@ [Device] Family=latticeecp2m -PartType=LFE2M100E -PartName=LFE2M100E-5F1152I +PartType=LFE2M35E +PartName=LFE2M35E-5F672C SpeedGrade=-5 -Package=FPBGA1152 -OperatingCondition=IND +Package=FPBGA672 +OperatingCondition=COM Status=P [IP] @@ -12,12 +12,12 @@ VendorName=Lattice Semiconductor Corporation CoreType=LPM CoreStatus=Demo CoreName=PCS -CoreRevision=6.0 +CoreRevision=6.1 ModuleName=serdes_2 SourceFormat=Schematic/VHDL ParameterFileVersion=1.0 -Date=02/25/2009 -Time=17:34:07 +Date=03/05/2009 +Time=15:36:10 [Parameters] Verilog=0 @@ -40,8 +40,8 @@ Rate3=None TxRefClk=CORE_TXREFCLK RxRefClk=CORE_RXREFCLK ClkRate=2 -ClkMult=10X -CalClkRate=200 +ClkMult=20X +CalClkRate=100 DataWidth=16 FPGAClkRate=100 TxRefClkCM=REFCLK @@ -50,8 +50,8 @@ RxRefClk1CM=REFCLK RxRefClk2CM=REFCLK RxRefClk3CM=REFCLK ClkRateH=1 -ClkMultH=10XH -CalClkRateH=200 +ClkMultH=20XH +CalClkRateH=100 DataWidthH=8 FPGAClkRateH=100 VCh0=0 @@ -127,6 +127,10 @@ ELSMCh0=FALSE ELSMCh1=FALSE ELSMCh2=FALSE ELSMCh3=FALSE +_teidleCh0=FALSE +_teidleCh1=FALSE +_teidleCh2=FALSE +_teidleCh3=FALSE Ports0=FALSE rdoPorts0=Serial Loopback Ports1=TRUE diff --git a/lattice/ecp2m/serdes/serdes_2.pp b/lattice/ecp2m/serdes/serdes_2.pp index df8bf66..a074848 100644 --- a/lattice/ecp2m/serdes/serdes_2.pp +++ b/lattice/ecp2m/serdes/serdes_2.pp @@ -1,4 +1,4 @@ -#define _device_name "LFE2M100E" +#define _device_name "LFE2M35E" #define _protocol_mode "Quad Based Protocol Mode" #define _protocol "G8B10B" #define _ch0_mode "DISABLE" @@ -8,8 +8,8 @@ #define _pll_txsrc "CORE_TXREFCLK" #define _pll_rxsrc "CORE_RXREFCLK" #define _datarange "MEDHIGH" -#define _refclk_mult "10X" -#define _refclk_rate 200 +#define _refclk_mult "20X" +#define _refclk_rate 100 #define _data_width "16" #define _fpgaintclk_rate 100 #define _ch0_tdrv_amp "0" @@ -76,6 +76,10 @@ #define _ch1_elsm "FALSE" #define _ch2_elsm "FALSE" #define _ch3_elsm "FALSE" +#define _ch0_teidle "FALSE" +#define _ch1_teidle "FALSE" +#define _ch2_teidle "FALSE" +#define _ch3_teidle "FALSE" #define _loopback "FALSE" #define _lbtype "Serial Loopback" #define _refck2core "FALSE" @@ -88,4 +92,4 @@ #define _lang vhdl #include -#include +#include diff --git a/lattice/ecp2m/serdes/serdes_2.readme b/lattice/ecp2m/serdes/serdes_2.readme index b0a982b..9330ce7 100644 --- a/lattice/ecp2m/serdes/serdes_2.readme +++ b/lattice/ecp2m/serdes/serdes_2.readme @@ -5,8 +5,8 @@ MODULE: serdes_2 DESIGN: serdes_2 FILENAME: serdes_2.readme - PROJECT: - VERSION: 1.0 + PROJECT: Unknown + VERSION: 2.0 This file is auto generated by the ispLEVER diff --git a/lattice/ecp2m/serdes/serdes_2.sym b/lattice/ecp2m/serdes/serdes_2.sym index e188781c4391aa7323d08119ef7a0f18fd49ff09..8b2c0372b6911d4f32645cec70237a11ea4f6be5 100644 GIT binary patch delta 15 WcmaFD_k@paO?X?$TcwR`aqIv!p#~EG delta 15 WcmaFD_k@paO}I -#include +#include diff --git a/lattice/ecp2m/serdes/serdes_3.readme b/lattice/ecp2m/serdes/serdes_3.readme index ce5c6b5..3c42ae3 100644 --- a/lattice/ecp2m/serdes/serdes_3.readme +++ b/lattice/ecp2m/serdes/serdes_3.readme @@ -5,8 +5,8 @@ MODULE: serdes_3 DESIGN: serdes_3 FILENAME: serdes_3.readme - PROJECT: - VERSION: 1.0 + PROJECT: Unknown + VERSION: 2.0 This file is auto generated by the ispLEVER diff --git a/lattice/ecp2m/serdes/serdes_3.sym b/lattice/ecp2m/serdes/serdes_3.sym index 150cd206ab58f214c4801b787f73ebcb57b31123..840729c6f5890fd69c20eea6277497bc86d1365b 100644 GIT binary patch delta 15 WcmaFD_k@paO?XJ*TcwR`aqIvy`~}_s delta 15 WcmaFD_k@paP59%Mw=x^q;@AN=+Xi|7 diff --git a/lattice/ecp2m/serdes/serdes_3.txt b/lattice/ecp2m/serdes/serdes_3.txt index 2c0c71c..9bb337d 100644 --- a/lattice/ecp2m/serdes/serdes_3.txt +++ b/lattice/ecp2m/serdes/serdes_3.txt @@ -14,8 +14,8 @@ PLL_SRC "CORE_TXREFCLK" DATARANGE "MEDHIGH" CH3_CDR_SRC "CORE_RXREFCLK" CH3_DATA_WIDTH "16" -CH3_REFCK_MULT "10X" -#REFCLK_RATE 200 +CH3_REFCK_MULT "20X" +#REFCLK_RATE 100 #FPGAINTCLK_RATE 100 CH3_TDRV_AMP "0" CH3_TX_PRE "DISABLE" diff --git a/testbenches/testbench_all_channels_p2p.vhd b/testbenches/testbench_all_channels_p2p.vhd index b00e3cd..4cdc2ca 100644 --- a/testbenches/testbench_all_channels_p2p.vhd +++ b/testbenches/testbench_all_channels_p2p.vhd @@ -83,7 +83,7 @@ architecture testbench_arch of testbench is IBUF_DEPTH : channel_config_t := (6,6,6,6); FIFO_TO_INT_DEPTH : channel_config_t := (6,6,6,6); FIFO_TO_APL_DEPTH : channel_config_t := (6,6,6,6); - IBUF_SECURE_MODE : channel_config_t := (c_YES,c_YES,c_YES,c_YES); + IBUF_SECURE_MODE : channel_config_t := (c_YES,c_YES,c_YES,c_NO); API_SECURE_MODE_TO_APL : channel_config_t := (c_YES,c_YES,c_YES,c_YES); API_SECURE_MODE_TO_INT : channel_config_t := (c_YES,c_YES,c_YES,c_YES); OBUF_DATA_COUNT_WIDTH : integer range 0 to 7 := std_DATA_COUNT_WIDTH; @@ -676,6 +676,20 @@ IPU_ERROR_PATTERN_IN <= (others => '0'); APL_ERROR_PATTERN_IN(95 downto 64) <= (others => '0'); + REGIO_NO_MORE_DATA_IN <= '0'; + PROC_REGIO : process(CLK) + begin + if rising_edge(CLK) then + if REGIO_WRITE_ENABLE_OUT = '1' then + if REGIO_ADDR_OUT = x"8001" then + REGIO_UNKNOWN_ADDR_IN <= '1'; + else + REGIO_UNKNOWN_ADDR_IN <= '0'; + end if; + end if; + end if; + end process; + process(CLK) begin if rising_edge(CLK) then diff --git a/testbenches/testbench_hublogic_ipudata.prj b/testbenches/testbench_hublogic_ipudata.prj index b4f47ca..21f6743 100644 --- a/testbenches/testbench_hublogic_ipudata.prj +++ b/testbenches/testbench_hublogic_ipudata.prj @@ -28,8 +28,8 @@ vhdl work "../trb_net16_ipudata.vhd" -- vhdl work "../trb_net16_endpoint_hades_full.vhd" -- vhdl work "../trb_net16_endpoint_active_4_channel.vhd" -- vhdl work "../trb_net_med_8bit_slow.vhd" -vhdl work "../trb_net16_hub_func.vhd" +--vhdl work "../trb_net16_hub_func.vhd" -- vhdl work "../trb_net16_hub_base.vhd" -vhdl work "../basics/wide_adder_17x16.vhd" -vhdl work "../trb_net16_hub_ipu_logic.vhd" +--vhdl work "../basics/wide_adder_17x16.vhd" +--vhdl work "../trb_net16_hub_ipu_logic.vhd" vhdl work "testbench_hublogic_ipudata.vhd" \ No newline at end of file diff --git a/testbenches/testbench_hublogic_ipudata.vhd b/testbenches/testbench_hublogic_ipudata.vhd index 7955041..db855bd 100644 --- a/testbenches/testbench_hublogic_ipudata.vhd +++ b/testbenches/testbench_hublogic_ipudata.vhd @@ -193,7 +193,7 @@ architecture testbench_arch of testbench is API_RUN_IN : in std_logic; API_SEQNR_IN : in std_logic_vector (7 downto 0); API_LENGTH_OUT : out std_logic_vector (15 downto 0); - + MY_ADDRESS_IN : in std_logic_vector (15 downto 0); --Information received with request IPU_NUMBER_OUT : out std_logic_vector (15 downto 0); IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0); @@ -280,38 +280,38 @@ begin CLK_EN <= '1'; - THE_HUB_LOGIC : trb_net16_hub_ipu_logic - port map( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - - --Internal interfaces to IOBufs - INIT_DATAREADY_IN => INIT_DATAREADY_IN, - INIT_DATA_IN => INIT_DATA_IN, - INIT_PACKET_NUM_IN => INIT_PACKET_NUM_IN, - INIT_READ_OUT => INIT_READ_OUT, - - INIT_DATAREADY_OUT => INIT_DATAREADY_OUT, - INIT_DATA_OUT => INIT_DATA_OUT, - INIT_PACKET_NUM_OUT => INIT_PACKET_NUM_OUT, - INIT_READ_IN => INIT_READ_IN, - - REPLY_DATAREADY_IN => REPLY_DATAREADY_IN, - REPLY_DATA_IN => REPLY_DATA_IN, - REPLY_PACKET_NUM_IN => REPLY_PACKET_NUM_IN, - REPLY_READ_OUT => REPLY_READ_OUT, - - REPLY_DATAREADY_OUT => REPLY_DATAREADY_OUT, - REPLY_DATA_OUT => REPLY_DATA_OUT, - REPLY_PACKET_NUM_OUT => REPLY_PACKET_NUM_OUT, - REPLY_READ_IN => REPLY_READ_IN, - - MY_ADDRESS_IN => x"F00E", - --Status ports - CTRL => (others => '0'), - CTRL_activepoints => (others => '1') - ); +-- THE_HUB_LOGIC : trb_net16_hub_ipu_logic +-- port map( +-- CLK => CLK, +-- RESET => RESET, +-- CLK_EN => CLK_EN, +-- +-- --Internal interfaces to IOBufs +-- INIT_DATAREADY_IN => INIT_DATAREADY_IN, +-- INIT_DATA_IN => INIT_DATA_IN, +-- INIT_PACKET_NUM_IN => INIT_PACKET_NUM_IN, +-- INIT_READ_OUT => INIT_READ_OUT, +-- +-- INIT_DATAREADY_OUT => INIT_DATAREADY_OUT, +-- INIT_DATA_OUT => INIT_DATA_OUT, +-- INIT_PACKET_NUM_OUT => INIT_PACKET_NUM_OUT, +-- INIT_READ_IN => INIT_READ_IN, +-- +-- REPLY_DATAREADY_IN => REPLY_DATAREADY_IN, +-- REPLY_DATA_IN => REPLY_DATA_IN, +-- REPLY_PACKET_NUM_IN => REPLY_PACKET_NUM_IN, +-- REPLY_READ_OUT => REPLY_READ_OUT, +-- +-- REPLY_DATAREADY_OUT => REPLY_DATAREADY_OUT, +-- REPLY_DATA_OUT => REPLY_DATA_OUT, +-- REPLY_PACKET_NUM_OUT => REPLY_PACKET_NUM_OUT, +-- REPLY_READ_IN => REPLY_READ_IN, +-- +-- MY_ADDRESS_IN => x"F00E", +-- --Status ports +-- CTRL => (others => '0'), +-- CTRL_activepoints => (others => '1') +-- ); THE_ACTIVE_API : trb_net16_api_base generic map( @@ -340,28 +340,44 @@ begin APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN(15 downto 0), APL_SEQNR_OUT => APL_SEQNR_OUT(7 downto 0), APL_LENGTH_IN => APL_LENGTH_IN(15 downto 0), - INT_MASTER_DATAREADY_OUT => INIT_DATAREADY_IN(0), - INT_MASTER_DATA_OUT => INIT_DATA_IN(c_DATA_WIDTH-1 downto 0), - INT_MASTER_PACKET_NUM_OUT => INIT_PACKET_NUM_IN(c_NUM_WIDTH-1 downto 0), - INT_MASTER_READ_IN => INIT_READ_OUT(0), - INT_MASTER_DATAREADY_IN => INIT_DATAREADY_OUT(0), - INT_MASTER_DATA_IN => INIT_DATA_OUT(15 downto 0), - INT_MASTER_PACKET_NUM_IN => INIT_PACKET_NUM_OUT(c_NUM_WIDTH-1 downto 0), - INT_MASTER_READ_OUT => INIT_READ_IN(0), - INT_SLAVE_DATAREADY_OUT => REPLY_DATAREADY_IN(0), - INT_SLAVE_DATA_OUT => REPLY_DATA_IN(c_DATA_WIDTH-1 downto 0), - INT_SLAVE_PACKET_NUM_OUT => REPLY_PACKET_NUM_IN(c_NUM_WIDTH-1 downto 0), - INT_SLAVE_READ_IN => REPLY_READ_OUT(0), - INT_SLAVE_DATAREADY_IN => REPLY_DATAREADY_OUT(0), - INT_SLAVE_DATA_IN => REPLY_DATA_OUT(15 downto 0), - INT_SLAVE_PACKET_NUM_IN => REPLY_PACKET_NUM_OUT(c_NUM_WIDTH-1 downto 0), - INT_SLAVE_READ_OUT => REPLY_READ_IN(0) +-- INT_MASTER_DATAREADY_OUT => INIT_DATAREADY_IN(0), +-- INT_MASTER_DATA_OUT => INIT_DATA_IN(c_DATA_WIDTH-1 downto 0), +-- INT_MASTER_PACKET_NUM_OUT => INIT_PACKET_NUM_IN(c_NUM_WIDTH-1 downto 0), +-- INT_MASTER_READ_IN => INIT_READ_OUT(0), +-- INT_MASTER_DATAREADY_IN => INIT_DATAREADY_OUT(0), +-- INT_MASTER_DATA_IN => INIT_DATA_OUT(15 downto 0), +-- INT_MASTER_PACKET_NUM_IN => INIT_PACKET_NUM_OUT(c_NUM_WIDTH-1 downto 0), +-- INT_MASTER_READ_OUT => INIT_READ_IN(0), +-- INT_SLAVE_DATAREADY_OUT => REPLY_DATAREADY_IN(0), +-- INT_SLAVE_DATA_OUT => REPLY_DATA_IN(c_DATA_WIDTH-1 downto 0), +-- INT_SLAVE_PACKET_NUM_OUT => REPLY_PACKET_NUM_IN(c_NUM_WIDTH-1 downto 0), +-- INT_SLAVE_READ_IN => REPLY_READ_OUT(0), +-- INT_SLAVE_DATAREADY_IN => REPLY_DATAREADY_OUT(0), +-- INT_SLAVE_DATA_IN => REPLY_DATA_OUT(15 downto 0), +-- INT_SLAVE_PACKET_NUM_IN => REPLY_PACKET_NUM_OUT(c_NUM_WIDTH-1 downto 0), +-- INT_SLAVE_READ_OUT => REPLY_READ_IN(0) + INT_MASTER_DATAREADY_OUT => INIT_DATAREADY_OUT(1), + INT_MASTER_DATA_OUT => INIT_DATA_OUT(31 downto 16), + INT_MASTER_PACKET_NUM_OUT => INIT_PACKET_NUM_OUT(5 downto 3), + INT_MASTER_READ_IN => INIT_READ_IN(1), + INT_MASTER_DATAREADY_IN => INIT_DATAREADY_IN(1), + INT_MASTER_DATA_IN => INIT_DATA_IN(31 downto 16), + INT_MASTER_PACKET_NUM_IN => INIT_PACKET_NUM_IN(5 downto 3), + INT_MASTER_READ_OUT => INIT_READ_OUT(1), + INT_SLAVE_DATAREADY_OUT => REPLY_DATAREADY_OUT(1), + INT_SLAVE_DATA_OUT => REPLY_DATA_OUT(31 downto 16), + INT_SLAVE_PACKET_NUM_OUT => REPLY_PACKET_NUM_OUT(5 downto 3), + INT_SLAVE_READ_IN => REPLY_READ_IN(1), + INT_SLAVE_DATAREADY_IN => REPLY_DATAREADY_IN(1), + INT_SLAVE_DATA_IN => REPLY_DATA_IN(31 downto 16), + INT_SLAVE_PACKET_NUM_IN => REPLY_PACKET_NUM_IN(5 downto 3), + INT_SLAVE_READ_OUT => REPLY_READ_OUT(1) ); REPLY_DATAREADY_IN(0) <= '0'; - gen_passive_apis : for i in 1 to 3 generate + gen_passive_apis : for i in 1 to 1 generate A_PASSIVE_API : trb_net16_api_base generic map( API_TYPE => c_API_PASSIVE @@ -448,7 +464,7 @@ APL_DATAREADY_IN(0) <= '0'; APL_SEND_IN(0) <= not APL_RUN_OUT(0); - gen_ipudatas : for i in 1 to 3 generate + gen_ipudatas : for i in 1 to 1 generate A_IPUDATA : trb_net16_ipudata port map( CLK => CLK, @@ -472,6 +488,7 @@ APL_SEND_IN(0) <= not APL_RUN_OUT(0); API_RUN_IN => APL_RUN_OUT(i), API_SEQNR_IN => APL_SEQNR_OUT((i+1)*8-1 downto i*8), API_LENGTH_OUT => APL_LENGTH_IN((i+1)*16-1 downto i*16), + MY_ADDRESS_IN => x"F00E", --Information received with request IPU_NUMBER_OUT => IPU_NUMBER_OUT((i+1)*16-1 downto i*16), IPU_INFORMATION_OUT => IPU_INFORMATION_OUT((i+1)*8-1 downto i*8), @@ -519,7 +536,7 @@ APL_SEND_IN(0) <= not APL_RUN_OUT(0); counter(i) <= 1; end if; IPU_DATAREADY_IN(i) <= '1'; - IPU_LENGTH_IN((i*16+15) downto i*16) <= std_logic_vector(to_unsigned(i+2,16)); + IPU_LENGTH_IN((i*16+15) downto i*16) <= std_logic_vector(to_unsigned(i,16)); IPU_DATA_IN((i*32+31) downto i*32) <= "0001100101010101" & x"EFE0"; end if; when 2 => diff --git a/testbenches/trb_net16_dummy_apl.vhd b/testbenches/trb_net16_dummy_apl.vhd index 20ac555..20f588f 100644 --- a/testbenches/trb_net16_dummy_apl.vhd +++ b/testbenches/trb_net16_dummy_apl.vhd @@ -66,12 +66,11 @@ begin -- reghigh <= x"DEAD"; -- reglow <= x"AFFE"; reg_F0 <= x"5e1d"; --x"0001"; - reg_F1 <= x"0000"; reg_F2 <= x"0000";--xor_all(APL_DATA_IN) & "000000000000011"; reg_F3 <= x"0000"; APL_DTYPE_OUT <= x"F"; - APL_TARGET_ADDRESS_OUT <= TARGET_ADDRESS; + APL_TARGET_ADDRESS_OUT <= x"ffff"; --TARGET_ADDRESS; process(current_state) begin @@ -83,7 +82,7 @@ begin end case; end process; - APL_READ_OUT <= '1'; --just read, do not check + APL_READ_OUT <= '0', '1' after 4ns; --just read, do not check APL_ERROR_PATTERN_OUT <= x"12345678"; --APL_DATA_OUT <= reg_counter; diff --git a/trb_net16_api_base.vhd b/trb_net16_api_base.vhd index e374692..19fac2f 100644 --- a/trb_net16_api_base.vhd +++ b/trb_net16_api_base.vhd @@ -698,7 +698,7 @@ INT_MASTER_DATAREADY_OUT <= buf_INT_MASTER_DATAREADY_OUT; fifo_to_apl_long_packet_num_out, state_to_apl, reg_APL_TYP_OUT, reg_APL_PACKET_NUM_OUT, sbuf_to_apl_free, INT_SLAVE_DATA_IN, INT_SLAVE_PACKET_NUM_IN, APL_MY_ADDRESS_IN, reg_APL_DATAREADY_OUT, slave_running, fifo_to_apl_read_before, throw_away,state_to_int, - saved_fifo_to_apl_packet_type,master_start) + saved_fifo_to_apl_packet_type,master_start, last_fifo_to_apl_read) begin reg_INT_SLAVE_READ_OUT <= not fifo_to_apl_full; fifo_to_apl_write <= reg_INT_SLAVE_READ_OUT and INT_SLAVE_DATAREADY_IN; diff --git a/trb_net16_endpoint_hades_full.vhd b/trb_net16_endpoint_hades_full.vhd index 1c7487e..85fef06 100644 --- a/trb_net16_endpoint_hades_full.vhd +++ b/trb_net16_endpoint_hades_full.vhd @@ -12,9 +12,9 @@ use work.trb_net_std.all; entity trb_net16_endpoint_hades_full is generic ( USE_CHANNEL : channel_config_t := (c_YES,c_YES,c_NO,c_YES); - IBUF_DEPTH : channel_config_t := (6,6,6,6); + IBUF_DEPTH : channel_config_t := (1,6,6,6); FIFO_TO_INT_DEPTH : channel_config_t := (6,6,6,6); - FIFO_TO_APL_DEPTH : channel_config_t := (6,6,6,6); + FIFO_TO_APL_DEPTH : channel_config_t := (1,1,1,1); IBUF_SECURE_MODE : channel_config_t := (c_YES,c_YES,c_YES,c_YES); API_SECURE_MODE_TO_APL : channel_config_t := (c_YES,c_YES,c_YES,c_YES); API_SECURE_MODE_TO_INT : channel_config_t := (c_YES,c_YES,c_YES,c_YES); @@ -145,6 +145,7 @@ architecture trb_net16_endpoint_hades_full_arch of trb_net16_endpoint_hades_full RESET : in std_logic; --connection to 1-wire interface ONEWIRE : inout std_logic; + MONITOR_OUT : out std_logic; --connection to id ram, according to memory map in TrbNetRegIO DATA_OUT : out std_logic_vector(15 downto 0); ADDR_OUT : out std_logic_vector(2 downto 0); @@ -495,6 +496,7 @@ architecture trb_net16_endpoint_hades_full_arch of trb_net16_endpoint_hades_full API_RUN_IN : in std_logic; API_SEQNR_IN : in std_logic_vector (7 downto 0); API_LENGTH_OUT : out std_logic_vector (15 downto 0); + MY_ADDRESS_IN : in std_logic_vector (15 downto 0); --Information received with request IPU_NUMBER_OUT : out std_logic_vector (15 downto 0); @@ -804,6 +806,7 @@ begin API_RUN_IN => buf_APL_RUN_OUT(i), API_SEQNR_IN => buf_APL_SEQNR_OUT((i+1)*8-1 downto i*8), API_LENGTH_OUT => buf_APL_LENGTH_IN((i+1)*16-1 downto i*16), + MY_ADDRESS_IN => MY_ADDRESS, --Information received with request IPU_NUMBER_OUT => IPU_NUMBER_OUT, IPU_INFORMATION_OUT => IPU_INFORMATION_OUT, @@ -919,6 +922,7 @@ begin RESET => RESET, --connection to 1-wire interface ONEWIRE => REGIO_ONEWIRE_INOUT, + MONITOR_OUT => open, --connection to id ram, according to memory map in TrbNetRegIO DATA_OUT => buf_IDRAM_DATA_IN, ADDR_OUT => buf_IDRAM_ADDR_IN, diff --git a/trb_net16_hub_base.vhd b/trb_net16_hub_base.vhd index 6a612ce..5934b3c 100644 --- a/trb_net16_hub_base.vhd +++ b/trb_net16_hub_base.vhd @@ -11,8 +11,8 @@ entity trb_net16_hub_base is --hub control HUB_CTRL_CHANNELNUM : integer range 0 to 3 := c_SLOW_CTRL_CHANNEL; HUB_CTRL_DEPTH : integer range 0 to 6 := c_FIFO_BRAM; - HUB_USED_CHANNELS : hub_channel_config_t := (c_YES,c_YES,c_YES,c_YES); - USE_CHECKSUM : hub_channel_config_t := (c_YES,c_YES,c_YES,c_YES); + HUB_USED_CHANNELS : hub_channel_config_t := (c_YES,c_YES,c_NO,c_YES); + USE_CHECKSUM : hub_channel_config_t := (c_NO,c_YES,c_YES,c_YES); USE_VENDOR_CORES : integer range 0 to 1 := c_YES; IBUF_SECURE_MODE : integer range 0 to 1 := c_NO; INIT_ADDRESS : std_logic_vector(15 downto 0) := x"F004"; @@ -21,7 +21,7 @@ entity trb_net16_hub_base is COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; --media interfaces - MII_NUMBER : integer range 2 to c_MAX_MII_PER_HUB := 4; + MII_NUMBER : integer range 2 to c_MAX_MII_PER_HUB := 3; MII_IBUF_DEPTH : hub_iobuf_config_t := std_HUB_IBUF_DEPTH; -- settings for external api connections INT_NUMBER : integer range 0 to c_MAX_API_PER_HUB := 0; @@ -242,6 +242,7 @@ architecture trb_net16_hub_base_arch of trb_net16_hub_base is REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); REPLY_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); + MY_ADDRESS_IN : in std_logic_vector (15 downto 0); --Status ports STAT_DEBUG : out std_logic_vector (31 downto 0); STAT_POINTS_locked : out std_logic_vector (31 downto 0); @@ -996,6 +997,7 @@ HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1'); REPLY_DATA_OUT => HUB_REPLY_DATA_OUT(next_point_num*c_DATA_WIDTH-1 downto first_point_num*c_DATA_WIDTH), REPLY_PACKET_NUM_OUT => HUB_REPLY_PACKET_NUM_OUT(next_point_num*c_NUM_WIDTH-1 downto first_point_num*c_NUM_WIDTH), REPLY_READ_IN => HUB_REPLY_READ_IN(next_point_num-1 downto first_point_num), + MY_ADDRESS_IN => HUB_ADDRESS, STAT_DEBUG => HUBLOGIC_IPU_STAT_DEBUG(31 downto 0), STAT_POINTS_locked => buf_STAT_POINTS_locked((i+1)*32-1 downto i*32), STAT_ERRORBITS => open, diff --git a/trb_net16_hub_func.vhd b/trb_net16_hub_func.vhd index 7a4f3c8..f23da94 100644 --- a/trb_net16_hub_func.vhd +++ b/trb_net16_hub_func.vhd @@ -18,22 +18,22 @@ package trb_net16_hub_func is constant c_MAX_TRG_PER_HUB : integer := 8; constant c_MAX_POINTS_PER_HUB : integer := 18; - constant std_HUB_IBUF_DEPTH : hub_iobuf_config_t :=( 6,6,6,6, --MII 0 - 6,6,6,6, - 6,6,6,6, - 6,6,6,6, - 6,6,6,6, - 6,6,6,6, - 6,6,6,6, - 6,6,6,6, - 6,6,6,6, - 6,6,6,6, - 6,6,6,6, - 6,6,6,6, - 6,6,6,6, - 6,6,6,6, - 6,6,6,6, - 6,6,6,6); --MII 15 + constant std_HUB_IBUF_DEPTH : hub_iobuf_config_t :=( 1,6,6,6, --MII 0 + 1,6,6,6, + 1,6,6,6, + 1,6,6,6, + 1,6,6,6, + 1,6,6,6, + 1,6,6,6, + 1,6,6,6, + 1,6,6,6, + 1,6,6,6, + 1,6,6,6, + 1,6,6,6, + 1,6,6,6, + 1,6,6,6, + 1,6,6,6, + 1,6,6,6); --MII 15 function calc_point_number (MII_NUMBER : integer; CHANNEL : integer; diff --git a/trb_net16_hub_logic.vhd b/trb_net16_hub_logic.vhd index 179eddd..908bdb2 100644 --- a/trb_net16_hub_logic.vhd +++ b/trb_net16_hub_logic.vhd @@ -85,7 +85,7 @@ architecture trb_net16_hub_logic_arch of trb_net16_hub_logic is ); end component; - component trb_net_ram_dp + component ram_dp generic( depth : integer := 3; width : integer := 16 @@ -417,7 +417,7 @@ STAT_ERRORBITS <= REPLY_combined_trm_F1 & REPLY_combined_trm_F2; current_REPLY_reading_hdr <= next_REPLY_reading_hdr or REPLY_reading_hdr; gen_saving_hdr : for i in 0 to POINT_NUMBER-1 generate - last_HDR_RAM : trb_net_ram_dp + last_HDR_RAM : ram_dp generic map( depth => 3, width => 16 diff --git a/trb_net16_ibuf.vhd b/trb_net16_ibuf.vhd index 11892cd..bd9c72f 100644 --- a/trb_net16_ibuf.vhd +++ b/trb_net16_ibuf.vhd @@ -47,6 +47,7 @@ entity trb_net16_ibuf is end entity; architecture trb_net16_ibuf_arch of trb_net16_ibuf is + component trb_net_CRC is port( CLK : in std_logic; @@ -57,6 +58,7 @@ architecture trb_net16_ibuf_arch of trb_net16_ibuf is CRC_match : out std_logic ); end component; + component trb_net16_fifo is generic ( USE_VENDOR_CORES : integer range 0 to 1 := c_NO; @@ -138,6 +140,7 @@ architecture trb_net16_ibuf_arch of trb_net16_ibuf is signal CRC_RESET, CRC_enable : std_logic; signal CRC_match : std_logic; signal crc_out : std_logic_vector(15 downto 0); + signal crc_active: std_logic; --crc active in this transfer, i.e. no short transfer signal last_fifo_read : std_logic; signal throw_away : std_logic; @@ -221,7 +224,7 @@ counter_match <= '1'; else saved_fifo_packet_type; gen_crc : if USE_CHECKSUM = 1 generate - CRC_gen : trb_net_CRC + THE_CRC : trb_net_CRC port map( CLK => CLK, RESET => CRC_RESET, @@ -230,18 +233,37 @@ counter_match <= '1'; CRC_OUT => crc_out, CRC_match => CRC_match ); + process(last_fifo_read, fifo_long_packet_num_out, current_fifo_packet_type) begin - CRC_enable <= last_fifo_read and not fifo_long_packet_num_out(2); - if current_fifo_packet_type = TYPE_TRM or (current_fifo_packet_type = TYPE_EOB) then + CRC_enable <= last_fifo_read and not fifo_long_packet_num_out(2); + if current_fifo_packet_type(2 downto 0) = TYPE_TRM or (current_fifo_packet_type(2 downto 0) = TYPE_EOB) then CRC_enable <= '0'; end if; - if (current_fifo_packet_type = TYPE_EOB or current_fifo_packet_type = TYPE_TRM) and fifo_long_packet_num_out = c_F0 then + if (current_fifo_packet_type(2 downto 0) = TYPE_EOB or current_fifo_packet_type(2 downto 0) = TYPE_TRM) and fifo_long_packet_num_out = c_F0 then CRC_enable <= '1'; end if; end process; end generate; + PROC_SAVE_CRC_USED : process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + CRC_active <= '0'; + else + if (last_fifo_read='1' and fifo_long_packet_num_out(2) = '0' and current_fifo_packet_type(2 downto 0) /= TYPE_TRM) or CRC_active = '1' then + CRC_active <= '1'; + else + CRC_active <= '0'; + end if; + if current_fifo_packet_type(2 downto 0) = TYPE_TRM and fifo_long_packet_num_out = c_F3 then + CRC_active <= '0'; + end if; + end if; + end if; + end process; + gen_no_crc : if USE_CHECKSUM = 0 generate CRC_match <= '1'; end generate; @@ -392,9 +414,13 @@ counter_match <= '1'; got_eob_init_out <= '0'; got_eob_reply_out <= '0'; throw_away <= '0'; - CRC_RESET <= RESET; + if RESET = '1' then + CRC_RESET <= '1'; + else + CRC_RESET <= '0'; + end if; if USE_CHECKSUM = 1 then - if current_fifo_packet_type = TYPE_TRM and fifo_long_packet_num_out = c_F2 then + if current_fifo_packet_type(2 downto 0) = TYPE_TRM and fifo_long_packet_num_out = c_F2 and CRC_active = '1' then tmp_INT_DATA_OUT(3) <= fifo_data_out(3) or not CRC_match; tmp_INT_DATA_OUT(4) <= fifo_data_out(4) or not counter_match; CRC_RESET <= '1'; @@ -475,6 +501,7 @@ counter_match <= '1'; end if; end if; end process; + proc_count_buffers : process(CLK) begin if rising_edge(CLK) then diff --git a/trb_net16_iobuf.vhd b/trb_net16_iobuf.vhd index 75d40cb..b0272b5 100644 --- a/trb_net16_iobuf.vhd +++ b/trb_net16_iobuf.vhd @@ -9,7 +9,7 @@ use work.trb_net_std.all; entity trb_net16_iobuf is generic ( - IBUF_DEPTH : integer range 0 to 6 := c_FIFO_BRAM;--std_FIFO_DEPTH; + IBUF_DEPTH : integer range 2 to 6 := c_FIFO_BRAM;--std_FIFO_DEPTH; IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;--std_IBUF_SECURE_MODE; SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; OBUF_DATA_COUNT_WIDTH : integer range 2 to 7 := std_DATA_COUNT_WIDTH; diff --git a/trb_net16_ipudata.vhd b/trb_net16_ipudata.vhd index 6284b86..f97154d 100644 --- a/trb_net16_ipudata.vhd +++ b/trb_net16_ipudata.vhd @@ -29,12 +29,13 @@ entity trb_net16_ipudata is API_READ_OUT : out std_logic; -- APL Control port API_RUN_IN : in std_logic; - API_SEQNR_IN : in std_logic_vector (7 downto 0); + API_SEQNR_IN : in std_logic_vector (7 downto 0); API_LENGTH_OUT : out std_logic_vector (15 downto 0); + MY_ADDRESS_IN : in std_logic_vector (15 downto 0); --Information received with request - IPU_NUMBER_OUT : out std_logic_vector (15 downto 0); - IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0); + IPU_NUMBER_OUT : out std_logic_vector (15 downto 0); + IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0); --start strobe IPU_START_READOUT_OUT: out std_logic; --detector data, equipped with DHDR @@ -60,7 +61,7 @@ architecture trb_net16_ipudata_arch of trb_net16_ipudata is signal buf_API_READ_OUT : std_logic; signal buf_API_DATAREADY_OUT : std_logic; signal buf_API_DATA_OUT : std_logic_vector (c_DATA_WIDTH-1 downto 0); - type state_t is (START, WAITING, READING); + type state_t is (START, WAITING, MAKE_DHDR, READING); signal state : state_t; signal buf_NUMBER : std_logic_vector (15 downto 0); signal buf_RND_CODE : std_logic_vector (7 downto 0); @@ -73,7 +74,9 @@ architecture trb_net16_ipudata_arch of trb_net16_ipudata is signal packet_number : std_logic_vector(c_NUM_WIDTH-1 downto 0); signal reg_IPU_DATA : std_logic_vector (15 downto 0); signal saved_IPU_READOUT_FINISHED_IN : std_logic; - signal state_bits : std_logic_vector(2 downto 0); + signal state_bits : std_logic_vector(2 downto 0); + signal dhdr_counter : std_logic_vector(1 downto 0); + signal first_ipu_read : std_logic; begin @@ -92,12 +95,15 @@ begin update_buffers <= '0'; waiting_word <= '0'; buf_API_DATAREADY_OUT <= '0'; + first_ipu_read <= '0'; else buf_API_READ_OUT <= '1'; + first_ipu_read <= '0'; case state is when START => - buf_API_SEND_OUT <= '0'; - update_buffers <= '0'; + buf_API_SEND_OUT <= '0'; + update_buffers <= '0'; + buf_START_READOUT <= '0'; if API_DATAREADY_IN = '1' and buf_API_READ_OUT = '1' and API_TYP_IN = TYPE_TRM then case API_PACKET_NUM_IN is when c_F0 => null; --crc field, ignore @@ -110,14 +116,38 @@ begin when others => null; end case; end if; + when WAITING => - if IPU_DATAREADY_IN = '1' then + if IPU_DATAREADY_IN = '1' and API_READ_IN = '1' then + first_ipu_read <= '1'; update_buffers <= '1'; - state <= READING; + state <= MAKE_DHDR; + dhdr_counter <= (others => '0'); + buf_API_DATA_OUT <= IPU_DATA_IN(31 downto 16); end if; - when READING => + + when MAKE_DHDR => update_buffers <= '0'; buf_API_SEND_OUT <= '1'; + buf_API_DATAREADY_OUT <= '1'; + if buf_API_DATAREADY_OUT = '1' and API_READ_IN = '1' then + dhdr_counter <= dhdr_counter + 1; + case dhdr_counter is + when "00" => --1st dhdr from apl + buf_API_DATA_OUT <= reg_IPU_DATA; + when "01" => --2nd dhdr from apl + buf_API_DATA_OUT <= buf_IPU_LENGTH_IN; + when "10" => --dhdr length + buf_API_DATA_OUT <= MY_ADDRESS_IN; + when "11" => --dhdr source address + state <= READING; + buf_API_DATAREADY_OUT <= '0'; + when others => + null; --turn into a black hole + end case; + end if; + + when READING => buf_API_DATAREADY_OUT <= IPU_DATAREADY_IN or waiting_word; if buf_API_DATAREADY_OUT = '1' and API_READ_IN = '1' then waiting_word <= '0'; @@ -129,11 +159,9 @@ begin buf_API_DATA_OUT <= reg_IPU_DATA; end if; if saved_IPU_READOUT_FINISHED_IN = '1' and waiting_word = '0' and IPU_DATAREADY_IN = '0' then - buf_API_SEND_OUT <= '0'; - buf_START_READOUT <= '0'; state <= START; end if; - if IPU_READOUT_FINISHED_IN = '1' then + if saved_IPU_READOUT_FINISHED_IN = '1' or IPU_READOUT_FINISHED_IN = '1' then update_buffers <= '1'; end if; when others => @@ -143,7 +171,7 @@ begin end if; end process; - buf_IPU_READ <= '1' when API_READ_IN = '1' and waiting_word = '0' and state = READING else '0'; + buf_IPU_READ <= '1' when API_READ_IN = '1' and waiting_word = '0' and (state = READING or first_ipu_read = '1') else '0'; PROC_buffer_inputs : process(CLK) @@ -196,7 +224,7 @@ begin end process; API_ERROR_PATTERN_OUT <= buf_IPU_ERROR_PATTERN_IN; - API_LENGTH_OUT <= buf_IPU_LENGTH_IN; + API_LENGTH_OUT <= buf_IPU_LENGTH_IN+2; API_READ_OUT <= buf_API_READ_OUT; API_DATAREADY_OUT <= buf_API_DATAREADY_OUT; API_DATA_OUT <= buf_API_DATA_OUT; diff --git a/trb_net16_med_ecp_sfp.vhd b/trb_net16_med_ecp_sfp.vhd index 39b96ea..1414fbd 100644 --- a/trb_net16_med_ecp_sfp.vhd +++ b/trb_net16_med_ecp_sfp.vhd @@ -1,6 +1,6 @@ --Media interface for Lattice ECP2M using PCS at 2GHz ---Still missing: link reset features, fifo full error handling, signals on stat_op +--Still missing: fifo full error handling LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; @@ -11,6 +11,9 @@ library work; use work.trb_net_std.all; entity trb_net16_med_ecp_sfp is + generic( + SERDES_NUM : integer range 0 to 3 := 0 + ); port( CLK : in std_logic; RESET : in std_logic; -- synchronous reset @@ -24,7 +27,6 @@ entity trb_net16_med_ecp_sfp is MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); MED_DATAREADY_OUT : out std_logic; MED_READ_IN : in std_logic; - REFCLK2CORE_OUT : out std_logic; --SFP Connection SD_RXD_P_IN : in std_logic; SD_RXD_N_IN : in std_logic; @@ -44,70 +46,203 @@ end entity; architecture med_ecp_sfp of trb_net16_med_ecp_sfp is - component serdes + component serdes_0 + port( + core_txrefclk : in std_logic; + core_rxrefclk : in std_logic; +-- refclkp : IN std_logic; +-- refclkn : IN std_logic; + hdinp0 : in std_logic; + hdinn0 : in std_logic; + ff_rxiclk_ch0 : in std_logic; + ff_txiclk_ch0 : in std_logic; + ff_ebrd_clk_0 : in std_logic; + ff_txdata_ch0 : in std_logic_vector(15 downto 0); + ff_tx_k_cntrl_ch0 : in std_logic_vector(1 downto 0); + ff_force_disp_ch0 : in std_logic_vector(1 downto 0); + ff_disp_sel_ch0 : in std_logic_vector(1 downto 0); + ff_correct_disp_ch0 : in std_logic_vector(1 downto 0); + ffc_rrst_ch0 : in std_logic; + ffc_lane_tx_rst_ch0 : in std_logic; + ffc_lane_rx_rst_ch0 : in std_logic; + ffc_txpwdnb_ch0 : in std_logic; + ffc_rxpwdnb_ch0 : in std_logic; + ffc_macro_rst : in std_logic; + ffc_quad_rst : in std_logic; + ffc_trst : in std_logic; + hdoutp0 : out std_logic; + hdoutn0 : out std_logic; + ff_rxdata_ch0 : out std_logic_vector(15 downto 0); + ff_rx_k_cntrl_ch0 : out std_logic_vector(1 downto 0); + ff_rxfullclk_ch0 : out std_logic; + ff_rxhalfclk_ch0 : out std_logic; + ff_disp_err_ch0 : out std_logic_vector(1 downto 0); + ff_cv_ch0 : out std_logic_vector(1 downto 0); + ffs_rlos_lo_ch0 : out std_logic; + ffs_ls_sync_status_ch0 : out std_logic; + ffs_cc_underrun_ch0 : out std_logic; + ffs_cc_overrun_ch0 : out std_logic; + ffs_txfbfifo_error_ch0 : out std_logic; + ffs_rxfbfifo_error_ch0 : out std_logic; + ffs_rlol_ch0 : out std_logic; + oob_out_ch0 : out std_logic; + ff_txfullclk : out std_logic; + ff_txhalfclk : out std_logic; + ffs_plol : out std_logic + ); + end component; + + component serdes_1 + port( + core_txrefclk : in std_logic; + core_rxrefclk : in std_logic; + hdinp1 : in std_logic; + hdinn1 : in std_logic; + ff_rxiclk_ch1 : in std_logic; + ff_txiclk_ch1 : in std_logic; + ff_ebrd_clk_1 : in std_logic; + ff_txdata_ch1 : in std_logic_vector(15 downto 0); + ff_tx_k_cntrl_ch1 : in std_logic_vector(1 downto 0); + ff_force_disp_ch1 : in std_logic_vector(1 downto 0); + ff_disp_sel_ch1 : in std_logic_vector(1 downto 0); + ff_correct_disp_ch1 : in std_logic_vector(1 downto 0); + ffc_rrst_ch1 : in std_logic; + ffc_lane_tx_rst_ch1 : in std_logic; + ffc_lane_rx_rst_ch1 : in std_logic; + ffc_txpwdnb_ch1 : in std_logic; + ffc_rxpwdnb_ch1 : in std_logic; + ffc_macro_rst : in std_logic; + ffc_quad_rst : in std_logic; + ffc_trst : in std_logic; + hdoutp1 : out std_logic; + hdoutn1 : out std_logic; + ff_rxdata_ch1 : out std_logic_vector(15 downto 0); + ff_rx_k_cntrl_ch1 : out std_logic_vector(1 downto 0); + ff_rxfullclk_ch1 : out std_logic; + ff_rxhalfclk_ch1 : out std_logic; + ff_disp_err_ch1 : out std_logic_vector(1 downto 0); + ff_cv_ch1 : out std_logic_vector(1 downto 0); + ffs_rlos_lo_ch1 : out std_logic; + ffs_ls_sync_status_ch1 : out std_logic; + ffs_cc_underrun_ch1 : out std_logic; + ffs_cc_overrun_ch1 : out std_logic; + ffs_txfbfifo_error_ch1 : out std_logic; + ffs_rxfbfifo_error_ch1 : out std_logic; + ffs_rlol_ch1 : out std_logic; + oob_out_ch1 : out std_logic; + ff_txfullclk : out std_logic; + ff_txhalfclk : out std_logic; + ffs_plol : out std_logic + ); + end component; + + + component serdes_2 + port( + core_txrefclk : in std_logic; + core_rxrefclk : in std_logic; + hdinp2 : in std_logic; + hdinn2 : in std_logic; + ff_rxiclk_ch2 : in std_logic; + ff_txiclk_ch2 : in std_logic; + ff_ebrd_clk_2 : in std_logic; + ff_txdata_ch2 : in std_logic_vector(15 downto 0); + ff_tx_k_cntrl_ch2 : in std_logic_vector(1 downto 0); + ff_force_disp_ch2 : in std_logic_vector(1 downto 0); + ff_disp_sel_ch2 : in std_logic_vector(1 downto 0); + ff_correct_disp_ch2 : in std_logic_vector(1 downto 0); + ffc_rrst_ch2 : in std_logic; + ffc_lane_tx_rst_ch2 : in std_logic; + ffc_lane_rx_rst_ch2 : in std_logic; + ffc_txpwdnb_ch2 : in std_logic; + ffc_rxpwdnb_ch2 : in std_logic; + ffc_macro_rst : in std_logic; + ffc_quad_rst : in std_logic; + ffc_trst : in std_logic; + hdoutp2 : out std_logic; + hdoutn2 : out std_logic; + ff_rxdata_ch2 : out std_logic_vector(15 downto 0); + ff_rx_k_cntrl_ch2 : out std_logic_vector(1 downto 0); + ff_rxfullclk_ch2 : out std_logic; + ff_rxhalfclk_ch2 : out std_logic; + ff_disp_err_ch2 : out std_logic_vector(1 downto 0); + ff_cv_ch2 : out std_logic_vector(1 downto 0); + ffs_rlos_lo_ch2 : out std_logic; + ffs_ls_sync_status_ch2 : out std_logic; + ffs_cc_underrun_ch2 : out std_logic; + ffs_cc_overrun_ch2 : out std_logic; + ffs_txfbfifo_error_ch2 : out std_logic; + ffs_rxfbfifo_error_ch2 : out std_logic; + ffs_rlol_ch2 : out std_logic; + oob_out_ch2 : out std_logic; + ff_txfullclk : out std_logic; + ff_txhalfclk : out std_logic; + ffs_plol : out std_logic + ); + end component; + + component serdes_3 port( - core_txrefclk : IN std_logic; --CLK - core_rxrefclk : IN std_logic; --CLK - hdinp2 : IN std_logic; --RX Data input - hdinn2 : IN std_logic; --RX Data input - ff_rxiclk_ch2 : IN std_logic; --CLK ff_txhalfclk - ff_txiclk_ch2 : IN std_logic; --CLK ff_txhalfclk - ff_ebrd_clk_2 : IN std_logic; --CLK ff_txfullclk - ff_txdata_ch2 : IN std_logic_vector(15 downto 0); --internal tx data - ff_tx_k_cntrl_ch2 : IN std_logic_vector(1 downto 0); --control character flag 00 - ff_force_disp_ch2 : IN std_logic_vector(1 downto 0); --activate disparity value 00 - ff_disp_sel_ch2 : IN std_logic_vector(1 downto 0); --disparity value in 00 - ff_correct_disp_ch2 : IN std_logic_vector(1 downto 0); --disparity check 00 - ffc_rrst_ch2 : IN std_logic; --RESET - ffc_signal_detect_ch2 : IN std_logic; --enable signal detect - ffc_enable_cgalign_ch2 : IN std_logic; --enable comma aligner 0 - ffc_lane_tx_rst_ch2 : IN std_logic; --RESET - ffc_lane_rx_rst_ch2 : IN std_logic; -- reset PCS (word alignment) - ffc_txpwdnb_ch2 : IN std_logic; --power down active low - ffc_rxpwdnb_ch2 : IN std_logic; --power down active low - ffc_macro_rst : IN std_logic; --RESET - ffc_quad_rst : IN std_logic; --RESET - ffc_trst : IN std_logic; --RESET - hdoutp2 : OUT std_logic; --TX Data output - hdoutn2 : OUT std_logic; --TX Data output - ff_rxdata_ch2 : OUT std_logic_vector(15 downto 0); --internal rx data - ff_rx_k_cntrl_ch2 : OUT std_logic_vector(1 downto 0); --control character flag - ff_rxfullclk_ch2 : OUT std_logic; --RX recovered CLK - ff_rxhalfclk_ch2 : OUT std_logic; --+ --RX half recovered CLK - ff_disp_err_ch2 : OUT std_logic_vector(1 downto 0); --disparity error flag - ff_cv_ch2 : OUT std_logic_vector(1 downto 0); --code violation flag - ffs_rlos_lo_ch2 : OUT std_logic; --NOT signal loss - ffs_ls_sync_status_ch2 : OUT std_logic; --+ --link state machine status - ffs_cc_underrun_ch2 : OUT std_logic; --Clock compensator FIFO error - ffs_cc_overrun_ch2 : OUT std_logic; --Clock compensator FIFO error - ffs_txfbfifo_error_ch2 : OUT std_logic; --TX FIFO error - ffs_rxfbfifo_error_ch2 : OUT std_logic; --RX FIFO error - ffs_rlol_ch2 : OUT std_logic; --Clock Recovery error - oob_out_ch2 : OUT std_logic; --internal output same as real serdes output - ff_txfullclk : OUT std_logic; --TX CLK - ff_txhalfclk : OUT std_logic; --TX CLK/2 <- interface CLK from MED to Serdes - refck2core : OUT std_logic; --+ --Reference CLK - ffs_plol : OUT std_logic --TX PLL error (not locked) + core_txrefclk : in std_logic; + core_rxrefclk : in std_logic; + hdinp3 : in std_logic; + hdinn3 : in std_logic; + ff_rxiclk_ch3 : in std_logic; + ff_txiclk_ch3 : in std_logic; + ff_ebrd_clk_3 : in std_logic; + ff_txdata_ch3 : in std_logic_vector(15 downto 0); + ff_tx_k_cntrl_ch3 : in std_logic_vector(1 downto 0); + ff_force_disp_ch3 : in std_logic_vector(1 downto 0); + ff_disp_sel_ch3 : in std_logic_vector(1 downto 0); + ff_correct_disp_ch3 : in std_logic_vector(1 downto 0); + ffc_rrst_ch3 : in std_logic; + ffc_lane_tx_rst_ch3 : in std_logic; + ffc_lane_rx_rst_ch3 : in std_logic; + ffc_txpwdnb_ch3 : in std_logic; + ffc_rxpwdnb_ch3 : in std_logic; + ffc_macro_rst : in std_logic; + ffc_quad_rst : in std_logic; + ffc_trst : in std_logic; + hdoutp3 : out std_logic; + hdoutn3 : out std_logic; + ff_rxdata_ch3 : out std_logic_vector(15 downto 0); + ff_rx_k_cntrl_ch3 : out std_logic_vector(1 downto 0); + ff_rxfullclk_ch3 : out std_logic; + ff_rxhalfclk_ch3 : out std_logic; + ff_disp_err_ch3 : out std_logic_vector(1 downto 0); + ff_cv_ch3 : out std_logic_vector(1 downto 0); + ffs_rlos_lo_ch3 : out std_logic; + ffs_ls_sync_status_ch3 : out std_logic; + ffs_cc_underrun_ch3 : out std_logic; + ffs_cc_overrun_ch3 : out std_logic; + ffs_txfbfifo_error_ch3 : out std_logic; + ffs_rxfbfifo_error_ch3 : out std_logic; + ffs_rlol_ch3 : out std_logic; + oob_out_ch3 : out std_logic; + ff_txfullclk : out std_logic; + ff_txhalfclk : out std_logic; + ffs_plol : out std_logic ); end component; component trb_net_fifo_16bit_bram_dualport is generic( USE_STATUS_FLAGS : integer := c_YES - ); - port( read_clock_in : in std_logic; - write_clock_in : in std_logic; - read_enable_in : in std_logic; - write_enable_in : in std_logic; - fifo_gsr_in : in std_logic; - write_data_in : in std_logic_vector(17 downto 0); - read_data_out : out std_logic_vector(17 downto 0); - full_out : out std_logic; - empty_out : out std_logic; - fifostatus_out : out std_logic_vector(3 downto 0); - valid_read_out : out std_logic; - almost_empty_out : out std_logic; - almost_full_out : out std_logic + ); + port( + read_clock_in : in std_logic; + write_clock_in : in std_logic; + read_enable_in : in std_logic; + write_enable_in : in std_logic; + fifo_gsr_in : in std_logic; + write_data_in : in std_logic_vector(17 downto 0); + read_data_out : out std_logic_vector(17 downto 0); + full_out : out std_logic; + empty_out : out std_logic; + fifostatus_out : out std_logic_vector(3 downto 0); + valid_read_out : out std_logic; + almost_empty_out : out std_logic; + almost_full_out : out std_logic ); end component; @@ -117,26 +252,25 @@ architecture med_ecp_sfp of trb_net16_med_ecp_sfp is DEPTH : integer := 3 ); port( - RESET : in std_logic; --Reset is neceessary to avoid optimization to shift register - CLK0 : in std_logic; --clock for first FF - CLK1 : in std_logic; --Clock for other FF - D_IN : in std_logic_vector(WIDTH-1 downto 0); --Data input - D_OUT : out std_logic_vector(WIDTH-1 downto 0) --Data output + RESET : in std_logic; + CLK0 : in std_logic; + CLK1 : in std_logic; + D_IN : in std_logic_vector(WIDTH-1 downto 0); + D_OUT : out std_logic_vector(WIDTH-1 downto 0) ); end component; - signal refck2core : std_logic; --reset signals signal ffc_quad_rst : std_logic; - signal ffc_lane_tx_rst_ch2 : std_logic; - signal ffc_lane_rx_rst_ch2 : std_logic; + signal ffc_lane_tx_rst : std_logic; + signal ffc_lane_rx_rst : std_logic; --serdes connections signal tx_data : std_logic_vector(15 downto 0); signal tx_k : std_logic_vector(1 downto 0); signal rx_data : std_logic_vector(15 downto 0); signal rx_k : std_logic_vector(1 downto 0); signal link_ok : std_logic_vector(0 downto 0); - signal link_error : std_logic_vector(9 downto 0); + signal link_error : std_logic_vector(8 downto 0); signal ff_rxhalfclk : std_logic; signal ff_txhalfclk : std_logic; --rx fifo signals @@ -212,7 +346,6 @@ architecture med_ecp_sfp of trb_net16_med_ecp_sfp is signal buf_STAT_OP : std_logic_vector(15 downto 15); signal buf_RESET_TRBNET_OUT : std_logic; signal resync_counter : std_logic_vector(2 downto 0); - signal internal_reset : std_logic; signal send_resync_counter : std_logic_vector(11 downto 0); signal next_send_resync : std_logic; signal send_resync : std_logic; @@ -438,27 +571,18 @@ begin end case; end process; -THE_DECODE_PROC: process( CURRENT_STATE, timing_ctr ) +THE_DECODE_PROC: process( CURRENT_STATE ) begin case CURRENT_STATE is when SLEEP => state_bits <= "0000"; - info_led <= '0'; - when QRST => state_bits <= "0001"; - info_led <= timing_ctr(21); -- too high - when WPAR => state_bits <= "0010"; - info_led <= timing_ctr(21) and timing_ctr(24); -- nice frequency for human eye - when WLOS => state_bits <= "0011"; - info_led <= timing_ctr(22); + when QRST => state_bits <= "0001"; + when WPAR => state_bits <= "0010"; + when WLOS => state_bits <= "0011"; when ALIGN => state_bits <= "0100"; - info_led <= timing_ctr(23); - when WRXA => state_bits <= "0101"; - info_led <= timing_ctr(24); - when WTXA => state_bits <= "0110"; - info_led <= timing_ctr(25); - when LINK => state_bits <= "0111"; - info_led <= '1'; - when others => state_bits <= "1111"; - info_led <= '0'; + when WRXA => state_bits <= "0101"; + when WTXA => state_bits <= "0110"; + when LINK => state_bits <= "0111"; + when others => state_bits <= "1111"; end case; end process THE_DECODE_PROC; @@ -480,61 +604,191 @@ THE_RX_ALLOW_SYNC: signal_sync -------------------------------------------------------------------------- -------------------------------------------------------------------------- -ffc_quad_rst <= quad_rst; -ffc_lane_tx_rst_ch2 <= lane_rst; -ffc_lane_rx_rst_ch2 <= lane_rst; - - +ffc_quad_rst <= quad_rst; +ffc_lane_tx_rst <= lane_rst; +ffc_lane_rx_rst <= lane_rst; --- SerDes clock output to FPGA fabric -refclk2core_out <= refck2core; -- Instantiation of serdes module -THE_SERDES: serdes - port map( - core_txrefclk => clk, - core_rxrefclk => clk, - hdinp2 => sd_rxd_p_in, - hdinn2 => sd_rxd_n_in, - ff_rxiclk_ch2 => ff_rxhalfclk, - ff_txiclk_ch2 => ff_txhalfclk, - ff_ebrd_clk_2 => ff_rxhalfclk, -- not used, just for completeness - ff_txdata_ch2 => tx_data, - ff_tx_k_cntrl_ch2 => tx_k, - ff_force_disp_ch2 => "00", - ff_disp_sel_ch2 => "00", - ff_correct_disp_ch2 => "00", - ffc_rrst_ch2 => '0', - ffc_lane_tx_rst_ch2 => ffc_lane_tx_rst_ch2, - ffc_lane_rx_rst_ch2 => ffc_lane_rx_rst_ch2, - ffc_txpwdnb_ch2 => '1', - ffc_rxpwdnb_ch2 => '1', - ffc_macro_rst => '0', - ffc_quad_rst => ffc_quad_rst, - ffc_trst => '0', - hdoutp2 => sd_txd_p_out, - hdoutn2 => sd_txd_n_out, - ff_rxdata_ch2 => rx_data, --comb_rx_data, - ff_rx_k_cntrl_ch2 => rx_k, --comb_rx_k, - ff_rxfullclk_ch2 => open, - ff_rxhalfclk_ch2 => ff_rxhalfclk, - ff_disp_err_ch2 => open, - ff_cv_ch2 => link_error(7 downto 6), - ffs_rlos_lo_ch2 => link_error(8), - ffs_ls_sync_status_ch2 => link_ok(0), - ffs_cc_underrun_ch2 => link_error(0), - ffs_cc_overrun_ch2 => link_error(1), - ffs_txfbfifo_error_ch2 => link_error(2), - ffs_rxfbfifo_error_ch2 => link_error(3), - ffs_rlol_ch2 => link_error(4), - oob_out_ch2 => open, - ff_txfullclk => open, - ff_txhalfclk => ff_txhalfclk, - refck2core => refck2core, - ffs_plol => link_error(5) - ); - -link_error(9) <= '0'; -- unused + gen_serdes_0 : if SERDES_NUM = 0 generate + THE_SERDES: serdes_0 + port map( + core_txrefclk => clk, + core_rxrefclk => clk, +-- refclkp => SD_REFCLK_P_IN, +-- refclkn => SD_REFCLK_N_IN, + hdinp0 => sd_rxd_p_in, + hdinn0 => sd_rxd_n_in, + ff_rxiclk_ch0 => ff_rxhalfclk, + ff_txiclk_ch0 => ff_txhalfclk, + ff_ebrd_clk_0 => ff_rxhalfclk, -- not used, just for completeness + ff_txdata_ch0 => tx_data, + ff_tx_k_cntrl_ch0 => tx_k, + ff_force_disp_ch0 => "00", + ff_disp_sel_ch0 => "00", + ff_correct_disp_ch0 => "00", + ffc_rrst_ch0 => '0', + ffc_lane_tx_rst_ch0 => ffc_lane_tx_rst, + ffc_lane_rx_rst_ch0 => ffc_lane_rx_rst, + ffc_txpwdnb_ch0 => '1', + ffc_rxpwdnb_ch0 => '1', + ffc_macro_rst => '0', + ffc_quad_rst => ffc_quad_rst, + ffc_trst => '0', + hdoutp0 => sd_txd_p_out, + hdoutn0 => sd_txd_n_out, + ff_rxdata_ch0 => rx_data, --comb_rx_data, + ff_rx_k_cntrl_ch0 => rx_k, --comb_rx_k, + ff_rxfullclk_ch0 => open, + ff_rxhalfclk_ch0 => ff_rxhalfclk, + ff_disp_err_ch0 => open, + ff_cv_ch0 => link_error(7 downto 6), + ffs_rlos_lo_ch0 => link_error(8), + ffs_ls_sync_status_ch0 => link_ok(0), + ffs_cc_underrun_ch0 => link_error(0), + ffs_cc_overrun_ch0 => link_error(1), + ffs_txfbfifo_error_ch0 => link_error(2), + ffs_rxfbfifo_error_ch0 => link_error(3), + ffs_rlol_ch0 => link_error(4), + oob_out_ch0 => open, + ff_txfullclk => open, + ff_txhalfclk => ff_txhalfclk, + ffs_plol => link_error(5) + ); + end generate; + gen_serdes_1 : if SERDES_NUM = 1 generate + THE_SERDES: serdes_1 + port map( + core_txrefclk => clk, + core_rxrefclk => clk, + hdinp1 => sd_rxd_p_in, + hdinn1 => sd_rxd_n_in, + ff_rxiclk_ch1 => ff_rxhalfclk, + ff_txiclk_ch1 => ff_txhalfclk, + ff_ebrd_clk_1 => ff_rxhalfclk, -- not used, just for completeness + ff_txdata_ch1 => tx_data, + ff_tx_k_cntrl_ch1 => tx_k, + ff_force_disp_ch1 => "00", + ff_disp_sel_ch1 => "00", + ff_correct_disp_ch1 => "00", + ffc_rrst_ch1 => '0', + ffc_lane_tx_rst_ch1 => ffc_lane_tx_rst, + ffc_lane_rx_rst_ch1 => ffc_lane_rx_rst, + ffc_txpwdnb_ch1 => '1', + ffc_rxpwdnb_ch1 => '1', + ffc_macro_rst => '0', + ffc_quad_rst => ffc_quad_rst, + ffc_trst => '0', + hdoutp1 => sd_txd_p_out, + hdoutn1 => sd_txd_n_out, + ff_rxdata_ch1 => rx_data, --comb_rx_data, + ff_rx_k_cntrl_ch1 => rx_k, --comb_rx_k, + ff_rxfullclk_ch1 => open, + ff_rxhalfclk_ch1 => ff_rxhalfclk, + ff_disp_err_ch1 => open, + ff_cv_ch1 => link_error(7 downto 6), + ffs_rlos_lo_ch1 => link_error(8), + ffs_ls_sync_status_ch1 => link_ok(0), + ffs_cc_underrun_ch1 => link_error(0), + ffs_cc_overrun_ch1 => link_error(1), + ffs_txfbfifo_error_ch1 => link_error(2), + ffs_rxfbfifo_error_ch1 => link_error(3), + ffs_rlol_ch1 => link_error(4), + oob_out_ch1 => open, + ff_txfullclk => open, + ff_txhalfclk => ff_txhalfclk, + ffs_plol => link_error(5) + ); + end generate; + gen_serdes_2 : if SERDES_NUM = 2 generate + THE_SERDES: serdes_2 + port map( + core_txrefclk => clk, + core_rxrefclk => clk, + hdinp2 => sd_rxd_p_in, + hdinn2 => sd_rxd_n_in, + ff_rxiclk_ch2 => ff_rxhalfclk, + ff_txiclk_ch2 => ff_txhalfclk, + ff_ebrd_clk_2 => ff_rxhalfclk, -- not used, just for completeness + ff_txdata_ch2 => tx_data, + ff_tx_k_cntrl_ch2 => tx_k, + ff_force_disp_ch2 => "00", + ff_disp_sel_ch2 => "00", + ff_correct_disp_ch2 => "00", + ffc_rrst_ch2 => '0', + ffc_lane_tx_rst_ch2 => ffc_lane_tx_rst, + ffc_lane_rx_rst_ch2 => ffc_lane_rx_rst, + ffc_txpwdnb_ch2 => '1', + ffc_rxpwdnb_ch2 => '1', + ffc_macro_rst => '0', + ffc_quad_rst => ffc_quad_rst, + ffc_trst => '0', + hdoutp2 => sd_txd_p_out, + hdoutn2 => sd_txd_n_out, + ff_rxdata_ch2 => rx_data, --comb_rx_data, + ff_rx_k_cntrl_ch2 => rx_k, --comb_rx_k, + ff_rxfullclk_ch2 => open, + ff_rxhalfclk_ch2 => ff_rxhalfclk, + ff_disp_err_ch2 => open, + ff_cv_ch2 => link_error(7 downto 6), + ffs_rlos_lo_ch2 => link_error(8), + ffs_ls_sync_status_ch2 => link_ok(0), + ffs_cc_underrun_ch2 => link_error(0), + ffs_cc_overrun_ch2 => link_error(1), + ffs_txfbfifo_error_ch2 => link_error(2), + ffs_rxfbfifo_error_ch2 => link_error(3), + ffs_rlol_ch2 => link_error(4), + oob_out_ch2 => open, + ff_txfullclk => open, + ff_txhalfclk => ff_txhalfclk, + ffs_plol => link_error(5) + ); + end generate; + gen_serdes_3 : if SERDES_NUM = 3 generate + THE_SERDES: serdes_3 + port map( + core_txrefclk => clk, + core_rxrefclk => clk, + hdinp3 => sd_rxd_p_in, + hdinn3 => sd_rxd_n_in, + ff_rxiclk_ch3 => ff_rxhalfclk, + ff_txiclk_ch3 => ff_txhalfclk, + ff_ebrd_clk_3 => ff_rxhalfclk, -- not used, just for completeness + ff_txdata_ch3 => tx_data, + ff_tx_k_cntrl_ch3 => tx_k, + ff_force_disp_ch3 => "00", + ff_disp_sel_ch3 => "00", + ff_correct_disp_ch3 => "00", + ffc_rrst_ch3 => '0', + ffc_lane_tx_rst_ch3 => ffc_lane_tx_rst, + ffc_lane_rx_rst_ch3 => ffc_lane_rx_rst, + ffc_txpwdnb_ch3 => '1', + ffc_rxpwdnb_ch3 => '1', + ffc_macro_rst => '0', + ffc_quad_rst => ffc_quad_rst, + ffc_trst => '0', + hdoutp3 => sd_txd_p_out, + hdoutn3 => sd_txd_n_out, + ff_rxdata_ch3 => rx_data, --comb_rx_data, + ff_rx_k_cntrl_ch3 => rx_k, --comb_rx_k, + ff_rxfullclk_ch3 => open, + ff_rxhalfclk_ch3 => ff_rxhalfclk, + ff_disp_err_ch3 => open, + ff_cv_ch3 => link_error(7 downto 6), + ffs_rlos_lo_ch3 => link_error(8), + ffs_ls_sync_status_ch3 => link_ok(0), + ffs_cc_underrun_ch3 => link_error(0), + ffs_cc_overrun_ch3 => link_error(1), + ffs_txfbfifo_error_ch3 => link_error(2), + ffs_rxfbfifo_error_ch3 => link_error(3), + ffs_rlol_ch3 => link_error(4), + oob_out_ch3 => open, + ff_txfullclk => open, + ff_txhalfclk => ff_txhalfclk, + ffs_plol => link_error(5) + ); + end generate; + ------------------------------------------------------------------------- -- RX Fifo & Data output @@ -680,18 +934,19 @@ end process; --TX Fifo & Data output to Serdes --------------------- THE_FIFO_FPGA_TO_SFP: trb_net_fifo_16bit_bram_dualport -generic map( - USE_STATUS_FLAGS => c_NO - ) -port map( read_clock_in => ff_txhalfclk, - write_clock_in => clock, - read_enable_in => fifo_tx_rd_en, - write_enable_in => fifo_tx_wr_en, - fifo_gsr_in => fifo_tx_reset, - write_data_in => fifo_tx_din, - read_data_out => fifo_tx_dout, - full_out => fifo_tx_full, - empty_out => fifo_tx_empty + generic map( + USE_STATUS_FLAGS => c_NO + ) + port map( + read_clock_in => ff_txhalfclk, + write_clock_in => clock, + read_enable_in => fifo_tx_rd_en, + write_enable_in => fifo_tx_wr_en, + fifo_gsr_in => fifo_tx_reset, + write_data_in => fifo_tx_din, + read_data_out => fifo_tx_dout, + full_out => fifo_tx_full, + empty_out => fifo_tx_empty ); fifo_tx_reset <= RESET; @@ -717,7 +972,6 @@ begin end if; end process THE_SERDES_INPUT_PROC; --- --Generate LED signals @@ -763,15 +1017,17 @@ stat_debug(6) <= rx_k(0); stat_debug(7) <= rx_k(1); stat_debug(8) <= rx_k_q(0); stat_debug(9) <= rx_k_q(1); ---stat_debug(9 downto 7) <= (others => '0'); -stat_debug(19 downto 10) <= link_error; +stat_debug(18 downto 10) <= link_error; +stat_debug(19) <= '0'; stat_debug(20) <= link_ok(0); stat_debug(38 downto 21) <= fifo_rx_din; stat_debug(39) <= swap_bytes; stat_debug(40) <= fifo_rx_wr_en; stat_debug(41) <= info_led; stat_debug(42) <= resync; -stat_debug(59 downto 43) <= (others => '0'); +stat_debug(43) <= ff_rxhalfclk; +stat_debug(44) <= ff_txhalfclk; +stat_debug(59 downto 45) <= (others => '0'); stat_debug(63 downto 60) <= link_error(3 downto 0); end architecture; \ No newline at end of file diff --git a/trb_net16_obuf.vhd b/trb_net16_obuf.vhd index 1d10675..0ed45ed 100644 --- a/trb_net16_obuf.vhd +++ b/trb_net16_obuf.vhd @@ -283,7 +283,7 @@ begin next_SEND_ACK_IN <= send_ACK; comb_dataready <= '0'; next_sending_state <= sending_state; - CRC_enable <= reg_INT_READ_OUT and INT_DATAREADY_IN and or_all(INT_PACKET_NUM_IN); + CRC_enable <= reg_INT_READ_OUT and INT_DATAREADY_IN and not INT_PACKET_NUM_IN(2); CRC_RESET <= RESET; --only data words are CRC'ed @@ -402,10 +402,10 @@ begin begin if rising_edge(CLK) then case REC_BUFFER_SIZE_IN(2 downto 0) is - when "010" => max_DATA_COUNT_minus_one <= conv_std_logic_vector(3, DATA_COUNT_WIDTH); - when "011" => max_DATA_COUNT_minus_one <= conv_std_logic_vector(7, DATA_COUNT_WIDTH); - when "110" => max_DATA_COUNT_minus_one <= conv_std_logic_vector(127, DATA_COUNT_WIDTH); - when "111" => max_DATA_COUNT_minus_one <= conv_std_logic_vector(127, DATA_COUNT_WIDTH); + when "010" => max_DATA_COUNT_minus_one <= conv_std_logic_vector(2, DATA_COUNT_WIDTH); + when "011" => max_DATA_COUNT_minus_one <= conv_std_logic_vector(4, DATA_COUNT_WIDTH); + when "110" => max_DATA_COUNT_minus_one <= conv_std_logic_vector(100, DATA_COUNT_WIDTH); + when "111" => max_DATA_COUNT_minus_one <= conv_std_logic_vector(100, DATA_COUNT_WIDTH); when others => max_DATA_COUNT_minus_one <= conv_std_logic_vector(1, DATA_COUNT_WIDTH); end case; end if; diff --git a/trb_net16_regIO.vhd b/trb_net16_regIO.vhd index 0f86a44..5a629cb 100644 --- a/trb_net16_regIO.vhd +++ b/trb_net16_regIO.vhd @@ -280,7 +280,7 @@ begin ADR_READ_OUT, ADR_DATAREADY_OUT, ADR_DATA_OUT, length, dont_understand, buf_rom_read_addr, ADR_SEND_OUT, rom_read_dout, COMMON_STAT_REG_IN, buf_COMMON_CTRL_REG_OUT, timeout, unknown, addr_counter_enable, DAT_UNKNOWN_ADDR_IN, dat_data_counter, - DAT_WRITE_ACK_IN, DAT_DATAREADY_IN_before + DAT_WRITE_ACK_IN, DAT_DATAREADY_IN_before, ADR_DONT_UNDERSTAND ) variable regnum_STAT : integer range 0 to 2**NUM_STAT_REGS-1; variable regnum_CTRL : integer range 0 to 2**NUM_CTRL_REGS-1; diff --git a/trb_net_std.vhd b/trb_net_std.vhd index 1947143..3553f51 100644 --- a/trb_net_std.vhd +++ b/trb_net_std.vhd @@ -64,7 +64,7 @@ package trb_net_std is constant std_TERM_SECURE_MODE : integer := c_NO; constant std_MUX_SECURE_MODE : integer := c_NO; constant std_FORCE_REPLY : integer := c_YES; - constant cfg_USE_CHECKSUM : channel_config_t := (c_YES,c_YES,c_YES,c_YES); + constant cfg_USE_CHECKSUM : channel_config_t := (c_NO,c_YES,c_YES,c_YES); constant cfg_USE_ACKNOWLEDGE : channel_config_t := (c_YES,c_YES,c_YES,c_YES); constant cfg_FORCE_REPLY : channel_config_t := (c_YES,c_YES,c_YES,c_YES); constant cfg_USE_REPLY_CHANNEL : channel_config_t := (c_YES,c_YES,c_YES,c_YES); diff --git a/xilinx/virtex2/trb_net16_fifo_arch.vhd b/xilinx/virtex2/trb_net16_fifo_arch.vhd index 4d10ca5..89c4962 100644 --- a/xilinx/virtex2/trb_net16_fifo_arch.vhd +++ b/xilinx/virtex2/trb_net16_fifo_arch.vhd @@ -124,11 +124,11 @@ begin ); end generate; - gen_OWN_CORES : if USE_VENDOR_CORES = c_NO generate +-- gen_OWN_CORES : if USE_VENDOR_CORES = c_NO generate gen_FIFO_LUT : if DEPTH < 6 generate fifo:xilinx_fifo_lut generic map ( - WIDTH => c_DATA_WIDTH + c_NUM_WIDTH, + WIDTH => c_DATA_WIDTH + 2, DEPTH => ((DEPTH+3)) ) port map ( @@ -142,7 +142,7 @@ begin empty => EMPTY_OUT ); end generate; - end generate; +-- end generate; -- gen_XILINX_CORES : if USE_VENDOR_CORES = c_YES generate -- gen_FIFO1 : if DEPTH = 1 generate @@ -158,7 +158,7 @@ begin -- empty => EMPTY_OUT -- ); -- end generate; --- +-- -- gen_FIFO2 : if DEPTH = 2 generate -- fifo:xilinx_fifo_18x32 -- port map ( @@ -172,8 +172,8 @@ begin -- empty => EMPTY_OUT -- ); -- end generate; --- --- +-- +-- -- gen_FIFO3 : if DEPTH = 3 generate -- fifo:xilinx_fifo_18x64 -- port map ( -- 2.43.0