From ccbda6872435846264c81ed8fbdb8d7af887c2c4 Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Thu, 7 Jul 2022 23:08:43 +0200 Subject: [PATCH] first ethernet cable inside FPGA for testing --- gbe_hub/trb3sc_gbe_hub.lpf | 49 +++- gbe_hub/trb3sc_gbe_hub.prj | 8 + gbe_hub/trb3sc_gbe_hub.vhd | 525 ++++++++++++++++++++++++++++--------- 3 files changed, 459 insertions(+), 123 deletions(-) diff --git a/gbe_hub/trb3sc_gbe_hub.lpf b/gbe_hub/trb3sc_gbe_hub.lpf index 9b2ad66..f37c8d3 100644 --- a/gbe_hub/trb3sc_gbe_hub.lpf +++ b/gbe_hub/trb3sc_gbe_hub.lpf @@ -1,7 +1,8 @@ # locate the PCS blocks -LOCATE COMP "GBE/physical/gbe_serdes/PCSD_INST" SITE "PCSD"; +#LOCATE COMP "GBE/physical/gbe_serdes/PCSD_INST" SITE "PCSD"; +LOCATE COMP "THE_GBE_MED_RAW_PCSA/gbe_serdes/PCSD_INST" SITE "PCSA"; LOCATE COMP "THE_GBE_MED_RAW_PCSB/gbe_serdes/PCSD_INST" SITE "PCSB"; LOCATE COMP "THE_GBE_MED_RAW_PCSC/gbe_serdes/PCSD_INST" SITE "PCSC"; LOCATE COMP "THE_GBE_MED_RAW_PCSD/gbe_serdes/PCSD_INST" SITE "PCSD"; @@ -15,6 +16,52 @@ FREQUENCY NET "GBE/clk_125_rx_from_pcs[0]" 125.0 MHz; ################################################################################################## +DEFINE PORT GROUP "DEB_group" "DBG*" ; +IOBUF GROUP "HUB_group" IO_TYPE=LVCMOS25 PULLMODE=NONE; + +LOCATE COMP "DBG_0" SITE "AP5"; +LOCATE COMP "DBG_2" SITE "AP2"; +LOCATE COMP "DBG_4" SITE "AN1"; +LOCATE COMP "DBG_6" SITE "AN3"; +LOCATE COMP "DBG_8" SITE "AL5"; +LOCATE COMP "DBG_10" SITE "AM6"; +LOCATE COMP "DBG_12" SITE "AL4"; +LOCATE COMP "DBG_14" SITE "AJ5"; +LOCATE COMP "DBG_16" SITE "AJ2"; +LOCATE COMP "DBG_18" SITE "AL3"; +LOCATE COMP "DBG_20" SITE "AD9"; +LOCATE COMP "DBG_22" SITE "AJ4"; +LOCATE COMP "DBG_24" SITE "V4"; +LOCATE COMP "DBG_26" SITE "V5"; +LOCATE COMP "DBG_28" SITE "T9"; +LOCATE COMP "DBG_30" SITE "T2"; +LOCATE COMP "DBG_32" SITE "P7"; +LOCATE COMP "DBG_34" SITE "R8"; +LOCATE COMP "DBG_36" SITE "R2"; +LOCATE COMP "DBG_38" SITE "P9"; +LOCATE COMP "DBG_1" SITE "AP6"; +LOCATE COMP "DBG_3" SITE "AP3"; +LOCATE COMP "DBG_5" SITE "AN2"; +LOCATE COMP "DBG_7" SITE "AM3"; +LOCATE COMP "DBG_9" SITE "AM5"; +LOCATE COMP "DBG_11" SITE "AN6"; +LOCATE COMP "DBG_13" SITE "AM4"; +LOCATE COMP "DBG_15" SITE "AJ6"; +LOCATE COMP "DBG_17" SITE "AJ3"; +LOCATE COMP "DBG_19" SITE "AK3"; +LOCATE COMP "DBG_21" SITE "AD8"; +LOCATE COMP "DBG_23" SITE "AK4"; +LOCATE COMP "DBG_25" SITE "V3"; +LOCATE COMP "DBG_27" SITE "W5"; +LOCATE COMP "DBG_29" SITE "T8"; +LOCATE COMP "DBG_31" SITE "T1"; +LOCATE COMP "DBG_33" SITE "P6"; +LOCATE COMP "DBG_35" SITE "T7"; +LOCATE COMP "DBG_37" SITE "R1"; +LOCATE COMP "DBG_39" SITE "P10"; + +################################################################################################## + # primary nets #USE PRIMARY NET "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/clk_rx_full[0]"; diff --git a/gbe_hub/trb3sc_gbe_hub.prj b/gbe_hub/trb3sc_gbe_hub.prj index 5ab8b32..f0288aa 100644 --- a/gbe_hub/trb3sc_gbe_hub.prj +++ b/gbe_hub/trb3sc_gbe_hub.prj @@ -230,6 +230,14 @@ add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_ #add_file -verilog -lib work "../../trbnet/gbe_trb/media/rate_resolution.v" add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/media/serdes_gbe_4ch_ds.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/base/rx_rb.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/base/tx_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/base/forwarder.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/base/gbe_lsm.vhd" + +add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/cores/rb_4k_9.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/cores/fifo_4k_9.vhd" + add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/base/gbe_med_raw.vhd" diff --git a/gbe_hub/trb3sc_gbe_hub.vhd b/gbe_hub/trb3sc_gbe_hub.vhd index e8ebcef..dd8407a 100644 --- a/gbe_hub/trb3sc_gbe_hub.vhd +++ b/gbe_hub/trb3sc_gbe_hub.vhd @@ -65,6 +65,7 @@ entity trb3sc_gbe_hub is ENPIRION_CLOCK : out std_logic; TEMPSENS : inout std_logic; --Test Connectors + DBG : out std_logic_vector(39 downto 0); TEST_LINE : out std_logic_vector(15 downto 0) ); @@ -121,6 +122,7 @@ architecture trb3sc_arch of trb3sc_gbe_hub is ---------------------------------------------------------------- signal tx_pll_lol_i : std_logic; + signal tx_pll_lol_a_i : std_logic; signal tx_pll_lol_b_i : std_logic; signal tx_pll_lol_c_i : std_logic; signal tx_pll_lol_d_i : std_logic; @@ -151,6 +153,50 @@ architecture trb3sc_arch of trb3sc_gbe_hub is signal mac_rx_eof : std_logic; signal mac_rx_err : std_logic; + signal fw_mac_rx_data_int : std_logic_vector(7 downto 0); + signal fw_mac_rx_wr_int : std_logic; + signal fw_mac_rx_eof_int : std_logic; + signal fw_mac_rx_err_int : std_logic; + signal fw_fifo_full_int : std_logic; + signal fw_fifo_wr_int : std_logic; + signal fw_fifo_data_int : std_logic_vector(8 downto 0); + signal fw_frame_req_int : std_logic; + signal fw_frame_ack_int : std_logic; + signal fw_frame_avail_int : std_logic; + signal fw_mac_tx_data_int : std_logic_vector(7 downto 0); + signal fw_mac_tx_read_int : std_logic; + signal fw_mac_fifoeof_int : std_logic; + signal fw_mac_fifoempty_int : std_logic; + signal fw_mac_fifoavail_int : std_logic; + signal fw_mac_ready_conf_int : std_logic; + signal fw_mac_reconf_int : std_logic; + signal fw_mac_an_ready_int : std_logic; + signal fw_link_active_int : std_logic; + signal fw_mac_tx_done_int : std_logic; + signal fw_mac_rx_fifofull_int : std_logic; + + signal bw_mac_rx_data_int : std_logic_vector(7 downto 0); + signal bw_mac_rx_wr_int : std_logic; + signal bw_mac_rx_eof_int : std_logic; + signal bw_mac_rx_err_int : std_logic; + signal bw_fifo_full_int : std_logic; + signal bw_fifo_wr_int : std_logic; + signal bw_fifo_data_int : std_logic_vector(8 downto 0); + signal bw_frame_req_int : std_logic; + signal bw_frame_ack_int : std_logic; + signal bw_frame_avail_int : std_logic; + signal bw_mac_tx_data_int : std_logic_vector(7 downto 0); + signal bw_mac_tx_read_int : std_logic; + signal bw_mac_fifoeof_int : std_logic; + signal bw_mac_fifoempty_int : std_logic; + signal bw_mac_fifoavail_int : std_logic; + signal bw_mac_ready_conf_int : std_logic; + signal bw_mac_reconf_int : std_logic; + signal bw_mac_an_ready_int : std_logic; + signal bw_link_active_int : std_logic; + signal bw_mac_tx_done_int : std_logic; + signal bw_mac_rx_fifofull_int : std_logic; + begin --------------------------------------------------------------------------- @@ -169,8 +215,8 @@ THE_CLOCK_RESET : entity work.clock_reset_handler SYS_CLK_OUT => clk_sys, REF_CLK_OUT => clk_full_osc, ENPIRION_CLOCK => ENPIRION_CLOCK, - LED_RED_OUT => LED_RJ_RED, - LED_GREEN_OUT => LED_RJ_GREEN, + LED_RED_OUT => open, --LED_RJ_RED, + LED_GREEN_OUT => open, --LED_RJ_GREEN, DEBUG_OUT => open ); @@ -229,26 +275,26 @@ THE_CLOCK_RESET : entity work.clock_reset_handler -- Trigger TRIGGER_IN => '0', -- MAC - MAC_READY_CONF_IN => mac_ready_conf, -- in std_logic; - MAC_RECONF_OUT => mac_reconf, -- out std_logic; - MAC_AN_READY_IN => mac_an_ready, -- in std_logic; - MAC_FIFOAVAIL_OUT => mac_fifoavail, -- out std_logic; - MAC_FIFOEOF_OUT => mac_fifoeof, -- out std_logic; - MAC_FIFOEMPTY_OUT => mac_fifoempty, -- out std_logic; - MAC_RX_FIFOFULL_OUT => mac_rx_fifofull, -- out std_logic; - MAC_TX_DATA_OUT => mac_tx_data, -- out std_logic_vector(7 downto 0); - MAC_TX_READ_IN => mac_tx_read, -- in std_logic; - MAC_TX_DISCRFRM_IN => mac_tx_discrfrm, -- in std_logic; - MAC_TX_STAT_EN_IN => mac_tx_stat_en, -- in std_logic; - MAC_TX_STATS_IN => mac_tx_stats, -- in std_logic_vector(30 downto 0); - MAC_TX_DONE_IN => mac_tx_done, -- in std_logic; - MAC_RX_FIFO_ERR_IN => mac_rx_fifo_err, -- in std_logic; - MAC_RX_STATS_IN => mac_rx_stats, -- in std_logic_vector(31 downto 0); - MAC_RX_DATA_IN => mac_rx_data, -- in std_logic_vector(7 downto 0); - MAC_RX_WRITE_IN => mac_rx_write, -- in std_logic; - MAC_RX_STAT_EN_IN => mac_rx_stat_en, -- in std_logic; - MAC_RX_EOF_IN => mac_rx_eof, -- in std_logic; - MAC_RX_ERROR_IN => mac_rx_err, -- in std_logic; + MAC_READY_CONF_IN => mac_ready_conf, + MAC_RECONF_OUT => mac_reconf, + MAC_AN_READY_IN => mac_an_ready, + MAC_FIFOAVAIL_OUT => mac_fifoavail, + MAC_FIFOEOF_OUT => mac_fifoeof, + MAC_FIFOEMPTY_OUT => mac_fifoempty, + MAC_RX_FIFOFULL_OUT => mac_rx_fifofull, + MAC_TX_DATA_OUT => mac_tx_data, + MAC_TX_READ_IN => mac_tx_read, + MAC_TX_DISCRFRM_IN => mac_tx_discrfrm, + MAC_TX_STAT_EN_IN => mac_tx_stat_en, + MAC_TX_STATS_IN => mac_tx_stats, + MAC_TX_DONE_IN => mac_tx_done, + MAC_RX_FIFO_ERR_IN => mac_rx_fifo_err, + MAC_RX_STATS_IN => mac_rx_stats, + MAC_RX_DATA_IN => mac_rx_data, + MAC_RX_WRITE_IN => mac_rx_write, + MAC_RX_STAT_EN_IN => mac_rx_stat_en, + MAC_RX_EOF_IN => mac_rx_eof, + MAC_RX_ERROR_IN => mac_rx_err, -- unique adresses MC_UNIQUE_ID_IN => timer.uid, MY_TRBNET_ADDRESS_IN => timer.network_address, @@ -275,7 +321,30 @@ THE_CLOCK_RESET : entity work.clock_reset_handler STATUS_OUT => status, DEBUG_OUT => open ); - + +-- DBG(0) <= mac_ready_conf; +-- DBG(1) <= mac_reconf; +-- DBG(2) <= mac_an_ready; +-- DBG(3) <= mac_fifoavail; +-- DBG(4) <= mac_fifoeof; +-- DBG(5) <= mac_fifoempty; +-- DBG(6) <= mac_rx_fifofull; +-- DBG(14 downto 7) <= mac_tx_data; +-- DBG(15) <= mac_tx_read; +-- DBG(16) <= mac_tx_discrfrm; +-- DBG(17) <= mac_tx_stat_en; +-- -- MAC_TX_STATS_IN => mac_tx_stats, +-- DBG(18) <= mac_tx_done; +-- DBG(19) <= mac_rx_fifo_err; +-- -- MAC_RX_STATS_IN => mac_rx_stats, +-- DBG(27 downto 20) <= mac_rx_data; +-- DBG(28) <= mac_rx_write; +-- DBG(29) <= mac_rx_stat_en; +-- DBG(30) <= mac_rx_eof; +-- DBG(31) <= mac_rx_err; +-- DBG(32) <= mac_rx_stats(18); -- control frame +-- DBG(33) <= CLK_SUPPL_PCLK; + ------------------------------------------------------------------------------- -- SCTRL endpoint for GbE standalone ------------------------------------------------------------------------------- @@ -397,10 +466,10 @@ THE_CLOCK_RESET : entity work.clock_reset_handler -- LED --------------------------------------------------------------------------- -- LED are green, orange, red, yellow, white(2), rj_green(2), rj_red(2), sfp_green(2), sfp_red(2) - LED_GREEN <= not status(0); --'0'; - LED_ORANGE <= not status(1); --'0'; - LED_RED <= not status(2); --'0'; - LED_YELLOW <= not status(5); --'0'; + LED_GREEN <= not status(2); --'0'; + LED_ORANGE <= not status(5); --'0'; + LED_RED <= not fw_link_active_int; --'0'; + LED_YELLOW <= not bw_link_active_int; --'0'; --GEN_HUB_LEDS : for i in 0 to 6 generate -- LED_HUB_LINKOK(i+1) <= not '0'; @@ -408,7 +477,6 @@ THE_CLOCK_RESET : entity work.clock_reset_handler -- LED_HUB_RX(i+1) <= not '0'; --end generate; - LED_HUB_LINKOK(1) <= not status_raw(10 * 8 + 2); --'0'; -- C2 LED_HUB_TX(1) <= not status_raw(10 * 8 + 5); --'0'; LED_HUB_RX(1) <= not '0'; @@ -432,13 +500,12 @@ THE_CLOCK_RESET : entity work.clock_reset_handler LED_HUB_LINKOK(6) <= not status_raw(5 * 8 + 2); --'0'; -- B1 LED_HUB_TX(6) <= not status_raw(5 * 8 + 5); --'0'; LED_HUB_RX(6) <= not '0'; - - LED_HUB_LINKOK(7) <= not '0'; -- B2 - LED_HUB_TX(7) <= not '0'; + LED_HUB_LINKOK(7) <= not status_raw(5 * 8 + 2); --'0'; -- B2 + LED_HUB_TX(7) <= not status_raw(6 * 8 + 5); --'0'; LED_HUB_RX(7) <= not '0'; - LED_HUB_LINKOK(8) <= not '0'; -- B3 - LED_HUB_TX(8) <= not '0'; + LED_HUB_LINKOK(8) <= not status_raw(5 * 8 + 2); --'0'; -- B3 + LED_HUB_TX(8) <= not status_raw(7 * 8 + 5); --'0'; LED_HUB_RX(8) <= not '0'; LED_SFP_GREEN(0) <= not status_raw(12 * 8 + 2); --'0'; -- D0 @@ -450,7 +517,12 @@ THE_CLOCK_RESET : entity work.clock_reset_handler LED_WHITE(1) <= not additional_reg(31); --'0'; LED_WHITE(0) <= not status(8); --'0'; + LED_RJ_GREEN(0) <= not status_raw(0 * 8 + 2); -- A0 + LED_RJ_RED(0) <= not status_raw(0 * 8 + 5); + LED_RJ_GREEN(1) <= not '0'; + LED_RJ_RED(1) <= not '0'; + --------------------------------------------------------------------------- -- PCSC is four ports downlink --------------------------------------------------------------------------- @@ -465,29 +537,57 @@ THE_CLOCK_RESET : entity work.clock_reset_handler CLK_125 => CLK_SUPPL_PCLK, CLK_125_RX => open, -- MAC status and config - MAC_READY_CONF_OUT => open, - MAC_RECONF_IN => (others => '0'), - MAC_AN_READY_OUT => open, + MAC_READY_CONF_OUT(0) => fw_mac_ready_conf_int, + MAC_READY_CONF_OUT(2 downto 1) => open, + MAC_READY_CONF_OUT(3) => bw_mac_ready_conf_int, + MAC_RECONF_IN(0) => fw_mac_reconf_int, + MAC_RECONF_IN(2 downto 1) => (others => '0'), + MAC_RECONF_IN(3) => bw_mac_reconf_int, + MAC_AN_READY_OUT(0) => fw_mac_an_ready_int, + MAC_AN_READY_OUT(2 downto 1) => open, + MAC_AN_READY_OUT(3) => bw_mac_an_ready_int, -- MAC data interface - MAC_FIFOAVAIL_IN => (others => '0'), - MAC_FIFOEOF_IN => (others => '0'), - MAC_FIFOEMPTY_IN => (others => '0'), - MAC_RX_FIFOFULL_IN => (others => '0'), + MAC_FIFOAVAIL_IN(0) => bw_mac_fifoavail_int, + MAC_FIFOAVAIL_IN(2 downto 1) => (others => '0'), + MAC_FIFOAVAIL_IN(3) => fw_mac_fifoavail_int, + MAC_FIFOEOF_IN(0) => bw_mac_fifoeof_int, + MAC_FIFOEOF_IN(2 downto 1) => (others => '0'), + MAC_FIFOEOF_IN(3) => fw_mac_fifoeof_int, + MAC_FIFOEMPTY_IN(0) => bw_mac_fifoempty_int, + MAC_FIFOEMPTY_IN(2 downto 1) => (others => '0'), + MAC_FIFOEMPTY_IN(3) => fw_mac_fifoempty_int, + MAC_RX_FIFOFULL_IN(0) => fw_mac_rx_fifofull_int, + MAC_RX_FIFOFULL_IN(2 downto 1) => (others => '0'), + MAC_RX_FIFOFULL_IN(3) => bw_mac_rx_fifofull_int, -- MAC TX interface - MAC_TX_DATA_IN => (others => '0'), - MAC_TX_READ_OUT => open, + MAC_TX_DATA_IN(7 downto 0) => bw_mac_tx_data_int, -- from TX_FIFO to C0 TX + MAC_TX_DATA_IN(23 downto 8) => (others => '0'), + MAC_TX_DATA_IN(31 downto 24) => fw_mac_tx_data_int, -- from TX_FIFO to C3 TX + MAC_TX_READ_OUT(0) => bw_mac_tx_read_int, + MAC_TX_READ_OUT(2 downto 1) => open, + MAC_TX_READ_OUT(3) => fw_mac_tx_read_int, MAC_TX_DISCRFRM_OUT => open, MAC_TX_STAT_EN_OUT => open, MAC_TX_STATS_OUT => open, - MAC_TX_DONE_OUT => open, + MAC_TX_DONE_OUT(0) => bw_mac_tx_done_int, + MAC_TX_DONE_OUT(2 downto 1) => open, + MAC_TX_DONE_OUT(3) => fw_mac_tx_done_int, -- MAC RX interface MAC_RX_FIFO_ERR_OUT => open, MAC_RX_STATS_OUT => open, - MAC_RX_DATA_OUT => open, - MAC_RX_WRITE_OUT => open, + MAC_RX_DATA_OUT(7 downto 0) => fw_mac_rx_data_int, -- from C0 RX to RX_RB + MAC_RX_DATA_OUT(23 downto 8) => open, + MAC_RX_DATA_OUT(31 downto 24) => bw_mac_rx_data_int, -- from C3 RX to RX_RB + MAC_RX_WRITE_OUT(0) => fw_mac_rx_wr_int, + MAC_RX_WRITE_OUT(2 downto 1) => open, + MAC_RX_WRITE_OUT(3) => bw_mac_rx_wr_int, MAC_RX_STAT_EN_OUT => open, - MAC_RX_EOF_OUT => open, - MAC_RX_ERROR_OUT => open, + MAC_RX_EOF_OUT(0) => fw_mac_rx_eof_int, + MAC_RX_EOF_OUT(2 downto 1) => open, + MAC_RX_EOF_OUT(3) => bw_mac_rx_eof_int, + MAC_RX_ERROR_OUT(0) => fw_mac_rx_err_int, + MAC_RX_ERROR_OUT(2 downto 1) => open, + MAC_RX_ERROR_OUT(3) => bw_mac_rx_err_int, -- SFP Connection SD_PRSNT_N_IN(0) => HUB_MOD0(3), SD_PRSNT_N_IN(1) => HUB_MOD0(4), @@ -511,12 +611,200 @@ THE_CLOCK_RESET : entity work.clock_reset_handler DEBUG_OUT => open ); + DBG(3 downto 0) <= fw_mac_rx_data_int(3 downto 0); + DBG(7 downto 4) <= fw_mac_tx_data_int(3 downto 0); + DBG(11 downto 8) <= bw_mac_rx_data_int(3 downto 0); + DBG(15 downto 12) <= bw_mac_tx_data_int(3 downto 0); + DBG(16) <= fw_mac_rx_wr_int; + DBG(17) <= bw_mac_rx_wr_int; + DBG(18) <= fw_mac_tx_read_int; + DBG(19) <= bw_mac_tx_read_int; + DBG(20) <= fw_mac_rx_eof_int; + DBG(21) <= bw_mac_rx_eof_int; + DBG(22) <= fw_mac_fifoeof_int; + DBG(23) <= bw_mac_fifoeof_int; + DBG(24) <= fw_mac_ready_conf_int; + DBG(25) <= bw_mac_ready_conf_int; + DBG(26) <= fw_mac_fifoempty_int; + DBG(27) <= bw_mac_fifoempty_int; + DBG(28) <= fw_mac_rx_fifofull_int; + DBG(29) <= bw_mac_rx_fifofull_int; + DBG(30) <= fw_mac_an_ready_int; + DBG(31) <= bw_mac_an_ready_int; + DBG(32) <= clear; + DBG(33) <= CLK_SUPPL_PCLK; + +-- DBG(7 downto 0) <= fw_mac_rx_data_int; +-- DBG(8) <= fw_mac_rx_wr_int; +-- DBG(9) <= fw_mac_rx_eof_int; +-- DBG(10) <= fw_mac_rx_err_int; +-- DBG(11) <= fw_mac_reconf_int; +-- DBG(12) <= fw_mac_ready_conf_int; +-- DBG(13) <= fw_mac_rx_fifofull_int; +-- DBG(14) <= fw_mac_an_ready_int; +-- DBG(15) <= '0'; +-- DBG(23 downto 16) <= mac_rx_data; +-- DBG(24) <= mac_rx_write; +-- DBG(25) <= mac_rx_eof; +-- DBG(26) <= mac_rx_err; +-- DBG(27) <= mac_reconf; +-- DBG(28) <= mac_ready_conf; +-- DBG(29) <= mac_rx_fifofull; +-- DBG(30) <= mac_an_ready; +-- DBG(31) <= link_tx_ready_i; +-- DBG(32) <= clear; +-- DBG(33) <= CLK_SUPPL_PCLK; + + THE_FW_GBE_LSM: entity gbe_lsm + port map( + CLK => CLK_SUPPL_PCLK, + CLEAR => clear, + RESET => reset_i, + -- + MAC_AN_COMPLETE_IN => fw_mac_an_ready_int, + MAC_READY_CONF_IN => fw_mac_ready_conf_int, + MAC_RECONF_OUT => fw_mac_reconf_int, + -- + LINK_ACTIVE_OUT => fw_link_active_int, + -- + DEBUG => open + ); + + THE_FW_RB: entity rx_rb + port map( + CLK => CLK_SUPPL_PCLK, + CLEAR => clear, + RESET => reset_i, + -- MAC interface (RX) + MAC_RX_DATA_IN => fw_mac_rx_data_int, + MAC_RX_WR_IN => fw_mac_rx_wr_int, + MAC_RX_EOF_IN => fw_mac_rx_eof_int, + MAC_RX_ERROR_IN => fw_mac_rx_err_int, + MAC_RX_FIFOFULL_OUT => fw_mac_rx_fifofull_int, -- BUG + -- FIFO interface (TX) + FIFO_FULL_IN => fw_fifo_full_int, + FIFO_WR_OUT => fw_fifo_wr_int, + FIFO_Q_OUT => fw_fifo_data_int, + FRAME_REQ_IN => fw_frame_req_int, + FRAME_ACK_OUT => fw_frame_ack_int, + FRAME_AVAIL_OUT => fw_frame_avail_int, + -- + DEBUG => open + ); + + THE_FW_FIFO: entity tx_fifo + port map( + CLK => CLK_SUPPL_PCLK, + CLEAR => clear, + RESET => reset_i, + -- MAC interface + MAC_TX_DATA_OUT => fw_mac_tx_data_int, + MAC_TX_READ_IN => fw_mac_tx_read_int, + MAC_FIFOEOF_OUT => fw_mac_fifoeof_int, + MAC_FIFOEMPTY_OUT => fw_mac_fifoempty_int, + MAC_FIFOAVAIL_OUT => fw_mac_fifoavail_int, + MAC_TX_DONE_IN => '0', -- not used + -- FIFO interface + FIFO_FULL_OUT => fw_fifo_full_int, + FIFO_WR_IN => fw_fifo_wr_int, + FIFO_D_IN => fw_fifo_data_int, + -- + DEBUG => open + ); + + THE_FW_FORWARDER: entity forwarder + port map( + CLK => CLK_SUPPL_PCLK, + CLEAR => clear, + RESET => reset_i, + -- + FRAME_AVAIL_IN => fw_frame_avail_int, + FIFO_FULL_IN => fw_fifo_full_int, + FRAME_REQ_OUT => fw_frame_req_int, + FRAME_ACK_IN => fw_frame_ack_int, + -- + DEBUG => open + ); + + THE_BW_GBE_LSM: entity gbe_lsm + port map( + CLK => CLK_SUPPL_PCLK, + CLEAR => clear, + RESET => reset_i, + -- + MAC_AN_COMPLETE_IN => bw_mac_an_ready_int, + MAC_READY_CONF_IN => bw_mac_ready_conf_int, + MAC_RECONF_OUT => bw_mac_reconf_int, + -- + LINK_ACTIVE_OUT => bw_link_active_int, + -- + DEBUG => open + ); + + THE_BW_RB: entity rx_rb + port map( + CLK => CLK_SUPPL_PCLK, + CLEAR => clear, + RESET => reset_i, + -- MAC interface (RX) + MAC_RX_DATA_IN => bw_mac_rx_data_int, + MAC_RX_WR_IN => bw_mac_rx_wr_int, + MAC_RX_EOF_IN => bw_mac_rx_eof_int, + MAC_RX_ERROR_IN => bw_mac_rx_err_int, + MAC_RX_FIFOFULL_OUT => bw_mac_rx_fifofull_int, -- BUG + -- FIFO interface (TX) + FIFO_FULL_IN => bw_fifo_full_int, + FIFO_WR_OUT => bw_fifo_wr_int, + FIFO_Q_OUT => bw_fifo_data_int, + FRAME_REQ_IN => bw_frame_req_int, + FRAME_ACK_OUT => bw_frame_ack_int, + FRAME_AVAIL_OUT => bw_frame_avail_int, + -- + DEBUG => open + ); + + THE_BW_FIFO: entity tx_fifo + port map( + CLK => CLK_SUPPL_PCLK, + CLEAR => clear, + RESET => reset_i, + -- MAC interface + MAC_TX_DATA_OUT => bw_mac_tx_data_int, + MAC_TX_READ_IN => bw_mac_tx_read_int, + MAC_FIFOEOF_OUT => bw_mac_fifoeof_int, + MAC_FIFOEMPTY_OUT => bw_mac_fifoempty_int, + MAC_FIFOAVAIL_OUT => bw_mac_fifoavail_int, + MAC_TX_DONE_IN => '0', -- not used + -- FIFO interface + FIFO_FULL_OUT => bw_fifo_full_int, + FIFO_WR_IN => bw_fifo_wr_int, + FIFO_D_IN => bw_fifo_data_int, + -- + DEBUG => open + ); + +-- -- - -- + + THE_BW_FORWARDER: entity forwarder + port map( + CLK => CLK_SUPPL_PCLK, + CLEAR => clear, + RESET => reset_i, + -- + FRAME_AVAIL_IN => bw_frame_avail_int, + FIFO_FULL_IN => bw_fifo_full_int, + FRAME_REQ_OUT => bw_frame_req_int, + FRAME_ACK_IN => bw_frame_ack_int, + -- + DEBUG => open + ); + --------------------------------------------------------------------------- -- PCSB is two ports downlink (6port hub addon) or four ports downlink (8port hub addon) --------------------------------------------------------------------------- THE_GBE_MED_RAW_PCSB: entity gbe_med_raw generic map( - LINKS_ACTIVE => "0011" + LINKS_ACTIVE => "1111" ) port map( RESET => reset_i, @@ -551,16 +839,16 @@ THE_CLOCK_RESET : entity work.clock_reset_handler -- SFP Connection SD_PRSNT_N_IN(0) => HUB_MOD0(5), SD_PRSNT_N_IN(1) => HUB_MOD0(6), - SD_PRSNT_N_IN(2) => '1', --HUB_MOD0(7), - SD_PRSNT_N_IN(3) => '1', --HUB_MOD0(8), + SD_PRSNT_N_IN(2) => HUB_MOD0(7), --'1', + SD_PRSNT_N_IN(3) => HUB_MOD0(8), --'1', SD_LOS_IN(0) => HUB_LOS(5), SD_LOS_IN(1) => HUB_LOS(6), - SD_LOS_IN(2) => '1', --HUB_LOS(7), - SD_LOS_IN(3) => '1', --HUB_LOS(8), + SD_LOS_IN(2) => HUB_LOS(7), --'1', + SD_LOS_IN(3) => HUB_LOS(8), --'1', SD_TXDIS_OUT(0) => HUB_TXDIS(5), SD_TXDIS_OUT(1) => HUB_TXDIS(6), - SD_TXDIS_OUT(2) => open, --HUB_TXDIS(7), - SD_TXDIS_OUT(3) => open, --HUB_TXDIS(8), + SD_TXDIS_OUT(2) => HUB_TXDIS(7), --open, + SD_TXDIS_OUT(3) => HUB_TXDIS(8), --open,mac_ready_conf -- SerDes control TX_PLOL_LOL_OUT => tx_pll_lol_b_i, TX_PCS_RST_IN => tx_pcs_rst_i, @@ -631,6 +919,66 @@ THE_CLOCK_RESET : entity work.clock_reset_handler DEBUG_OUT => open ); +--------------------------------------------------------------------------- +-- PCSA is one port uplink (backplane) +--------------------------------------------------------------------------- + THE_GBE_MED_RAW_PCSA: entity gbe_med_raw + generic map( + LINKS_ACTIVE => "0001" + ) + port map( + RESET => reset_i, + GSR_N => GSR_N, + CLK_SYS => clk_sys, + CLK_125 => CLK_SUPPL_PCLK, + CLK_125_RX => open, + -- MAC status and config + MAC_READY_CONF_OUT => open, + MAC_RECONF_IN => (others => '0'), + MAC_AN_READY_OUT => open, + -- MAC data interface + MAC_FIFOAVAIL_IN => (others => '0'), + MAC_FIFOEOF_IN => (others => '0'), + MAC_FIFOEMPTY_IN => (others => '0'), + MAC_RX_FIFOFULL_IN => (others => '0'), + -- MAC TX interface + MAC_TX_DATA_IN => (others => '0'), + MAC_TX_READ_OUT => open, + MAC_TX_DISCRFRM_OUT => open, + MAC_TX_STAT_EN_OUT => open, + MAC_TX_STATS_OUT => open, + MAC_TX_DONE_OUT => open, + -- MAC RX interface + MAC_RX_FIFO_ERR_OUT => open, + MAC_RX_STATS_OUT => open, + MAC_RX_DATA_OUT => open, + MAC_RX_WRITE_OUT => open, + MAC_RX_STAT_EN_OUT => open, + MAC_RX_EOF_OUT => open, + MAC_RX_ERROR_OUT => open, + -- SFP Connection + SD_PRSNT_N_IN(0) => HUB_MOD0(5), + SD_PRSNT_N_IN(1) => '1', + SD_PRSNT_N_IN(2) => '1', + SD_PRSNT_N_IN(3) => '1', + SD_LOS_IN(0) => HUB_LOS(5), + SD_LOS_IN(1) => '1', + SD_LOS_IN(2) => '1', + SD_LOS_IN(3) => '1', + SD_TXDIS_OUT(0) => HUB_TXDIS(5), + SD_TXDIS_OUT(1) => open, + SD_TXDIS_OUT(2) => open, + SD_TXDIS_OUT(3) => open, + -- SerDes control + TX_PLOL_LOL_OUT => tx_pll_lol_a_i, + TX_PCS_RST_IN => tx_pcs_rst_i, + RX_LINK_READY_OUT => open, + TX_LINK_READY_IN => open, + -- Debug + STATUS_OUT => status_raw(1 * 32 - 1 downto 0 * 32), + DEBUG_OUT => open + ); + --------------------------------------------------------------------------- -- RSL for TX of SerDes, based on extRSL logic --------------------------------------------------------------------------- @@ -646,73 +994,6 @@ THE_CLOCK_RESET : entity work.clock_reset_handler STATE_OUT => open ); - tx_pll_lol_i <= tx_pll_lol_b_i or tx_pll_lol_c_i or tx_pll_lol_d_i; + tx_pll_lol_i <= tx_pll_lol_a_i or tx_pll_lol_b_i or tx_pll_lol_c_i or tx_pll_lol_d_i; - - --- GBE : entity work.gbe_wrapper_single --- generic map( --- DO_SIMULATION => 0, --- INCLUDE_DEBUG => 0, --- USE_INTERNAL_TRBNET_DUMMY => 0, --- USE_EXTERNAL_TRBNET_DUMMY => 0, --- RX_PATH_ENABLE => 1, --- FIXED_SIZE_MODE => 1, --- INCREMENTAL_MODE => 1, --- FIXED_SIZE => 100, --- FIXED_DELAY_MODE => 1, --- UP_DOWN_MODE => 0, --- UP_DOWN_LIMIT => 100, --- FIXED_DELAY => 100, --- --- NUMBER_OF_GBE_LINKS => 4, --- LINKS_ACTIVE => "0001", --- --- LINK_HAS_READOUT => "0000", --- LINK_HAS_SLOWCTRL => "0001", --- LINK_HAS_DHCP => "0001", --- LINK_HAS_ARP => "0001", --- LINK_HAS_PING => "0001", --- LINK_HAS_FWD => "0000" --- ) --- port map( --- CLK_SYS_IN => clk_sys, --- CLK_125_IN => CLK_SUPPL_PCLK, --- RESET => reset_i, --- GSR_N => GSR_N, --- -- Trigger --- TRIGGER_IN => '0', --- -- SFP --- SD_PRSNT_N_IN(0) => SFP_MOD0(0), --- SD_LOS_IN(0) => SFP_LOS(0), --- SD_TXDIS_OUT(0) => SFP_TX_DIS(0), --- -- unique adresses --- MC_UNIQUE_ID_IN => timer.uid, --- MY_TRBNET_ADDRESS_IN => timer.network_address, --- ISSUE_REBOOT_OUT => reboot_from_gbe, --- -- slow control by GbE --- GSC_CLK_IN => clk_sys, --- GSC_INIT_DATAREADY_OUT => gsc_init_dataready, --- GSC_INIT_DATA_OUT => gsc_init_data, --- GSC_INIT_PACKET_NUM_OUT => gsc_init_packet_num, --- GSC_INIT_READ_IN => gsc_init_read, --- GSC_REPLY_DATAREADY_IN => gsc_reply_dataready, --- GSC_REPLY_DATA_IN => gsc_reply_data, --- GSC_REPLY_PACKET_NUM_IN => gsc_reply_packet_num, --- GSC_REPLY_READ_OUT => gsc_reply_read, --- GSC_BUSY_IN => gsc_busy, --- -- readout --- BUS_IP_RX => busgbeip_rx, --- BUS_IP_TX => busgbeip_tx, --- BUS_REG_RX => busgbereg_rx, --- BUS_REG_TX => busgbereg_tx, --- -- reset --- MAKE_RESET_OUT => reset_via_gbe, --- -- debug --- STATUS_OUT => status, --- DEBUG_OUT => open --- ); --- --- SFP_TX_DIS(1) <= '1'; - end architecture; -- 2.43.0