From cccdaa70d2e1c605fd6731b92e14635a08496a9f Mon Sep 17 00:00:00 2001 From: Cahit Date: Wed, 16 Dec 2015 14:31:31 +0100 Subject: [PATCH] updated 32PinAddOn project top module with record entities --- releases/tdc_v2.3/trb3_periph_32PinAddOn.vhd | 598 ++++++------------- 1 file changed, 170 insertions(+), 428 deletions(-) diff --git a/releases/tdc_v2.3/trb3_periph_32PinAddOn.vhd b/releases/tdc_v2.3/trb3_periph_32PinAddOn.vhd index edd0412..e32398b 100644 --- a/releases/tdc_v2.3/trb3_periph_32PinAddOn.vhd +++ b/releases/tdc_v2.3/trb3_periph_32PinAddOn.vhd @@ -27,8 +27,6 @@ entity trb3_periph_32PinAddOn is CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 2/(1357), 200 MHz, only in case of problems SERDES_INT_TX : out std_logic_vector(3 downto 0); SERDES_INT_RX : in std_logic_vector(3 downto 0); - SERDES_ADDON_TX : out std_logic_vector(11 downto 0); - SERDES_ADDON_RX : in std_logic_vector(11 downto 0); --Inter-FPGA Communication FPGA5_COMM : inout std_logic_vector(11 downto 0); --Bit 0/1 input, serial link RX active @@ -58,7 +56,7 @@ entity trb3_periph_32PinAddOn is LED_YELLOW : out std_logic; SUPPL : in std_logic; --terminated diff pair, PCLK, Pads --Test Connectors - TEST_LINE : out std_logic_vector(15 downto 0) + TEST_LINE : inout std_logic_vector(15 downto 0) ); attribute syn_useioff : boolean; --no IO-FF for LEDs relaxes timing constraints @@ -85,18 +83,14 @@ entity trb3_periph_32PinAddOn is attribute syn_useioff of DAC_OUT_SCK : signal is true; attribute syn_useioff of DAC_OUT_CS : signal is true; attribute syn_useioff of DAC_OUT_CLR : signal is true; - + end entity; architecture trb3_periph_32PinAddOn_arch of trb3_periph_32PinAddOn is - --Constants - constant REGIO_NUM_STAT_REGS : integer := 0; - constant REGIO_NUM_CTRL_REGS : integer := 0; - - attribute syn_keep : boolean; - attribute syn_preserve : boolean; + attribute syn_keep : boolean; + attribute syn_preserve : boolean; --Clock / Reset signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL @@ -110,106 +104,32 @@ architecture trb3_periph_32PinAddOn_arch of trb3_periph_32PinAddOn is attribute syn_preserve of GSR_N : signal is true; --Media Interface - signal med_stat_op : std_logic_vector (1*16-1 downto 0); - signal med_ctrl_op : std_logic_vector (1*16-1 downto 0); - signal med_stat_debug : std_logic_vector (1*64-1 downto 0); - signal med_data_out : std_logic_vector (1*16-1 downto 0); - signal med_packet_num_out : std_logic_vector (1*3-1 downto 0); - signal med_dataready_out : std_logic; - signal med_read_out : std_logic; - signal med_data_in : std_logic_vector (1*16-1 downto 0); - signal med_packet_num_in : std_logic_vector (1*3-1 downto 0); - signal med_dataready_in : std_logic; - signal med_read_in : std_logic; - - --LVL1 channel - signal timing_trg_received_i : std_logic; + signal med_stat_debug : std_logic_vector (1*64-1 downto 0); + signal med2int : med2int_array_t(0 to 0); + signal int2med : int2med_array_t(0 to 0); + + signal timing_trg_received_i : std_logic; --READOUT signal readout_rx : READOUT_RX; signal readout_tx : readout_tx_array_t(0 to 0); --Slow Control channel - signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0); - signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); - signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0); - signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0); - signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0); - signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0); - signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0); - signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0); - - --RegIO - signal regio_addr_out : std_logic_vector (15 downto 0); - signal regio_read_enable_out : std_logic; - signal regio_write_enable_out : std_logic; - signal regio_data_out : std_logic_vector (31 downto 0); - signal regio_data_in : std_logic_vector (31 downto 0); - signal regio_dataready_in : std_logic; - signal regio_no_more_data_in : std_logic; - signal regio_write_ack_in : std_logic; - signal regio_unknown_addr_in : std_logic; - signal regio_timeout_out : std_logic; - - --Timer - signal global_time : std_logic_vector(31 downto 0); - signal local_time : std_logic_vector(7 downto 0); - signal time_since_last_trg : std_logic_vector(31 downto 0); - signal timer_ticks : std_logic_vector(1 downto 0); - - --Flash - signal spimem_read_en : std_logic; - signal spimem_write_en : std_logic; - signal spimem_data_in : std_logic_vector(31 downto 0); - signal spimem_addr : std_logic_vector(8 downto 0); - signal spimem_data_out : std_logic_vector(31 downto 0); - signal spimem_dataready_out : std_logic; - signal spimem_no_more_data_out : std_logic; - signal spimem_unknown_addr_out : std_logic; - signal spimem_write_ack_out : std_logic; - - signal spidac_read_en : std_logic; - signal spidac_write_en : std_logic; - signal spidac_data_in : std_logic_vector(31 downto 0); - signal spidac_addr : std_logic_vector(4 downto 0); - signal spidac_data_out : std_logic_vector(31 downto 0); - signal spidac_ack : std_logic; - signal spidac_busy : std_logic; - - signal dac_cs_i : std_logic_vector(3 downto 0); - signal dac_sck_i : std_logic; - signal dac_sdi_i : std_logic; - - signal spi_bram_addr : std_logic_vector(7 downto 0); - signal spi_bram_wr_d : std_logic_vector(7 downto 0); - signal spi_bram_rd_d : std_logic_vector(7 downto 0); - signal spi_bram_we : std_logic; - - signal trig_out : std_logic_vector(3 downto 0); - signal trig_din : std_logic_vector(31 downto 0); - signal trig_dout : std_logic_vector(31 downto 0); - signal trig_write : std_logic := '0'; - signal trig_read : std_logic := '0'; - signal trig_ack : std_logic := '0'; - signal trig_nack : std_logic := '0'; - signal trig_addr : std_logic_vector(15 downto 0) := (others => '0'); - - signal stat_out : std_logic_vector(3 downto 0); - signal stat_din : std_logic_vector(31 downto 0); - signal stat_dout : std_logic_vector(31 downto 0); - signal stat_write : std_logic := '0'; - signal stat_read : std_logic := '0'; - signal stat_ack : std_logic := '0'; - signal stat_nack : std_logic := '0'; - signal stat_addr : std_logic_vector(15 downto 0) := (others => '0'); - - signal sed_error : std_logic; - signal bussed_rx, bustdc_rx : CTRLBUS_RX; - signal bussed_tx, bustdc_tx : CTRLBUS_TX; - + signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); + + signal ctrlbus_rx, bustdc_rx, bustools_rx, bus_master_out : CTRLBUS_RX; + signal ctrlbus_tx, bustdc_tx, bustools_tx, bus_master_in : CTRLBUS_TX; + signal bus_master_active : std_logic; + signal timer : TIMERS; + signal lcd_data : std_logic_vector(511 downto 0); + signal lcd_out : std_logic_vector(4 downto 0); + signal feature_outputs_i : std_logic_vector(15 downto 0); + signal spi_cs, spi_mosi, spi_miso, spi_clk, spi_clr : std_logic_vector(15 downto 0); + signal uart_rx, uart_tx, debug_rx, debug_tx : std_logic; + signal trig_gen_out_i : std_logic_vector(3 downto 0); + signal sed_error_i : std_logic; --TDC - signal hit_in_i : std_logic_vector(64 downto 1); - signal logic_analyser_i : std_logic_vector(15 downto 0); + signal hit_in_i : std_logic_vector(64 downto 1); begin --------------------------------------------------------------------------- @@ -223,15 +143,15 @@ begin RESET_DELAY => x"FEEE" ) port map( - CLEAR_IN => '0', -- reset input (high active, async) - CLEAR_N_IN => '1', -- reset input (low active, async) - CLK_IN => clk_200_i, -- raw master clock, NOT from PLL/DLL! - SYSCLK_IN => clk_100_i, -- PLL/DLL remastered clock - PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async) - RESET_IN => '0', -- general reset signal (SYSCLK) - TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK) - CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE! - RESET_OUT => reset_i, -- synchronous reset out (SYSCLK) + CLEAR_IN => '0', -- reset input (high active, async) + CLEAR_N_IN => '1', -- reset input (low active, async) + CLK_IN => clk_200_i, -- raw master clock, NOT from PLL/DLL! + SYSCLK_IN => clk_100_i, -- PLL/DLL remastered clock + PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async) + RESET_IN => '0', -- general reset signal (SYSCLK) + TRB_RESET_IN => med2int(0).stat_op(13), -- TRBnet reset signal (SYSCLK) + CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE! + RESET_OUT => reset_i, -- synchronous reset out (SYSCLK) DEBUG_OUT => open ); @@ -248,7 +168,7 @@ begin LOCK => pll_lock ); - pll_calibration: entity work.pll_in125_out33 + pll_calibration : entity work.pll_in125_out33 port map ( CLK => CLK_GPLL_LEFT, CLKOP => osc_int, @@ -272,14 +192,14 @@ begin CLEAR => clear_i, CLK_EN => '1', --Internal Connection - MED_DATA_IN => med_data_out, - MED_PACKET_NUM_IN => med_packet_num_out, - MED_DATAREADY_IN => med_dataready_out, - MED_READ_OUT => med_read_in, - MED_DATA_OUT => med_data_in, - MED_PACKET_NUM_OUT => med_packet_num_in, - MED_DATAREADY_OUT => med_dataready_in, - MED_READ_IN => med_read_out, + MED_DATA_IN => int2med(0).data, + MED_PACKET_NUM_IN => int2med(0).packet_num, + MED_DATAREADY_IN => int2med(0).dataready, + MED_READ_OUT => med2int(0).tx_read, + MED_DATA_OUT => med2int(0).data, + MED_PACKET_NUM_OUT => med2int(0).packet_num, + MED_DATAREADY_OUT => med2int(0).dataready, + MED_READ_IN => '1', REFCLK2CORE_OUT => open, --SFP Connection SD_RXD_P_IN => SERDES_INT_RX(2), @@ -292,8 +212,8 @@ begin SD_LOS_IN => FPGA5_COMM(0), SD_TXDIS_OUT => FPGA5_COMM(2), -- Status and control port - STAT_OP => med_stat_op, - CTRL_OP => med_ctrl_op, + STAT_OP => med2int(0).stat_op, + CTRL_OP => int2med(0).ctrl_op, STAT_DEBUG => med_stat_debug, CTRL_DEBUG => (others => '0') ); @@ -301,21 +221,13 @@ begin --------------------------------------------------------------------------- -- Endpoint --------------------------------------------------------------------------- - - THE_ENDPOINT : trb_net16_endpoint_hades_full_handler - generic map( - REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS, - REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, + THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record + generic map ( ADDRESS_MASK => x"FFFF", BROADCAST_BITMASK => x"FF", - BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR, - REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)), - REGIO_HARDWARE_VERSION => HARDWARE_INFO, - REGIO_INCLUDED_FEATURES => INCLUDED_FEATURES, - REGIO_INIT_ADDRESS => INIT_ADDRESS, - REGIO_USE_VAR_ENDPOINT_ID => c_YES, - CLOCK_FREQUENCY => CLOCK_FREQUENCY, + REGIO_INIT_ENDPOINT_ID => x"0001", TIMING_TRIGGER_RAW => c_YES, + REGIO_USE_VAR_ENDPOINT_ID => c_YES, --Configure data handler DATA_INTERFACE_NUMBER => 1, DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE, @@ -325,346 +237,174 @@ begin HEADER_BUFFER_DEPTH => 9, HEADER_BUFFER_FULL_THRESH => 2**9-16 ) + port map( - CLK => clk_100_i, - RESET => reset_i, - CLK_EN => '1', - MED_DATAREADY_OUT => med_dataready_out, -- open, -- - MED_DATA_OUT => med_data_out, -- open, -- - MED_PACKET_NUM_OUT => med_packet_num_out, -- open, -- - MED_READ_IN => med_read_in, - MED_DATAREADY_IN => med_dataready_in, - MED_DATA_IN => med_data_in, - MED_PACKET_NUM_IN => med_packet_num_in, - MED_READ_OUT => med_read_out, -- open, -- - MED_STAT_OP_IN => med_stat_op, - MED_CTRL_OP_OUT => med_ctrl_op, + -- Misc + CLK => clk_100_i, + RESET => reset_i, + CLK_EN => '1', + + -- Media direction port + MEDIA_MED2INT => med2int(0), + MEDIA_INT2MED => int2med(0), --Timing trigger in - TRG_TIMING_TRG_RECEIVED_IN => timing_trg_received_i, - --LVL1 trigger to FEE - LVL1_TRG_DATA_VALID_OUT => readout_rx.data_valid, - LVL1_VALID_TIMING_TRG_OUT => readout_rx.valid_timing_trg, - LVL1_VALID_NOTIMING_TRG_OUT => readout_rx.valid_notiming_trg, - LVL1_INVALID_TRG_OUT => readout_rx.invalid_trg, - - LVL1_TRG_TYPE_OUT => readout_rx.trg_type, - LVL1_TRG_NUMBER_OUT => readout_rx.trg_number, - LVL1_TRG_CODE_OUT => readout_rx.trg_code, - LVL1_TRG_INFORMATION_OUT => readout_rx.trg_information, - LVL1_INT_TRG_NUMBER_OUT => readout_rx.trg_int_number, - - --Information about trigger handler errors - TRG_MULTIPLE_TRG_OUT => readout_rx.trg_multiple, - TRG_TIMEOUT_DETECTED_OUT => readout_rx.trg_timeout, - TRG_SPURIOUS_TRG_OUT => readout_rx.trg_spurious, - TRG_MISSING_TMG_TRG_OUT => readout_rx.trg_missing, - TRG_SPIKE_DETECTED_OUT => readout_rx.trg_spike, - - --Response from FEE - FEE_TRG_RELEASE_IN(0) => readout_tx(0).busy_release, - FEE_TRG_STATUSBITS_IN => readout_tx(0).statusbits, - FEE_DATA_IN => readout_tx(0).data, - FEE_DATA_WRITE_IN(0) => readout_tx(0).data_write, - FEE_DATA_FINISHED_IN(0) => readout_tx(0).data_finished, - FEE_DATA_ALMOST_FULL_OUT(0) => readout_rx.buffer_almost_full, - - -- Slow Control Data Port - REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00 - REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 - REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe, - REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe, - REGIO_STAT_REG_IN => stat_reg, --start 0x80 - REGIO_CTRL_REG_OUT => ctrl_reg, --start 0xc0 - REGIO_STAT_STROBE_OUT => stat_reg_strobe, - REGIO_CTRL_STROBE_OUT => ctrl_reg_strobe, + TRG_TIMING_TRG_RECEIVED_IN => timing_trg_received_i, + + READOUT_RX => readout_rx, + READOUT_TX => readout_tx, + + --Slow Control Port + REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 + BUS_RX => ctrlbus_rx, + BUS_TX => ctrlbus_tx, + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE, REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'), - - BUS_ADDR_OUT => regio_addr_out, - BUS_READ_ENABLE_OUT => regio_read_enable_out, - BUS_WRITE_ENABLE_OUT => regio_write_enable_out, - BUS_DATA_OUT => regio_data_out, - BUS_DATA_IN => regio_data_in, - BUS_DATAREADY_IN => regio_dataready_in, - BUS_NO_MORE_DATA_IN => regio_no_more_data_in, - BUS_WRITE_ACK_IN => regio_write_ack_in, - BUS_UNKNOWN_ADDR_IN => regio_unknown_addr_in, - BUS_TIMEOUT_OUT => regio_timeout_out, - ONEWIRE_INOUT => TEMPSENS, - ONEWIRE_MONITOR_OUT => open, - - TIME_GLOBAL_OUT => global_time, - TIME_LOCAL_OUT => local_time, - TIME_SINCE_LAST_TRG_OUT => time_since_last_trg, - TIME_TICKS_OUT => timer_ticks, - - STAT_DEBUG_IPU => open, - STAT_DEBUG_1 => open, - STAT_DEBUG_2 => open, - STAT_DEBUG_DATA_HANDLER_OUT => open, - STAT_DEBUG_IPU_HANDLER_OUT => open, - STAT_TRIGGER_OUT => open, - CTRL_MPLEX => (others => '0'), - IOBUF_CTRL_GEN => (others => '0'), - STAT_ONEWIRE => open, - STAT_ADDR_DEBUG => open, - DEBUG_LVL1_HANDLER_OUT => open + ONEWIRE_INOUT => TEMPSENS, + --Timing registers + TIMERS_OUT => timer ); ---------------------------------------------------------------------------- --- AddOn ---------------------------------------------------------------------------- timing_trg_received_i <= TRIGGER_LEFT; --------------------------------------------------------------------------- -- Bus Handler --------------------------------------------------------------------------- - THE_BUS_HANDLER : trb_net16_regio_bus_handler + THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record generic map( - PORT_NUMBER => 6, - PORT_ADDRESSES => (0 => x"d000", 1 => x"d400", 2 => x"c000", 3 => x"cf00", 4 => x"cf80", - 5 => x"d500", - others => x"0000"), - PORT_ADDR_MASK => (0 => 9, 1 => 5, 2 => 12, 3 => 6, 4 => 7, - 5 => 4, - others => 0), - PORT_MASK_ENABLE => 1 + PORT_NUMBER => 2, + PORT_ADDRESSES => (0 => x"d000", 1 => x"c000", others => x"0000"), + PORT_ADDR_MASK => (0 => 12, 1 => 12, others => 0), + PORT_MASK_ENABLE => 1 ) port map( CLK => clk_100_i, RESET => reset_i, - DAT_ADDR_IN => regio_addr_out, - DAT_DATA_IN => regio_data_out, - DAT_DATA_OUT => regio_data_in, - DAT_READ_ENABLE_IN => regio_read_enable_out, - DAT_WRITE_ENABLE_IN => regio_write_enable_out, - DAT_TIMEOUT_IN => regio_timeout_out, - DAT_DATAREADY_OUT => regio_dataready_in, - DAT_WRITE_ACK_OUT => regio_write_ack_in, - DAT_NO_MORE_DATA_OUT => regio_no_more_data_in, - DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in, - - --Bus Handler (SPI Flash control) - BUS_READ_ENABLE_OUT(0) => spimem_read_en, - BUS_WRITE_ENABLE_OUT(0) => spimem_write_en, - BUS_DATA_OUT(0*32+31 downto 0*32) => spimem_data_in, - BUS_ADDR_OUT(0*16+8 downto 0*16) => spimem_addr, - BUS_ADDR_OUT(0*16+15 downto 0*16+9) => open, - BUS_TIMEOUT_OUT(0) => open, - BUS_DATA_IN(0*32+31 downto 0*32) => spimem_data_out, - BUS_DATAREADY_IN(0) => spimem_dataready_out, - BUS_WRITE_ACK_IN(0) => spimem_write_ack_out, - BUS_NO_MORE_DATA_IN(0) => spimem_no_more_data_out, - BUS_UNKNOWN_ADDR_IN(0) => spimem_unknown_addr_out, - --Bus Handler (SPI DAC) - BUS_READ_ENABLE_OUT(1) => spidac_read_en, - BUS_WRITE_ENABLE_OUT(1) => spidac_write_en, - BUS_DATA_OUT(1*32+31 downto 1*32) => spidac_data_in, - BUS_ADDR_OUT(1*16+4 downto 1*16) => spidac_addr, - BUS_ADDR_OUT(1*16+15 downto 1*16+5) => open, - BUS_TIMEOUT_OUT(1) => open, - BUS_DATA_IN(1*32+31 downto 1*32) => spidac_data_out, - BUS_DATAREADY_IN(1) => spidac_ack, - BUS_WRITE_ACK_IN(1) => spidac_ack, - BUS_NO_MORE_DATA_IN(1) => spidac_busy, - BUS_UNKNOWN_ADDR_IN(1) => '0', - --TDC - BUS_READ_ENABLE_OUT(2) => bustdc_rx.read, - BUS_WRITE_ENABLE_OUT(2) => bustdc_rx.write, - BUS_DATA_OUT(2*32+31 downto 2*32) => bustdc_rx.data, - BUS_ADDR_OUT(2*16+15 downto 2*16) => bustdc_rx.addr, - BUS_TIMEOUT_OUT(2) => bustdc_rx.timeout, - BUS_DATA_IN(2*32+31 downto 2*32) => bustdc_tx.data, - BUS_DATAREADY_IN(2) => bustdc_tx.ack, - BUS_WRITE_ACK_IN(2) => bustdc_tx.ack, - BUS_NO_MORE_DATA_IN(2) => bustdc_tx.nack, - BUS_UNKNOWN_ADDR_IN(2) => bustdc_tx.unknown, - --Trigger logic registers - BUS_READ_ENABLE_OUT(3) => trig_read, - BUS_WRITE_ENABLE_OUT(3) => trig_write, - BUS_DATA_OUT(3*32+31 downto 3*32) => trig_din, - BUS_ADDR_OUT(3*16+15 downto 3*16) => trig_addr, - BUS_TIMEOUT_OUT(3) => open, - BUS_DATA_IN(3*32+31 downto 3*32) => trig_dout, - BUS_DATAREADY_IN(3) => trig_ack, - BUS_WRITE_ACK_IN(3) => trig_ack, - BUS_NO_MORE_DATA_IN(3) => '0', - BUS_UNKNOWN_ADDR_IN(3) => trig_nack, - --Input statistics - BUS_READ_ENABLE_OUT(4) => stat_read, - BUS_WRITE_ENABLE_OUT(4) => stat_write, - BUS_DATA_OUT(4*32+31 downto 4*32) => stat_din, - BUS_ADDR_OUT(4*16+15 downto 4*16) => stat_addr, - BUS_TIMEOUT_OUT(4) => open, - BUS_DATA_IN(4*32+31 downto 4*32) => stat_dout, - BUS_DATAREADY_IN(4) => stat_ack, - BUS_WRITE_ACK_IN(4) => stat_ack, - BUS_NO_MORE_DATA_IN(4) => '0', - BUS_UNKNOWN_ADDR_IN(4) => stat_nack, - --SEU Detection - BUS_READ_ENABLE_OUT(5) => bussed_rx.read, - BUS_WRITE_ENABLE_OUT(5) => bussed_rx.write, - BUS_DATA_OUT(5*32+31 downto 5*32) => bussed_rx.data, - BUS_ADDR_OUT(5*16+15 downto 5*16) => bussed_rx.addr, - BUS_TIMEOUT_OUT(5) => bussed_rx.timeout, - BUS_DATA_IN(5*32+31 downto 5*32) => bussed_tx.data, - BUS_DATAREADY_IN(5) => bussed_tx.ack, - BUS_WRITE_ACK_IN(5) => bussed_tx.ack, - BUS_NO_MORE_DATA_IN(5) => bussed_tx.nack, - BUS_UNKNOWN_ADDR_IN(5) => bussed_tx.unknown, + REGIO_RX => ctrlbus_rx, + REGIO_TX => ctrlbus_tx, + + BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED + BUS_RX(1) => bustdc_rx, --TDC config + BUS_TX(0) => bustools_tx, + BUS_TX(1) => bustdc_tx, STAT_DEBUG => open ); --------------------------------------------------------------------------- --- SPI / Flash +-- Control Tools --------------------------------------------------------------------------- - THE_SPI_RELOAD : entity work.spi_flash_and_fpga_reload + THE_TOOLS : entity work.trb3_tools port map( - CLK_IN => clk_100_i, - RESET_IN => reset_i, - - BUS_ADDR_IN => spimem_addr, - BUS_READ_IN => spimem_read_en, - BUS_WRITE_IN => spimem_write_en, - BUS_DATAREADY_OUT => spimem_dataready_out, - BUS_WRITE_ACK_OUT => spimem_write_ack_out, - BUS_UNKNOWN_ADDR_OUT => spimem_unknown_addr_out, - BUS_NO_MORE_DATA_OUT => spimem_no_more_data_out, - BUS_DATA_IN => spimem_data_in, - BUS_DATA_OUT => spimem_data_out, - - DO_REBOOT_IN => common_ctrl_reg(15), - PROGRAMN => PROGRAMN, + CLK => clk_100_i, + RESET => reset_i, - SPI_CS_OUT => FLASH_CS, - SPI_SCK_OUT => FLASH_CLK, - SPI_SDO_OUT => FLASH_DIN, - SPI_SDI_IN => FLASH_DOUT + --Flash & Reload + FLASH_CS => FLASH_CS, + FLASH_CLK => FLASH_CLK, + FLASH_IN => FLASH_DOUT, + FLASH_OUT => FLASH_DIN, + PROGRAMN => PROGRAMN, + REBOOT_IN => common_ctrl_reg(15), + --SPI + SPI_CS_OUT => spi_cs, + SPI_MOSI_OUT => spi_mosi, + SPI_MISO_IN => spi_miso, + SPI_CLK_OUT => spi_clk, + SPI_CLR_OUT => spi_clr, + --LCD + LCD_DATA_IN => lcd_data, + UART_RX_IN => uart_rx, + UART_TX_OUT => uart_tx, + DEBUG_RX_IN => debug_rx, + DEBUG_TX_OUT => debug_tx, + + --Trigger & Monitor + MONITOR_INPUTS(19 downto 0) => INP(19 downto 0), + MONITOR_INPUTS(23 downto 20) => trig_gen_out_i, + TRIG_GEN_INPUTS => INP(15 downto 0), + TRIG_GEN_OUTPUTS => trig_gen_out_i, + LCD_OUT => lcd_out, + --SED + SED_ERROR_OUT => sed_error_i, + --Slowcontrol + BUS_RX => bustools_rx, + BUS_TX => bustools_tx, + --Control master for default settings + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + DEBUG_OUT => open ); -------------------------------------------------------------------------------- --- SPI -------------------------------------------------------------------------------- +--------------------------------------------------------------------------- +-- Feature I/O +--------------------------------------------------------------------------- gen_SPI : if INCLUDE_SPI = 1 generate - DAC_SPI : spi_ltc2600 - generic map ( - BITS => 14, - WAITCYCLES => 100) - port map ( - CLK_IN => clk_100_i, - RESET_IN => reset_i, - -- Slave bus - BUS_READ_IN => spidac_read_en, - BUS_WRITE_IN => spidac_write_en, - BUS_BUSY_OUT => spidac_busy, - BUS_ACK_OUT => spidac_ack, - BUS_ADDR_IN => spidac_addr, - BUS_DATA_IN => spidac_data_in, - BUS_DATA_OUT => spidac_data_out, - -- SPI connections - SPI_CS_OUT(0) => DAC_OUT_CS, - SPI_SDI_IN => DAC_IN_SDI, - SPI_SDO_OUT => DAC_OUT_SDO, - SPI_SCK_OUT => DAC_OUT_SCK, - SPI_CLR_OUT(0) => DAC_OUT_CLR - ); + DAC_OUT_CS <= spi_cs(0); + DAC_OUT_SDO <= spi_mosi(0); + DAC_OUT_SCK <= spi_clk(0); + DAC_OUT_CLR <= spi_clr(0); + spi_miso(0) <= DAC_IN_SDI; end generate; - - gen_NO_SPI : if INCLUDE_SPI = 0 generate - DAC_OUT_SDO <= trig_out(0); - DAC_OUT_SCK <= trig_out(1); - DAC_OUT_CS <= trig_out(2); - DAC_OUT_CLR <= trig_out(3); + DAC_OUT_SDO <= trig_gen_out_i(0); + DAC_OUT_SCK <= trig_gen_out_i(1); + DAC_OUT_CS <= trig_gen_out_i(2); + DAC_OUT_CLR <= trig_gen_out_i(3); end generate; ---------------------------------------------------------------------------- --- Trigger logic ---------------------------------------------------------------------------- - gen_TRIGGER_LOGIC : if INCLUDE_TRIGGER_LOGIC = 1 generate - THE_TRIG_LOGIC : input_to_trigger_logic - generic map( - INPUTS => PHYSICAL_INPUTS, - OUTPUTS => 4 - ) - port map( - CLK => clk_100_i, - - INPUT => INP(PHYSICAL_INPUTS-1 downto 0), - OUTPUT => trig_out, - - DATA_IN => trig_din, - DATA_OUT => trig_dout, - WRITE_IN => trig_write, - READ_IN => trig_read, - ACK_OUT => trig_ack, - NACK_OUT => trig_nack, - ADDR_IN => trig_addr - ); - FPGA5_COMM(10 downto 7) <= trig_out; - FPGA5_COMM(6 downto 3) <= (others => 'Z'); - FPGA5_COMM(1) <= 'Z'; - end generate; + FPGA5_COMM(10 downto 7) <= trig_gen_out_i; + FPGA5_COMM(6 downto 3) <= (others => 'Z'); + FPGA5_COMM(1) <= 'Z'; + + feature_outputs_i(0) <= uart_rx; + feature_outputs_i(1) <= uart_tx; + feature_outputs_i(2) <= spi_cs(1); + feature_outputs_i(3) <= spi_mosi(1); + feature_outputs_i(4) <= spi_clk(1); + spi_miso(1) <= TEST_LINE(5); + feature_outputs_i(7) <= lcd_out(4); --lcd_cs + feature_outputs_i(8) <= lcd_out(0); --lcd_rst + feature_outputs_i(9) <= lcd_out(3); --lcd_dc + feature_outputs_i(10) <= lcd_out(2); --lcd_mosi + feature_outputs_i(11) <= lcd_out(1); --lcd_sck + --12 is LCD MISO, but not used + feature_outputs_i(14) <= debug_rx; + feature_outputs_i(15) <= debug_tx; --------------------------------------------------------------------------- --- Input Statistics +-- LCD Data to display --------------------------------------------------------------------------- - gen_STATISTICS : if INCLUDE_STATISTICS = 1 generate - - THE_STAT_LOGIC : entity work.input_statistics - generic map( - INPUTS => PHYSICAL_INPUTS, - SINGLE_FIFO_ONLY => USE_SINGLE_FIFO - ) - port map( - CLK => clk_100_i, - - INPUT => INP(PHYSICAL_INPUTS-1 downto 0), - - DATA_IN => stat_din, - DATA_OUT => stat_dout, - WRITE_IN => stat_write, - READ_IN => stat_read, - ACK_OUT => stat_ack, - NACK_OUT => stat_nack, - ADDR_IN => stat_addr - ); - end generate; - ---------------------------------------------------------------------------- --- SED Detection ---------------------------------------------------------------------------- - THE_SED : entity work.sedcheck - port map( - CLK => clk_100_i, - ERROR_OUT => sed_error, - BUS_RX => bussed_rx, - BUS_TX => bussed_tx - ); + lcd_data(15 downto 0) <= timer.network_address; + lcd_data(47 downto 16) <= timer.microsecond; + lcd_data(79 downto 48) <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)); + lcd_data(511 downto 80) <= (others => '0'); --------------------------------------------------------------------------- -- LED --------------------------------------------------------------------------- - LED_GREEN <= not med_stat_op(9); - LED_ORANGE <= not med_stat_op(10); + LED_GREEN <= not med2int(0).stat_op(9); + LED_ORANGE <= not med2int(0).stat_op(10); LED_RED <= '1'; - LED_YELLOW <= not med_stat_op(11); + LED_YELLOW <= not med2int(0).stat_op(11); --------------------------------------------------------------------------- --- Test Connector - Logic Analyser +-- Test Connector - Additional Features --------------------------------------------------------------------------- - - TEST_LINE <= logic_analyser_i; +-- TEST_LINE <= feature_outputs_i; ------------------------------------------------------------------------------- -- TDC ------------------------------------------------------------------------------- - THE_TDC : TDC_record + THE_TDC : entity work.TDC_record generic map ( CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels per module STATUS_REG_NR => 21, -- Number of status regs @@ -680,10 +420,12 @@ begin -- Trigger signals from handler BUSRDO_RX => readout_rx, BUSRDO_TX => readout_tx(0), - -- - LOGIC_ANALYSER_OUT => TEST_LINE, + -- Slow control bus BUS_RX => bustdc_rx, - BUS_TX => bustdc_tx + BUS_TX => bustdc_tx, + -- Dubug signals + INFO_IN => timer, + LOGIC_ANALYSER_OUT => TEST_LINE ); -- For single edge measurements -- 2.43.0