From cd0b4449f485f58d4c81d213c24f8625af1c845d Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Fri, 26 Nov 2021 08:56:55 +0100 Subject: [PATCH] first version of new media interface for ECP3 --- media_interfaces/med_ecp3_sfp_sync_all_RS.vhd | 304 +++++++++++------- 1 file changed, 181 insertions(+), 123 deletions(-) diff --git a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd index 5d68ab6..003ad80 100644 --- a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd +++ b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd @@ -6,43 +6,52 @@ USE IEEE.numeric_std.all; library work; use work.trb_net_std.all; -use work.trb_net_components.all; -use work.med_sync_define.all; +--use work.trb_net_components.all; +use work.med_sync_define_RS.all; entity med_ecp3_sfp_sync_all_RS is - generic( - IS_MODE : int_array_t(0 to 3) := (c_IS_UNUSED, c_IS_UNUSED, c_IS_UNUSED, c_IS_UNUSED) + generic( + SIM_MODE : integer := 0; + IS_MODE : int_array_t(0 to 3) := (c_IS_UNUSED, c_IS_UNUSED, c_IS_UNUSED, c_IS_UNUSED); + IS_WAP_ZERO : integer := 1 ); port( - CLK_REF_FULL : in std_logic; -- 200 MHz reference clock - SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock + -- Clocks and reset + CLK_REF_FULL : in std_logic; -- TRBnet reference clock + SYSCLK : in std_logic; -- FPGA fabric clock RESET : in std_logic; -- synchronous reset CLEAR : in std_logic; -- asynchronous reset - - --Internal Connection TX/RX + -- Media Interface TX/RX MEDIA_MED2INT : out med2int_array_t(0 to 3); MEDIA_INT2MED : in int2med_array_t(0 to 3); - - --Sync operation - RX_DLM_OUT : out std_logic_vector(3 downto 0) := x"0"; - RX_DLM_WORD_OUT : out std_logic_vector(4*8-1 downto 0) := (others => '0'); - TX_DLM_IN : in std_logic_vector(3 downto 0) := x"0"; - TX_DLM_WORD_IN : in std_logic_vector(4*8-1 downto 0) := (others => '0'); - WORD_SYNC_IN : in std_logic := '1'; + -- Sync operation + RX_DLM_OUT : out std_logic_vector(3 downto 0); -- DLM received + RX_DLM_WORD_OUT : out std_logic_vector(4*8-1 downto 0); + TX_DLM_IN : in std_logic; + TX_DLM_WORD_IN : in std_logic_vector(7 downto 0); + RX_RST_OUT : out std_logic; -- RST received + RX_RST_WORD_OUT : out std_logic_vector(7 downto 0); + TX_RST_IN : in std_logic; + TX_RST_WORD_IN : in std_logic_vector(7 downto 0); + WORD_SYNC_IN : in std_logic; WORD_SYNC_OUT : out std_logic; - SYNC_TX_PLL_IN : in std_logic; - SYNC_TX_PLL_OUT : out std_logic; - DESTROY_LINK_IN : in std_logic_vector(3 downto 0); - + MASTER_CLK_IN : in std_logic; -- recovered RX clock in (only master ports in quad) + MASTER_CLK_OUT : out std_logic; -- recovered RX clock out (slave port in quad) + MASTER_RESET_OUT : out std_logic; + DESTROY_LINK_IN : in std_logic_vector(3 downto 0); -- disable SFP transmitter + LINK_TX_READY_IN : in std_logic; -- TX PLLs are operational + TX_PLL_LOL_OUT : out std_logic; -- status signal of TX PLL + TX_RESET_OUT : out std_logic; + SYNC_TX_PLL_IN : in std_logic; -- bit0 alignment for TX Serializer + RST_QUAD_IN : in std_logic; + RST_TX_SERDES_IN : in std_logic; --SFP Connection SD_PRSNT_N_IN : in std_logic_vector(3 downto 0); -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) SD_LOS_IN : in std_logic_vector(3 downto 0); -- SFP Loss Of Signal ('0' = OK, '1' = no signal) SD_TXDIS_OUT : out std_logic_vector(3 downto 0); -- SFP disable - --Control Interface BUS_RX : in CTRLBUS_RX; BUS_TX : out CTRLBUS_TX; - -- Status and control port STAT_DEBUG : out std_logic_vector (63 downto 0); CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0') @@ -111,10 +120,26 @@ architecture med_ecp3_sfp_sync_all_RS_arch of med_ecp3_sfp_sync_all_RS is signal powerup_ch : std_logic_vector(3 downto 0); signal tx_ref_clk_i : std_logic; + + signal tx_dlm_word_i : std_logic_vector(7 downto 0); + signal tx_dlm_i : std_logic; + + signal tx_rst_word_i : std_logic_vector(4*8-1 downto 0); + signal tx_rst_i : std_logic_vector(3 downto 0); + + signal rx_rst_word_i : std_logic_vector(4*8-1 downto 0); + signal rx_rst_i : std_logic_vector(3 downto 0); + + signal master_reset_i : std_logic_vector(3 downto 0); + signal tx_reset_i : std_logic_vector(3 downto 0); signal quad_mode : integer range 0 to 100; begin + +-- unused = 0 +-- master = 1 +-- slave = 8 ------------------------------------------------- -- check settings of media interface @@ -122,12 +147,12 @@ begin quad_mode <= IS_MODE(3) + IS_MODE(2) + IS_MODE(1) + IS_MODE(0); -- reject illegal combinations - assert not (quad_mode = 0) report "Error: QUAD not used" severity error; - assert not (quad_mode > 11) report "Error: multi slave QUAD detected" severity error; + assert not (quad_mode = 0) report "Error: QUAD not used" severity error; + assert not (quad_mode > 11) report "Error: multi slave QUAD detected" severity error; -- notify user on status assert not ((quad_mode >= 1) and (quad_mode <= 4)) report "Note: QUAD with only master ports detected" severity note; - assert not (quad_mode = 8) report "Note: QUAD with one slave port detected" severity note; + assert not (quad_mode = 8) report "Note: QUAD with one slave port detected" severity note; assert not ((quad_mode >= 9) and (quad_mode <= 11)) report "Note: mixed master/slave QUAD detected" severity note; ------------------------------------------------- @@ -140,7 +165,8 @@ begin ------------------------------------------------- -- SFPs are disabled on unused SerDes channels -------------------------------------------------- +------------------------------------------------- + -- we can include the LINK_TX_READY_IN signal here for master ports SD_TXDIS_OUT(3) <= DESTROY_LINK_IN(3) when IS_MODE(3) = c_IS_MASTER else '1' when IS_MODE(3) = c_IS_UNUSED else '0'; @@ -157,11 +183,44 @@ begin ------------------------------------------------- -- TX ref clock ------------------------------------------------- - SYNC_TX_PLL_OUT <= clk_rx_full(0) when ((quad_mode >= 8) and (IS_MODE(0) = c_IS_SLAVE)) else - clk_rx_full(1) when ((quad_mode >= 8) and (IS_MODE(1) = c_IS_SLAVE)) else - clk_rx_full(2) when ((quad_mode >= 8) and (IS_MODE(2) = c_IS_SLAVE)) else - clk_rx_full(3) when ((quad_mode >= 8) and (IS_MODE(3) = c_IS_SLAVE)) else + MASTER_CLK_OUT <= clk_rx_full(0) when ((quad_mode >= 8) and (IS_MODE(0) = c_IS_SLAVE)) else + clk_rx_full(1) when ((quad_mode >= 8) and (IS_MODE(1) = c_IS_SLAVE)) else + clk_rx_full(2) when ((quad_mode >= 8) and (IS_MODE(2) = c_IS_SLAVE)) else + clk_rx_full(3) when ((quad_mode >= 8) and (IS_MODE(3) = c_IS_SLAVE)) else + '0'; + +------------------------------------------------- +-- master reset +------------------------------------------------- + MASTER_RESET_OUT <= master_reset_i(0) when ((quad_mode >= 8) and (IS_MODE(0) = c_IS_SLAVE)) else + master_reset_i(1) when ((quad_mode >= 8) and (IS_MODE(1) = c_IS_SLAVE)) else + master_reset_i(2) when ((quad_mode >= 8) and (IS_MODE(2) = c_IS_SLAVE)) else + master_reset_i(3) when ((quad_mode >= 8) and (IS_MODE(3) = c_IS_SLAVE)) else + '0'; + +------------------------------------------------- +-- reset komma +------------------------------------------------- + RX_RST_OUT <= rx_rst_i(0) when ((quad_mode >= 8) and (IS_MODE(0) = c_IS_SLAVE)) else + rx_rst_i(1) when ((quad_mode >= 8) and (IS_MODE(1) = c_IS_SLAVE)) else + rx_rst_i(2) when ((quad_mode >= 8) and (IS_MODE(2) = c_IS_SLAVE)) else + rx_rst_i(3) when ((quad_mode >= 8) and (IS_MODE(3) = c_IS_SLAVE)) else + '0'; + + RX_RST_WORD_OUT <= rx_rst_word_i(7 downto 0) when ((quad_mode >= 8) and (IS_MODE(0) = c_IS_SLAVE)) else + rx_rst_word_i(15 downto 8) when ((quad_mode >= 8) and (IS_MODE(1) = c_IS_SLAVE)) else + rx_rst_word_i(23 downto 16) when ((quad_mode >= 8) and (IS_MODE(2) = c_IS_SLAVE)) else + rx_rst_word_i(31 downto 24) when ((quad_mode >= 8) and (IS_MODE(3) = c_IS_SLAVE)) else '0'; + +------------------------------------------------- +-- TX PLL reset +------------------------------------------------- + TX_RESET_OUT <= tx_reset_i(0) when ((quad_mode >= 8) and (IS_MODE(0) = c_IS_SLAVE)) else + tx_reset_i(1) when ((quad_mode >= 8) and (IS_MODE(1) = c_IS_SLAVE)) else + tx_reset_i(2) when ((quad_mode >= 8) and (IS_MODE(2) = c_IS_SLAVE)) else + tx_reset_i(3) when ((quad_mode >= 8) and (IS_MODE(3) = c_IS_SLAVE)) else + '0'; ------------------------------------------------- -- Serdes @@ -173,7 +232,6 @@ begin hdoutp_ch0 => hdoutp(0), hdoutn_ch0 => hdoutn(0), txiclk_ch0 => clk_tx_full(0), -- drives TX FIFO bridge --- rxiclk_ch0 => clk_rx_full(0), -- drives RX FIFO bridge rx_full_clk_ch0 => clk_rx_full(0), -- recovered RX clock rx_half_clk_ch0 => clk_rx_half(0), tx_full_clk_ch0 => clk_tx_full(0), -- TX clock from PLL @@ -181,7 +239,7 @@ begin fpga_rxrefclk_ch0 => CLK_REF_FULL, -- reference RX clock txdata_ch0 => tx_data(0*8+7 downto 0*8), tx_k_ch0 => tx_k(0), - tx_force_disp_ch0 => tx_cd(0), + tx_force_disp_ch0 => '0', -- not needed tx_disp_sel_ch0 => '0', rxdata_ch0 => rx_data(0*8+7 downto 0*8), rx_k_ch0 => rx_k(0), @@ -205,7 +263,6 @@ begin hdoutp_ch1 => hdoutp(1), hdoutn_ch1 => hdoutn(1), txiclk_ch1 => clk_tx_full(1), --- rxiclk_ch1 => clk_rx_full(1), rx_full_clk_ch1 => clk_rx_full(1), rx_half_clk_ch1 => clk_rx_half(1), tx_full_clk_ch1 => clk_tx_full(1), @@ -213,7 +270,7 @@ begin fpga_rxrefclk_ch1 => CLK_REF_FULL, txdata_ch1 => tx_data(1*8+7 downto 1*8), tx_k_ch1 => tx_k(1), - tx_force_disp_ch1 => tx_cd(1), + tx_force_disp_ch1 => '0', -- not needed tx_disp_sel_ch1 => '0', rxdata_ch1 => rx_data(1*8+7 downto 1*8), rx_k_ch1 => rx_k(1), @@ -237,7 +294,6 @@ begin hdoutp_ch2 => hdoutp(2), hdoutn_ch2 => hdoutn(2), txiclk_ch2 => clk_tx_full(2), --- rxiclk_ch2 => clk_rx_full(2), rx_full_clk_ch2 => clk_rx_full(2), rx_half_clk_ch2 => clk_rx_half(2), tx_full_clk_ch2 => clk_tx_full(2), @@ -245,7 +301,7 @@ begin fpga_rxrefclk_ch2 => CLK_REF_FULL, txdata_ch2 => tx_data(2*8+7 downto 2*8), tx_k_ch2 => tx_k(2), - tx_force_disp_ch2 => tx_cd(2), + tx_force_disp_ch2 => '0', -- not needed tx_disp_sel_ch2 => '0', rxdata_ch2 => rx_data(2*8+7 downto 2*8), rx_k_ch2 => rx_k(2), @@ -269,7 +325,6 @@ begin hdoutp_ch3 => hdoutp(3), hdoutn_ch3 => hdoutn(3), txiclk_ch3 => clk_tx_full(3), --- rxiclk_ch3 => clk_rx_full(3), rx_full_clk_ch3 => clk_rx_full(3), rx_half_clk_ch3 => clk_rx_half(3), tx_full_clk_ch3 => clk_tx_full(3), @@ -277,7 +332,7 @@ begin fpga_rxrefclk_ch3 => CLK_REF_FULL, txdata_ch3 => tx_data(3*8+7 downto 3*8), tx_k_ch3 => tx_k(3), - tx_force_disp_ch3 => tx_cd(3), + tx_force_disp_ch3 => '0', -- not needed tx_disp_sel_ch3 => '0', rxdata_ch3 => rx_data(3*8+7 downto 3*8), rx_k_ch3 => rx_k(3), @@ -307,65 +362,70 @@ begin SCI_RD => sci_read_i, SCI_WRN => sci_write_i, - fpga_txrefclk => SYNC_TX_PLL_IN, -- reference TX clock + fpga_txrefclk => MASTER_CLK_IN, -- reference TX clock tx_serdes_rst_c => '0', - tx_pll_lol_qd_s => tx_pll_lol, - rst_qd_c => rst_qd(0), - serdes_rst_qd_c => '0', - tx_sync_qd_c => '0' + tx_pll_lol_qd_s => TX_PLL_LOL_OUT, + rst_qd_c => RST_QUAD_IN, + serdes_rst_qd_c => RST_TX_SERDES_IN, + tx_sync_qd_c => SYNC_TX_PLL_IN ); gen_control : for i in 0 to 3 generate gen_used_control : if (IS_MODE(i) = c_IS_SLAVE) or (IS_MODE(i) = c_IS_MASTER) generate THE_MED_CONTROL : entity work.med_sync_control_RS - generic map( - IS_WAP_ZERO => 1, + generic map( + SIM_MODE => SIM_MODE, + IS_WAP_ZERO => IS_WAP_ZERO, IS_MODE => IS_MODE(i) ) port map( - CLK_SYS => SYSCLK, - CLK_RXI => clk_rx_full(i), - CLK_RXHALF => clk_rx_half(i), - CLK_TXI => clk_tx_full(i), - CLK_REF => CLK_REF_FULL, - RESET => RESET, - CLEAR => CLEAR, - - SFP_LOS => SD_LOS_IN(i), - TX_LOL => tx_pll_lol, - RX_CDR_LOL => rx_cdr_lol(i), - RX_LOS => rx_los_low(i), - WA_POSITION => wa_position(i*4+3 downto i*4), - - WORD_SYNC_IN => '1', - WORD_SYNC_OUT => open, - - RX_SERDES_RST => rx_serdes_rst(i), - RX_PCS_RST => rx_pcs_rst(i), - QUAD_RST => rst_qd(i), - TX_PCS_RST => tx_pcs_rst(i), - - MEDIA_MED2INT => MEDIA_MED2INT(i), - MEDIA_INT2MED => MEDIA_INT2MED(i), - - TX_DATA => tx_data(i*8+7 downto i*8), - TX_K => tx_k(i), - TX_CD => tx_cd(i), - RX_DATA => rx_data(i*8+7 downto i*8), - RX_K => rx_k(i), - - TX_DLM_WORD => TX_DLM_WORD_IN(i*8+7 downto i*8), - TX_DLM => TX_DLM_IN(i), - RX_DLM_WORD => RX_DLM_WORD_OUT(i*8+7 downto i*8), - RX_DLM => RX_DLM_OUT(i), - - STAT_TX_CONTROL => stat_tx_control_i(i*32+31 downto i*32), - STAT_RX_CONTROL => stat_rx_control_i(i*32+31 downto i*32), - DEBUG_TX_CONTROL => debug_tx_control_i(i*32+31 downto i*32), - DEBUG_RX_CONTROL => debug_rx_control_i(i*32+31 downto i*32), - STAT_RESET => stat_fsm_reset_i(i*32+31 downto i*32) - ); + -- clocks and resets + CLK_SYS => SYSCLK, + CLK_RXI => clk_rx_full(i), + CLK_RXHALF => clk_rx_half(i), + CLK_TXI => clk_tx_full(i), + CLK_REF => CLK_REF_FULL, + RESET => RESET, + CLEAR => CLEAR, + -- Media Interface + MEDIA_MED2INT => MEDIA_MED2INT(i), + MEDIA_INT2MED => MEDIA_INT2MED(i), + -- status signals from SerDes + SFP_LOS_IN => SD_LOS_IN(i), + RX_CDR_LOL_IN => rx_cdr_lol(i), + RX_LOS_IN => rx_los_low(i), + WA_POSITION_IN => wa_position(i*4+3 downto i*4), + LINK_TX_READY_IN => LINK_TX_READY_IN, + -- control signals to SerDes + RX_SERDES_RST => rx_serdes_rst(i), + RX_PCS_RST => rx_pcs_rst(i), + -- SerDes data streams + TX_DATA_OUT => tx_data(i*8+7 downto i*8), + TX_K_OUT => tx_k(i), + RX_DATA_IN => rx_data(i*8+7 downto i*8), + RX_K_IN => rx_k(i), + -- ports for synchronous operation + WORD_SYNC_IN => WORD_SYNC_IN, + WORD_SYNC_OUT => WORD_SYNC_OUT, + TX_DLM_IN => tx_dlm_i, + TX_DLM_WORD_IN => tx_dlm_word_i, + TX_RST_IN => tx_rst_i(i), + TX_RST_WORD_IN => tx_rst_word_i(i*8+7 downto i*8), + RX_DLM_OUT => RX_DLM_OUT(i), + RX_DLM_WORD_OUT => RX_DLM_WORD_OUT(i*8+7 downto i*8), + RX_RST_OUT => rx_rst_i(i), + RX_RST_WORD_OUT => rx_rst_word_i(i*8+7 downto i*8), + MASTER_RESET_OUT => master_reset_i(i), + TX_RESET_OUT => tx_reset_i(i), + -- Status and debug signals + STAT_TX_CONTROL => stat_tx_control_i(i*32+31 downto i*32), + STAT_RX_CONTROL => stat_rx_control_i(i*32+31 downto i*32), + DEBUG_TX_CONTROL => debug_tx_control_i(i*32+31 downto i*32), + DEBUG_RX_CONTROL => debug_rx_control_i(i*32+31 downto i*32), + STAT_RESET => stat_fsm_reset_i(i*32+31 downto i*32), + DEBUG_OUT => open + ); cv_cnt(i) <= cv_cnt(i) + 1 when rx_error(i) = '1' and rising_edge(clk_rx_full(i)); end generate; @@ -376,42 +436,40 @@ gen_control : for i in 0 to 3 generate MEDIA_MED2INT(i).stat_op <= x"0007"; end generate; -end generate; - -THE_SCI_READER : entity work.sci_reader_RS - port map( - CLK => SYSCLK, - RESET => RESET, - --SCI - SCI_WRDATA => sci_data_in_i, - SCI_RDDATA => sci_data_out_i, - SCI_ADDR => sci_addr_i, - SCI_SEL => sci_ch_i, - SCI_RD => sci_read_i, - SCI_WR => sci_write_i, - -- WAP - WA_POS_OUT => wa_position, - --Slowcontrol - BUS_RX => BUS_RX, - BUS_TX => BUS_TX, - -- - MEDIA_STATUS_REG_IN(31 downto 0) => stat_rx_control_i(31 downto 0), - MEDIA_STATUS_REG_IN(63 downto 32) => stat_tx_control_i(31 downto 0), - MEDIA_STATUS_REG_IN(191 downto 64) => stat_fsm_reset_i(127 downto 0), - MEDIA_STATUS_REG_IN(199 downto 192) => cv_cnt_sys(0), - MEDIA_STATUS_REG_IN(207 downto 200) => cv_cnt_sys(1), - MEDIA_STATUS_REG_IN(215 downto 208) => cv_cnt_sys(2), - MEDIA_STATUS_REG_IN(223 downto 216) => cv_cnt_sys(3), - MEDIA_STATUS_REG_IN(255 downto 224) => (others => '0'), - DEBUG_OUT => open - ); - -cv_cnt_sys <= cv_cnt when rising_edge(SYSCLK); - - -STAT_DEBUG(13 downto 0) <= debug_tx_control_i(13 downto 0); -STAT_DEBUG(15 downto 14) <= debug_tx_control_i(17 downto 16); - - +end generate; + + THE_SCI_READER : entity work.sci_reader_RS + port map( + CLK => SYSCLK, + RESET => RESET, + --SCI + SCI_WRDATA => sci_data_in_i, + SCI_RDDATA => sci_data_out_i, + SCI_ADDR => sci_addr_i, + SCI_SEL => sci_ch_i, + SCI_RD => sci_read_i, + SCI_WR => sci_write_i, + -- WAP + WA_POS_OUT => wa_position, + --Slowcontrol + BUS_RX => BUS_RX, + BUS_TX => BUS_TX, + -- + MEDIA_STATUS_REG_IN(31 downto 0) => stat_rx_control_i(31 downto 0), + MEDIA_STATUS_REG_IN(63 downto 32) => stat_tx_control_i(31 downto 0), + MEDIA_STATUS_REG_IN(191 downto 64) => stat_fsm_reset_i(127 downto 0), + MEDIA_STATUS_REG_IN(199 downto 192) => cv_cnt_sys(0), + MEDIA_STATUS_REG_IN(207 downto 200) => cv_cnt_sys(1), + MEDIA_STATUS_REG_IN(215 downto 208) => cv_cnt_sys(2), + MEDIA_STATUS_REG_IN(223 downto 216) => cv_cnt_sys(3), + MEDIA_STATUS_REG_IN(255 downto 224) => (others => '0'), + DEBUG_OUT => open + ); + + cv_cnt_sys <= cv_cnt when rising_edge(SYSCLK); + + STAT_DEBUG(13 downto 0) <= debug_tx_control_i(13 downto 0); + STAT_DEBUG(15 downto 14) <= debug_tx_control_i(17 downto 16); + end architecture; -- 2.43.0