From cd2358590ad1f14b67289c0894a941a57fc1b660 Mon Sep 17 00:00:00 2001
From: hadaq <hadaq>
Date: Thu, 26 Aug 2010 18:05:04 +0000
Subject: [PATCH] new register settings (lvl1 info)

---
 cts.tex | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/cts.tex b/cts.tex
index 42daf56..9774474 100644
--- a/cts.tex
+++ b/cts.tex
@@ -19,6 +19,8 @@ For all registers described in this subsection refer to the Fig.\ref{cts_logic}
      \item[Bit 6] Force update Shower pedestals trigger (write ..1..0)
      \item[Bit 7] Disable Shower pedestals update (generated once during each spill off)
      \item[Bit 8] Enable Shower calibration trigger
+     \item[Bit 14] Enable beam inhibit
+     \item[Bit 31] Enable trigger line test, this works together with self trigger (set the requried frequency)
     \end{description}
   \item [0xA0C1] LVL1/LVL2 trigger settings:
     \begin{description}
@@ -54,10 +56,16 @@ For all registers described in this subsection refer to the Fig.\ref{cts_logic}
     \begin{description}
      \item[Bit 23 -- 0] Number of events per EB 
     \end{description}
-  \item [0xA0E3] LVL2 - events per EB
+  \item [0xA0E3] Self trigger
     \begin{description}
      \item[Bit 27 -- 0] When 0 the internal triggering is disabled, when different than 0 the internal trigger is enabled and $frequency = 1/Value*10ns $
     \end{description}
+  \item [0xA0E4] LVL1 trigger information
+    \begin{description}
+     \item[Bit 6 -- 0] LVL1 trigger information(6 -- 0)
+     \item[Bit 13 -- 8] LVL1 trigger information(13 -- 8)
+    \end{description}
+
 \end{description}
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-- 
2.43.0