From ce8d4bbc49239cfd414dc1350a2c38f6268dff6a Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Thu, 7 Jul 2022 23:09:35 +0200 Subject: [PATCH] first version of forwarding infrastructure --- gbe_trb_ecp3/base/forwarder.vhd | 82 +++ gbe_trb_ecp3/base/gbe_lsm.vhd | 137 +++++ gbe_trb_ecp3/base/rx_rb.vhd | 284 +++++++++ gbe_trb_ecp3/base/tx_fifo.vhd | 99 ++++ gbe_trb_ecp3/cores/fifo_4k_9.ipx | 9 + gbe_trb_ecp3/cores/fifo_4k_9.vhd | 963 +++++++++++++++++++++++++++++++ gbe_trb_ecp3/cores/rb_4k_9.ipx | 10 + gbe_trb_ecp3/cores/rb_4k_9.vhd | 449 ++++++++++++++ 8 files changed, 2033 insertions(+) create mode 100644 gbe_trb_ecp3/base/forwarder.vhd create mode 100644 gbe_trb_ecp3/base/gbe_lsm.vhd create mode 100644 gbe_trb_ecp3/base/rx_rb.vhd create mode 100644 gbe_trb_ecp3/base/tx_fifo.vhd create mode 100644 gbe_trb_ecp3/cores/fifo_4k_9.ipx create mode 100644 gbe_trb_ecp3/cores/fifo_4k_9.vhd create mode 100644 gbe_trb_ecp3/cores/rb_4k_9.ipx create mode 100644 gbe_trb_ecp3/cores/rb_4k_9.vhd diff --git a/gbe_trb_ecp3/base/forwarder.vhd b/gbe_trb_ecp3/base/forwarder.vhd new file mode 100644 index 0000000..e9cda4c --- /dev/null +++ b/gbe_trb_ecp3/base/forwarder.vhd @@ -0,0 +1,82 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; + +entity forwarder is + port( + CLK : in std_logic; + CLEAR : in std_logic; + RESET : in std_logic; + -- + FRAME_AVAIL_IN : in std_logic; + FIFO_FULL_IN : in std_logic; + FRAME_REQ_OUT : out std_logic; + FRAME_ACK_IN : in std_logic; + -- + DEBUG : out std_logic_vector(15 downto 0) + ); +end entity forwarder; + +architecture forwarder_arch of forwarder is + +-- Components + +-- state machine signals + type state_t is (IDLE,REQ,ACK); + signal STATE, NEXT_STATE : state_t; + +-- Signals + signal rb_full : std_logic; + signal req_x : std_logic; + signal req_q : std_logic; + +begin + + ----------------------------------------------------------- + -- statemachine: clocked process + ----------------------------------------------------------- + THE_FSM: process( CLK, CLEAR ) + begin + if ( CLEAR = '1' ) then + STATE <= IDLE; + req_q <= '0'; + elsif( rising_edge(CLK) ) then + STATE <= NEXT_STATE; + req_q <= req_x; + end if; + end process THE_FSM; + + THE_STATE_TRANSITIONS: process( STATE, FIFO_FULL_IN, FRAME_AVAIL_IN, FRAME_ACK_IN ) + begin + req_x <= '0'; + + case STATE is + + when IDLE => + if( (FIFO_FULL_IN = '0') and (FRAME_AVAIL_IN = '1') ) then + NEXT_STATE <= REQ; + req_x <= '1'; + else + NEXT_STATE <= IDLE; + end if; + + when REQ => + if( FRAME_ACK_IN = '1' ) then + NEXT_STATE <= ACK; + else + NEXT_STATE <= REQ; + end if; + + when ACK => + NEXT_STATE <= IDLE; + + when others => + NEXT_STATE <= IDLE; + end case; + end process THE_STATE_TRANSITIONS; + + FRAME_REQ_OUT <= req_q; + +end architecture; diff --git a/gbe_trb_ecp3/base/gbe_lsm.vhd b/gbe_trb_ecp3/base/gbe_lsm.vhd new file mode 100644 index 0000000..4f284ae --- /dev/null +++ b/gbe_trb_ecp3/base/gbe_lsm.vhd @@ -0,0 +1,137 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; + +entity gbe_lsm is + port( + CLK : in std_logic; + CLEAR : in std_logic; + RESET : in std_logic; + -- + MAC_AN_COMPLETE_IN : in std_logic; -- PCS Autonegotiation completed + MAC_READY_CONF_IN : in std_logic; -- MAC configuration completed + MAC_RECONF_OUT : out std_logic; -- start MAC configuration + -- + LINK_ACTIVE_OUT : out std_logic; + -- + DEBUG : out std_logic_vector(15 downto 0) + ); +end entity gbe_lsm; + +architecture gbe_lsm_arch of gbe_lsm is + +-- Components + +-- state machine signals + type state_t is (INACTIVE,WAIT_PCS,ENABLE_MAC,DELAY,ACTIVATED); + signal STATE, NEXT_STATE : state_t; + +-- Signals + signal dly_ctr : unsigned(15 downto 0); + signal ce_dly_ctr : std_logic; + signal rst_dly_ctr : std_logic; + signal dly_ctr_done : std_logic; + signal reconf_mac : std_logic; + +begin + + MAC_RECONF_OUT <= reconf_mac; + + LINK_ACTIVE_OUT <= '1' when (STATE = ACTIVATED) else '0'; + + THE_DLY_CTR: process( CLK, CLEAR ) + begin + if( CLEAR = '1' ) then + dly_ctr <= (others => '0'); + elsif( rising_edge(CLK) ) then + if ( rst_dly_ctr = '1' ) then + dly_ctr <= (others => '0'); + elsif( ce_dly_ctr = '1' ) then + dly_ctr <= dly_ctr + 1; + end if; + end if; + end process THE_DLY_CTR; + + dly_ctr_done <= '1' when dly_ctr = x"ffff" else '0'; + + ----------------------------------------------------------- + -- statemachine: clocked process + ----------------------------------------------------------- + THE_FSM: process( CLK, CLEAR ) + begin + if ( CLEAR = '1' ) then + STATE <= INACTIVE; + elsif( rising_edge(CLK) ) then + STATE <= NEXT_STATE; + end if; + end process THE_FSM; + + THE_STATE_TRANSITIONS: process( STATE, MAC_AN_COMPLETE_IN, MAC_READY_CONF_IN, dly_ctr_done ) + begin + reconf_mac <= '0'; + ce_dly_ctr <= '0'; + rst_dly_ctr <= '0'; + + case STATE is + + when INACTIVE => + rst_dly_ctr <= '1'; + if( MAC_AN_COMPLETE_IN = '1' ) then + NEXT_STATE <= WAIT_PCS; + else + NEXT_STATE <= INACTIVE; + end if; + + when WAIT_PCS => + ce_dly_ctr <= '1'; + if( MAC_AN_COMPLETE_IN = '0' ) then + NEXT_STATE <= INACTIVE; + else + if( dly_ctr_done = '1' ) then + NEXT_STATE <= ENABLE_MAC; + reconf_mac <= '1'; + else + NEXT_STATE <= WAIT_PCS; + end if; + end if; + + when ENABLE_MAC => + rst_dly_ctr <= '1'; + if( MAC_AN_COMPLETE_IN = '0' ) then + NEXT_STATE <= INACTIVE; + else + if( MAC_READY_CONF_IN = '1' ) then + NEXT_STATE <= DELAY; + else + NEXT_STATE <= ENABLE_MAC; + end if; + end if; + + when DELAY => + ce_dly_ctr <= '1'; + if( MAC_AN_COMPLETE_IN = '0' ) then + NEXT_STATE <= INACTIVE; + else + if( dly_ctr_done = '1' ) then + NEXT_STATE <= ACTIVATED; + else + NEXT_STATE <= DELAY; + end if; + end if; + + when ACTIVATED => + rst_dly_ctr <= '1'; + if( MAC_AN_COMPLETE_IN = '0' ) then + NEXT_STATE <= INACTIVE; + else + NEXT_STATE <= ACTIVATED; + end if; + + when others => + NEXT_STATE <= INACTIVE; + end case; + end process THE_STATE_TRANSITIONS; + +end architecture; diff --git a/gbe_trb_ecp3/base/rx_rb.vhd b/gbe_trb_ecp3/base/rx_rb.vhd new file mode 100644 index 0000000..6d1763c --- /dev/null +++ b/gbe_trb_ecp3/base/rx_rb.vhd @@ -0,0 +1,284 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; + +entity rx_rb is + port( + CLK : in std_logic; + CLEAR : in std_logic; + RESET : in std_logic; + -- MAC interface (RX) + MAC_RX_DATA_IN : in std_logic_vector(7 downto 0); -- RX data from TSMAC + MAC_RX_WR_IN : in std_logic; -- RX data write from TSMAC + MAC_RX_EOF_IN : in std_logic; -- RX EndOfFrame from TSMAC + MAC_RX_ERROR_IN : in std_logic; -- RX Error from TSMAC + MAC_RX_FIFOFULL_OUT : out std_logic; + -- FIFO interface (TX) + FIFO_FULL_IN : in std_logic; -- TX fifo full, delay read from ring buffer + FIFO_WR_OUT : out std_logic; -- TX fifo write + FIFO_Q_OUT : out std_logic_vector(8 downto 0); -- TX data + FRAME_REQ_IN : in std_logic; -- one pulse starts readout of frame stored in ring buffer + FRAME_ACK_OUT : out std_logic; -- one pulse for "end of frame" + FRAME_AVAIL_OUT : out std_logic; -- number of frames stored in ring buffer + -- + DEBUG : out std_logic_vector(15 downto 0) + ); +end entity rx_rb; + +architecture rx_rb_arch of rx_rb is + +-- Components + component rb_4k_9 + port( + WRADDRESS : in std_logic_vector(11 downto 0); + RDADDRESS : in std_logic_vector(11 downto 0); + DATA : in std_logic_vector(8 downto 0); + WE : in std_logic; + RDCLOCK : in std_logic; + RDCLOCKEN : in std_logic; + RESET : in std_logic; + WRCLOCK : in std_logic; + WRCLOCKEN : in std_logic; + Q : out std_logic_vector(8 downto 0) + ); + end component rb_4k_9; + +-- state machine signals + type state_t is (RX_DENY,RX_READY,RX_FRAME,FRAME_OK,FRAME_BAD,FORWARD,SKIP); + signal STATE, NEXT_STATE : state_t; + +-- Signals + signal rd_ptr : unsigned(11 downto 0); + signal wr_ptr : unsigned(11 downto 0); + signal last_wr_ptr : std_logic_vector(11 downto 0); + signal rb_used : unsigned(11 downto 0); + signal rb_full : std_logic; + signal rb_empty : std_logic; + signal ce_wr_ptr : std_logic; + signal ld_wr_ptr : std_logic; + signal ce_rd_ptr : std_logic; + signal wr_ram : std_logic; + signal rd_ram : std_logic; + signal ram_q : std_logic_vector(8 downto 0); + signal frame_active : std_logic; + signal frame_requested : std_logic; + signal fifo_wr_int : std_logic; + signal empty_read_ack : std_logic; + signal normal_read_ack : std_logic; + + signal frames_avail : unsigned(7 downto 0); + + +begin + + -- FrameActive: we must not change to "receive" in the middle of a frame + -- when "buffer full" condition is deasserted + THE_FRAME_ACTIVE_PROC: process( CLK, CLEAR ) + begin + if( CLEAR = '1' ) then + frame_active <= '0'; + elsif( rising_edge(CLK) ) then + if( (MAC_RX_WR_IN = '1') and (frame_active = '0') ) then + frame_active <= '1'; + elsif( (MAC_RX_EOF_IN = '1') and (frame_active = '1') ) then + frame_active <= '0'; + end if; + end if; + end process THE_FRAME_ACTIVE_PROC; + + -- Write pointer for ring buffer + THE_WR_PTR_PROC: process( CLK, CLEAR ) + begin + if( CLEAR = '1' ) then + wr_ptr <= (others => '0'); + elsif( rising_edge(CLK) ) then + if ( ld_wr_ptr = '1' ) then + wr_ptr <= unsigned(last_wr_ptr); + elsif( ce_wr_ptr = '1' ) then + wr_ptr <= wr_ptr + 1; + end if; + end if; + end process THE_WR_PTR_PROC; + + -- Read pointer for ring buffer + THE_RD_PTR_PROC: process( CLK, CLEAR ) + begin + if( CLEAR = '1' ) then + rd_ptr <= (others => '0'); + elsif( rising_edge(CLK) ) then + if( ce_rd_ptr = '1' ) then + rd_ptr <= rd_ptr + 1; + end if; + end if; + end process THE_RD_PTR_PROC; + + -- ring buffer fill level + rb_used <= wr_ptr - rd_ptr; + + -- ring buffer full + -- TAKE CARE: the last byte of a frame is taken into account + -- by "one less" for the full condition + rb_full <= '1' when (rb_used(11 downto 1) = b"1111_1111_111") else '0'; + + rb_empty <= '1' when (rb_used(11 downto 0) = b"0000_0000_0000") else '0'; + + MAC_RX_FIFOFULL_OUT <= rb_full; + + -- last write pointer: used to drop a broken frame, in case + THE_LAST_WR_PTR_PROC: process( CLK, CLEAR ) + begin + if( CLEAR = '1' ) then + last_wr_ptr <= (others => '0'); + elsif( rising_edge(CLK) ) then + if( (STATE = RX_READY) and (MAC_RX_WR_IN = '1') ) then + last_wr_ptr <= std_logic_vector(wr_ptr); + end if; + end if; + end process THE_LAST_WR_PTR_PROC; + + -- DPRAM as ring buffer + THE_DP_RAM: rb_4k_9 + port map( + WRADDRESS => std_logic_vector(wr_ptr), + RDADDRESS => std_logic_vector(rd_ptr), + DATA(8) => MAC_RX_EOF_IN, + DATA(7 downto 0) => MAC_RX_DATA_IN, + WE => wr_ram, + RDCLOCK => CLK, + RDCLOCKEN => '1', + RESET => CLEAR, + WRCLOCK => CLK, + WRCLOCKEN => '1', + Q => ram_q + ); + + -- write signal + wr_ram <= '1' when ((STATE = RX_READY) and (MAC_RX_WR_IN = '1') and (rb_full = '0')) or + ((STATE = RX_FRAME) and (MAC_RX_WR_IN = '1') and (rb_full = '0')) + else '0'; + ce_wr_ptr <= '1' when ((STATE = RX_READY) and (MAC_RX_WR_IN = '1') and (rb_full = '0')) or + ((STATE = RX_FRAME) and (MAC_RX_WR_IN = '1') and (rb_full = '0')) + else '0'; + + -- FrameReq signal, one pulse only + THE_FRAME_REQ_PROC: process( CLK, CLEAR ) + begin + if( CLEAR = '1' ) then + frame_requested <= '0'; + elsif( rising_edge(CLK) ) then + if( (FRAME_REQ_IN = '1') and (frame_requested = '0') ) then + frame_requested <= '1'; + elsif( ((ram_q(8) = '1') and (frame_requested = '1')) or (empty_read_ack = '1') ) then + frame_requested <= '0'; + end if; + end if; + end process THE_FRAME_REQ_PROC; + + -- EmptyReadAck signal, used to handle a request to RX_RB with no frame to send + empty_read_ack <= FRAME_REQ_IN and rb_empty when rising_edge(CLK); + + -- NormalReadAck signal + normal_read_ack <= ram_q(8) and fifo_wr_int; + + -- read signal + rd_ram <= '1' when ((frame_requested = '1') and (ram_q(8) = '0') and (FIFO_FULL_IN = '0') and (rb_empty = '0')) else '0'; + ce_rd_ptr <= '1' when ((frame_requested = '1') and (ram_q(8) = '0') and (FIFO_FULL_IN = '0') and (rb_empty = '0')) else '0'; + + FRAME_ACK_OUT <= normal_read_ack or empty_read_ack; + + FIFO_Q_OUT <= ram_q; + + fifo_wr_int <= rd_ram when rising_edge(CLK); + + FIFO_WR_OUT <= fifo_wr_int; + + -- FramesAvailable counter + THE_FRAMES_AVAIL_PROC: process( CLK, CLEAR ) + begin + if( CLEAR = '1' ) then + frames_avail <= (others => '0'); + elsif( rising_edge(CLK) ) then + if ( (STATE = FRAME_OK) and (normal_read_ack = '0') ) then + -- one frame written successfully + frames_avail <= frames_avail + 1; + elsif( (STATE /= FRAME_OK) and (normal_read_ack = '1') ) then + -- one frame read successfully + frames_avail <= frames_avail - 1; + end if; + end if; + end process THE_FRAMES_AVAIL_PROC; + + FRAME_AVAIL_OUT <= '1' when (frames_avail /= x"00") else '0'; + + ----------------------------------------------------------- + -- statemachine: clocked process + ----------------------------------------------------------- + THE_FSM: process( CLK, CLEAR ) + begin + if ( CLEAR = '1' ) then + STATE <= RX_DENY; + elsif( rising_edge(CLK) ) then + STATE <= NEXT_STATE; + end if; + end process THE_FSM; + + THE_STATE_TRANSITIONS: process( STATE, MAC_RX_WR_IN, MAC_RX_EOF_IN, MAC_RX_ERROR_IN, frame_active, rb_full ) + begin + ld_wr_ptr <= '0'; + + case STATE is + + when RX_DENY => + if( (frame_active = '0') and (rb_full = '0') ) then + NEXT_STATE <= RX_READY; + else + NEXT_STATE <= RX_DENY; + end if; + + when RX_READY => + if( MAC_RX_WR_IN = '1' ) then + NEXT_STATE <= RX_FRAME; + else + NEXT_STATE <= RX_READY; + end if; + + when RX_FRAME => + if ( (MAC_RX_EOF_IN = '1') and (MAC_RX_ERROR_IN = '0') and (rb_full = '0') ) then + NEXT_STATE <= FRAME_OK; + elsif( (MAC_RX_EOF_IN = '1') and ((MAC_RX_ERROR_IN = '1') or (rb_full = '1')) ) then + NEXT_STATE <= FRAME_BAD; + ld_wr_ptr <= '1'; + else + NEXT_STATE <= RX_FRAME; + end if; + + when FRAME_OK => + NEXT_STATE <= FORWARD; + + when FORWARD => + if( rb_full = '0' ) then + NEXT_STATE <= RX_READY; + else + NEXT_STATE <= RX_DENY; + end if; + + when FRAME_BAD => + NEXT_STATE <= SKIP; + + when SKIP => + if( rb_full = '0' ) then + NEXT_STATE <= RX_READY; + else + NEXT_STATE <= RX_DENY; + end if; + + when others => + NEXT_STATE <= RX_DENY; + end case; + end process THE_STATE_TRANSITIONS; + + + +end architecture; diff --git a/gbe_trb_ecp3/base/tx_fifo.vhd b/gbe_trb_ecp3/base/tx_fifo.vhd new file mode 100644 index 0000000..bcf8d7b --- /dev/null +++ b/gbe_trb_ecp3/base/tx_fifo.vhd @@ -0,0 +1,99 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; + +entity tx_fifo is + port( + CLK : in std_logic; + CLEAR : in std_logic; + RESET : in std_logic; + -- MAC interface + MAC_TX_DATA_OUT : out std_logic_vector(7 downto 0); + MAC_TX_READ_IN : in std_logic; + MAC_FIFOEOF_OUT : out std_logic; -- end of frame marker + MAC_FIFOEMPTY_OUT : out std_logic; -- must never happen during TX + MAC_FIFOAVAIL_OUT : out std_logic; -- starts TX process in MAC + MAC_TX_DONE_IN : in std_logic; -- frame sent + -- FIFO interface + FIFO_FULL_OUT : out std_logic; + FIFO_WR_IN : in std_logic; + FIFO_D_IN : in std_logic_vector(8 downto 0); + -- + DEBUG : out std_logic_vector(15 downto 0) + ); +end entity tx_fifo; + +architecture tx_fifo_arch of tx_fifo is + +-- Components + component fifo_4k_9 + port( + DATA : in std_logic_vector(8 downto 0); + CLOCK : in std_logic; + WREN : in std_logic; + RDEN : in std_logic; + RESET : in std_logic; + Q : out std_logic_vector(8 downto 0); + EMPTY : out std_logic; + FULL : out std_logic; + ALMOSTFULL : out std_logic + ); + end component fifo_4k_9; + +-- state machine signals + +-- Signals + signal frames_avail : unsigned(7 downto 0); + signal frame_written : std_logic; + signal frame_read : std_logic; + signal mac_fifoeof : std_logic; + signal mac_tx_read : std_logic; + +begin + + -- TX FIFO storing full outgoing frames + THE_TX_FIFO: fifo_4k_9 + port map( + DATA => FIFO_D_IN, + CLOCK => CLK, + WREN => FIFO_WR_IN, + RDEN => MAC_TX_READ_IN, + RESET => CLEAR, + Q(8) => mac_fifoeof, + Q(7 downto 0) => MAC_TX_DATA_OUT, + EMPTY => MAC_FIFOEMPTY_OUT, + FULL => open, + ALMOSTFULL => FIFO_FULL_OUT + ); + + MAC_FIFOEOF_OUT <= mac_fifoeof; + + mac_tx_read <= MAC_TX_READ_IN when rising_edge(CLK); + + -- one frame written to FIFO + frame_written <= '1' when (FIFO_D_IN(8) = '1') and (FIFO_WR_IN = '1') else '0'; + + -- one frame read from FIFO + frame_read <= '1' when (mac_fifoeof = '1') and (mac_tx_read = '1') else '0'; + + -- FramesAvailable counter + THE_FRAMES_AVAIL_PROC: process( CLK, CLEAR ) + begin + if( CLEAR = '1' ) then + frames_avail <= (others => '0'); + elsif( rising_edge(CLK) ) then + if ( (frame_written = '1') and (frame_read = '0') ) then + -- one frame written successfully + frames_avail <= frames_avail + 1; + elsif( (frame_written = '0') and (frame_read = '1') ) then + -- one frame read successfully + frames_avail <= frames_avail - 1; + end if; + end if; + end process THE_FRAMES_AVAIL_PROC; + + MAC_FIFOAVAIL_OUT <= '1' when (frames_avail /= x"00") else '0'; + +end architecture; diff --git a/gbe_trb_ecp3/cores/fifo_4k_9.ipx b/gbe_trb_ecp3/cores/fifo_4k_9.ipx new file mode 100644 index 0000000..2633d11 --- /dev/null +++ b/gbe_trb_ecp3/cores/fifo_4k_9.ipx @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/gbe_trb_ecp3/cores/fifo_4k_9.vhd b/gbe_trb_ecp3/cores/fifo_4k_9.vhd new file mode 100644 index 0000000..9c80125 --- /dev/null +++ b/gbe_trb_ecp3/cores/fifo_4k_9.vhd @@ -0,0 +1,963 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 +-- Module Version: 5.1 +--/opt/lattice/diamond/3.12/ispfpga/bin/lin64/scuba -w -n fifo_4k_9 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 4096 -width 9 -depth 4096 -no_enable -pe -1 -pf 4092 + +-- Wed Jul 6 08:38:58 2022 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity fifo_4k_9 is + port ( + Data: in std_logic_vector(8 downto 0); + Clock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + Q: out std_logic_vector(8 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostFull: out std_logic); +end fifo_4k_9; + +architecture Structure of fifo_4k_9 is + + -- internal signal declarations + signal invout_2: std_logic; + signal invout_1: std_logic; + signal rden_i_inv: std_logic; + signal invout_0: std_logic; + signal r_nw_inv: std_logic; + signal r_nw: std_logic; + signal fcnt_en_inv: std_logic; + signal fcnt_en: std_logic; + signal empty_i: std_logic; + signal empty_d: std_logic; + signal full_i: std_logic; + signal full_d: std_logic; + signal ifcount_0: std_logic; + signal ifcount_1: std_logic; + signal bdcnt_bctr_ci: std_logic; + signal ifcount_2: std_logic; + signal ifcount_3: std_logic; + signal co0: std_logic; + signal ifcount_4: std_logic; + signal ifcount_5: std_logic; + signal co1: std_logic; + signal ifcount_6: std_logic; + signal ifcount_7: std_logic; + signal co2: std_logic; + signal ifcount_8: std_logic; + signal ifcount_9: std_logic; + signal co3: std_logic; + signal ifcount_10: std_logic; + signal ifcount_11: std_logic; + signal co4: std_logic; + signal ifcount_12: std_logic; + signal co6: std_logic; + signal co5: std_logic; + signal cmp_ci: std_logic; + signal rden_i: std_logic; + signal co0_1: std_logic; + signal co1_1: std_logic; + signal co2_1: std_logic; + signal co3_1: std_logic; + signal co4_1: std_logic; + signal co5_1: std_logic; + signal cmp_le_1: std_logic; + signal cmp_le_1_c: std_logic; + signal cmp_ci_1: std_logic; + signal co0_2: std_logic; + signal co1_2: std_logic; + signal co2_2: std_logic; + signal co3_2: std_logic; + signal co4_2: std_logic; + signal wren_i: std_logic; + signal co5_2: std_logic; + signal wren_i_inv: std_logic; + signal cmp_ge_d1: std_logic; + signal cmp_ge_d1_c: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_ctr_ci: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0_3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1_3: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2_3: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co3_3: std_logic; + signal wcount_8: std_logic; + signal wcount_9: std_logic; + signal iwcount_10: std_logic; + signal iwcount_11: std_logic; + signal co4_3: std_logic; + signal wcount_10: std_logic; + signal wcount_11: std_logic; + signal iwcount_12: std_logic; + signal co6_1: std_logic; + signal co5_3: std_logic; + signal wcount_12: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_ctr_ci: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_4: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_4: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_4: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co3_4: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal ircount_10: std_logic; + signal ircount_11: std_logic; + signal co4_4: std_logic; + signal rcount_10: std_logic; + signal rcount_11: std_logic; + signal ircount_12: std_logic; + signal co6_2: std_logic; + signal co5_4: std_logic; + signal rcount_12: std_logic; + signal mdout1_1_0: std_logic; + signal mdout1_0_0: std_logic; + signal mdout1_1_1: std_logic; + signal mdout1_0_1: std_logic; + signal mdout1_1_2: std_logic; + signal mdout1_0_2: std_logic; + signal mdout1_1_3: std_logic; + signal mdout1_0_3: std_logic; + signal mdout1_1_4: std_logic; + signal mdout1_0_4: std_logic; + signal mdout1_1_5: std_logic; + signal mdout1_0_5: std_logic; + signal mdout1_1_6: std_logic; + signal mdout1_0_6: std_logic; + signal mdout1_1_7: std_logic; + signal mdout1_0_7: std_logic; + signal rcount_11_ff: std_logic; + signal mdout1_1_8: std_logic; + signal mdout1_0_8: std_logic; + signal cmp_ci_2: std_logic; + signal fcnt_en_inv_inv: std_logic; + signal cnt_con: std_logic; + signal fcount_0: std_logic; + signal fcount_1: std_logic; + signal co0_5: std_logic; + signal cnt_con_inv: std_logic; + signal fcount_2: std_logic; + signal fcount_3: std_logic; + signal co1_5: std_logic; + signal fcount_4: std_logic; + signal fcount_5: std_logic; + signal co2_5: std_logic; + signal fcount_6: std_logic; + signal fcount_7: std_logic; + signal co3_5: std_logic; + signal fcount_8: std_logic; + signal fcount_9: std_logic; + signal co4_5: std_logic; + signal scuba_vhi: std_logic; + signal fcount_10: std_logic; + signal fcount_11: std_logic; + signal co5_5: std_logic; + signal fcount_12: std_logic; + signal af_d: std_logic; + signal af_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component ALEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; LE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component CB2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CON: in std_logic; CO: out std_logic; NC0: out std_logic; + NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component MUX21 + port (D0: in std_logic; D1: in std_logic; SD: in std_logic; + Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component DP16KC + generic (GSR : in String; WRITEMODE_B : in String; + WRITEMODE_A : in String; CSDECODE_B : in String; + CSDECODE_A : in String; REGMODE_B : in String; + REGMODE_A : in String; DATA_WIDTH_B : in Integer; + DATA_WIDTH_A : in Integer); + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; + WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; + WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_4k_9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is ""; + attribute RESETMODE of pdp_ram_0_0_1 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_1_0_0 : label is "fifo_4k_9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_0_0 : label is ""; + attribute RESETMODE of pdp_ram_1_0_0 : label is "SYNC"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t4: AND2 + port map (A=>WrEn, B=>invout_2, Z=>wren_i); + + INV_8: INV + port map (A=>full_i, Z=>invout_2); + + AND2_t3: AND2 + port map (A=>RdEn, B=>invout_1, Z=>rden_i); + + INV_7: INV + port map (A=>empty_i, Z=>invout_1); + + AND2_t2: AND2 + port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con); + + XOR2_t1: XOR2 + port map (A=>wren_i, B=>rden_i, Z=>fcnt_en); + + INV_6: INV + port map (A=>rden_i, Z=>rden_i_inv); + + INV_5: INV + port map (A=>wren_i, Z=>wren_i_inv); + + LUT4_1: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, + AD0=>empty_i, DO0=>empty_d); + + LUT4_0: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, + AD0=>full_i, DO0=>full_d); + + AND2_t0: AND2 + port map (A=>rden_i, B=>invout_0, Z=>r_nw); + + INV_4: INV + port map (A=>wren_i, Z=>invout_0); + + INV_3: INV + port map (A=>fcnt_en, Z=>fcnt_en_inv); + + INV_2: INV + port map (A=>cnt_con, Z=>cnt_con_inv); + + INV_1: INV + port map (A=>r_nw, Z=>r_nw_inv); + + INV_0: INV + port map (A=>fcnt_en_inv, Z=>fcnt_en_inv_inv); + + pdp_ram_0_0_1: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wcount_0, + ADA4=>wcount_1, ADA5=>wcount_2, ADA6=>wcount_3, + ADA7=>wcount_4, ADA8=>wcount_5, ADA9=>wcount_6, + ADA10=>wcount_7, ADA11=>wcount_8, ADA12=>wcount_9, + ADA13=>wcount_10, CEA=>wren_i, CLKA=>Clock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>wcount_11, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rcount_0, + ADB4=>rcount_1, ADB5=>rcount_2, ADB6=>rcount_3, + ADB7=>rcount_4, ADB8=>rcount_5, ADB9=>rcount_6, + ADB10=>rcount_7, ADB11=>rcount_8, ADB12=>rcount_9, + ADB13=>rcount_10, CEB=>rden_i, CLKB=>Clock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rcount_11, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, DOB1=>mdout1_0_1, + DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, DOB4=>mdout1_0_4, + DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, DOB7=>mdout1_0_7, + DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_1_0_0: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wcount_0, + ADA4=>wcount_1, ADA5=>wcount_2, ADA6=>wcount_3, + ADA7=>wcount_4, ADA8=>wcount_5, ADA9=>wcount_6, + ADA10=>wcount_7, ADA11=>wcount_8, ADA12=>wcount_9, + ADA13=>wcount_10, CEA=>wren_i, CLKA=>Clock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>wcount_11, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rcount_0, + ADB4=>rcount_1, ADB5=>rcount_2, ADB6=>rcount_3, + ADB7=>rcount_4, ADB8=>rcount_5, ADB9=>rcount_6, + ADB10=>rcount_7, ADB11=>rcount_8, ADB12=>rcount_9, + ADB13=>rcount_10, CEB=>rden_i, CLKB=>Clock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rcount_11, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, DOB1=>mdout1_1_1, + DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, DOB4=>mdout1_1_4, + DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, DOB7=>mdout1_1_7, + DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + FF_42: FD1P3DX + port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_0); + + FF_41: FD1P3DX + port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_1); + + FF_40: FD1P3DX + port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_2); + + FF_39: FD1P3DX + port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_3); + + FF_38: FD1P3DX + port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_4); + + FF_37: FD1P3DX + port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_5); + + FF_36: FD1P3DX + port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_6); + + FF_35: FD1P3DX + port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_7); + + FF_34: FD1P3DX + port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_8); + + FF_33: FD1P3DX + port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_9); + + FF_32: FD1P3DX + port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_10); + + FF_31: FD1P3DX + port map (D=>ifcount_11, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_11); + + FF_30: FD1P3DX + port map (D=>ifcount_12, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_12); + + FF_29: FD1S3BX + port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i); + + FF_28: FD1S3DX + port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i); + + FF_27: FD1P3DX + port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_0); + + FF_26: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_1); + + FF_25: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_2); + + FF_24: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_3); + + FF_23: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_4); + + FF_22: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_5); + + FF_21: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_6); + + FF_20: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_7); + + FF_19: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_8); + + FF_18: FD1P3DX + port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_9); + + FF_17: FD1P3DX + port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_10); + + FF_16: FD1P3DX + port map (D=>iwcount_11, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_11); + + FF_15: FD1P3DX + port map (D=>iwcount_12, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_12); + + FF_14: FD1P3DX + port map (D=>ircount_0, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_0); + + FF_13: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_1); + + FF_12: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_2); + + FF_11: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_3); + + FF_10: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_4); + + FF_9: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_5); + + FF_8: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_6); + + FF_7: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_7); + + FF_6: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_8); + + FF_5: FD1P3DX + port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_9); + + FF_4: FD1P3DX + port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_10); + + FF_3: FD1P3DX + port map (D=>ircount_11, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_11); + + FF_2: FD1P3DX + port map (D=>ircount_12, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_12); + + FF_1: FD1P3DX + port map (D=>rcount_11, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, + Q=>rcount_11_ff); + + FF_0: FD1S3DX + port map (D=>af_d, CK=>Clock, CD=>Reset, Q=>AlmostFull); + + bdcnt_bctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, + CI=>scuba_vlo, COUT=>bdcnt_bctr_ci, S0=>open, S1=>open); + + bdcnt_bctr_0: CB2 + port map (CI=>bdcnt_bctr_ci, PC0=>fcount_0, PC1=>fcount_1, + CON=>cnt_con, CO=>co0, NC0=>ifcount_0, NC1=>ifcount_1); + + bdcnt_bctr_1: CB2 + port map (CI=>co0, PC0=>fcount_2, PC1=>fcount_3, CON=>cnt_con, + CO=>co1, NC0=>ifcount_2, NC1=>ifcount_3); + + bdcnt_bctr_2: CB2 + port map (CI=>co1, PC0=>fcount_4, PC1=>fcount_5, CON=>cnt_con, + CO=>co2, NC0=>ifcount_4, NC1=>ifcount_5); + + bdcnt_bctr_3: CB2 + port map (CI=>co2, PC0=>fcount_6, PC1=>fcount_7, CON=>cnt_con, + CO=>co3, NC0=>ifcount_6, NC1=>ifcount_7); + + bdcnt_bctr_4: CB2 + port map (CI=>co3, PC0=>fcount_8, PC1=>fcount_9, CON=>cnt_con, + CO=>co4, NC0=>ifcount_8, NC1=>ifcount_9); + + bdcnt_bctr_5: CB2 + port map (CI=>co4, PC0=>fcount_10, PC1=>fcount_11, CON=>cnt_con, + CO=>co5, NC0=>ifcount_10, NC1=>ifcount_11); + + bdcnt_bctr_6: CB2 + port map (CI=>co5, PC0=>fcount_12, PC1=>scuba_vlo, CON=>cnt_con, + CO=>co6, NC0=>ifcount_12, NC1=>open); + + e_cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, + S1=>open); + + e_cmp_0: ALEB2 + port map (A0=>fcount_0, A1=>fcount_1, B0=>rden_i, B1=>scuba_vlo, + CI=>cmp_ci, LE=>co0_1); + + e_cmp_1: ALEB2 + port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co0_1, LE=>co1_1); + + e_cmp_2: ALEB2 + port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co1_1, LE=>co2_1); + + e_cmp_3: ALEB2 + port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co2_1, LE=>co3_1); + + e_cmp_4: ALEB2 + port map (A0=>fcount_8, A1=>fcount_9, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co3_1, LE=>co4_1); + + e_cmp_5: ALEB2 + port map (A0=>fcount_10, A1=>fcount_11, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co4_1, LE=>co5_1); + + e_cmp_6: ALEB2 + port map (A0=>fcount_12, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co5_1, LE=>cmp_le_1_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>cmp_le_1_c, COUT=>open, S0=>cmp_le_1, + S1=>open); + + g_cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, + S1=>open); + + g_cmp_0: AGEB2 + port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, + CI=>cmp_ci_1, GE=>co0_2); + + g_cmp_1: AGEB2 + port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, + CI=>co0_2, GE=>co1_2); + + g_cmp_2: AGEB2 + port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i, + CI=>co1_2, GE=>co2_2); + + g_cmp_3: AGEB2 + port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i, + CI=>co2_2, GE=>co3_2); + + g_cmp_4: AGEB2 + port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i, + CI=>co3_2, GE=>co4_2); + + g_cmp_5: AGEB2 + port map (A0=>fcount_10, A1=>fcount_11, B0=>wren_i, B1=>wren_i, + CI=>co4_2, GE=>co5_2); + + g_cmp_6: AGEB2 + port map (A0=>fcount_12, A1=>scuba_vlo, B0=>wren_i_inv, + B1=>scuba_vlo, CI=>co5_2, GE=>cmp_ge_d1_c); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>cmp_ge_d1_c, COUT=>open, S0=>cmp_ge_d1, + S1=>open); + + w_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_ctr_ci, S0=>open, + S1=>open); + + w_ctr_0: CU2 + port map (CI=>w_ctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0_3, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_ctr_1: CU2 + port map (CI=>co0_3, PC0=>wcount_2, PC1=>wcount_3, CO=>co1_3, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_ctr_2: CU2 + port map (CI=>co1_3, PC0=>wcount_4, PC1=>wcount_5, CO=>co2_3, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_ctr_3: CU2 + port map (CI=>co2_3, PC0=>wcount_6, PC1=>wcount_7, CO=>co3_3, + NC0=>iwcount_6, NC1=>iwcount_7); + + w_ctr_4: CU2 + port map (CI=>co3_3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4_3, + NC0=>iwcount_8, NC1=>iwcount_9); + + w_ctr_5: CU2 + port map (CI=>co4_3, PC0=>wcount_10, PC1=>wcount_11, CO=>co5_3, + NC0=>iwcount_10, NC1=>iwcount_11); + + w_ctr_6: CU2 + port map (CI=>co5_3, PC0=>wcount_12, PC1=>scuba_vlo, CO=>co6_1, + NC0=>iwcount_12, NC1=>open); + + r_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open, + S1=>open); + + r_ctr_0: CU2 + port map (CI=>r_ctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_4, + NC0=>ircount_0, NC1=>ircount_1); + + r_ctr_1: CU2 + port map (CI=>co0_4, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_4, + NC0=>ircount_2, NC1=>ircount_3); + + r_ctr_2: CU2 + port map (CI=>co1_4, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_4, + NC0=>ircount_4, NC1=>ircount_5); + + r_ctr_3: CU2 + port map (CI=>co2_4, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_4, + NC0=>ircount_6, NC1=>ircount_7); + + r_ctr_4: CU2 + port map (CI=>co3_4, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_4, + NC0=>ircount_8, NC1=>ircount_9); + + r_ctr_5: CU2 + port map (CI=>co4_4, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_4, + NC0=>ircount_10, NC1=>ircount_11); + + r_ctr_6: CU2 + port map (CI=>co5_4, PC0=>rcount_12, PC1=>scuba_vlo, CO=>co6_2, + NC0=>ircount_12, NC1=>open); + + mux_8: MUX21 + port map (D0=>mdout1_0_0, D1=>mdout1_1_0, SD=>rcount_11_ff, + Z=>Q(0)); + + mux_7: MUX21 + port map (D0=>mdout1_0_1, D1=>mdout1_1_1, SD=>rcount_11_ff, + Z=>Q(1)); + + mux_6: MUX21 + port map (D0=>mdout1_0_2, D1=>mdout1_1_2, SD=>rcount_11_ff, + Z=>Q(2)); + + mux_5: MUX21 + port map (D0=>mdout1_0_3, D1=>mdout1_1_3, SD=>rcount_11_ff, + Z=>Q(3)); + + mux_4: MUX21 + port map (D0=>mdout1_0_4, D1=>mdout1_1_4, SD=>rcount_11_ff, + Z=>Q(4)); + + mux_3: MUX21 + port map (D0=>mdout1_0_5, D1=>mdout1_1_5, SD=>rcount_11_ff, + Z=>Q(5)); + + mux_2: MUX21 + port map (D0=>mdout1_0_6, D1=>mdout1_1_6, SD=>rcount_11_ff, + Z=>Q(6)); + + mux_1: MUX21 + port map (D0=>mdout1_0_7, D1=>mdout1_1_7, SD=>rcount_11_ff, + Z=>Q(7)); + + mux_0: MUX21 + port map (D0=>mdout1_0_8, D1=>mdout1_1_8, SD=>rcount_11_ff, + Z=>Q(8)); + + af_cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, + S1=>open); + + af_cmp_0: AGEB2 + port map (A0=>fcount_0, A1=>fcount_1, B0=>fcnt_en_inv_inv, + B1=>cnt_con, CI=>cmp_ci_2, GE=>co0_5); + + af_cmp_1: AGEB2 + port map (A0=>fcount_2, A1=>fcount_3, B0=>cnt_con_inv, + B1=>scuba_vhi, CI=>co0_5, GE=>co1_5); + + af_cmp_2: AGEB2 + port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>co1_5, GE=>co2_5); + + af_cmp_3: AGEB2 + port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>co2_5, GE=>co3_5); + + af_cmp_4: AGEB2 + port map (A0=>fcount_8, A1=>fcount_9, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>co3_5, GE=>co4_5); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + af_cmp_5: AGEB2 + port map (A0=>fcount_10, A1=>fcount_11, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>co4_5, GE=>co5_5); + + af_cmp_6: AGEB2 + port map (A0=>fcount_12, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co5_5, GE=>af_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a2: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>af_d_c, COUT=>open, S0=>af_d, S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of fifo_4k_9 is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:ALEB2 use entity ecp3.ALEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:CB2 use entity ecp3.CB2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:MUX21 use entity ecp3.MUX21(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:DP16KC use entity ecp3.DP16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_trb_ecp3/cores/rb_4k_9.ipx b/gbe_trb_ecp3/cores/rb_4k_9.ipx new file mode 100644 index 0000000..ece8310 --- /dev/null +++ b/gbe_trb_ecp3/cores/rb_4k_9.ipx @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/gbe_trb_ecp3/cores/rb_4k_9.vhd b/gbe_trb_ecp3/cores/rb_4k_9.vhd new file mode 100644 index 0000000..e750608 --- /dev/null +++ b/gbe_trb_ecp3/cores/rb_4k_9.vhd @@ -0,0 +1,449 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 +-- Module Version: 6.5 +--/opt/lattice/diamond/3.12/ispfpga/bin/lin64/scuba -w -n rb_4k_9 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 10 -rp 0011 -rdata_width 9 -data_width 9 -num_rows 4096 -memfile /home/michaelb/PONE/XXX/rb_4k_9.mem -memformat orca -cascade -1 + +-- Mon Jul 4 22:09:52 2022 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity rb_4k_9 is + port ( + WrAddress: in std_logic_vector(11 downto 0); + RdAddress: in std_logic_vector(11 downto 0); + Data: in std_logic_vector(8 downto 0); + WE: in std_logic; + RdClock: in std_logic; + RdClockEn: in std_logic; + Reset: in std_logic; + WrClock: in std_logic; + WrClockEn: in std_logic; + Q: out std_logic_vector(8 downto 0)); +end rb_4k_9; + +architecture Structure of rb_4k_9 is + + -- internal signal declarations + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + signal mdout1_1_0: std_logic; + signal mdout1_0_0: std_logic; + signal mdout1_1_1: std_logic; + signal mdout1_0_1: std_logic; + signal mdout1_1_2: std_logic; + signal mdout1_0_2: std_logic; + signal mdout1_1_3: std_logic; + signal mdout1_0_3: std_logic; + signal mdout1_1_4: std_logic; + signal mdout1_0_4: std_logic; + signal mdout1_1_5: std_logic; + signal mdout1_0_5: std_logic; + signal mdout1_1_6: std_logic; + signal mdout1_0_6: std_logic; + signal mdout1_1_7: std_logic; + signal mdout1_0_7: std_logic; + signal raddr11_ff: std_logic; + signal mdout1_1_8: std_logic; + signal mdout1_0_8: std_logic; + + -- local component declarations + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component MUX21 + port (D0: in std_logic; D1: in std_logic; SD: in std_logic; + Z: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component DP16KC + generic (INITVAL_3F : in String; INITVAL_3E : in String; + INITVAL_3D : in String; INITVAL_3C : in String; + INITVAL_3B : in String; INITVAL_3A : in String; + INITVAL_39 : in String; INITVAL_38 : in String; + INITVAL_37 : in String; INITVAL_36 : in String; + INITVAL_35 : in String; INITVAL_34 : in String; + INITVAL_33 : in String; INITVAL_32 : in String; + INITVAL_31 : in String; INITVAL_30 : in String; + INITVAL_2F : in String; INITVAL_2E : in String; + INITVAL_2D : in String; INITVAL_2C : in String; + INITVAL_2B : in String; INITVAL_2A : in String; + INITVAL_29 : in String; INITVAL_28 : in String; + INITVAL_27 : in String; INITVAL_26 : in String; + INITVAL_25 : in String; INITVAL_24 : in String; + INITVAL_23 : in String; INITVAL_22 : in String; + INITVAL_21 : in String; INITVAL_20 : in String; + INITVAL_1F : in String; INITVAL_1E : in String; + INITVAL_1D : in String; INITVAL_1C : in String; + INITVAL_1B : in String; INITVAL_1A : in String; + INITVAL_19 : in String; INITVAL_18 : in String; + INITVAL_17 : in String; INITVAL_16 : in String; + INITVAL_15 : in String; INITVAL_14 : in String; + INITVAL_13 : in String; INITVAL_12 : in String; + INITVAL_11 : in String; INITVAL_10 : in String; + INITVAL_0F : in String; INITVAL_0E : in String; + INITVAL_0D : in String; INITVAL_0C : in String; + INITVAL_0B : in String; INITVAL_0A : in String; + INITVAL_09 : in String; INITVAL_08 : in String; + INITVAL_07 : in String; INITVAL_06 : in String; + INITVAL_05 : in String; INITVAL_04 : in String; + INITVAL_03 : in String; INITVAL_02 : in String; + INITVAL_01 : in String; INITVAL_00 : in String; + GSR : in String; WRITEMODE_B : in String; + WRITEMODE_A : in String; CSDECODE_B : in String; + CSDECODE_A : in String; REGMODE_B : in String; + REGMODE_A : in String; DATA_WIDTH_B : in Integer; + DATA_WIDTH_A : in Integer); + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; + WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; + WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of rb_4k_9_0_0_1 : label is "rb_4k_9.lpc"; + attribute MEM_INIT_FILE of rb_4k_9_0_0_1 : label is "rb_4k_9.mem"; + attribute RESETMODE of rb_4k_9_0_0_1 : label is "SYNC"; + attribute MEM_LPC_FILE of rb_4k_9_1_0_0 : label is "rb_4k_9.lpc"; + attribute MEM_INIT_FILE of rb_4k_9_1_0_0 : label is "rb_4k_9.mem"; + attribute RESETMODE of rb_4k_9_1_0_0 : label is "SYNC"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + rb_4k_9_0_0_1: DP16KC + generic map (INITVAL_3F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_39=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_38=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_37=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_36=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_35=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_34=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_33=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_32=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_31=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_30=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_29=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_28=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_27=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_26=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_25=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_24=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_23=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_22=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_21=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_20=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_09=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_08=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_07=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_06=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_05=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_04=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_03=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_02=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_01=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_00=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", + REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>WrAddress(0), + ADA4=>WrAddress(1), ADA5=>WrAddress(2), ADA6=>WrAddress(3), + ADA7=>WrAddress(4), ADA8=>WrAddress(5), ADA9=>WrAddress(6), + ADA10=>WrAddress(7), ADA11=>WrAddress(8), + ADA12=>WrAddress(9), ADA13=>WrAddress(10), CEA=>WrClockEn, + CLKA=>WrClock, OCEA=>WrClockEn, WEA=>WE, CSA0=>WrAddress(11), + CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, + ADB3=>RdAddress(0), ADB4=>RdAddress(1), ADB5=>RdAddress(2), + ADB6=>RdAddress(3), ADB7=>RdAddress(4), ADB8=>RdAddress(5), + ADB9=>RdAddress(6), ADB10=>RdAddress(7), ADB11=>RdAddress(8), + ADB12=>RdAddress(9), ADB13=>RdAddress(10), CEB=>RdClockEn, + CLKB=>RdClock, OCEB=>RdClockEn, WEB=>scuba_vlo, + CSB0=>RdAddress(11), CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_0_0, DOB1=>mdout1_0_1, + DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, DOB4=>mdout1_0_4, + DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, DOB7=>mdout1_0_7, + DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + rb_4k_9_1_0_0: DP16KC + generic map (INITVAL_3F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_39=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_38=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_37=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_36=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_35=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_34=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_33=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_32=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_31=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_30=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_29=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_28=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_27=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_26=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_25=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_24=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_23=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_22=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_21=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_20=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_09=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_08=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_07=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_06=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_05=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_04=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_03=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_02=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_01=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_00=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", + REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>WrAddress(0), + ADA4=>WrAddress(1), ADA5=>WrAddress(2), ADA6=>WrAddress(3), + ADA7=>WrAddress(4), ADA8=>WrAddress(5), ADA9=>WrAddress(6), + ADA10=>WrAddress(7), ADA11=>WrAddress(8), + ADA12=>WrAddress(9), ADA13=>WrAddress(10), CEA=>WrClockEn, + CLKA=>WrClock, OCEA=>WrClockEn, WEA=>WE, CSA0=>WrAddress(11), + CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, + ADB3=>RdAddress(0), ADB4=>RdAddress(1), ADB5=>RdAddress(2), + ADB6=>RdAddress(3), ADB7=>RdAddress(4), ADB8=>RdAddress(5), + ADB9=>RdAddress(6), ADB10=>RdAddress(7), ADB11=>RdAddress(8), + ADB12=>RdAddress(9), ADB13=>RdAddress(10), CEB=>RdClockEn, + CLKB=>RdClock, OCEB=>RdClockEn, WEB=>scuba_vlo, + CSB0=>RdAddress(11), CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_1_0, DOB1=>mdout1_1_1, + DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, DOB4=>mdout1_1_4, + DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, DOB7=>mdout1_1_7, + DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + FF_0: FD1P3DX + port map (D=>RdAddress(11), SP=>RdClockEn, CK=>RdClock, + CD=>scuba_vlo, Q=>raddr11_ff); + + mux_8: MUX21 + port map (D0=>mdout1_0_0, D1=>mdout1_1_0, SD=>raddr11_ff, + Z=>Q(0)); + + mux_7: MUX21 + port map (D0=>mdout1_0_1, D1=>mdout1_1_1, SD=>raddr11_ff, + Z=>Q(1)); + + mux_6: MUX21 + port map (D0=>mdout1_0_2, D1=>mdout1_1_2, SD=>raddr11_ff, + Z=>Q(2)); + + mux_5: MUX21 + port map (D0=>mdout1_0_3, D1=>mdout1_1_3, SD=>raddr11_ff, + Z=>Q(3)); + + mux_4: MUX21 + port map (D0=>mdout1_0_4, D1=>mdout1_1_4, SD=>raddr11_ff, + Z=>Q(4)); + + mux_3: MUX21 + port map (D0=>mdout1_0_5, D1=>mdout1_1_5, SD=>raddr11_ff, + Z=>Q(5)); + + mux_2: MUX21 + port map (D0=>mdout1_0_6, D1=>mdout1_1_6, SD=>raddr11_ff, + Z=>Q(6)); + + mux_1: MUX21 + port map (D0=>mdout1_0_7, D1=>mdout1_1_7, SD=>raddr11_ff, + Z=>Q(7)); + + mux_0: MUX21 + port map (D0=>mdout1_0_8, D1=>mdout1_1_8, SD=>raddr11_ff, + Z=>Q(8)); + +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of rb_4k_9 is + for Structure + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:MUX21 use entity ecp3.MUX21(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:DP16KC use entity ecp3.DP16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on -- 2.43.0