From ce8f7fefd145520125a2d069d43a136a64c48c5a Mon Sep 17 00:00:00 2001 From: hadaq Date: Mon, 14 Jan 2013 10:59:45 +0000 Subject: [PATCH] *** empty log message *** --- tdc_releases/tdc_v_stretcher/Adder_304.vhd | 1310 ---------------- tdc_releases/tdc_v_stretcher/BusHandler.vhd | 82 - tdc_releases/tdc_v_stretcher/Channel.vhd | 215 --- tdc_releases/tdc_v_stretcher/Channel_200.vhd | 315 ---- .../tdc_v_stretcher/Encoder_304_Bit.vhd | 498 ------ .../tdc_v_stretcher/FIFO_32x32_OutReg.vhd | 932 ----------- .../tdc_v_stretcher/LogicAnalyser.vhd | 80 - tdc_releases/tdc_v_stretcher/ROM_FIFO.vhd | 262 ---- .../tdc_v_stretcher/ROM_encoder_3.vhd | 262 ---- tdc_releases/tdc_v_stretcher/Readout.vhd | 1105 ------------- .../tdc_v_stretcher/Reference_Channel.vhd | 131 -- .../tdc_v_stretcher/Reference_Channel_200.vhd | 437 ------ .../tdc_v_stretcher/ShiftRegisterSISO.vhd | 59 - tdc_releases/tdc_v_stretcher/TDC.vhd | 432 ------ tdc_releases/tdc_v_stretcher/bit_sync.vhd | 60 - .../trb3_periph_constraints.lpf.jan | 1381 ----------------- tdc_releases/tdc_v_stretcher/up_counter.vhd | 41 - 17 files changed, 7602 deletions(-) delete mode 100644 tdc_releases/tdc_v_stretcher/Adder_304.vhd delete mode 100644 tdc_releases/tdc_v_stretcher/BusHandler.vhd delete mode 100644 tdc_releases/tdc_v_stretcher/Channel.vhd delete mode 100644 tdc_releases/tdc_v_stretcher/Channel_200.vhd delete mode 100644 tdc_releases/tdc_v_stretcher/Encoder_304_Bit.vhd delete mode 100644 tdc_releases/tdc_v_stretcher/FIFO_32x32_OutReg.vhd delete mode 100644 tdc_releases/tdc_v_stretcher/LogicAnalyser.vhd delete mode 100644 tdc_releases/tdc_v_stretcher/ROM_FIFO.vhd delete mode 100644 tdc_releases/tdc_v_stretcher/ROM_encoder_3.vhd delete mode 100644 tdc_releases/tdc_v_stretcher/Readout.vhd delete mode 100644 tdc_releases/tdc_v_stretcher/Reference_Channel.vhd delete mode 100644 tdc_releases/tdc_v_stretcher/Reference_Channel_200.vhd delete mode 100644 tdc_releases/tdc_v_stretcher/ShiftRegisterSISO.vhd delete mode 100644 tdc_releases/tdc_v_stretcher/TDC.vhd delete mode 100644 tdc_releases/tdc_v_stretcher/bit_sync.vhd delete mode 100644 tdc_releases/tdc_v_stretcher/trb3_periph_constraints.lpf.jan delete mode 100644 tdc_releases/tdc_v_stretcher/up_counter.vhd diff --git a/tdc_releases/tdc_v_stretcher/Adder_304.vhd b/tdc_releases/tdc_v_stretcher/Adder_304.vhd deleted file mode 100644 index d5b4914..0000000 --- a/tdc_releases/tdc_v_stretcher/Adder_304.vhd +++ /dev/null @@ -1,1310 +0,0 @@ -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp3; -use ecp3.components.all; --- synopsys translate_on - - -entity Adder_304 is - port (CLK : in std_logic; - RESET : in std_logic; - DataA : in std_logic_vector(303 downto 0); - DataB : in std_logic_vector(303 downto 0); - ClkEn : in std_logic; - Result : out std_logic_vector(303 downto 0) - ); -end Adder_304; - -architecture Structure of Adder_304 is - --- internal signal declarations - signal r0_sum : std_logic_vector(303 downto 0); - signal tsum : std_logic_vector(303 downto 0); - signal co : std_logic_vector(151 downto 0); - signal scuba_vlo : std_logic; - --- local component declarations - component FADD2B - port (A0 : in std_logic; - A1 : in std_logic; - B0 : in std_logic; - B1 : in std_logic; - CI : in std_logic; - COUT : out std_logic; - S0 : out std_logic; - S1 : out std_logic); - end component; - component FD1P3DX - port (D : in std_logic; - SP : in std_logic; - CK : in std_logic; - CD : in std_logic; - Q : out std_logic); - end component; - component VLO - port (Z : out std_logic); - end component; - - attribute GSR : string; - attribute GSR of FF_303 : label is "ENABLED"; - attribute GSR of FF_302 : label is "ENABLED"; - attribute GSR of FF_301 : label is "ENABLED"; - attribute GSR of FF_300 : label is "ENABLED"; - attribute GSR of FF_299 : label is "ENABLED"; - attribute GSR of FF_298 : label is "ENABLED"; - attribute GSR of FF_297 : label is "ENABLED"; - attribute GSR of FF_296 : label is "ENABLED"; - attribute GSR of FF_295 : label is "ENABLED"; - attribute GSR of FF_294 : label is "ENABLED"; - attribute GSR of FF_293 : label is "ENABLED"; - attribute GSR of FF_292 : label is "ENABLED"; - attribute GSR of FF_291 : label is "ENABLED"; - attribute GSR of FF_290 : label is "ENABLED"; - attribute GSR of FF_289 : label is "ENABLED"; - attribute GSR of FF_288 : label is "ENABLED"; - attribute GSR of FF_287 : label is "ENABLED"; - attribute GSR of FF_286 : label is "ENABLED"; - attribute GSR of FF_285 : label is "ENABLED"; - attribute GSR of FF_284 : label is "ENABLED"; - attribute GSR of FF_283 : label is "ENABLED"; - attribute GSR of FF_282 : label is "ENABLED"; - attribute GSR of FF_281 : label is "ENABLED"; - attribute GSR of FF_280 : label is "ENABLED"; - attribute GSR of FF_279 : label is "ENABLED"; - attribute GSR of FF_278 : label is "ENABLED"; - attribute GSR of FF_277 : label is "ENABLED"; - attribute GSR of FF_276 : label is "ENABLED"; - attribute GSR of FF_275 : label is "ENABLED"; - attribute GSR of FF_274 : label is "ENABLED"; - attribute GSR of FF_273 : label is "ENABLED"; - attribute GSR of FF_272 : label is "ENABLED"; - attribute GSR of FF_271 : label is "ENABLED"; - attribute GSR of FF_270 : label is "ENABLED"; - attribute GSR of FF_269 : label is "ENABLED"; - attribute GSR of FF_268 : label is "ENABLED"; - attribute GSR of FF_267 : label is "ENABLED"; - attribute GSR of FF_266 : label is "ENABLED"; - attribute GSR of FF_265 : label is "ENABLED"; - attribute GSR of FF_264 : label is "ENABLED"; - attribute GSR of FF_263 : label is "ENABLED"; - attribute GSR of FF_262 : label is "ENABLED"; - attribute GSR of FF_261 : label is "ENABLED"; - attribute GSR of FF_260 : label is "ENABLED"; - attribute GSR of FF_259 : label is "ENABLED"; - attribute GSR of FF_258 : label is "ENABLED"; - attribute GSR of FF_257 : label is "ENABLED"; - attribute GSR of FF_256 : label is "ENABLED"; - attribute GSR of FF_255 : label is "ENABLED"; - attribute GSR of FF_254 : label is "ENABLED"; - attribute GSR of FF_253 : label is "ENABLED"; - attribute GSR of FF_252 : label is "ENABLED"; - attribute GSR of FF_251 : label is "ENABLED"; - attribute GSR of FF_250 : label is "ENABLED"; - attribute GSR of FF_249 : label is "ENABLED"; - attribute GSR of FF_248 : label is "ENABLED"; - attribute GSR of FF_247 : label is "ENABLED"; - attribute GSR of FF_246 : label is "ENABLED"; - attribute GSR of FF_245 : label is "ENABLED"; - attribute GSR of FF_244 : label is "ENABLED"; - attribute GSR of FF_243 : label is "ENABLED"; - attribute GSR of FF_242 : label is "ENABLED"; - attribute GSR of FF_241 : label is "ENABLED"; - attribute GSR of FF_240 : label is "ENABLED"; - attribute GSR of FF_239 : label is "ENABLED"; - attribute GSR of FF_238 : label is "ENABLED"; - attribute GSR of FF_237 : label is "ENABLED"; - attribute GSR of FF_236 : label is "ENABLED"; - attribute GSR of FF_235 : label is "ENABLED"; - attribute GSR of FF_234 : label is "ENABLED"; - attribute GSR of FF_233 : label is "ENABLED"; - attribute GSR of FF_232 : label is "ENABLED"; - attribute GSR of FF_231 : label is "ENABLED"; - attribute GSR of FF_230 : label is "ENABLED"; - attribute GSR of FF_229 : label is "ENABLED"; - attribute GSR of FF_228 : label is "ENABLED"; - attribute GSR of FF_227 : label is "ENABLED"; - attribute GSR of FF_226 : label is "ENABLED"; - attribute GSR of FF_225 : label is "ENABLED"; - attribute GSR of FF_224 : label is "ENABLED"; - attribute GSR of FF_223 : label is "ENABLED"; - attribute GSR of FF_222 : label is "ENABLED"; - attribute GSR of FF_221 : label is "ENABLED"; - attribute GSR of FF_220 : label is "ENABLED"; - attribute GSR of FF_219 : label is "ENABLED"; - attribute GSR of FF_218 : label is "ENABLED"; - attribute GSR of FF_217 : label is "ENABLED"; - attribute GSR of FF_216 : label is "ENABLED"; - attribute GSR of FF_215 : label is "ENABLED"; - attribute GSR of FF_214 : label is "ENABLED"; - attribute GSR of FF_213 : label is "ENABLED"; - attribute GSR of FF_212 : label is "ENABLED"; - attribute GSR of FF_211 : label is "ENABLED"; - attribute GSR of FF_210 : label is "ENABLED"; - attribute GSR of FF_209 : label is "ENABLED"; - attribute GSR of FF_208 : label is "ENABLED"; - attribute GSR of FF_207 : label is "ENABLED"; - attribute GSR of FF_206 : label is "ENABLED"; - attribute GSR of FF_205 : label is "ENABLED"; - attribute GSR of FF_204 : label is "ENABLED"; - attribute GSR of FF_203 : label is "ENABLED"; - attribute GSR of FF_202 : label is "ENABLED"; - attribute GSR of FF_201 : label is "ENABLED"; - attribute GSR of FF_200 : label is "ENABLED"; - attribute GSR of FF_199 : label is "ENABLED"; - attribute GSR of FF_198 : label is "ENABLED"; - attribute GSR of FF_197 : label is "ENABLED"; - attribute GSR of FF_196 : label is "ENABLED"; - attribute GSR of FF_195 : label is "ENABLED"; - attribute GSR of FF_194 : label is "ENABLED"; - attribute GSR of FF_193 : label is "ENABLED"; - attribute GSR of FF_192 : label is "ENABLED"; - attribute GSR of FF_191 : label is "ENABLED"; - attribute GSR of FF_190 : label is "ENABLED"; - attribute GSR of FF_189 : label is "ENABLED"; - attribute GSR of FF_188 : label is "ENABLED"; - attribute GSR of FF_187 : label is "ENABLED"; - attribute GSR of FF_186 : label is "ENABLED"; - attribute GSR of FF_185 : label is "ENABLED"; - attribute GSR of FF_184 : label is "ENABLED"; - attribute GSR of FF_183 : label is "ENABLED"; - attribute GSR of FF_182 : label is "ENABLED"; - attribute GSR of FF_181 : label is "ENABLED"; - attribute GSR of FF_180 : label is "ENABLED"; - attribute GSR of FF_179 : label is "ENABLED"; - attribute GSR of FF_178 : label is "ENABLED"; - attribute GSR of FF_177 : label is "ENABLED"; - attribute GSR of FF_176 : label is "ENABLED"; - attribute GSR of FF_175 : label is "ENABLED"; - attribute GSR of FF_174 : label is "ENABLED"; - attribute GSR of FF_173 : label is "ENABLED"; - attribute GSR of FF_172 : label is "ENABLED"; - attribute GSR of FF_171 : label is "ENABLED"; - attribute GSR of FF_170 : label is "ENABLED"; - attribute GSR of FF_169 : label is "ENABLED"; - attribute GSR of FF_168 : label is "ENABLED"; - attribute GSR of FF_167 : label is "ENABLED"; - attribute GSR of FF_166 : label is "ENABLED"; - attribute GSR of FF_165 : label is "ENABLED"; - attribute GSR of FF_164 : label is "ENABLED"; - attribute GSR of FF_163 : label is "ENABLED"; - attribute GSR of FF_162 : label is "ENABLED"; - attribute GSR of FF_161 : label is "ENABLED"; - attribute GSR of FF_160 : label is "ENABLED"; - attribute GSR of FF_159 : label is "ENABLED"; - attribute GSR of FF_158 : label is "ENABLED"; - attribute GSR of FF_157 : label is "ENABLED"; - attribute GSR of FF_156 : label is "ENABLED"; - attribute GSR of FF_155 : label is "ENABLED"; - attribute GSR of FF_154 : label is "ENABLED"; - attribute GSR of FF_153 : label is "ENABLED"; - attribute GSR of FF_152 : label is "ENABLED"; - attribute GSR of FF_151 : label is "ENABLED"; - attribute GSR of FF_150 : label is "ENABLED"; - attribute GSR of FF_149 : label is "ENABLED"; - attribute GSR of FF_148 : label is "ENABLED"; - attribute GSR of FF_147 : label is "ENABLED"; - attribute GSR of FF_146 : label is "ENABLED"; - attribute GSR of FF_145 : label is "ENABLED"; - attribute GSR of FF_144 : label is "ENABLED"; - attribute GSR of FF_143 : label is "ENABLED"; - attribute GSR of FF_142 : label is "ENABLED"; - attribute GSR of FF_141 : label is "ENABLED"; - attribute GSR of FF_140 : label is "ENABLED"; - attribute GSR of FF_139 : label is "ENABLED"; - attribute GSR of FF_138 : label is "ENABLED"; - attribute GSR of FF_137 : label is "ENABLED"; - attribute GSR of FF_136 : label is "ENABLED"; - attribute GSR of FF_135 : label is "ENABLED"; - attribute GSR of FF_134 : label is "ENABLED"; - attribute GSR of FF_133 : label is "ENABLED"; - attribute GSR of FF_132 : label is "ENABLED"; - attribute GSR of FF_131 : label is "ENABLED"; - attribute GSR of FF_130 : label is "ENABLED"; - attribute GSR of FF_129 : label is "ENABLED"; - attribute GSR of FF_128 : label is "ENABLED"; - attribute GSR of FF_127 : label is "ENABLED"; - attribute GSR of FF_126 : label is "ENABLED"; - attribute GSR of FF_125 : label is "ENABLED"; - attribute GSR of FF_124 : label is "ENABLED"; - attribute GSR of FF_123 : label is "ENABLED"; - attribute GSR of FF_122 : label is "ENABLED"; - attribute GSR of FF_121 : label is "ENABLED"; - attribute GSR of FF_120 : label is "ENABLED"; - attribute GSR of FF_119 : label is "ENABLED"; - attribute GSR of FF_118 : label is "ENABLED"; - attribute GSR of FF_117 : label is "ENABLED"; - attribute GSR of FF_116 : label is "ENABLED"; - attribute GSR of FF_115 : label is "ENABLED"; - attribute GSR of FF_114 : label is "ENABLED"; - attribute GSR of FF_113 : label is "ENABLED"; - attribute GSR of FF_112 : label is "ENABLED"; - attribute GSR of FF_111 : label is "ENABLED"; - attribute GSR of FF_110 : label is "ENABLED"; - attribute GSR of FF_109 : label is "ENABLED"; - attribute GSR of FF_108 : label is "ENABLED"; - attribute GSR of FF_107 : label is "ENABLED"; - attribute GSR of FF_106 : label is "ENABLED"; - attribute GSR of FF_105 : label is "ENABLED"; - attribute GSR of FF_104 : label is "ENABLED"; - attribute GSR of FF_103 : label is "ENABLED"; - attribute GSR of FF_102 : label is "ENABLED"; - attribute GSR of FF_101 : label is "ENABLED"; - attribute GSR of FF_100 : label is "ENABLED"; - attribute GSR of FF_99 : label is "ENABLED"; - attribute GSR of FF_98 : label is "ENABLED"; - attribute GSR of FF_97 : label is "ENABLED"; - attribute GSR of FF_96 : label is "ENABLED"; - attribute GSR of FF_95 : label is "ENABLED"; - attribute GSR of FF_94 : label is "ENABLED"; - attribute GSR of FF_93 : label is "ENABLED"; - attribute GSR of FF_92 : label is "ENABLED"; - attribute GSR of FF_91 : label is "ENABLED"; - attribute GSR of FF_90 : label is "ENABLED"; - attribute GSR of FF_89 : label is "ENABLED"; - attribute GSR of FF_88 : label is "ENABLED"; - attribute GSR of FF_87 : label is "ENABLED"; - attribute GSR of FF_86 : label is "ENABLED"; - attribute GSR of FF_85 : label is "ENABLED"; - attribute GSR of FF_84 : label is "ENABLED"; - attribute GSR of FF_83 : label is "ENABLED"; - attribute GSR of FF_82 : label is "ENABLED"; - attribute GSR of FF_81 : label is "ENABLED"; - attribute GSR of FF_80 : label is "ENABLED"; - attribute GSR of FF_79 : label is "ENABLED"; - attribute GSR of FF_78 : label is "ENABLED"; - attribute GSR of FF_77 : label is "ENABLED"; - attribute GSR of FF_76 : label is "ENABLED"; - attribute GSR of FF_75 : label is "ENABLED"; - attribute GSR of FF_74 : label is "ENABLED"; - attribute GSR of FF_73 : label is "ENABLED"; - attribute GSR of FF_72 : label is "ENABLED"; - attribute GSR of FF_71 : label is "ENABLED"; - attribute GSR of FF_70 : label is "ENABLED"; - attribute GSR of FF_69 : label is "ENABLED"; - attribute GSR of FF_68 : label is "ENABLED"; - attribute GSR of FF_67 : label is "ENABLED"; - attribute GSR of FF_66 : label is "ENABLED"; - attribute GSR of FF_65 : label is "ENABLED"; - attribute GSR of FF_64 : label is "ENABLED"; - attribute GSR of FF_63 : label is "ENABLED"; - attribute GSR of FF_62 : label is "ENABLED"; - attribute GSR of FF_61 : label is "ENABLED"; - attribute GSR of FF_60 : label is "ENABLED"; - attribute GSR of FF_59 : label is "ENABLED"; - attribute GSR of FF_58 : label is "ENABLED"; - attribute GSR of FF_57 : label is "ENABLED"; - attribute GSR of FF_56 : label is "ENABLED"; - attribute GSR of FF_55 : label is "ENABLED"; - attribute GSR of FF_54 : label is "ENABLED"; - attribute GSR of FF_53 : label is "ENABLED"; - attribute GSR of FF_52 : label is "ENABLED"; - attribute GSR of FF_51 : label is "ENABLED"; - attribute GSR of FF_50 : label is "ENABLED"; - attribute GSR of FF_49 : label is "ENABLED"; - attribute GSR of FF_48 : label is "ENABLED"; - attribute GSR of FF_47 : label is "ENABLED"; - attribute GSR of FF_46 : label is "ENABLED"; - attribute GSR of FF_45 : label is "ENABLED"; - attribute GSR of FF_44 : label is "ENABLED"; - attribute GSR of FF_43 : label is "ENABLED"; - attribute GSR of FF_42 : label is "ENABLED"; - attribute GSR of FF_41 : label is "ENABLED"; - attribute GSR of FF_40 : label is "ENABLED"; - attribute GSR of FF_39 : label is "ENABLED"; - attribute GSR of FF_38 : label is "ENABLED"; - attribute GSR of FF_37 : label is "ENABLED"; - attribute GSR of FF_36 : label is "ENABLED"; - attribute GSR of FF_35 : label is "ENABLED"; - attribute GSR of FF_34 : label is "ENABLED"; - attribute GSR of FF_33 : label is "ENABLED"; - attribute GSR of FF_32 : label is "ENABLED"; - attribute GSR of FF_31 : label is "ENABLED"; - attribute GSR of FF_30 : label is "ENABLED"; - attribute GSR of FF_29 : label is "ENABLED"; - attribute GSR of FF_28 : label is "ENABLED"; - attribute GSR of FF_27 : label is "ENABLED"; - attribute GSR of FF_26 : label is "ENABLED"; - attribute GSR of FF_25 : label is "ENABLED"; - attribute GSR of FF_24 : label is "ENABLED"; - attribute GSR of FF_23 : label is "ENABLED"; - attribute GSR of FF_22 : label is "ENABLED"; - attribute GSR of FF_21 : label is "ENABLED"; - attribute GSR of FF_20 : label is "ENABLED"; - attribute GSR of FF_19 : label is "ENABLED"; - attribute GSR of FF_18 : label is "ENABLED"; - attribute GSR of FF_17 : label is "ENABLED"; - attribute GSR of FF_16 : label is "ENABLED"; - attribute GSR of FF_15 : label is "ENABLED"; - attribute GSR of FF_14 : label is "ENABLED"; - attribute GSR of FF_13 : label is "ENABLED"; - attribute GSR of FF_12 : label is "ENABLED"; - attribute GSR of FF_11 : label is "ENABLED"; - attribute GSR of FF_10 : label is "ENABLED"; - attribute GSR of FF_9 : label is "ENABLED"; - attribute GSR of FF_8 : label is "ENABLED"; - attribute GSR of FF_7 : label is "ENABLED"; - attribute GSR of FF_6 : label is "ENABLED"; - attribute GSR of FF_5 : label is "ENABLED"; - attribute GSR of FF_4 : label is "ENABLED"; - attribute GSR of FF_3 : label is "ENABLED"; - attribute GSR of FF_2 : label is "ENABLED"; - attribute GSR of FF_1 : label is "ENABLED"; - attribute GSR of FF_0 : label is "ENABLED"; - attribute syn_keep : boolean; - -begin - - FF_303 : FD1P3DX - port map (D => tsum(303), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(303)); - FF_302 : FD1P3DX - port map (D => tsum(302), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(302)); - FF_301 : FD1P3DX - port map (D => tsum(301), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(301)); - FF_300 : FD1P3DX - port map (D => tsum(300), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(300)); - FF_299 : FD1P3DX - port map (D => tsum(299), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(299)); - FF_298 : FD1P3DX - port map (D => tsum(298), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(298)); - FF_297 : FD1P3DX - port map (D => tsum(297), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(297)); - FF_296 : FD1P3DX - port map (D => tsum(296), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(296)); - FF_295 : FD1P3DX - port map (D => tsum(295), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(295)); - FF_294 : FD1P3DX - port map (D => tsum(294), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(294)); - FF_293 : FD1P3DX - port map (D => tsum(293), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(293)); - FF_292 : FD1P3DX - port map (D => tsum(292), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(292)); - FF_291 : FD1P3DX - port map (D => tsum(291), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(291)); - FF_290 : FD1P3DX - port map (D => tsum(290), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(290)); - FF_289 : FD1P3DX - port map (D => tsum(289), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(289)); - FF_288 : FD1P3DX - port map (D => tsum(288), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(288)); - FF_287 : FD1P3DX - port map (D => tsum(287), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(287)); - FF_286 : FD1P3DX - port map (D => tsum(286), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(286)); - FF_285 : FD1P3DX - port map (D => tsum(285), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(285)); - FF_284 : FD1P3DX - port map (D => tsum(284), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(284)); - FF_283 : FD1P3DX - port map (D => tsum(283), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(283)); - FF_282 : FD1P3DX - port map (D => tsum(282), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(282)); - FF_281 : FD1P3DX - port map (D => tsum(281), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(281)); - FF_280 : FD1P3DX - port map (D => tsum(280), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(280)); - FF_279 : FD1P3DX - port map (D => tsum(279), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(279)); - FF_278 : FD1P3DX - port map (D => tsum(278), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(278)); - FF_277 : FD1P3DX - port map (D => tsum(277), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(277)); - FF_276 : FD1P3DX - port map (D => tsum(276), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(276)); - FF_275 : FD1P3DX - port map (D => tsum(275), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(275)); - FF_274 : FD1P3DX - port map (D => tsum(274), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(274)); - FF_273 : FD1P3DX - port map (D => tsum(273), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(273)); - FF_272 : FD1P3DX - port map (D => tsum(272), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(272)); - FF_271 : FD1P3DX - port map (D => tsum(271), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(271)); - FF_270 : FD1P3DX - port map (D => tsum(270), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(270)); - FF_269 : FD1P3DX - port map (D => tsum(269), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(269)); - FF_268 : FD1P3DX - port map (D => tsum(268), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(268)); - FF_267 : FD1P3DX - port map (D => tsum(267), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(267)); - FF_266 : FD1P3DX - port map (D => tsum(266), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(266)); - FF_265 : FD1P3DX - port map (D => tsum(265), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(265)); - FF_264 : FD1P3DX - port map (D => tsum(264), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(264)); - FF_263 : FD1P3DX - port map (D => tsum(263), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(263)); - FF_262 : FD1P3DX - port map (D => tsum(262), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(262)); - FF_261 : FD1P3DX - port map (D => tsum(261), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(261)); - FF_260 : FD1P3DX - port map (D => tsum(260), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(260)); - FF_259 : FD1P3DX - port map (D => tsum(259), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(259)); - FF_258 : FD1P3DX - port map (D => tsum(258), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(258)); - FF_257 : FD1P3DX - port map (D => tsum(257), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(257)); - FF_256 : FD1P3DX - port map (D => tsum(256), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(256)); - FF_255 : FD1P3DX - port map (D => tsum(255), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(255)); - FF_254 : FD1P3DX - port map (D => tsum(254), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(254)); - FF_253 : FD1P3DX - port map (D => tsum(253), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(253)); - FF_252 : FD1P3DX - port map (D => tsum(252), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(252)); - FF_251 : FD1P3DX - port map (D => tsum(251), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(251)); - FF_250 : FD1P3DX - port map (D => tsum(250), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(250)); - FF_249 : FD1P3DX - port map (D => tsum(249), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(249)); - FF_248 : FD1P3DX - port map (D => tsum(248), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(248)); - FF_247 : FD1P3DX - port map (D => tsum(247), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(247)); - FF_246 : FD1P3DX - port map (D => tsum(246), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(246)); - FF_245 : FD1P3DX - port map (D => tsum(245), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(245)); - FF_244 : FD1P3DX - port map (D => tsum(244), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(244)); - FF_243 : FD1P3DX - port map (D => tsum(243), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(243)); - FF_242 : FD1P3DX - port map (D => tsum(242), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(242)); - FF_241 : FD1P3DX - port map (D => tsum(241), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(241)); - FF_240 : FD1P3DX - port map (D => tsum(240), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(240)); - FF_239 : FD1P3DX - port map (D => tsum(239), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(239)); - FF_238 : FD1P3DX - port map (D => tsum(238), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(238)); - FF_237 : FD1P3DX - port map (D => tsum(237), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(237)); - FF_236 : FD1P3DX - port map (D => tsum(236), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(236)); - FF_235 : FD1P3DX - port map (D => tsum(235), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(235)); - FF_234 : FD1P3DX - port map (D => tsum(234), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(234)); - FF_233 : FD1P3DX - port map (D => tsum(233), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(233)); - FF_232 : FD1P3DX - port map (D => tsum(232), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(232)); - FF_231 : FD1P3DX - port map (D => tsum(231), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(231)); - FF_230 : FD1P3DX - port map (D => tsum(230), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(230)); - FF_229 : FD1P3DX - port map (D => tsum(229), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(229)); - FF_228 : FD1P3DX - port map (D => tsum(228), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(228)); - FF_227 : FD1P3DX - port map (D => tsum(227), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(227)); - FF_226 : FD1P3DX - port map (D => tsum(226), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(226)); - FF_225 : FD1P3DX - port map (D => tsum(225), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(225)); - FF_224 : FD1P3DX - port map (D => tsum(224), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(224)); - FF_223 : FD1P3DX - port map (D => tsum(223), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(223)); - FF_222 : FD1P3DX - port map (D => tsum(222), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(222)); - FF_221 : FD1P3DX - port map (D => tsum(221), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(221)); - FF_220 : FD1P3DX - port map (D => tsum(220), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(220)); - FF_219 : FD1P3DX - port map (D => tsum(219), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(219)); - FF_218 : FD1P3DX - port map (D => tsum(218), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(218)); - FF_217 : FD1P3DX - port map (D => tsum(217), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(217)); - FF_216 : FD1P3DX - port map (D => tsum(216), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(216)); - FF_215 : FD1P3DX - port map (D => tsum(215), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(215)); - FF_214 : FD1P3DX - port map (D => tsum(214), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(214)); - FF_213 : FD1P3DX - port map (D => tsum(213), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(213)); - FF_212 : FD1P3DX - port map (D => tsum(212), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(212)); - FF_211 : FD1P3DX - port map (D => tsum(211), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(211)); - FF_210 : FD1P3DX - port map (D => tsum(210), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(210)); - FF_209 : FD1P3DX - port map (D => tsum(209), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(209)); - FF_208 : FD1P3DX - port map (D => tsum(208), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(208)); - FF_207 : FD1P3DX - port map (D => tsum(207), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(207)); - FF_206 : FD1P3DX - port map (D => tsum(206), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(206)); - FF_205 : FD1P3DX - port map (D => tsum(205), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(205)); - FF_204 : FD1P3DX - port map (D => tsum(204), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(204)); - FF_203 : FD1P3DX - port map (D => tsum(203), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(203)); - FF_202 : FD1P3DX - port map (D => tsum(202), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(202)); - FF_201 : FD1P3DX - port map (D => tsum(201), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(201)); - FF_200 : FD1P3DX - port map (D => tsum(200), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(200)); - FF_199 : FD1P3DX - port map (D => tsum(199), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(199)); - FF_198 : FD1P3DX - port map (D => tsum(198), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(198)); - FF_197 : FD1P3DX - port map (D => tsum(197), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(197)); - FF_196 : FD1P3DX - port map (D => tsum(196), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(196)); - FF_195 : FD1P3DX - port map (D => tsum(195), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(195)); - FF_194 : FD1P3DX - port map (D => tsum(194), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(194)); - FF_193 : FD1P3DX - port map (D => tsum(193), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(193)); - FF_192 : FD1P3DX - port map (D => tsum(192), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(192)); - FF_191 : FD1P3DX - port map (D => tsum(191), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(191)); - FF_190 : FD1P3DX - port map (D => tsum(190), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(190)); - FF_189 : FD1P3DX - port map (D => tsum(189), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(189)); - FF_188 : FD1P3DX - port map (D => tsum(188), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(188)); - FF_187 : FD1P3DX - port map (D => tsum(187), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(187)); - FF_186 : FD1P3DX - port map (D => tsum(186), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(186)); - FF_185 : FD1P3DX - port map (D => tsum(185), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(185)); - FF_184 : FD1P3DX - port map (D => tsum(184), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(184)); - FF_183 : FD1P3DX - port map (D => tsum(183), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(183)); - FF_182 : FD1P3DX - port map (D => tsum(182), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(182)); - FF_181 : FD1P3DX - port map (D => tsum(181), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(181)); - FF_180 : FD1P3DX - port map (D => tsum(180), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(180)); - FF_179 : FD1P3DX - port map (D => tsum(179), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(179)); - FF_178 : FD1P3DX - port map (D => tsum(178), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(178)); - FF_177 : FD1P3DX - port map (D => tsum(177), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(177)); - FF_176 : FD1P3DX - port map (D => tsum(176), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(176)); - FF_175 : FD1P3DX - port map (D => tsum(175), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(175)); - FF_174 : FD1P3DX - port map (D => tsum(174), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(174)); - FF_173 : FD1P3DX - port map (D => tsum(173), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(173)); - FF_172 : FD1P3DX - port map (D => tsum(172), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(172)); - FF_171 : FD1P3DX - port map (D => tsum(171), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(171)); - FF_170 : FD1P3DX - port map (D => tsum(170), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(170)); - FF_169 : FD1P3DX - port map (D => tsum(169), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(169)); - FF_168 : FD1P3DX - port map (D => tsum(168), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(168)); - FF_167 : FD1P3DX - port map (D => tsum(167), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(167)); - FF_166 : FD1P3DX - port map (D => tsum(166), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(166)); - FF_165 : FD1P3DX - port map (D => tsum(165), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(165)); - FF_164 : FD1P3DX - port map (D => tsum(164), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(164)); - FF_163 : FD1P3DX - port map (D => tsum(163), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(163)); - FF_162 : FD1P3DX - port map (D => tsum(162), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(162)); - FF_161 : FD1P3DX - port map (D => tsum(161), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(161)); - FF_160 : FD1P3DX - port map (D => tsum(160), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(160)); - FF_159 : FD1P3DX - port map (D => tsum(159), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(159)); - FF_158 : FD1P3DX - port map (D => tsum(158), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(158)); - FF_157 : FD1P3DX - port map (D => tsum(157), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(157)); - FF_156 : FD1P3DX - port map (D => tsum(156), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(156)); - FF_155 : FD1P3DX - port map (D => tsum(155), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(155)); - FF_154 : FD1P3DX - port map (D => tsum(154), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(154)); - FF_153 : FD1P3DX - port map (D => tsum(153), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(153)); - FF_152 : FD1P3DX - port map (D => tsum(152), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(152)); - FF_151 : FD1P3DX - port map (D => tsum(151), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(151)); - FF_150 : FD1P3DX - port map (D => tsum(150), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(150)); - FF_149 : FD1P3DX - port map (D => tsum(149), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(149)); - FF_148 : FD1P3DX - port map (D => tsum(148), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(148)); - FF_147 : FD1P3DX - port map (D => tsum(147), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(147)); - FF_146 : FD1P3DX - port map (D => tsum(146), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(146)); - FF_145 : FD1P3DX - port map (D => tsum(145), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(145)); - FF_144 : FD1P3DX - port map (D => tsum(144), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(144)); - FF_143 : FD1P3DX - port map (D => tsum(143), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(143)); - FF_142 : FD1P3DX - port map (D => tsum(142), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(142)); - FF_141 : FD1P3DX - port map (D => tsum(141), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(141)); - FF_140 : FD1P3DX - port map (D => tsum(140), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(140)); - FF_139 : FD1P3DX - port map (D => tsum(139), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(139)); - FF_138 : FD1P3DX - port map (D => tsum(138), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(138)); - FF_137 : FD1P3DX - port map (D => tsum(137), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(137)); - FF_136 : FD1P3DX - port map (D => tsum(136), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(136)); - FF_135 : FD1P3DX - port map (D => tsum(135), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(135)); - FF_134 : FD1P3DX - port map (D => tsum(134), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(134)); - FF_133 : FD1P3DX - port map (D => tsum(133), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(133)); - FF_132 : FD1P3DX - port map (D => tsum(132), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(132)); - FF_131 : FD1P3DX - port map (D => tsum(131), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(131)); - FF_130 : FD1P3DX - port map (D => tsum(130), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(130)); - FF_129 : FD1P3DX - port map (D => tsum(129), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(129)); - FF_128 : FD1P3DX - port map (D => tsum(128), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(128)); - FF_127 : FD1P3DX - port map (D => tsum(127), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(127)); - FF_126 : FD1P3DX - port map (D => tsum(126), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(126)); - FF_125 : FD1P3DX - port map (D => tsum(125), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(125)); - FF_124 : FD1P3DX - port map (D => tsum(124), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(124)); - FF_123 : FD1P3DX - port map (D => tsum(123), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(123)); - FF_122 : FD1P3DX - port map (D => tsum(122), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(122)); - FF_121 : FD1P3DX - port map (D => tsum(121), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(121)); - FF_120 : FD1P3DX - port map (D => tsum(120), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(120)); - FF_119 : FD1P3DX - port map (D => tsum(119), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(119)); - FF_118 : FD1P3DX - port map (D => tsum(118), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(118)); - FF_117 : FD1P3DX - port map (D => tsum(117), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(117)); - FF_116 : FD1P3DX - port map (D => tsum(116), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(116)); - FF_115 : FD1P3DX - port map (D => tsum(115), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(115)); - FF_114 : FD1P3DX - port map (D => tsum(114), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(114)); - FF_113 : FD1P3DX - port map (D => tsum(113), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(113)); - FF_112 : FD1P3DX - port map (D => tsum(112), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(112)); - FF_111 : FD1P3DX - port map (D => tsum(111), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(111)); - FF_110 : FD1P3DX - port map (D => tsum(110), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(110)); - FF_109 : FD1P3DX - port map (D => tsum(109), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(109)); - FF_108 : FD1P3DX - port map (D => tsum(108), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(108)); - FF_107 : FD1P3DX - port map (D => tsum(107), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(107)); - FF_106 : FD1P3DX - port map (D => tsum(106), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(106)); - FF_105 : FD1P3DX - port map (D => tsum(105), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(105)); - FF_104 : FD1P3DX - port map (D => tsum(104), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(104)); - FF_103 : FD1P3DX - port map (D => tsum(103), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(103)); - FF_102 : FD1P3DX - port map (D => tsum(102), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(102)); - FF_101 : FD1P3DX - port map (D => tsum(101), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(101)); - FF_100 : FD1P3DX - port map (D => tsum(100), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(100)); - FF_99 : FD1P3DX - port map (D => tsum(99), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(99)); - FF_98 : FD1P3DX - port map (D => tsum(98), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(98)); - FF_97 : FD1P3DX - port map (D => tsum(97), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(97)); - FF_96 : FD1P3DX - port map (D => tsum(96), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(96)); - FF_95 : FD1P3DX - port map (D => tsum(95), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(95)); - FF_94 : FD1P3DX - port map (D => tsum(94), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(94)); - FF_93 : FD1P3DX - port map (D => tsum(93), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(93)); - FF_92 : FD1P3DX - port map (D => tsum(92), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(92)); - FF_91 : FD1P3DX - port map (D => tsum(91), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(91)); - FF_90 : FD1P3DX - port map (D => tsum(90), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(90)); - FF_89 : FD1P3DX - port map (D => tsum(89), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(89)); - FF_88 : FD1P3DX - port map (D => tsum(88), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(88)); - FF_87 : FD1P3DX - port map (D => tsum(87), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(87)); - FF_86 : FD1P3DX - port map (D => tsum(86), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(86)); - FF_85 : FD1P3DX - port map (D => tsum(85), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(85)); - FF_84 : FD1P3DX - port map (D => tsum(84), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(84)); - FF_83 : FD1P3DX - port map (D => tsum(83), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(83)); - FF_82 : FD1P3DX - port map (D => tsum(82), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(82)); - FF_81 : FD1P3DX - port map (D => tsum(81), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(81)); - FF_80 : FD1P3DX - port map (D => tsum(80), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(80)); - FF_79 : FD1P3DX - port map (D => tsum(79), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(79)); - FF_78 : FD1P3DX - port map (D => tsum(78), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(78)); - FF_77 : FD1P3DX - port map (D => tsum(77), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(77)); - FF_76 : FD1P3DX - port map (D => tsum(76), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(76)); - FF_75 : FD1P3DX - port map (D => tsum(75), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(75)); - FF_74 : FD1P3DX - port map (D => tsum(74), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(74)); - FF_73 : FD1P3DX - port map (D => tsum(73), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(73)); - FF_72 : FD1P3DX - port map (D => tsum(72), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(72)); - FF_71 : FD1P3DX - port map (D => tsum(71), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(71)); - FF_70 : FD1P3DX - port map (D => tsum(70), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(70)); - FF_69 : FD1P3DX - port map (D => tsum(69), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(69)); - FF_68 : FD1P3DX - port map (D => tsum(68), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(68)); - FF_67 : FD1P3DX - port map (D => tsum(67), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(67)); - FF_66 : FD1P3DX - port map (D => tsum(66), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(66)); - FF_65 : FD1P3DX - port map (D => tsum(65), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(65)); - FF_64 : FD1P3DX - port map (D => tsum(64), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(64)); - FF_63 : FD1P3DX - port map (D => tsum(63), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(63)); - FF_62 : FD1P3DX - port map (D => tsum(62), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(62)); - FF_61 : FD1P3DX - port map (D => tsum(61), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(61)); - FF_60 : FD1P3DX - port map (D => tsum(60), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(60)); - FF_59 : FD1P3DX - port map (D => tsum(59), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(59)); - FF_58 : FD1P3DX - port map (D => tsum(58), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(58)); - FF_57 : FD1P3DX - port map (D => tsum(57), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(57)); - FF_56 : FD1P3DX - port map (D => tsum(56), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(56)); - FF_55 : FD1P3DX - port map (D => tsum(55), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(55)); - FF_54 : FD1P3DX - port map (D => tsum(54), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(54)); - FF_53 : FD1P3DX - port map (D => tsum(53), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(53)); - FF_52 : FD1P3DX - port map (D => tsum(52), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(52)); - FF_51 : FD1P3DX - port map (D => tsum(51), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(51)); - FF_50 : FD1P3DX - port map (D => tsum(50), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(50)); - FF_49 : FD1P3DX - port map (D => tsum(49), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(49)); - FF_48 : FD1P3DX - port map (D => tsum(48), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(48)); - FF_47 : FD1P3DX - port map (D => tsum(47), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(47)); - FF_46 : FD1P3DX - port map (D => tsum(46), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(46)); - FF_45 : FD1P3DX - port map (D => tsum(45), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(45)); - FF_44 : FD1P3DX - port map (D => tsum(44), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(44)); - FF_43 : FD1P3DX - port map (D => tsum(43), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(43)); - FF_42 : FD1P3DX - port map (D => tsum(42), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(42)); - FF_41 : FD1P3DX - port map (D => tsum(41), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(41)); - FF_40 : FD1P3DX - port map (D => tsum(40), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(40)); - FF_39 : FD1P3DX - port map (D => tsum(39), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(39)); - FF_38 : FD1P3DX - port map (D => tsum(38), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(38)); - FF_37 : FD1P3DX - port map (D => tsum(37), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(37)); - FF_36 : FD1P3DX - port map (D => tsum(36), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(36)); - FF_35 : FD1P3DX - port map (D => tsum(35), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(35)); - FF_34 : FD1P3DX - port map (D => tsum(34), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(34)); - FF_33 : FD1P3DX - port map (D => tsum(33), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(33)); - FF_32 : FD1P3DX - port map (D => tsum(32), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(32)); - FF_31 : FD1P3DX - port map (D => tsum(31), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(31)); - FF_30 : FD1P3DX - port map (D => tsum(30), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(30)); - FF_29 : FD1P3DX - port map (D => tsum(29), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(29)); - FF_28 : FD1P3DX - port map (D => tsum(28), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(28)); - FF_27 : FD1P3DX - port map (D => tsum(27), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(27)); - FF_26 : FD1P3DX - port map (D => tsum(26), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(26)); - FF_25 : FD1P3DX - port map (D => tsum(25), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(25)); - FF_24 : FD1P3DX - port map (D => tsum(24), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(24)); - FF_23 : FD1P3DX - port map (D => tsum(23), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(23)); - FF_22 : FD1P3DX - port map (D => tsum(22), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(22)); - FF_21 : FD1P3DX - port map (D => tsum(21), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(21)); - FF_20 : FD1P3DX - port map (D => tsum(20), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(20)); - FF_19 : FD1P3DX - port map (D => tsum(19), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(19)); - FF_18 : FD1P3DX - port map (D => tsum(18), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(18)); - FF_17 : FD1P3DX - port map (D => tsum(17), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(17)); - FF_16 : FD1P3DX - port map (D => tsum(16), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(16)); - FF_15 : FD1P3DX - port map (D => tsum(15), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(15)); - FF_14 : FD1P3DX - port map (D => tsum(14), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(14)); - FF_13 : FD1P3DX - port map (D => tsum(13), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(13)); - FF_12 : FD1P3DX - port map (D => tsum(12), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(12)); - FF_11 : FD1P3DX - port map (D => tsum(11), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(11)); - FF_10 : FD1P3DX - port map (D => tsum(10), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(10)); - FF_9 : FD1P3DX - port map (D => tsum(9), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(9)); - FF_8 : FD1P3DX - port map (D => tsum(8), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(8)); - FF_7 : FD1P3DX - port map (D => tsum(7), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(7)); - FF_6 : FD1P3DX - port map (D => tsum(6), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(6)); - FF_5 : FD1P3DX - port map (D => tsum(5), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(5)); - FF_4 : FD1P3DX - port map (D => tsum(4), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(4)); - FF_3 : FD1P3DX - port map (D => tsum(3), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(3)); - FF_2 : FD1P3DX - port map (D => tsum(2), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(2)); - FF_1 : FD1P3DX - port map (D => tsum(1), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(1)); - FF_0 : FD1P3DX - port map (D => tsum(0), SP => CLKEn, CK => CLK, CD => Reset, - Q => r0_sum(0)); - - GEN_0_ADD : FADD2B - port map (A0 => DataA(0), - A1 => DataA(1), - B0 => DataB(0), - B1 => DataB(1), - CI => scuba_vlo, - COUT => co(0), - S0 => tsum(0), - S1 => tsum(1)); - - GEN : for i in 1 to 151 generate - ADD : FADD2B - port map (A0 => DataA(2*i), - A1 => DataA(2*i+1), - B0 => DataB(2*i), - B1 => DataB(2*i+1), - CI => co(i-1), - COUT => co(i), - S0 => tsum(2*i), - S1 => tsum(2*i+1)); - end generate GEN; - - scuba_vlo_inst : VLO - port map (Z => scuba_vlo); - - Result <= r0_sum; - -end Structure; - - --- synopsys translate_off -library ecp3; -configuration Structure_CON of adder_304 is - for Structure - for all : FADD2B use entity ecp3.FADD2B(V); end for; - for all : FD1P3DX use entity ecp3.FD1P3DX(V); end for; - for all : VLO use entity ecp3.VLO(V); end for; - end for; -end Structure_CON; --- synopsys translate_on diff --git a/tdc_releases/tdc_v_stretcher/BusHandler.vhd b/tdc_releases/tdc_v_stretcher/BusHandler.vhd deleted file mode 100644 index d340fb7..0000000 --- a/tdc_releases/tdc_v_stretcher/BusHandler.vhd +++ /dev/null @@ -1,82 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb3_components.all; -use work.version.all; - -entity BusHandler is - generic ( - BUS_LENGTH : integer range 0 to 64 := 2); - port ( - RESET : in std_logic; - CLK : in std_logic; --- - DATA_IN : in std_logic_vector_array_32(0 to BUS_LENGTH); - READ_EN_IN : in std_logic; - WRITE_EN_IN : in std_logic; - ADDR_IN : in std_logic_vector(6 downto 0); - DATA_OUT : out std_logic_vector(31 downto 0); - DATAREADY_OUT : out std_logic; - UNKNOWN_ADDR_OUT : out std_logic); -end BusHandler; - -architecture Behavioral of BusHandler is - - --Output signals - signal data_out_reg : std_logic_vector(31 downto 0); - signal data_ready_reg : std_logic; - signal unknown_addr_reg : std_logic; - -begin - - READ_WRITE_RESPONSE : process (CLK, RESET) - begin - if rising_edge(CLK) then - if RESET = '1' then - data_out_reg <= (others => '0'); - data_ready_reg <= '0'; - unknown_addr_reg <= '0'; - elsif READ_EN_IN = '1' then - if to_integer(unsigned(ADDR_IN)) > BUS_LENGTH then -- if bigger than 64 - data_out_reg <= (others => '0'); - data_ready_reg <= '0'; - unknown_addr_reg <= '1'; - else - data_out_reg <= DATA_IN(to_integer(unsigned(ADDR_IN))); - data_ready_reg <= '1'; - unknown_addr_reg <= '0'; - end if; - elsif WRITE_EN_IN = '1' then - data_out_reg <= (others => '0'); - data_ready_reg <= '0'; - unknown_addr_reg <= '1'; - else - data_out_reg <= (others => '0'); - data_ready_reg <= '0'; - unknown_addr_reg <= '0'; - end if; - end if; - end process READ_WRITE_RESPONSE; - - - --FifoWriteSignal : process (CLK) - --begin - -- if rising_edge(CLK) then - -- if RESET = '1' then - -- unknown_addr_reg <= '0'; - -- else - -- unknown_addr_reg <= '1'; - -- end if; - -- end if; - --end process FifoWriteSignal; - - DATA_OUT <= data_out_reg; - DATAREADY_OUT <= data_ready_reg; - UNKNOWN_ADDR_OUT <= unknown_addr_reg; - -end Behavioral; - diff --git a/tdc_releases/tdc_v_stretcher/Channel.vhd b/tdc_releases/tdc_v_stretcher/Channel.vhd deleted file mode 100644 index 37c7abb..0000000 --- a/tdc_releases/tdc_v_stretcher/Channel.vhd +++ /dev/null @@ -1,215 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb3_components.all; -use work.version.all; - -entity Channel is - - generic ( - CHANNEL_ID : integer range 1 to 64); - port ( - RESET_200 : in std_logic; - RESET_100 : in std_logic; - RESET_COUNTERS : in std_logic; - CLK_200 : in std_logic; - CLK_100 : in std_logic; --- - HIT_IN : in std_logic; - SCALER_IN : in std_logic; - READ_EN_IN : in std_logic; - FIFO_DATA_OUT : out std_logic_vector(31 downto 0); - FIFO_EMPTY_OUT : out std_logic; - FIFO_FULL_OUT : out std_logic; - FIFO_ALMOST_FULL_OUT : out std_logic; - COARSE_COUNTER_IN : in std_logic_vector(10 downto 0); - EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0); - TRIGGER_WINDOW_END_IN : in std_logic; - DATA_FINISHED_IN : in std_logic; - RUN_MODE : in std_logic; --- - LOST_HIT_NUMBER : out std_logic_vector(23 downto 0); - HIT_DETECT_NUMBER : out std_logic_vector(23 downto 0); - ENCODER_START_NUMBER : out std_logic_vector(23 downto 0); - FIFO_WR_NUMBER : out std_logic_vector(23 downto 0); --- - Channel_DEBUG : out std_logic_vector(31 downto 0) - ); - -end Channel; - -architecture Channel of Channel is -------------------------------------------------------------------------------- --- Signal Declarations -------------------------------------------------------------------------------- - - -- reset - signal reset_counters_200 : std_logic; - - -- hit signals - signal hit_in_i : std_logic; - signal hit_buf : std_logic; - - -- time stamp - signal coarse_cntr_reg : std_logic_vector(10 downto 0); - - -- debug - signal sync_q : std_logic_vector(2 downto 0); - signal hit_pulse : std_logic; - signal fifo_wr_en_i : std_logic; - signal fifo_wr_en_reg : std_logic; - signal encoder_start_i : std_logic; - signal encoder_start_reg : std_logic; - signal lost_hit_cntr : unsigned(23 downto 0); - signal hit_detect_cntr : unsigned(23 downto 0); - signal encoder_start_cntr : unsigned(23 downto 0); - signal fifo_wr_cntr : unsigned(23 downto 0); - - -- other - signal trg_win_end_i : std_logic; - signal data_finished_i : std_logic; - signal run_mode_i : std_logic; - -------------------------------------------------------------------------------- - - attribute syn_keep : boolean; - attribute syn_keep of hit_buf : signal is true; - attribute syn_preserve : boolean; - attribute syn_preserve of coarse_cntr_reg : signal is true; - -------------------------------------------------------------------------------- - -begin - - hit_in_i <= HIT_IN; - hit_buf <= not hit_in_i; - - Channel_200_1 : Channel_200 - generic map ( - CHANNEL_ID => CHANNEL_ID) - port map ( - CLK_200 => CLK_200, - RESET_200 => RESET_200, - CLK_100 => CLK_100, - RESET_100 => RESET_100, - HIT_IN => hit_buf, - EPOCH_COUNTER_IN => EPOCH_COUNTER_IN, - TRIGGER_WINDOW_END_IN => trg_win_end_i, - DATA_FINISHED_IN => data_finished_i, - RUN_MODE => run_mode_i, - COARSE_COUNTER_IN => coarse_cntr_reg, - READ_EN_IN => READ_EN_IN, - FIFO_DATA_OUT => FIFO_DATA_OUT, - FIFO_EMPTY_OUT => FIFO_EMPTY_OUT, - FIFO_FULL_OUT => FIFO_FULL_OUT, - FIFO_ALMOST_FULL_OUT => FIFO_ALMOST_FULL_OUT, - FIFO_WR_OUT => fifo_wr_en_i, - ENCODER_START_OUT => encoder_start_i); - - trg_win_end_i <= TRIGGER_WINDOW_END_IN when rising_edge(CLK_200); - data_finished_i <= DATA_FINISHED_IN when rising_edge(CLK_100); - run_mode_i <= RUN_MODE when rising_edge(CLK_100); - encoder_start_reg <= encoder_start_i when rising_edge(CLK_200); - fifo_wr_en_reg <= fifo_wr_en_i when rising_edge(CLK_200); - - CoarseCounter : ShiftRegisterSISO - generic map ( - DEPTH => 1, - WIDTH => 11) - port map ( - CLK => CLK_200, - RESET => RESET_200, - D_IN => COARSE_COUNTER_IN, - D_OUT => coarse_cntr_reg); - -------------------------------------------------------------------------------- --- DEBUG Counters -------------------------------------------------------------------------------- - reset_counters_200 <= RESET_COUNTERS when rising_edge(CLK_200); - - --purpose: Hit Signal Synchroniser - sync_q(0) <= SCALER_IN when rising_edge(CLK_200); - sync_q(1) <= sync_q(0) when rising_edge(CLK_200); - sync_q(2) <= sync_q(1) when rising_edge(CLK_200); - - edge_to_pulse_1 : edge_to_pulse - port map ( - clock => CLK_200, - en_clk => '1', - signal_in => sync_q(2), - pulse => hit_pulse); - - --purpose: Counts the detected but unwritten hits - Lost_Hit_Counter : process (CLK_200) - begin - if rising_edge(CLK_200) then - if RESET_200 = '1' or reset_counters_200 = '1' then - lost_hit_cntr <= (others => '0'); - elsif hit_pulse = '1' then - lost_hit_cntr <= lost_hit_cntr + to_unsigned(1, 1); - elsif fifo_wr_en_reg = '1' then - lost_hit_cntr <= lost_hit_cntr - to_unsigned(1, 1); - end if; - end if; - end process Lost_Hit_Counter; - - LOST_HIT_NUMBER <= std_logic_vector(lost_hit_cntr) when rising_edge(CLK_100); - - --purpose: Counts the detected hits - Hit_Detect_Counter : process (CLK_200, RESET_200, hit_pulse) - begin - if rising_edge(CLK_200) then - if RESET_200 = '1' or reset_counters_200 = '1' then - hit_detect_cntr <= (others => '0'); - elsif hit_pulse = '1' then - hit_detect_cntr <= hit_detect_cntr + to_unsigned(1, 1); - end if; - end if; - end process Hit_Detect_Counter; - - HIT_DETECT_NUMBER <= std_logic_vector(hit_detect_cntr) when rising_edge(CLK_100); - - --purpose: Counts the encoder start times - Encoder_Start_Counter : process (CLK_200) - begin - if rising_edge(CLK_200) then - if RESET_200 = '1' or reset_counters_200 = '1' then - encoder_start_cntr <= (others => '0'); - elsif encoder_start_reg = '1' then - encoder_start_cntr <= encoder_start_cntr + to_unsigned(1, 1); - end if; - end if; - end process Encoder_Start_Counter; - - ENCODER_START_NUMBER <= std_logic_vector(encoder_start_cntr) when rising_edge(CLK_100); - - --purpose: Counts the written hits - FIFO_WR_Counter : process (CLK_200) - begin - if rising_edge(CLK_200) then - if RESET_200 = '1' or reset_counters_200 = '1' then - fifo_wr_cntr <= (others => '0'); - elsif fifo_wr_en_reg = '1' then - fifo_wr_cntr <= fifo_wr_cntr + to_unsigned(1, 1); - end if; - end if; - end process FIFO_WR_Counter; - - FIFO_WR_NUMBER <= std_logic_vector(fifo_wr_cntr) when rising_edge(CLK_100); - - --Channel_DEBUG(0) <= HIT_IN; - --Channel_DEBUG(1) <= result_2_reg; - --Channel_DEBUG(2) <= hit_detect_i; - --Channel_DEBUG(3) <= hit_detect_reg; - --Channel_DEBUG(4) <= '0'; - --Channel_DEBUG(5) <= ff_array_en_i; - --Channel_DEBUG(6) <= encoder_start_i; - --Channel_DEBUG(7) <= fifo_wr_i; - --Channel_DEBUG(15 downto 8) <= result_i(7 downto 0); - --Channel_DEBUG(31 downto 16) <= (others => '0'); - -end Channel; diff --git a/tdc_releases/tdc_v_stretcher/Channel_200.vhd b/tdc_releases/tdc_v_stretcher/Channel_200.vhd deleted file mode 100644 index 0420990..0000000 --- a/tdc_releases/tdc_v_stretcher/Channel_200.vhd +++ /dev/null @@ -1,315 +0,0 @@ -------------------------------------------------------------------------------- --- Title : Channel 200 MHz Part --- Project : -------------------------------------------------------------------------------- --- File : Channel_200.vhd --- Author : c.ugur@gsi.de --- Created : 2012-08-28 --- Last update: 2012-11-09 -------------------------------------------------------------------------------- --- Description: -------------------------------------------------------------------------------- - -library IEEE; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb3_components.all; -use work.version.all; - -entity Channel_200 is - generic ( - CHANNEL_ID : integer range 1 to 64); - port ( - CLK_200 : in std_logic; -- 200 MHz clk - RESET_200 : in std_logic; -- reset sync with 200Mhz clk - CLK_100 : in std_logic; -- 100 MHz clk - RESET_100 : in std_logic; -- reset sync with 100Mhz clk --- - HIT_IN : in std_logic; -- hit in - EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0); -- system coarse counter - TRIGGER_WINDOW_END_IN : in std_logic; - DATA_FINISHED_IN : in std_logic; - RUN_MODE : in std_logic; - COARSE_COUNTER_IN : in std_logic_vector(10 downto 0); - READ_EN_IN : in std_logic; -- read en signal - FIFO_DATA_OUT : out std_logic_vector(31 downto 0); -- fifo data out - FIFO_EMPTY_OUT : out std_logic; -- fifo empty signal - FIFO_FULL_OUT : out std_logic; -- fifo full signal - FIFO_ALMOST_FULL_OUT : out std_logic; --- - FIFO_WR_OUT : out std_logic; - ENCODER_START_OUT : out std_logic); - - -end Channel_200; - -architecture Channel_200 of Channel_200 is - - -- carry chain - signal data_a_i : std_logic_vector(303 downto 0); - signal data_b_i : std_logic_vector(303 downto 0); - signal result_i : std_logic_vector(303 downto 0); - signal ff_array_en_i : std_logic; - - -- hit detection - signal result_2_reg : std_logic; - signal hit_detect_i : std_logic; - signal hit_detect_reg : std_logic; - signal hit_detect_2reg : std_logic; - - -- time stamp - signal time_stamp_i : std_logic_vector(10 downto 0); - signal coarse_cntr_reg : std_logic_vector(10 downto 0); - - -- encoder - signal encoder_start_i : std_logic; - signal encoder_finished_i : std_logic; - signal encoder_data_out_i : std_logic_vector(9 downto 0); - signal encoder_debug_i : std_logic_vector(31 downto 0); - - -- coarse counter overflow - signal coarse_cntr_overflow_release : std_logic; - signal coarse_cntr_overflow_flag : std_logic; - - -- epoch counter - signal epoch_cntr : std_logic_vector(27 downto 0); - signal epoch_word_first : std_logic_vector(31 downto 0); - signal epoch_cntr_up : std_logic; - signal epoch_capture_time : std_logic_vector(10 downto 0); - - -- fifo - signal fifo_data_out_i : std_logic_vector(31 downto 0); - signal fifo_data_in_i : std_logic_vector(31 downto 0); - signal fifo_empty_i : std_logic; - signal fifo_full_i : std_logic; - signal fifo_was_full_i : std_logic; - signal fifo_almost_full_i : std_logic; - signal fifo_wr_en_i : std_logic; - signal fifo_rd_en_i : std_logic; - - -- other - signal read_en_reg : std_logic; - signal read_en_2reg : std_logic; - signal first_read_i : std_logic; - signal trg_win_end_i : std_logic; - - attribute syn_keep : boolean; - attribute syn_keep of ff_array_en_i : signal is true; - attribute syn_keep of trg_win_end_i : signal is true; - attribute syn_keep of encoder_start_i : signal is true; - attribute syn_preserve : boolean; - attribute syn_preserve of trg_win_end_i : signal is true; - - - -begin -- Channel_200 - - trg_win_end_i <= TRIGGER_WINDOW_END_IN when rising_edge(CLK_200); - - --purpose: Tapped Delay Line 304 (Carry Chain) with wave launcher (21) double transition - FC : Adder_304 - port map ( - CLK => CLK_200, - RESET => RESET_200, - DataA => data_a_i, - DataB => data_b_i, - ClkEn => ff_array_en_i, - Result => result_i); - data_a_i <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" & x"7FFFFFF"; - data_b_i <= x"000000000000000000000000000000000000000000000000000000000000000000000" & not(HIT_IN) & x"000000" & "00" & HIT_IN; - ff_array_en_i <= not(hit_detect_i or hit_detect_reg or hit_detect_2reg); - - result_2_reg <= result_i(2) when rising_edge(CLK_200); - hit_detect_i <= (not result_2_reg) and result_i(2); -- detects the hit by - -- comparing the - -- previous state of the - -- hit detection bit - hit_detect_reg <= hit_detect_i when rising_edge(CLK_200); - hit_detect_2reg <= hit_detect_reg when rising_edge(CLK_200); - coarse_cntr_reg <= COARSE_COUNTER_IN when rising_edge(CLK_200); - encoder_start_i <= hit_detect_reg; - ENCODER_START_OUT <= encoder_start_i; - - TimeStampCapture : process (CLK_200) - begin - if rising_edge(CLK_200) then - if RESET_200 = '1' then - time_stamp_i <= (others => '0'); - elsif hit_detect_reg = '1' then - time_stamp_i <= coarse_cntr_reg; - end if; - end if; - end process TimeStampCapture; - - epoch_capture_time <= "00000000111"; - - EpochCounterCapture : process (CLK_200) - begin - if rising_edge(CLK_200) then - if RESET_200 = '1' then - epoch_cntr <= (others => '0'); - epoch_cntr_up <= '0'; - elsif coarse_cntr_reg = epoch_capture_time then - epoch_cntr <= EPOCH_COUNTER_IN; - epoch_cntr_up <= '1'; - end if; - end if; - end process EpochCounterCapture; - - --purpose: Encoder - Encoder : Encoder_304_Bit - port map ( - RESET => RESET_200, - CLK => CLK_200, - START_IN => encoder_start_i, - THERMOCODE_IN => result_i, - FINISHED_OUT => encoder_finished_i, - BINARY_CODE_OUT => encoder_data_out_i, - ENCODER_DEBUG => encoder_debug_i); - - FIFO : FIFO_32x32_OutReg - port map ( - Data => fifo_data_in_i, - WrClock => CLK_200, - RdClock => CLK_100, - WrEn => fifo_wr_en_i, - RdEn => fifo_rd_en_i, - Reset => RESET_100, - RPReset => RESET_200, - Q => fifo_data_out_i, - Empty => fifo_empty_i, - Full => fifo_full_i, - AlmostFull => fifo_almost_full_i); - - fifo_rd_en_i <= READ_EN_IN or fifo_full_i; - - -- purpose: Sets the Overflow Flag - CoarseCounterOverflowFlag : process (CLK_200) - begin - if rising_edge(CLK_200) then - if RESET_200 = '1' then - coarse_cntr_overflow_flag <= '0'; - elsif epoch_cntr_up = '1' or trg_win_end_i = '1' then - coarse_cntr_overflow_flag <= '1'; - elsif coarse_cntr_overflow_release = '1' then - coarse_cntr_overflow_flag <= '0'; - end if; - end if; - end process CoarseCounterOverflowFlag; - - -- purpose: Generate Fifo Wr Signal - FifoWriteSignal : process (CLK_200) - begin - if rising_edge(CLK_200) then - if RESET_200 = '1' then - fifo_data_in_i <= (others => '0'); - coarse_cntr_overflow_release <= '0'; - fifo_wr_en_i <= '0'; - elsif encoder_finished_i = '1' then - --if coarse_cntr_overflow_flag = '0' then - -- fifo_data_in_i(31) <= '1'; -- data marker - -- fifo_data_in_i(30 downto 29) <= "00"; -- reserved bits - -- fifo_data_in_i(28 downto 22) <= std_logic_vector(to_unsigned(CHANNEL_ID, 7)); -- channel number - -- fifo_data_in_i(21 downto 12) <= encoder_data_out_i; -- fine time from the encoder - -- fifo_data_in_i(11) <= '1'; --edge_type_i; -- rising '1' or falling '0' edge - ---- fifo_data_in_i(10 downto 0) <= time_stamp_reg; -- hit time stamp - -- fifo_data_in_i(10 downto 0) <= time_stamp_i; -- hit time stamp - -- coarse_cntr_overflow_release <= '0'; - -- fifo_wr_en_i <= '1'; - --else - --if and_all(TIME_STAMP_IN(10 downto 3)) = '1' then -- for the hits after 0x7f8 - --if and_all(time_stamp_i(10 downto 3)) = '1' then -- for the hits after 0x7f8 - -- fifo_data_in_i(31) <= '1'; -- data marker - -- fifo_data_in_i(30 downto 29) <= "00"; -- reserved bits - -- fifo_data_in_i(28 downto 22) <= std_logic_vector(to_unsigned(CHANNEL_ID, 7)); -- channel number - -- fifo_data_in_i(21 downto 12) <= encoder_data_out_i; -- fine time from the encoder - -- fifo_data_in_i(11) <= '1'; --edge_type_i; -- rising '1' or falling '0' edge - -- --fifo_data_in_i(10 downto 0) <= time_stamp_reg; -- hit time stamp - -- fifo_data_in_i(10 downto 0) <= time_stamp_i; -- hit time stamp - -- coarse_cntr_overflow_release <= '0'; - -- fifo_wr_en_i <= '1'; - --else - - fifo_data_in_i(31 downto 29) <= "011"; - fifo_data_in_i(28) <= '0'; - fifo_data_in_i(27 downto 0) <= epoch_cntr; - coarse_cntr_overflow_release <= '1'; - fifo_wr_en_i <= '1'; - --end if; - --end if; - elsif coarse_cntr_overflow_release = '1' then - fifo_data_in_i(31) <= '1'; -- data marker - fifo_data_in_i(30 downto 29) <= "00"; -- reserved bits - fifo_data_in_i(28 downto 22) <= std_logic_vector(to_unsigned(CHANNEL_ID, 7)); -- channel number - fifo_data_in_i(21 downto 12) <= encoder_data_out_i; -- fine time from the encoder - fifo_data_in_i(11) <= '1'; --edge_type_i; -- rising '1' or falling '0' edge - --fifo_data_in_i(10 downto 0) <= time_stamp_reg; -- hit time stamp - fifo_data_in_i(10 downto 0) <= time_stamp_i; -- hit time stamp - coarse_cntr_overflow_release <= '0'; - fifo_wr_en_i <= '1'; - else - fifo_data_in_i <= (others => '0'); - coarse_cntr_overflow_release <= '0'; - fifo_wr_en_i <= '0'; - end if; - end if; - end process FifoWriteSignal; - - FIFO_WR_OUT <= fifo_wr_en_i; - - EpochCounterCaptureFirstWord : process (CLK_100, RESET_100) - begin - if rising_edge(CLK_100) then - if RESET_100 = '1' then - epoch_word_first <= x"60000000"; - elsif DATA_FINISHED_IN = '1' and RUN_MODE = '0' then - epoch_word_first <= x"60000000"; - elsif fifo_data_out_i(31 downto 29) = "011" then - epoch_word_first <= fifo_data_out_i; - end if; - end if; - end process EpochCounterCaptureFirstWord; - - read_en_reg <= READ_EN_IN when rising_edge(CLK_100); - read_en_2reg <= read_en_reg when rising_edge(CLK_100); - first_read_i <= read_en_reg and not(read_en_2reg) when rising_edge(CLK_100); - - FifoWasFull : process (CLK_100, RESET_100) - begin - if rising_edge(CLK_100) then - if RESET_100 = '1' then - fifo_was_full_i <= '0'; - elsif fifo_full_i = '1' then - fifo_was_full_i <= '1'; - elsif fifo_empty_i = '1' then - fifo_was_full_i <= '0'; - end if; - end if; - end process FifoWasFull; - - RegisterOutputs : process (CLK_100) - begin - if rising_edge(CLK_100) then - if RESET_100 = '1' then - FIFO_DATA_OUT <= (others => '1'); - FIFO_EMPTY_OUT <= '0'; - FIFO_FULL_OUT <= '0'; - FIFO_ALMOST_FULL_OUT <= '0'; - else - if first_read_i = '1' and fifo_was_full_i = '1' then - FIFO_DATA_OUT <= epoch_word_first; - else - FIFO_DATA_OUT <= fifo_data_out_i; - end if; - FIFO_EMPTY_OUT <= fifo_empty_i; - FIFO_FULL_OUT <= fifo_full_i; - FIFO_ALMOST_FULL_OUT <= fifo_almost_full_i; - end if; - end if; - end process RegisterOutputs; - -end Channel_200; diff --git a/tdc_releases/tdc_v_stretcher/Encoder_304_Bit.vhd b/tdc_releases/tdc_v_stretcher/Encoder_304_Bit.vhd deleted file mode 100644 index 9b9a63e..0000000 --- a/tdc_releases/tdc_v_stretcher/Encoder_304_Bit.vhd +++ /dev/null @@ -1,498 +0,0 @@ -------------------------------------------------------------------------------- --- Title : Encoder 304 bits -------------------------------------------------------------------------------- --- File : Encoder_304_Bit.vhd --- Author : Cahit Ugur --- Created : 2011-11-28 --- Last update: 2012-11-12 -------------------------------------------------------------------------------- --- Description: Encoder for 304 bits -------------------------------------------------------------------------------- --- Revisions : --- Date Version Author Description --- 2011-11-28 1.0 ugur Created -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_unsigned.all; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb3_components.all; -use work.version.all; - --- synopsys translate_off -library ecp3; -use ecp3.components.all; --- synopsys translate_on - -entity Encoder_304_Bit is - port ( - RESET : in std_logic; -- system reset - CLK : in std_logic; -- system clock - START_IN : in std_logic; - THERMOCODE_IN : in std_logic_vector(303 downto 0); - FINISHED_OUT : out std_logic; - BINARY_CODE_OUT : out std_logic_vector(9 downto 0); - ENCODER_DEBUG : out std_logic_vector(31 downto 0) - ); -end Encoder_304_Bit; - -architecture behavioral of Encoder_304_Bit is - -------------------------------------------------------------------------------- --- Component Declarations -------------------------------------------------------------------------------- - component LUT4 - generic ( - INIT : std_logic_vector); - port ( - A, B, C, D : in std_ulogic; - Z : out std_ulogic); - end component; - -------------------------------------------------------------------------------- --- Signal Declarations -------------------------------------------------------------------------------- - signal P_lut : std_logic_vector(37 downto 0); - signal P_one : std_logic_vector(37 downto 0); - signal mux_control : std_logic_vector(5 downto 0); - signal mux_control_reg : std_logic_vector(5 downto 0); - signal mux_control_2reg : std_logic_vector(5 downto 0); - signal mux_control_3reg : std_logic_vector(5 downto 0); - signal mux_control_4reg : std_logic_vector(5 downto 0); - signal interval_reg : std_logic_vector(8 downto 0); - signal interval_binary : std_logic_vector(2 downto 0); - signal binary_code_f : std_logic_vector(8 downto 0); - signal binary_code_r : std_logic_vector(8 downto 0); - signal start_reg : std_logic; - signal start_2reg : std_logic; - signal start_3reg : std_logic; - signal rom_done_i : std_logic; -- indicates that the encoding of rising edge is done - signal rom_done_reg : std_logic; -- indicates that the encoding of rising edge is done - signal interval_detected_i : std_logic; - signal address_i : std_logic_vector(9 downto 0); - signal q_reg : std_logic_vector(7 downto 0); - signal q_2reg : std_logic_vector(7 downto 0); --- FSM signals - type FSM is (IDLE, START_CNT_2, START_CNT_3, START_CNT_4); - signal FSM_CURRENT, FSM_NEXT : FSM; - - signal start_cnt_1_fsm : std_logic; - signal start_cnt_2_fsm : std_logic; - signal start_cnt_3_fsm : std_logic; - signal start_cnt_4_fsm : std_logic; - signal start_cnt_1_i : std_logic; - signal start_cnt_2_i : std_logic; - signal start_cnt_3_i : std_logic; - signal start_cnt_4_i : std_logic; --- - signal proc_cnt_1 : std_logic_vector(3 downto 0); - signal proc_cnt_2 : std_logic_vector(3 downto 0); - signal proc_cnt_3 : std_logic_vector(3 downto 0); - signal proc_cnt_4 : std_logic_vector(3 downto 0); - signal proc_finished_1 : std_logic; - signal proc_finished_2 : std_logic; - signal proc_finished_3 : std_logic; - signal proc_finished_4 : std_logic; - signal conv_finished_i : std_logic; - - attribute syn_keep : boolean; - attribute syn_keep of mux_control : signal is true; - attribute syn_keep of mux_control_reg : signal is true; - attribute syn_keep of mux_control_2reg : signal is true; - attribute syn_keep of mux_control_3reg : signal is true; - attribute syn_keep of mux_control_4reg : signal is true; -------------------------------------------------------------------------------- -begin - - --purpose : Register signals - Register_Signals : process (CLK, RESET) - begin - if rising_edge(CLK) then - if RESET = '1' then - start_reg <= '0'; - start_2reg <= '0'; - start_3reg <= '0'; - mux_control_reg <= (others => '0'); - mux_control_2reg <= (others => '0'); - mux_control_3reg <= (others => '0'); - mux_control_4reg <= (others => '0'); - q_2reg <= (others => '0'); - rom_done_reg <= '0'; - interval_detected_i <= '0'; - else - start_reg <= START_IN; - start_2reg <= start_reg; - start_3reg <= start_2reg; - mux_control_reg <= mux_control; - mux_control_2reg <= mux_control_reg; - mux_control_3reg <= mux_control_2reg; - mux_control_4reg <= mux_control_3reg; - q_2reg <= q_reg; - rom_done_reg <= rom_done_i; - interval_detected_i <= rom_done_i and rom_done_reg; - end if; - end if; - end process Register_Signals; - - Interval_Determination_First : LUT4 - generic map (INIT => X"15A8") - port map (A => '1', B => '1', C => THERMOCODE_IN(0), D => START_IN, - Z => P_lut(0)); - - Interval_Determination : for i in 1 to 37 generate - U : LUT4 - generic map (INIT => X"15A8") - port map (A => THERMOCODE_IN(8*i-2), B => THERMOCODE_IN(8*i-1), C => THERMOCODE_IN(8*i), D => START_IN, - Z => P_lut(i)); - end generate Interval_Determination; -------------------------------------------------------------------------------- - - Gen_P_one : for i in 0 to 36 generate - P_one(i) <= P_lut(i) and (not P_lut(i+1)) when rising_edge(CLK); - end generate Gen_P_one; - - P_one_assign : process (CLK, START_IN, P_lut) - begin - if rising_edge(CLK) then - if RESET = '1' or START_IN = '0' then - P_one(37) <= '0'; - else - P_one(37) <= P_lut(37); - end if; - end if; - end process P_one_assign; - - Interval_Number_to_Binary : process (CLK, RESET) - begin -- The interval number with the 0-1 transition is converted from 1-of-N code to binary - -- code for the control of the MUX. - if rising_edge(CLK) then - if RESET = '1' then - mux_control <= (others => '0'); - elsif START_IN = '1' or start_reg = '1' then - mux_control(0) <= P_one(0) or P_one(2) or P_one(4) or P_one(6) or P_one(8) or P_one(10) or - P_one(12) or P_one(14) or P_one(16) or P_one(18) or P_one(20) or P_one(22) or - P_one(24) or P_one(26) or P_one(28) or P_one(30) or P_one(32) or P_one(34) or - P_one(36); - mux_control(1) <= P_one(1) or P_one(2) or P_one(5) or P_one(6) or P_one(9) or P_one(10) or - P_one(13) or P_one(14) or P_one(17) or P_one(18) or P_one(21) or P_one(22) or - P_one(25) or P_one(26) or P_one(29) or P_one(30) or P_one(33) or P_one(34) or - P_one(37); - mux_control(2) <= P_one(3) or P_one(4) or P_one(5) or P_one(6) or P_one(11) or P_one(12) or - P_one(13) or P_one(14) or P_one(19) or P_one(20) or P_one(21) or P_one(22) or - P_one(27) or P_one(28) or P_one(29) or P_one(30) or P_one(35) or P_one(36) or - P_one(37); - mux_control(3) <= P_one(7) or P_one(8) or P_one(9) or P_one(10) or P_one(11) or P_one(12) or - P_one(13) or P_one(14) or P_one(23) or P_one(24) or P_one(25) or P_one(26) or - P_one(27) or P_one(28) or P_one(29) or P_one(30); - mux_control(4) <= P_one(15) or P_one(16) or P_one(17) or P_one(18) or P_one(19) or P_one(20) or - P_one(21) or P_one(22) or P_one(23) or P_one(24) or P_one(25) or P_one(26) or - P_one(27) or P_one(28) or P_one(29) or P_one(30); - mux_control(5) <= P_one(31) or P_one(32) or P_one(33) or P_one(34) or P_one(35) or P_one(36) or - P_one(37); - else - mux_control <= (others => '0'); - end if; - end if; - end process Interval_Number_to_Binary; - - Interval_Selection : process (CLK, RESET) - begin -- The interval with the 0-1 transition is selected. - if rising_edge(CLK) then - if RESET = '1' then - interval_reg <= (others => '0'); - else - case mux_control is - when "000001" => interval_reg <= THERMOCODE_IN(7 downto 0) & '1'; - when "000010" => interval_reg <= THERMOCODE_IN(15 downto 7); - when "000011" => interval_reg <= THERMOCODE_IN(23 downto 15); - when "000100" => interval_reg <= THERMOCODE_IN(31 downto 23); - when "000101" => interval_reg <= THERMOCODE_IN(39 downto 31); - when "000110" => interval_reg <= THERMOCODE_IN(47 downto 39); - when "000111" => interval_reg <= THERMOCODE_IN(55 downto 47); - when "001000" => interval_reg <= THERMOCODE_IN(63 downto 55); - when "001001" => interval_reg <= THERMOCODE_IN(71 downto 63); - when "001010" => interval_reg <= THERMOCODE_IN(79 downto 71); - when "001011" => interval_reg <= THERMOCODE_IN(87 downto 79); - when "001100" => interval_reg <= THERMOCODE_IN(95 downto 87); - when "001101" => interval_reg <= THERMOCODE_IN(103 downto 95); - when "001110" => interval_reg <= THERMOCODE_IN(111 downto 103); - when "001111" => interval_reg <= THERMOCODE_IN(119 downto 111); - when "010000" => interval_reg <= THERMOCODE_IN(127 downto 119); - when "010001" => interval_reg <= THERMOCODE_IN(135 downto 127); - when "010010" => interval_reg <= THERMOCODE_IN(143 downto 135); - when "010011" => interval_reg <= THERMOCODE_IN(151 downto 143); - when "010100" => interval_reg <= THERMOCODE_IN(159 downto 151); - when "010101" => interval_reg <= THERMOCODE_IN(167 downto 159); - when "010110" => interval_reg <= THERMOCODE_IN(175 downto 167); - when "010111" => interval_reg <= THERMOCODE_IN(183 downto 175); - when "011000" => interval_reg <= THERMOCODE_IN(191 downto 183); - when "011001" => interval_reg <= THERMOCODE_IN(199 downto 191); - when "011010" => interval_reg <= THERMOCODE_IN(207 downto 199); - when "011011" => interval_reg <= THERMOCODE_IN(215 downto 207); - when "011100" => interval_reg <= THERMOCODE_IN(223 downto 215); - when "011101" => interval_reg <= THERMOCODE_IN(231 downto 223); - when "011110" => interval_reg <= THERMOCODE_IN(239 downto 231); - when "011111" => interval_reg <= THERMOCODE_IN(247 downto 239); - when "100000" => interval_reg <= THERMOCODE_IN(255 downto 247); - when "100001" => interval_reg <= THERMOCODE_IN(263 downto 255); - when "100010" => interval_reg <= THERMOCODE_IN(271 downto 263); - when "100011" => interval_reg <= THERMOCODE_IN(279 downto 271); - when "100100" => interval_reg <= THERMOCODE_IN(287 downto 279); - when "100101" => interval_reg <= THERMOCODE_IN(295 downto 287); - when "100110" => interval_reg <= THERMOCODE_IN(303 downto 295); - when others => interval_reg <= (others => '0'); - end case; - end if; - end if; - end process Interval_Selection; - - ROM_Encoder_1 : ROM_Encoder - port map ( - Address => address_i, - OutClock => CLK, - OutClockEn => '1', - Reset => RESET, - Q => q_reg); - address_i <= start_3reg & interval_reg; - rom_done_i <= q_2reg(7); - interval_binary <= q_2reg(2 downto 0); - - Binary_Code_Calculation_rf : process (CLK, RESET) - begin - if rising_edge(CLK) then - if RESET = '1' then - binary_code_f <= (others => '0'); - binary_code_r <= (others => '0'); - elsif rom_done_i = '1' then - binary_code_r <= (mux_control_4reg - 1) & interval_binary; - binary_code_f <= binary_code_r; - end if; - end if; - end process Binary_Code_Calculation_rf; - - --purpose: FSMs the encoder - FSM_CLK : process (CLK, RESET) - begin - if rising_edge(CLK) then - if RESET = '1' then - FSM_CURRENT <= IDLE; - start_cnt_1_i <= '0'; - start_cnt_2_i <= '0'; - start_cnt_3_i <= '0'; - start_cnt_4_i <= '0'; - else - FSM_CURRENT <= FSM_NEXT; - start_cnt_1_i <= start_cnt_1_fsm; - start_cnt_2_i <= start_cnt_2_fsm; - start_cnt_3_i <= start_cnt_3_fsm; - start_cnt_4_i <= start_cnt_4_fsm; - end if; - end if; - end process FSM_CLK; - - FSM_PROC : process (FSM_CURRENT, START_IN) - begin - - FSM_NEXT <= IDLE; - start_cnt_1_fsm <= '0'; - start_cnt_2_fsm <= '0'; - start_cnt_3_fsm <= '0'; - start_cnt_4_fsm <= '0'; - - case (FSM_CURRENT) is - when IDLE => - if START_IN = '1' then - FSM_NEXT <= START_CNT_2; - start_cnt_1_fsm <= '1'; - end if; - - when START_CNT_2 => - if START_IN = '1' then - FSM_NEXT <= START_CNT_3; - start_cnt_2_fsm <= '1'; - else - FSM_NEXT <= START_CNT_2; - end if; - - when START_CNT_3 => - if START_IN = '1' then - FSM_NEXT <= START_CNT_4; - start_cnt_3_fsm <= '1'; - else - FSM_NEXT <= START_CNT_3; - end if; - - when START_CNT_4 => - if START_IN = '1' then - FSM_NEXT <= IDLE; - start_cnt_4_fsm <= '1'; - else - FSM_NEXT <= START_CNT_4; - end if; - - when others => - FSM_NEXT <= IDLE; - end case; - end process FSM_PROC; - - --purpose : Conversion number 1 - Conv_1 : process (CLK, RESET) - begin - if rising_edge(CLK) then - if RESET = '1' then - proc_cnt_1 <= x"6"; - proc_finished_1 <= '0'; - elsif start_cnt_1_i = '1' then - proc_cnt_1 <= x"1"; - proc_finished_1 <= '0'; - elsif proc_cnt_1 = x"5" then - proc_cnt_1 <= proc_cnt_1 + 1; - proc_finished_1 <= '1'; - elsif proc_cnt_1 = x"6" then - proc_cnt_1 <= x"6"; - proc_finished_1 <= '0'; - else - proc_cnt_1 <= proc_cnt_1 + 1; - proc_finished_1 <= '0'; - end if; - end if; - end process Conv_1; - - --purpose : Conversion number 2 - Conv_2 : process (CLK, RESET) - begin - if rising_edge(CLK) then - if RESET = '1' then - proc_cnt_2 <= x"6"; - proc_finished_2 <= '0'; - elsif start_cnt_2_i = '1' then - proc_cnt_2 <= x"1"; - proc_finished_2 <= '0'; - elsif proc_cnt_2 = x"5" then - proc_cnt_2 <= proc_cnt_2 + 1; - proc_finished_2 <= '1'; - elsif proc_cnt_2 = x"6" then - proc_cnt_2 <= x"6"; - proc_finished_2 <= '0'; - else - proc_cnt_2 <= proc_cnt_2 + 1; - proc_finished_2 <= '0'; - end if; - end if; - end process Conv_2; - - --purpose : Conversion number 3 - Conv_3 : process (CLK, RESET) - begin - if rising_edge(CLK) then - if RESET = '1' then - proc_cnt_3 <= x"6"; - proc_finished_3 <= '0'; - elsif start_cnt_3_i = '1' then - proc_cnt_3 <= x"1"; - proc_finished_3 <= '0'; - elsif proc_cnt_3 = x"5" then - proc_cnt_3 <= proc_cnt_3 + 1; - proc_finished_3 <= '1'; - elsif proc_cnt_3 = x"6" then - proc_cnt_3 <= x"6"; - proc_finished_3 <= '0'; - else - proc_cnt_3 <= proc_cnt_3 + 1; - proc_finished_3 <= '0'; - end if; - end if; - end process Conv_3; - - --purpose : Conversion number 4 - Conv_4 : process (CLK, RESET) - begin - if rising_edge(CLK) then - if RESET = '1' then - proc_cnt_4 <= x"6"; - proc_finished_4 <= '0'; - elsif start_cnt_4_i = '1' then - proc_cnt_4 <= x"1"; - proc_finished_4 <= '0'; - elsif proc_cnt_4 = x"5" then - proc_cnt_4 <= proc_cnt_4 + 1; - proc_finished_4 <= '1'; - elsif proc_cnt_4 = x"6" then - proc_cnt_4 <= x"6"; - proc_finished_4 <= '0'; - else - proc_cnt_4 <= proc_cnt_4 + 1; - proc_finished_4 <= '0'; - end if; - end if; - end process Conv_4; - - Binary_Code_Calculation : process (CLK, RESET) - begin - if rising_edge(CLK) then - if RESET = '1' then - BINARY_CODE_OUT <= (others => '0'); - FINISHED_OUT <= '0'; - elsif conv_finished_i = '1' and interval_detected_i = '1' then - BINARY_CODE_OUT <= ('0' & binary_code_r) + ('0' & binary_code_f); - FINISHED_OUT <= '1'; - else --- BINARY_CODE_OUT <= (others => '0'); - FINISHED_OUT <= '0'; - end if; - end if; - end process Binary_Code_Calculation; - - conv_finished_i <= proc_finished_1 or proc_finished_2 or proc_finished_3 or proc_finished_4; - - -------------------------------------------------------------------------------- --- DEBUG -------------------------------------------------------------------------------- - ----purpose : Conversion number 1 - --Conv_1 : process (CLK, RESET) - --begin - -- if rising_edge(CLK) then - -- if RESET = '1' then - -- proc_cnt_1 <= x"3"; - -- proc_finished_1 <= '0'; - -- elsif START_IN = '1' then - -- proc_cnt_1 <= x"1"; - -- proc_finished_1 <= '0'; - -- elsif proc_cnt_1 = x"1" or proc_cnt_1 = x"2" then - -- proc_cnt_1 <= proc_cnt_1 + 1; - -- proc_finished_1 <= '1'; - -- elsif proc_cnt_1 = x"3" then - -- proc_cnt_1 <= x"3"; - -- proc_finished_1 <= '0'; - -- else - -- proc_cnt_1 <= proc_cnt_1 + 1; - -- proc_finished_1 <= '0'; - -- end if; - -- end if; - --end process Conv_1; - - --Binary_Code_Calculation : process (CLK, RESET) - --begin - -- if rising_edge(CLK) then - -- if RESET = '1' then - -- BINARY_CODE_OUT <= (others => '0'); - -- FINISHED_OUT <= '0'; - -- elsif proc_finished_1 = '1' then - -- BINARY_CODE_OUT <= address_i; --'0' & interval_reg; - -- FINISHED_OUT <= '1'; - -- else - -- BINARY_CODE_OUT <= (others => '0'); - -- FINISHED_OUT <= '0'; - -- end if; - -- end if; - --end process Binary_Code_Calculation; - - ----ENCODER_DEBUG(8 downto 0) <= interval_reg; - -end behavioral; diff --git a/tdc_releases/tdc_v_stretcher/FIFO_32x32_OutReg.vhd b/tdc_releases/tdc_v_stretcher/FIFO_32x32_OutReg.vhd deleted file mode 100644 index c7c766a..0000000 --- a/tdc_releases/tdc_v_stretcher/FIFO_32x32_OutReg.vhd +++ /dev/null @@ -1,932 +0,0 @@ --- VHDL netlist generated by SCUBA Diamond_1.4_Production (87) --- Module Version: 5.4 ---/opt/lattice/diamond/1.4/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 32 -width 32 -depth 32 -rdata_width 32 -regout -no_enable -pe -1 -pf 28 -e - --- Tue Jun 26 11:56:52 2012 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp3; -use ecp3.components.all; --- synopsys translate_on - -entity FIFO_32x32_OutReg is - port ( - Data : in std_logic_vector(31 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(31 downto 0); - Empty : out std_logic; - Full : out std_logic; - AlmostFull : out std_logic); -end FIFO_32x32_OutReg; - -architecture Structure of FIFO_32x32_OutReg is - - -- internal signal declarations - signal invout_1 : std_logic; - signal invout_0 : std_logic; - signal w_gdata_0 : std_logic; - signal w_gdata_1 : std_logic; - signal w_gdata_2 : std_logic; - signal w_gdata_3 : std_logic; - signal w_gdata_4 : std_logic; - signal wptr_0 : std_logic; - signal wptr_1 : std_logic; - signal wptr_2 : std_logic; - signal wptr_3 : std_logic; - signal wptr_4 : std_logic; - signal wptr_5 : std_logic; - signal r_gdata_0 : std_logic; - signal r_gdata_1 : std_logic; - signal r_gdata_2 : std_logic; - signal r_gdata_3 : std_logic; - signal r_gdata_4 : std_logic; - signal rptr_0 : std_logic; - signal rptr_1 : std_logic; - signal rptr_2 : std_logic; - signal rptr_3 : std_logic; - signal rptr_4 : std_logic; - signal rptr_5 : std_logic; - signal w_gcount_0 : std_logic; - signal w_gcount_1 : std_logic; - signal w_gcount_2 : std_logic; - signal w_gcount_3 : std_logic; - signal w_gcount_4 : std_logic; - signal w_gcount_5 : std_logic; - signal r_gcount_0 : std_logic; - signal r_gcount_1 : std_logic; - signal r_gcount_2 : std_logic; - signal r_gcount_3 : std_logic; - signal r_gcount_4 : std_logic; - signal r_gcount_5 : std_logic; - signal w_gcount_r20 : std_logic; - signal w_gcount_r0 : std_logic; - signal w_gcount_r21 : std_logic; - signal w_gcount_r1 : std_logic; - signal w_gcount_r22 : std_logic; - signal w_gcount_r2 : std_logic; - signal w_gcount_r23 : std_logic; - signal w_gcount_r3 : std_logic; - signal w_gcount_r24 : std_logic; - signal w_gcount_r4 : std_logic; - signal w_gcount_r25 : std_logic; - signal w_gcount_r5 : std_logic; - signal r_gcount_w20 : std_logic; - signal r_gcount_w0 : std_logic; - signal r_gcount_w21 : std_logic; - signal r_gcount_w1 : std_logic; - signal r_gcount_w22 : std_logic; - signal r_gcount_w2 : std_logic; - signal r_gcount_w23 : std_logic; - signal r_gcount_w3 : std_logic; - signal r_gcount_w24 : std_logic; - signal r_gcount_w4 : std_logic; - signal r_gcount_w25 : std_logic; - signal r_gcount_w5 : std_logic; - signal empty_i : std_logic; - signal rRst : std_logic; - signal full_i : std_logic; - signal iwcount_0 : std_logic; - signal iwcount_1 : std_logic; - signal w_gctr_ci : std_logic; - signal iwcount_2 : std_logic; - signal iwcount_3 : std_logic; - signal co0 : std_logic; - signal iwcount_4 : std_logic; - signal iwcount_5 : std_logic; - signal co2 : std_logic; - signal wcount_5 : std_logic; - signal co1 : std_logic; - signal ircount_0 : std_logic; - signal ircount_1 : std_logic; - signal r_gctr_ci : std_logic; - signal ircount_2 : std_logic; - signal ircount_3 : std_logic; - signal co0_1 : std_logic; - signal ircount_4 : std_logic; - signal ircount_5 : std_logic; - signal co2_1 : std_logic; - signal rcount_5 : std_logic; - signal co1_1 : std_logic; - signal rden_i : std_logic; - signal cmp_ci : std_logic; - signal wcount_r0 : std_logic; - signal wcount_r1 : std_logic; - signal rcount_0 : std_logic; - signal rcount_1 : std_logic; - signal co0_2 : std_logic; - signal w_g2b_xor_cluster_0 : std_logic; - signal wcount_r3 : std_logic; - signal rcount_2 : std_logic; - signal rcount_3 : std_logic; - signal co1_2 : std_logic; - signal wcount_r4 : std_logic; - signal empty_cmp_clr : std_logic; - signal rcount_4 : std_logic; - signal empty_cmp_set : std_logic; - signal empty_d : std_logic; - signal empty_d_c : std_logic; - signal cmp_ci_1 : std_logic; - signal wcount_0 : std_logic; - signal wcount_1 : std_logic; - signal co0_3 : std_logic; - signal wcount_2 : std_logic; - signal wcount_3 : std_logic; - signal co1_3 : std_logic; - signal full_cmp_clr : std_logic; - signal wcount_4 : std_logic; - signal full_cmp_set : std_logic; - signal full_d : std_logic; - signal full_d_c : std_logic; - signal scuba_vhi : std_logic; - signal iaf_setcount_0 : std_logic; - signal iaf_setcount_1 : std_logic; - signal af_set_ctr_ci : std_logic; - signal iaf_setcount_2 : std_logic; - signal iaf_setcount_3 : std_logic; - signal co0_4 : std_logic; - signal iaf_setcount_4 : std_logic; - signal iaf_setcount_5 : std_logic; - signal co2_2 : std_logic; - signal af_setcount_5 : std_logic; - signal co1_4 : std_logic; - signal wren_i : std_logic; - signal cmp_ci_2 : std_logic; - signal rcount_w0 : std_logic; - signal rcount_w1 : std_logic; - signal af_setcount_0 : std_logic; - signal af_setcount_1 : std_logic; - signal co0_5 : std_logic; - signal r_g2b_xor_cluster_0 : std_logic; - signal rcount_w3 : std_logic; - signal af_setcount_2 : std_logic; - signal af_setcount_3 : std_logic; - signal co1_5 : std_logic; - signal rcount_w4 : std_logic; - signal af_set_cmp_clr : std_logic; - signal af_setcount_4 : std_logic; - signal af_set_cmp_set : std_logic; - signal af_set : std_logic; - signal af_set_c : std_logic; - signal scuba_vlo : std_logic; - - -- local component declarations - component AGEB2 - port (A0 : in std_logic; A1 : in std_logic; B0 : in std_logic; - B1 : in std_logic; CI : in std_logic; GE : out std_logic); - end component; - component AND2 - port (A : in std_logic; B : in std_logic; Z : out std_logic); - end component; - component CU2 - port (CI : in std_logic; PC0 : in std_logic; PC1 : in std_logic; - CO : out std_logic; NC0 : out std_logic; NC1 : out std_logic); - end component; - component FADD2B - port (A0 : in std_logic; A1 : in std_logic; B0 : in std_logic; - B1 : in std_logic; CI : in std_logic; COUT : out std_logic; - S0 : out std_logic; S1 : out std_logic); - end component; - component FD1P3BX - port (D : in std_logic; SP : in std_logic; CK : in std_logic; - PD : in std_logic; Q : out std_logic); - end component; - component FD1P3DX - port (D : in std_logic; SP : in std_logic; CK : in std_logic; - CD : in std_logic; Q : out std_logic); - end component; - component FD1S3BX - port (D : in std_logic; CK : in std_logic; PD : in std_logic; - Q : out std_logic); - end component; - component FD1S3DX - port (D : in std_logic; CK : in std_logic; CD : in std_logic; - Q : out std_logic); - end component; - component INV - port (A : in std_logic; Z : out std_logic); - end component; - component OR2 - port (A : in std_logic; B : in std_logic; Z : out std_logic); - end component; - component ROM16X1A - generic (INITVAL : in std_logic_vector(15 downto 0)); - port (AD3 : in std_logic; AD2 : in std_logic; AD1 : in std_logic; - AD0 : in std_logic; DO0 : out std_logic); - end component; - component VHI - port (Z : out std_logic); - end component; - component VLO - port (Z : out std_logic); - end component; - component XOR2 - port (A : in std_logic; B : in std_logic; Z : out std_logic); - end component; - component PDPW16KC - generic (GSR : in string; CSDECODE_R : in string; - CSDECODE_W : in string; REGMODE : in string; - DATA_WIDTH_R : in integer; DATA_WIDTH_W : in integer); - port (DI0 : in std_logic; DI1 : in std_logic; DI2 : in std_logic; - DI3 : in std_logic; DI4 : in std_logic; DI5 : in std_logic; - DI6 : in std_logic; DI7 : in std_logic; DI8 : in std_logic; - DI9 : in std_logic; DI10 : in std_logic; DI11 : in std_logic; - DI12 : in std_logic; DI13 : in std_logic; - DI14 : in std_logic; DI15 : in std_logic; - DI16 : in std_logic; DI17 : in std_logic; - DI18 : in std_logic; DI19 : in std_logic; - DI20 : in std_logic; DI21 : in std_logic; - DI22 : in std_logic; DI23 : in std_logic; - DI24 : in std_logic; DI25 : in std_logic; - DI26 : in std_logic; DI27 : in std_logic; - DI28 : in std_logic; DI29 : in std_logic; - DI30 : in std_logic; DI31 : in std_logic; - DI32 : in std_logic; DI33 : in std_logic; - DI34 : in std_logic; DI35 : in std_logic; - ADW0 : in std_logic; ADW1 : in std_logic; - ADW2 : in std_logic; ADW3 : in std_logic; - ADW4 : in std_logic; ADW5 : in std_logic; - ADW6 : in std_logic; ADW7 : in std_logic; - ADW8 : in std_logic; BE0 : in std_logic; BE1 : in std_logic; - BE2 : in std_logic; BE3 : in std_logic; CEW : in std_logic; - CLKW : in std_logic; CSW0 : in std_logic; - CSW1 : in std_logic; CSW2 : in std_logic; - ADR0 : in std_logic; ADR1 : in std_logic; - ADR2 : in std_logic; ADR3 : in std_logic; - ADR4 : in std_logic; ADR5 : in std_logic; - ADR6 : in std_logic; ADR7 : in std_logic; - ADR8 : in std_logic; ADR9 : in std_logic; - ADR10 : in std_logic; ADR11 : in std_logic; - ADR12 : in std_logic; ADR13 : in std_logic; - CER : in std_logic; CLKR : in std_logic; CSR0 : in std_logic; - CSR1 : in std_logic; CSR2 : in std_logic; RST : in std_logic; - DO0 : out std_logic; DO1 : out std_logic; - DO2 : out std_logic; DO3 : out std_logic; - DO4 : out std_logic; DO5 : out std_logic; - DO6 : out std_logic; DO7 : out std_logic; - DO8 : out std_logic; DO9 : out std_logic; - DO10 : out std_logic; DO11 : out std_logic; - DO12 : out std_logic; DO13 : out std_logic; - DO14 : out std_logic; DO15 : out std_logic; - DO16 : out std_logic; DO17 : out std_logic; - DO18 : out std_logic; DO19 : out std_logic; - DO20 : out std_logic; DO21 : out std_logic; - DO22 : out std_logic; DO23 : out std_logic; - DO24 : out std_logic; DO25 : out std_logic; - DO26 : out std_logic; DO27 : out std_logic; - DO28 : out std_logic; DO29 : out std_logic; - DO30 : out std_logic; DO31 : out std_logic; - DO32 : out std_logic; DO33 : out std_logic; - DO34 : out std_logic; DO35 : out std_logic); - end component; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute RESETMODE : string; - attribute GSR : string; - attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "FIFO_32x32_OutReg.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; - attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC"; - attribute GSR of FF_68 : label is "ENABLED"; - attribute GSR of FF_67 : label is "ENABLED"; - attribute GSR of FF_66 : label is "ENABLED"; - attribute GSR of FF_65 : label is "ENABLED"; - attribute GSR of FF_64 : label is "ENABLED"; - attribute GSR of FF_63 : label is "ENABLED"; - attribute GSR of FF_62 : label is "ENABLED"; - attribute GSR of FF_61 : label is "ENABLED"; - attribute GSR of FF_60 : label is "ENABLED"; - attribute GSR of FF_59 : label is "ENABLED"; - attribute GSR of FF_58 : label is "ENABLED"; - attribute GSR of FF_57 : label is "ENABLED"; - attribute GSR of FF_56 : label is "ENABLED"; - attribute GSR of FF_55 : label is "ENABLED"; - attribute GSR of FF_54 : label is "ENABLED"; - attribute GSR of FF_53 : label is "ENABLED"; - attribute GSR of FF_52 : label is "ENABLED"; - attribute GSR of FF_51 : label is "ENABLED"; - attribute GSR of FF_50 : label is "ENABLED"; - attribute GSR of FF_49 : label is "ENABLED"; - attribute GSR of FF_48 : label is "ENABLED"; - attribute GSR of FF_47 : label is "ENABLED"; - attribute GSR of FF_46 : label is "ENABLED"; - attribute GSR of FF_45 : label is "ENABLED"; - attribute GSR of FF_44 : label is "ENABLED"; - attribute GSR of FF_43 : label is "ENABLED"; - attribute GSR of FF_42 : label is "ENABLED"; - attribute GSR of FF_41 : label is "ENABLED"; - attribute GSR of FF_40 : label is "ENABLED"; - attribute GSR of FF_39 : label is "ENABLED"; - attribute GSR of FF_38 : label is "ENABLED"; - attribute GSR of FF_37 : label is "ENABLED"; - attribute GSR of FF_36 : label is "ENABLED"; - attribute GSR of FF_35 : label is "ENABLED"; - attribute GSR of FF_34 : label is "ENABLED"; - attribute GSR of FF_33 : label is "ENABLED"; - attribute GSR of FF_32 : label is "ENABLED"; - attribute GSR of FF_31 : label is "ENABLED"; - attribute GSR of FF_30 : label is "ENABLED"; - attribute GSR of FF_29 : label is "ENABLED"; - attribute GSR of FF_28 : label is "ENABLED"; - attribute GSR of FF_27 : label is "ENABLED"; - attribute GSR of FF_26 : label is "ENABLED"; - attribute GSR of FF_25 : label is "ENABLED"; - attribute GSR of FF_24 : label is "ENABLED"; - attribute GSR of FF_23 : label is "ENABLED"; - attribute GSR of FF_22 : label is "ENABLED"; - attribute GSR of FF_21 : label is "ENABLED"; - attribute GSR of FF_20 : label is "ENABLED"; - attribute GSR of FF_19 : label is "ENABLED"; - attribute GSR of FF_18 : label is "ENABLED"; - attribute GSR of FF_17 : label is "ENABLED"; - attribute GSR of FF_16 : label is "ENABLED"; - attribute GSR of FF_15 : label is "ENABLED"; - attribute GSR of FF_14 : label is "ENABLED"; - attribute GSR of FF_13 : label is "ENABLED"; - attribute GSR of FF_12 : label is "ENABLED"; - attribute GSR of FF_11 : label is "ENABLED"; - attribute GSR of FF_10 : label is "ENABLED"; - attribute GSR of FF_9 : label is "ENABLED"; - attribute GSR of FF_8 : label is "ENABLED"; - attribute GSR of FF_7 : label is "ENABLED"; - attribute GSR of FF_6 : label is "ENABLED"; - attribute GSR of FF_5 : label is "ENABLED"; - attribute GSR of FF_4 : label is "ENABLED"; - attribute GSR of FF_3 : label is "ENABLED"; - attribute GSR of FF_2 : label is "ENABLED"; - attribute GSR of FF_1 : label is "ENABLED"; - attribute GSR of FF_0 : label is "ENABLED"; - attribute syn_keep : boolean; - -begin - -- component instantiation statements - AND2_t12 : AND2 - port map (A => WrEn, B => invout_1, Z => wren_i); - - INV_1 : INV - port map (A => full_i, Z => invout_1); - - AND2_t11 : AND2 - port map (A => RdEn, B => invout_0, Z => rden_i); - - INV_0 : INV - port map (A => empty_i, Z => invout_0); - - OR2_t10 : OR2 - port map (A => Reset, B => RPReset, Z => rRst); - - XOR2_t9 : XOR2 - port map (A => wcount_0, B => wcount_1, Z => w_gdata_0); - - XOR2_t8 : XOR2 - port map (A => wcount_1, B => wcount_2, Z => w_gdata_1); - - XOR2_t7 : XOR2 - port map (A => wcount_2, B => wcount_3, Z => w_gdata_2); - - XOR2_t6 : XOR2 - port map (A => wcount_3, B => wcount_4, Z => w_gdata_3); - - XOR2_t5 : XOR2 - port map (A => wcount_4, B => wcount_5, Z => w_gdata_4); - - XOR2_t4 : XOR2 - port map (A => rcount_0, B => rcount_1, Z => r_gdata_0); - - XOR2_t3 : XOR2 - port map (A => rcount_1, B => rcount_2, Z => r_gdata_1); - - XOR2_t2 : XOR2 - port map (A => rcount_2, B => rcount_3, Z => r_gdata_2); - - XOR2_t1 : XOR2 - port map (A => rcount_3, B => rcount_4, Z => r_gdata_3); - - XOR2_t0 : XOR2 - port map (A => rcount_4, B => rcount_5, Z => r_gdata_4); - - LUT4_15 : ROM16X1A - generic map (initval => X"6996") - port map (AD3 => w_gcount_r22, AD2 => w_gcount_r23, - AD1 => w_gcount_r24, AD0 => w_gcount_r25, - DO0 => w_g2b_xor_cluster_0); - - LUT4_14 : ROM16X1A - generic map (initval => X"6996") - port map (AD3 => w_gcount_r24, AD2 => w_gcount_r25, AD1 => scuba_vlo, - AD0 => scuba_vlo, DO0 => wcount_r4); - - LUT4_13 : ROM16X1A - generic map (initval => X"6996") - port map (AD3 => w_gcount_r23, AD2 => w_gcount_r24, - AD1 => w_gcount_r25, AD0 => scuba_vlo, DO0 => wcount_r3); - - LUT4_12 : ROM16X1A - generic map (initval => X"6996") - port map (AD3 => w_gcount_r21, AD2 => w_gcount_r22, - AD1 => w_gcount_r23, AD0 => wcount_r4, DO0 => wcount_r1); - - LUT4_11 : ROM16X1A - generic map (initval => X"6996") - port map (AD3 => w_gcount_r20, AD2 => w_gcount_r21, - AD1 => w_gcount_r22, AD0 => wcount_r3, DO0 => wcount_r0); - - LUT4_10 : ROM16X1A - generic map (initval => X"6996") - port map (AD3 => r_gcount_w22, AD2 => r_gcount_w23, - AD1 => r_gcount_w24, AD0 => r_gcount_w25, - DO0 => r_g2b_xor_cluster_0); - - LUT4_9 : ROM16X1A - generic map (initval => X"6996") - port map (AD3 => r_gcount_w24, AD2 => r_gcount_w25, AD1 => scuba_vlo, - AD0 => scuba_vlo, DO0 => rcount_w4); - - LUT4_8 : ROM16X1A - generic map (initval => X"6996") - port map (AD3 => r_gcount_w23, AD2 => r_gcount_w24, - AD1 => r_gcount_w25, AD0 => scuba_vlo, DO0 => rcount_w3); - - LUT4_7 : ROM16X1A - generic map (initval => X"6996") - port map (AD3 => r_gcount_w21, AD2 => r_gcount_w22, - AD1 => r_gcount_w23, AD0 => rcount_w4, DO0 => rcount_w1); - - LUT4_6 : ROM16X1A - generic map (initval => X"6996") - port map (AD3 => r_gcount_w20, AD2 => r_gcount_w21, - AD1 => r_gcount_w22, AD0 => rcount_w3, DO0 => rcount_w0); - - LUT4_5 : ROM16X1A - generic map (initval => X"0410") - port map (AD3 => rptr_5, AD2 => rcount_5, AD1 => w_gcount_r25, - AD0 => scuba_vlo, DO0 => empty_cmp_set); - - LUT4_4 : ROM16X1A - generic map (initval => X"1004") - port map (AD3 => rptr_5, AD2 => rcount_5, AD1 => w_gcount_r25, - AD0 => scuba_vlo, DO0 => empty_cmp_clr); - - LUT4_3 : ROM16X1A - generic map (initval => X"0140") - port map (AD3 => wptr_5, AD2 => wcount_5, AD1 => r_gcount_w25, - AD0 => scuba_vlo, DO0 => full_cmp_set); - - LUT4_2 : ROM16X1A - generic map (initval => X"4001") - port map (AD3 => wptr_5, AD2 => wcount_5, AD1 => r_gcount_w25, - AD0 => scuba_vlo, DO0 => full_cmp_clr); - - LUT4_1 : ROM16X1A - generic map (initval => X"4c32") - port map (AD3 => af_setcount_5, AD2 => wcount_5, AD1 => r_gcount_w25, - AD0 => wptr_5, DO0 => af_set_cmp_set); - - LUT4_0 : ROM16X1A - generic map (initval => X"8001") - port map (AD3 => af_setcount_5, AD2 => wcount_5, AD1 => r_gcount_w25, - AD0 => wptr_5, DO0 => af_set_cmp_clr); - - pdp_ram_0_0_0 : PDPW16KC - generic map (CSDECODE_R => "0b001", CSDECODE_W => "0b001", GSR => "DISABLED", - REGMODE => "OUTREG", DATA_WIDTH_R => 36, DATA_WIDTH_W => 36) - port map (DI0 => Data(0), DI1 => Data(1), DI2 => Data(2), DI3 => Data(3), - DI4 => Data(4), DI5 => Data(5), DI6 => Data(6), DI7 => Data(7), - DI8 => Data(8), DI9 => Data(9), DI10 => Data(10), DI11 => Data(11), - DI12 => Data(12), DI13 => Data(13), DI14 => Data(14), - DI15 => Data(15), DI16 => Data(16), DI17 => Data(17), - DI18 => Data(18), DI19 => Data(19), DI20 => Data(20), - DI21 => Data(21), DI22 => Data(22), DI23 => Data(23), - DI24 => Data(24), DI25 => Data(25), DI26 => Data(26), - DI27 => Data(27), DI28 => Data(28), DI29 => Data(29), - DI30 => Data(30), DI31 => Data(31), DI32 => scuba_vlo, - DI33 => scuba_vlo, DI34 => scuba_vlo, DI35 => scuba_vlo, - ADW0 => wptr_0, ADW1 => wptr_1, ADW2 => wptr_2, ADW3 => wptr_3, - ADW4 => wptr_4, ADW5 => scuba_vlo, ADW6 => scuba_vlo, - ADW7 => scuba_vlo, ADW8 => scuba_vlo, BE0 => scuba_vhi, - BE1 => scuba_vhi, BE2 => scuba_vhi, BE3 => scuba_vhi, CEW => wren_i, - CLKW => WrClock, CSW0 => scuba_vhi, CSW1 => scuba_vlo, - CSW2 => scuba_vlo, ADR0 => scuba_vlo, ADR1 => scuba_vlo, - ADR2 => scuba_vlo, ADR3 => scuba_vlo, ADR4 => scuba_vlo, - ADR5 => rptr_0, ADR6 => rptr_1, ADR7 => rptr_2, ADR8 => rptr_3, - ADR9 => rptr_4, ADR10 => scuba_vlo, ADR11 => scuba_vlo, - ADR12 => scuba_vlo, ADR13 => scuba_vlo, CER => scuba_vhi, - CLKR => RdClock, CSR0 => rden_i, CSR1 => scuba_vlo, - CSR2 => scuba_vlo, RST => Reset, DO0 => Q(18), DO1 => Q(19), - DO2 => Q(20), DO3 => Q(21), DO4 => Q(22), DO5 => Q(23), DO6 => Q(24), - DO7 => Q(25), DO8 => Q(26), DO9 => Q(27), DO10 => Q(28), DO11 => Q(29), - DO12 => Q(30), DO13 => Q(31), DO14 => open, DO15 => open, DO16 => open, - DO17 => open, DO18 => Q(0), DO19 => Q(1), DO20 => Q(2), DO21 => Q(3), - DO22 => Q(4), DO23 => Q(5), DO24 => Q(6), DO25 => Q(7), DO26 => Q(8), - DO27 => Q(9), DO28 => Q(10), DO29 => Q(11), DO30 => Q(12), - DO31 => Q(13), DO32 => Q(14), DO33 => Q(15), DO34 => Q(16), - DO35 => Q(17)); - - FF_68 : FD1P3BX - port map (D => iwcount_0, SP => wren_i, CK => WrClock, PD => Reset, - Q => wcount_0); - - FF_67 : FD1P3DX - port map (D => iwcount_1, SP => wren_i, CK => WrClock, CD => Reset, - Q => wcount_1); - - FF_66 : FD1P3DX - port map (D => iwcount_2, SP => wren_i, CK => WrClock, CD => Reset, - Q => wcount_2); - - FF_65 : FD1P3DX - port map (D => iwcount_3, SP => wren_i, CK => WrClock, CD => Reset, - Q => wcount_3); - - FF_64 : FD1P3DX - port map (D => iwcount_4, SP => wren_i, CK => WrClock, CD => Reset, - Q => wcount_4); - - FF_63 : FD1P3DX - port map (D => iwcount_5, SP => wren_i, CK => WrClock, CD => Reset, - Q => wcount_5); - - FF_62 : FD1P3DX - port map (D => w_gdata_0, SP => wren_i, CK => WrClock, CD => Reset, - Q => w_gcount_0); - - FF_61 : FD1P3DX - port map (D => w_gdata_1, SP => wren_i, CK => WrClock, CD => Reset, - Q => w_gcount_1); - - FF_60 : FD1P3DX - port map (D => w_gdata_2, SP => wren_i, CK => WrClock, CD => Reset, - Q => w_gcount_2); - - FF_59 : FD1P3DX - port map (D => w_gdata_3, SP => wren_i, CK => WrClock, CD => Reset, - Q => w_gcount_3); - - FF_58 : FD1P3DX - port map (D => w_gdata_4, SP => wren_i, CK => WrClock, CD => Reset, - Q => w_gcount_4); - - FF_57 : FD1P3DX - port map (D => wcount_5, SP => wren_i, CK => WrClock, CD => Reset, - Q => w_gcount_5); - - FF_56 : FD1P3DX - port map (D => wcount_0, SP => wren_i, CK => WrClock, CD => Reset, - Q => wptr_0); - - FF_55 : FD1P3DX - port map (D => wcount_1, SP => wren_i, CK => WrClock, CD => Reset, - Q => wptr_1); - - FF_54 : FD1P3DX - port map (D => wcount_2, SP => wren_i, CK => WrClock, CD => Reset, - Q => wptr_2); - - FF_53 : FD1P3DX - port map (D => wcount_3, SP => wren_i, CK => WrClock, CD => Reset, - Q => wptr_3); - - FF_52 : FD1P3DX - port map (D => wcount_4, SP => wren_i, CK => WrClock, CD => Reset, - Q => wptr_4); - - FF_51 : FD1P3DX - port map (D => wcount_5, SP => wren_i, CK => WrClock, CD => Reset, - Q => wptr_5); - - FF_50 : FD1P3BX - port map (D => ircount_0, SP => rden_i, CK => RdClock, PD => rRst, - Q => rcount_0); - - FF_49 : FD1P3DX - port map (D => ircount_1, SP => rden_i, CK => RdClock, CD => rRst, - Q => rcount_1); - - FF_48 : FD1P3DX - port map (D => ircount_2, SP => rden_i, CK => RdClock, CD => rRst, - Q => rcount_2); - - FF_47 : FD1P3DX - port map (D => ircount_3, SP => rden_i, CK => RdClock, CD => rRst, - Q => rcount_3); - - FF_46 : FD1P3DX - port map (D => ircount_4, SP => rden_i, CK => RdClock, CD => rRst, - Q => rcount_4); - - FF_45 : FD1P3DX - port map (D => ircount_5, SP => rden_i, CK => RdClock, CD => rRst, - Q => rcount_5); - - FF_44 : FD1P3DX - port map (D => r_gdata_0, SP => rden_i, CK => RdClock, CD => rRst, - Q => r_gcount_0); - - FF_43 : FD1P3DX - port map (D => r_gdata_1, SP => rden_i, CK => RdClock, CD => rRst, - Q => r_gcount_1); - - FF_42 : FD1P3DX - port map (D => r_gdata_2, SP => rden_i, CK => RdClock, CD => rRst, - Q => r_gcount_2); - - FF_41 : FD1P3DX - port map (D => r_gdata_3, SP => rden_i, CK => RdClock, CD => rRst, - Q => r_gcount_3); - - FF_40 : FD1P3DX - port map (D => r_gdata_4, SP => rden_i, CK => RdClock, CD => rRst, - Q => r_gcount_4); - - FF_39 : FD1P3DX - port map (D => rcount_5, SP => rden_i, CK => RdClock, CD => rRst, - Q => r_gcount_5); - - FF_38 : FD1P3DX - port map (D => rcount_0, SP => rden_i, CK => RdClock, CD => rRst, - Q => rptr_0); - - FF_37 : FD1P3DX - port map (D => rcount_1, SP => rden_i, CK => RdClock, CD => rRst, - Q => rptr_1); - - FF_36 : FD1P3DX - port map (D => rcount_2, SP => rden_i, CK => RdClock, CD => rRst, - Q => rptr_2); - - FF_35 : FD1P3DX - port map (D => rcount_3, SP => rden_i, CK => RdClock, CD => rRst, - Q => rptr_3); - - FF_34 : FD1P3DX - port map (D => rcount_4, SP => rden_i, CK => RdClock, CD => rRst, - Q => rptr_4); - - FF_33 : FD1P3DX - port map (D => rcount_5, SP => rden_i, CK => RdClock, CD => rRst, - Q => rptr_5); - - FF_32 : FD1S3DX - port map (D => w_gcount_0, CK => RdClock, CD => Reset, Q => w_gcount_r0); - - FF_31 : FD1S3DX - port map (D => w_gcount_1, CK => RdClock, CD => Reset, Q => w_gcount_r1); - - FF_30 : FD1S3DX - port map (D => w_gcount_2, CK => RdClock, CD => Reset, Q => w_gcount_r2); - - FF_29 : FD1S3DX - port map (D => w_gcount_3, CK => RdClock, CD => Reset, Q => w_gcount_r3); - - FF_28 : FD1S3DX - port map (D => w_gcount_4, CK => RdClock, CD => Reset, Q => w_gcount_r4); - - FF_27 : FD1S3DX - port map (D => w_gcount_5, CK => RdClock, CD => Reset, Q => w_gcount_r5); - - FF_26 : FD1S3DX - port map (D => r_gcount_0, CK => WrClock, CD => rRst, Q => r_gcount_w0); - - FF_25 : FD1S3DX - port map (D => r_gcount_1, CK => WrClock, CD => rRst, Q => r_gcount_w1); - - FF_24 : FD1S3DX - port map (D => r_gcount_2, CK => WrClock, CD => rRst, Q => r_gcount_w2); - - FF_23 : FD1S3DX - port map (D => r_gcount_3, CK => WrClock, CD => rRst, Q => r_gcount_w3); - - FF_22 : FD1S3DX - port map (D => r_gcount_4, CK => WrClock, CD => rRst, Q => r_gcount_w4); - - FF_21 : FD1S3DX - port map (D => r_gcount_5, CK => WrClock, CD => rRst, Q => r_gcount_w5); - - FF_20 : FD1S3DX - port map (D => w_gcount_r0, CK => RdClock, CD => Reset, - Q => w_gcount_r20); - - FF_19 : FD1S3DX - port map (D => w_gcount_r1, CK => RdClock, CD => Reset, - Q => w_gcount_r21); - - FF_18 : FD1S3DX - port map (D => w_gcount_r2, CK => RdClock, CD => Reset, - Q => w_gcount_r22); - - FF_17 : FD1S3DX - port map (D => w_gcount_r3, CK => RdClock, CD => Reset, - Q => w_gcount_r23); - - FF_16 : FD1S3DX - port map (D => w_gcount_r4, CK => RdClock, CD => Reset, - Q => w_gcount_r24); - - FF_15 : FD1S3DX - port map (D => w_gcount_r5, CK => RdClock, CD => Reset, - Q => w_gcount_r25); - - FF_14 : FD1S3DX - port map (D => r_gcount_w0, CK => WrClock, CD => rRst, Q => r_gcount_w20); - - FF_13 : FD1S3DX - port map (D => r_gcount_w1, CK => WrClock, CD => rRst, Q => r_gcount_w21); - - FF_12 : FD1S3DX - port map (D => r_gcount_w2, CK => WrClock, CD => rRst, Q => r_gcount_w22); - - FF_11 : FD1S3DX - port map (D => r_gcount_w3, CK => WrClock, CD => rRst, Q => r_gcount_w23); - - FF_10 : FD1S3DX - port map (D => r_gcount_w4, CK => WrClock, CD => rRst, Q => r_gcount_w24); - - FF_9 : FD1S3DX - port map (D => r_gcount_w5, CK => WrClock, CD => rRst, Q => r_gcount_w25); - - FF_8 : FD1S3BX - port map (D => empty_d, CK => RdClock, PD => rRst, Q => empty_i); - - FF_7 : FD1S3DX - port map (D => full_d, CK => WrClock, CD => Reset, Q => full_i); - - FF_6 : FD1P3BX - port map (D => iaf_setcount_0, SP => wren_i, CK => WrClock, PD => Reset, - Q => af_setcount_0); - - FF_5 : FD1P3DX - port map (D => iaf_setcount_1, SP => wren_i, CK => WrClock, CD => Reset, - Q => af_setcount_1); - - FF_4 : FD1P3BX - port map (D => iaf_setcount_2, SP => wren_i, CK => WrClock, PD => Reset, - Q => af_setcount_2); - - FF_3 : FD1P3DX - port map (D => iaf_setcount_3, SP => wren_i, CK => WrClock, CD => Reset, - Q => af_setcount_3); - - FF_2 : FD1P3DX - port map (D => iaf_setcount_4, SP => wren_i, CK => WrClock, CD => Reset, - Q => af_setcount_4); - - FF_1 : FD1P3DX - port map (D => iaf_setcount_5, SP => wren_i, CK => WrClock, CD => Reset, - Q => af_setcount_5); - - FF_0 : FD1S3DX - port map (D => af_set, CK => WrClock, CD => Reset, Q => AlmostFull); - - w_gctr_cia : FADD2B - port map (A0 => scuba_vlo, A1 => scuba_vhi, B0 => scuba_vlo, - B1 => scuba_vhi, CI => scuba_vlo, COUT => w_gctr_ci, S0 => open, - S1 => open); - - w_gctr_0 : CU2 - port map (CI => w_gctr_ci, PC0 => wcount_0, PC1 => wcount_1, CO => co0, - NC0 => iwcount_0, NC1 => iwcount_1); - - w_gctr_1 : CU2 - port map (CI => co0, PC0 => wcount_2, PC1 => wcount_3, CO => co1, - NC0 => iwcount_2, NC1 => iwcount_3); - - w_gctr_2 : CU2 - port map (CI => co1, PC0 => wcount_4, PC1 => wcount_5, CO => co2, - NC0 => iwcount_4, NC1 => iwcount_5); - - r_gctr_cia : FADD2B - port map (A0 => scuba_vlo, A1 => scuba_vhi, B0 => scuba_vlo, - B1 => scuba_vhi, CI => scuba_vlo, COUT => r_gctr_ci, S0 => open, - S1 => open); - - r_gctr_0 : CU2 - port map (CI => r_gctr_ci, PC0 => rcount_0, PC1 => rcount_1, CO => co0_1, - NC0 => ircount_0, NC1 => ircount_1); - - r_gctr_1 : CU2 - port map (CI => co0_1, PC0 => rcount_2, PC1 => rcount_3, CO => co1_1, - NC0 => ircount_2, NC1 => ircount_3); - - r_gctr_2 : CU2 - port map (CI => co1_1, PC0 => rcount_4, PC1 => rcount_5, CO => co2_1, - NC0 => ircount_4, NC1 => ircount_5); - - empty_cmp_ci_a : FADD2B - port map (A0 => scuba_vlo, A1 => rden_i, B0 => scuba_vlo, B1 => rden_i, - CI => scuba_vlo, COUT => cmp_ci, S0 => open, S1 => open); - - empty_cmp_0 : AGEB2 - port map (A0 => rcount_0, A1 => rcount_1, B0 => wcount_r0, - B1 => wcount_r1, CI => cmp_ci, GE => co0_2); - - empty_cmp_1 : AGEB2 - port map (A0 => rcount_2, A1 => rcount_3, B0 => w_g2b_xor_cluster_0, - B1 => wcount_r3, CI => co0_2, GE => co1_2); - - empty_cmp_2 : AGEB2 - port map (A0 => rcount_4, A1 => empty_cmp_set, B0 => wcount_r4, - B1 => empty_cmp_clr, CI => co1_2, GE => empty_d_c); - - a0 : FADD2B - port map (A0 => scuba_vlo, A1 => scuba_vlo, B0 => scuba_vlo, - B1 => scuba_vlo, CI => empty_d_c, COUT => open, S0 => empty_d, - S1 => open); - - full_cmp_ci_a : FADD2B - port map (A0 => scuba_vlo, A1 => wren_i, B0 => scuba_vlo, B1 => wren_i, - CI => scuba_vlo, COUT => cmp_ci_1, S0 => open, S1 => open); - - full_cmp_0 : AGEB2 - port map (A0 => wcount_0, A1 => wcount_1, B0 => rcount_w0, - B1 => rcount_w1, CI => cmp_ci_1, GE => co0_3); - - full_cmp_1 : AGEB2 - port map (A0 => wcount_2, A1 => wcount_3, B0 => r_g2b_xor_cluster_0, - B1 => rcount_w3, CI => co0_3, GE => co1_3); - - full_cmp_2 : AGEB2 - port map (A0 => wcount_4, A1 => full_cmp_set, B0 => rcount_w4, - B1 => full_cmp_clr, CI => co1_3, GE => full_d_c); - - a1 : FADD2B - port map (A0 => scuba_vlo, A1 => scuba_vlo, B0 => scuba_vlo, - B1 => scuba_vlo, CI => full_d_c, COUT => open, S0 => full_d, - S1 => open); - - scuba_vhi_inst : VHI - port map (Z => scuba_vhi); - - af_set_ctr_cia : FADD2B - port map (A0 => scuba_vlo, A1 => scuba_vhi, B0 => scuba_vlo, - B1 => scuba_vhi, CI => scuba_vlo, COUT => af_set_ctr_ci, S0 => open, - S1 => open); - - af_set_ctr_0 : CU2 - port map (CI => af_set_ctr_ci, PC0 => af_setcount_0, - PC1 => af_setcount_1, CO => co0_4, NC0 => iaf_setcount_0, - NC1 => iaf_setcount_1); - - af_set_ctr_1 : CU2 - port map (CI => co0_4, PC0 => af_setcount_2, PC1 => af_setcount_3, - CO => co1_4, NC0 => iaf_setcount_2, NC1 => iaf_setcount_3); - - af_set_ctr_2 : CU2 - port map (CI => co1_4, PC0 => af_setcount_4, PC1 => af_setcount_5, - CO => co2_2, NC0 => iaf_setcount_4, NC1 => iaf_setcount_5); - - af_set_cmp_ci_a : FADD2B - port map (A0 => scuba_vlo, A1 => wren_i, B0 => scuba_vlo, B1 => wren_i, - CI => scuba_vlo, COUT => cmp_ci_2, S0 => open, S1 => open); - - af_set_cmp_0 : AGEB2 - port map (A0 => af_setcount_0, A1 => af_setcount_1, B0 => rcount_w0, - B1 => rcount_w1, CI => cmp_ci_2, GE => co0_5); - - af_set_cmp_1 : AGEB2 - port map (A0 => af_setcount_2, A1 => af_setcount_3, - B0 => r_g2b_xor_cluster_0, B1 => rcount_w3, CI => co0_5, GE => co1_5); - - af_set_cmp_2 : AGEB2 - port map (A0 => af_setcount_4, A1 => af_set_cmp_set, B0 => rcount_w4, - B1 => af_set_cmp_clr, CI => co1_5, GE => af_set_c); - - scuba_vlo_inst : VLO - port map (Z => scuba_vlo); - - a2 : FADD2B - port map (A0 => scuba_vlo, A1 => scuba_vlo, B0 => scuba_vlo, - B1 => scuba_vlo, CI => af_set_c, COUT => open, S0 => af_set, - S1 => open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp3; -configuration Structure_CON of FIFO_32x32_OutReg is - for Structure - for all : AGEB2 use entity ecp3.AGEB2(V); end for; - for all : AND2 use entity ecp3.AND2(V); end for; - for all : CU2 use entity ecp3.CU2(V); end for; - for all : FADD2B use entity ecp3.FADD2B(V); end for; - for all : FD1P3BX use entity ecp3.FD1P3BX(V); end for; - for all : FD1P3DX use entity ecp3.FD1P3DX(V); end for; - for all : FD1S3BX use entity ecp3.FD1S3BX(V); end for; - for all : FD1S3DX use entity ecp3.FD1S3DX(V); end for; - for all : INV use entity ecp3.INV(V); end for; - for all : OR2 use entity ecp3.OR2(V); end for; - for all : ROM16X1A use entity ecp3.ROM16X1A(V); end for; - for all : VHI use entity ecp3.VHI(V); end for; - for all : VLO use entity ecp3.VLO(V); end for; - for all : XOR2 use entity ecp3.XOR2(V); end for; - for all : PDPW16KC use entity ecp3.PDPW16KC(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/tdc_releases/tdc_v_stretcher/LogicAnalyser.vhd b/tdc_releases/tdc_v_stretcher/LogicAnalyser.vhd deleted file mode 100644 index 66df513..0000000 --- a/tdc_releases/tdc_v_stretcher/LogicAnalyser.vhd +++ /dev/null @@ -1,80 +0,0 @@ -------------------------------------------------------------------------------- --- Title : Logic Analyser Signals --- Project : -------------------------------------------------------------------------------- --- File : LogicAnalyser.vhd --- Author : cugur@gsi.de --- Created : 2012-10-26 --- Last update: 2012-10-26 -------------------------------------------------------------------------------- --- Description: -------------------------------------------------------------------------------- - -library IEEE; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb3_components.all; - -entity LogicAnalyser is - generic ( - CHANNEL_NUMBER : integer range 2 to 65; - STATUS_REG_NR : integer range 0 to 6); - - port ( - CLK : in std_logic; - RESET : in std_logic; --- - DATA_IN : in std_logic_vector(3*32-1 downto 0); - CONTROL_IN : in std_logic_vector(3 downto 0); - DATA_OUT : out std_logic_vector(15 downto 0) - ); - -end LogicAnalyser; - - -architecture behavioral of LogicAnalyser is - - signal mux_out : std_logic_vector(15 downto 0); - -begin -- behavioral - -------------------------------------------------------------------------------- --- Logic Analyser Signals -------------------------------------------------------------------------------- - REG_LOGIC_ANALYSER_OUTPUT : process (CLK, RESET) - begin - if rising_edge(CLK) then - if RESET = '1' then - mux_out <= (others => '0'); - elsif CONTROL_IN = x"1" then -- TRBNET connections debugging - mux_out(7 downto 0) <= DATA_IN(7 downto 0); --fsm_debug; - mux_out(8) <= DATA_IN(8); --REFERENCE_TIME; - mux_out(9) <= DATA_IN(9); --VALID_TIMING_TRG_IN; - mux_out(10) <= DATA_IN(10); --VALID_NOTIMING_TRG_IN; - mux_out(11) <= DATA_IN(11); --INVALID_TRG_IN; - mux_out(12) <= DATA_IN(12); --TRG_DATA_VALID_IN; - mux_out(13) <= DATA_IN(13); --data_wr_reg; - mux_out(14) <= DATA_IN(14); --data_finished_reg; - mux_out(15) <= DATA_IN(15); --trg_release_reg; - elsif CONTROL_IN = x"2" then -- Reference channel debugging - mux_out <= DATA_IN(31 downto 16); --ref_debug_i(15 downto 0); - elsif CONTROL_IN = x"3" then -- Data out - mux_out(7 downto 0) <= DATA_IN(7 downto 0); --fsm_debug; - mux_out(8) <= DATA_IN(8); --REFERENCE_TIME; - mux_out(9) <= DATA_IN(13); --data_wr_reg; - mux_out(15 downto 10) <= DATA_IN(37 downto 32); --data_out_reg(27 downto 22); - - --elsif CONTROL_IN = x"4" then -- channel debugging - -- mux_out <= DATA_IN(); --ch_debug_i(1)(15 downto 0); - end if; - end if; - end process REG_LOGIC_ANALYSER_OUTPUT; - - DATA_OUT <= mux_out; - - -end behavioral; diff --git a/tdc_releases/tdc_v_stretcher/ROM_FIFO.vhd b/tdc_releases/tdc_v_stretcher/ROM_FIFO.vhd deleted file mode 100644 index efc10c3..0000000 --- a/tdc_releases/tdc_v_stretcher/ROM_FIFO.vhd +++ /dev/null @@ -1,262 +0,0 @@ --- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 5.0 ---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 00 -rp 1100 -addr_width 8 -data_width 4 -num_rows 256 -memfile /home/ugur/Projects/trb3/tdc_test/ipexpress/ROM_FIFO/rom0_mem_file.mem -memformat hex -cascade -1 -e - --- Fri Nov 11 12:43:08 2011 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp3; -use ecp3.components.all; --- synopsys translate_on - -entity ROM_FIFO is - port ( - Address : in std_logic_vector(7 downto 0); - OutClock : in std_logic; - OutClockEn : in std_logic; - Reset : in std_logic; - Q : out std_logic_vector(3 downto 0)); -end ROM_FIFO; - -architecture Structure of ROM_FIFO is - - -- internal signal declarations - signal scuba_vhi : std_logic; - signal scuba_vlo : std_logic; - - -- local component declarations - component VHI - port (Z : out std_logic); - end component; - component VLO - port (Z : out std_logic); - end component; - component DP16KC - generic (INITVAL_3F : in string; INITVAL_3E : in string; - INITVAL_3D : in string; INITVAL_3C : in string; - INITVAL_3B : in string; INITVAL_3A : in string; - INITVAL_39 : in string; INITVAL_38 : in string; - INITVAL_37 : in string; INITVAL_36 : in string; - INITVAL_35 : in string; INITVAL_34 : in string; - INITVAL_33 : in string; INITVAL_32 : in string; - INITVAL_31 : in string; INITVAL_30 : in string; - INITVAL_2F : in string; INITVAL_2E : in string; - INITVAL_2D : in string; INITVAL_2C : in string; - INITVAL_2B : in string; INITVAL_2A : in string; - INITVAL_29 : in string; INITVAL_28 : in string; - INITVAL_27 : in string; INITVAL_26 : in string; - INITVAL_25 : in string; INITVAL_24 : in string; - INITVAL_23 : in string; INITVAL_22 : in string; - INITVAL_21 : in string; INITVAL_20 : in string; - INITVAL_1F : in string; INITVAL_1E : in string; - INITVAL_1D : in string; INITVAL_1C : in string; - INITVAL_1B : in string; INITVAL_1A : in string; - INITVAL_19 : in string; INITVAL_18 : in string; - INITVAL_17 : in string; INITVAL_16 : in string; - INITVAL_15 : in string; INITVAL_14 : in string; - INITVAL_13 : in string; INITVAL_12 : in string; - INITVAL_11 : in string; INITVAL_10 : in string; - INITVAL_0F : in string; INITVAL_0E : in string; - INITVAL_0D : in string; INITVAL_0C : in string; - INITVAL_0B : in string; INITVAL_0A : in string; - INITVAL_09 : in string; INITVAL_08 : in string; - INITVAL_07 : in string; INITVAL_06 : in string; - INITVAL_05 : in string; INITVAL_04 : in string; - INITVAL_03 : in string; INITVAL_02 : in string; - INITVAL_01 : in string; INITVAL_00 : in string; - GSR : in string; WRITEMODE_B : in string; - WRITEMODE_A : in string; CSDECODE_B : in string; - CSDECODE_A : in string; REGMODE_B : in string; - REGMODE_A : in string; DATA_WIDTH_B : in integer; - DATA_WIDTH_A : in integer); - port (DIA0 : in std_logic; DIA1 : in std_logic; - DIA2 : in std_logic; DIA3 : in std_logic; - DIA4 : in std_logic; DIA5 : in std_logic; - DIA6 : in std_logic; DIA7 : in std_logic; - DIA8 : in std_logic; DIA9 : in std_logic; - DIA10 : in std_logic; DIA11 : in std_logic; - DIA12 : in std_logic; DIA13 : in std_logic; - DIA14 : in std_logic; DIA15 : in std_logic; - DIA16 : in std_logic; DIA17 : in std_logic; - ADA0 : in std_logic; ADA1 : in std_logic; - ADA2 : in std_logic; ADA3 : in std_logic; - ADA4 : in std_logic; ADA5 : in std_logic; - ADA6 : in std_logic; ADA7 : in std_logic; - ADA8 : in std_logic; ADA9 : in std_logic; - ADA10 : in std_logic; ADA11 : in std_logic; - ADA12 : in std_logic; ADA13 : in std_logic; - CEA : in std_logic; CLKA : in std_logic; OCEA : in std_logic; - WEA : in std_logic; CSA0 : in std_logic; CSA1 : in std_logic; - CSA2 : in std_logic; RSTA : in std_logic; - DIB0 : in std_logic; DIB1 : in std_logic; - DIB2 : in std_logic; DIB3 : in std_logic; - DIB4 : in std_logic; DIB5 : in std_logic; - DIB6 : in std_logic; DIB7 : in std_logic; - DIB8 : in std_logic; DIB9 : in std_logic; - DIB10 : in std_logic; DIB11 : in std_logic; - DIB12 : in std_logic; DIB13 : in std_logic; - DIB14 : in std_logic; DIB15 : in std_logic; - DIB16 : in std_logic; DIB17 : in std_logic; - ADB0 : in std_logic; ADB1 : in std_logic; - ADB2 : in std_logic; ADB3 : in std_logic; - ADB4 : in std_logic; ADB5 : in std_logic; - ADB6 : in std_logic; ADB7 : in std_logic; - ADB8 : in std_logic; ADB9 : in std_logic; - ADB10 : in std_logic; ADB11 : in std_logic; - ADB12 : in std_logic; ADB13 : in std_logic; - CEB : in std_logic; CLKB : in std_logic; OCEB : in std_logic; - WEB : in std_logic; CSB0 : in std_logic; CSB1 : in std_logic; - CSB2 : in std_logic; RSTB : in std_logic; - DOA0 : out std_logic; DOA1 : out std_logic; - DOA2 : out std_logic; DOA3 : out std_logic; - DOA4 : out std_logic; DOA5 : out std_logic; - DOA6 : out std_logic; DOA7 : out std_logic; - DOA8 : out std_logic; DOA9 : out std_logic; - DOA10 : out std_logic; DOA11 : out std_logic; - DOA12 : out std_logic; DOA13 : out std_logic; - DOA14 : out std_logic; DOA15 : out std_logic; - DOA16 : out std_logic; DOA17 : out std_logic; - DOB0 : out std_logic; DOB1 : out std_logic; - DOB2 : out std_logic; DOB3 : out std_logic; - DOB4 : out std_logic; DOB5 : out std_logic; - DOB6 : out std_logic; DOB7 : out std_logic; - DOB8 : out std_logic; DOB9 : out std_logic; - DOB10 : out std_logic; DOB11 : out std_logic; - DOB12 : out std_logic; DOB13 : out std_logic; - DOB14 : out std_logic; DOB15 : out std_logic; - DOB16 : out std_logic; DOB17 : out std_logic); - end component; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute RESETMODE : string; - attribute MEM_LPC_FILE of ROM_FIFO_0_0_0 : label is "ROM_FIFO.lpc"; - attribute MEM_INIT_FILE of ROM_FIFO_0_0_0 : label is "rom0_mem_file.mem"; - attribute RESETMODE of ROM_FIFO_0_0_0 : label is "SYNC"; - -begin - -- component instantiation statements - scuba_vhi_inst : VHI - port map (Z => scuba_vhi); - - scuba_vlo_inst : VLO - port map (Z => scuba_vlo); - - ROM_FIFO_0_0_0 : DP16KC - generic map (INITVAL_3F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_39 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_38 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_37 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_36 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_35 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_34 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_33 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_32 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_31 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_30 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_29 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_28 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_27 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_26 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_25 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_24 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_23 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_22 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_21 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_20 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_19 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_18 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_17 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_16 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_15 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_14 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_13 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_12 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_11 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_10 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_09 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_08 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_07 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_06 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_05 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_04 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_03 => "0x10010040100601004010080100401006010040100A01004010060100401008010040100601004010", - INITVAL_02 => "0x0C010040100601004010080100401006010040100A01004010060100401008010040100601004010", - INITVAL_01 => "0x0E010040100601004010080100401006010040100A01004010060100401008010040100601004010", - INITVAL_00 => "0x0C010040100601004010080100401006010040100A01004010060100401008010040100601004010", - CSDECODE_B => "0b111", CSDECODE_A => "0b000", WRITEMODE_B => "NORMAL", - WRITEMODE_A => "NORMAL", GSR => "DISABLED", REGMODE_B => "NOREG", - REGMODE_A => "NOREG", DATA_WIDTH_B => 4, DATA_WIDTH_A => 4) - port map (DIA0 => scuba_vlo, DIA1 => scuba_vlo, DIA2 => scuba_vlo, - DIA3 => scuba_vlo, DIA4 => scuba_vlo, DIA5 => scuba_vlo, - DIA6 => scuba_vlo, DIA7 => scuba_vlo, DIA8 => scuba_vlo, - DIA9 => scuba_vlo, DIA10 => scuba_vlo, DIA11 => scuba_vlo, - DIA12 => scuba_vlo, DIA13 => scuba_vlo, DIA14 => scuba_vlo, - DIA15 => scuba_vlo, DIA16 => scuba_vlo, DIA17 => scuba_vlo, - ADA0 => scuba_vlo, ADA1 => scuba_vlo, ADA2 => Address(0), - ADA3 => Address(1), ADA4 => Address(2), ADA5 => Address(3), - ADA6 => Address(4), ADA7 => Address(5), ADA8 => Address(6), - ADA9 => Address(7), ADA10 => scuba_vlo, ADA11 => scuba_vlo, - ADA12 => scuba_vlo, ADA13 => scuba_vlo, CEA => OutClockEn, - CLKA => OutClock, OCEA => OutClockEn, WEA => scuba_vlo, - CSA0 => scuba_vlo, CSA1 => scuba_vlo, CSA2 => scuba_vlo, - RSTA => Reset, DIB0 => scuba_vlo, DIB1 => scuba_vlo, - DIB2 => scuba_vlo, DIB3 => scuba_vlo, DIB4 => scuba_vlo, - DIB5 => scuba_vlo, DIB6 => scuba_vlo, DIB7 => scuba_vlo, - DIB8 => scuba_vlo, DIB9 => scuba_vlo, DIB10 => scuba_vlo, - DIB11 => scuba_vlo, DIB12 => scuba_vlo, DIB13 => scuba_vlo, - DIB14 => scuba_vlo, DIB15 => scuba_vlo, DIB16 => scuba_vlo, - DIB17 => scuba_vlo, ADB0 => scuba_vlo, ADB1 => scuba_vlo, - ADB2 => scuba_vlo, ADB3 => scuba_vlo, ADB4 => scuba_vlo, - ADB5 => scuba_vlo, ADB6 => scuba_vlo, ADB7 => scuba_vlo, - ADB8 => scuba_vlo, ADB9 => scuba_vlo, ADB10 => scuba_vlo, - ADB11 => scuba_vlo, ADB12 => scuba_vlo, ADB13 => scuba_vlo, - CEB => scuba_vhi, CLKB => scuba_vlo, OCEB => scuba_vhi, - WEB => scuba_vlo, CSB0 => scuba_vlo, CSB1 => scuba_vlo, - CSB2 => scuba_vlo, RSTB => scuba_vlo, DOA0 => Q(0), DOA1 => Q(1), - DOA2 => Q(2), DOA3 => Q(3), DOA4 => open, DOA5 => open, DOA6 => open, - DOA7 => open, DOA8 => open, DOA9 => open, DOA10 => open, DOA11 => open, - DOA12 => open, DOA13 => open, DOA14 => open, DOA15 => open, - DOA16 => open, DOA17 => open, DOB0 => open, DOB1 => open, DOB2 => open, - DOB3 => open, DOB4 => open, DOB5 => open, DOB6 => open, DOB7 => open, - DOB8 => open, DOB9 => open, DOB10 => open, DOB11 => open, - DOB12 => open, DOB13 => open, DOB14 => open, DOB15 => open, - DOB16 => open, DOB17 => open); - -end Structure; - --- synopsys translate_off -library ecp3; -configuration Structure_CON of ROM_FIFO is - for Structure - for all : VHI use entity ecp3.VHI(V); end for; - for all : VLO use entity ecp3.VLO(V); end for; - for all : DP16KC use entity ecp3.DP16KC(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/tdc_releases/tdc_v_stretcher/ROM_encoder_3.vhd b/tdc_releases/tdc_v_stretcher/ROM_encoder_3.vhd deleted file mode 100644 index 765bf32..0000000 --- a/tdc_releases/tdc_v_stretcher/ROM_encoder_3.vhd +++ /dev/null @@ -1,262 +0,0 @@ --- VHDL netlist generated by SCUBA Diamond_1.4_Production (87) --- Module Version: 5.0 ---/opt/lattice/diamond/1.4/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 00 -rp 1100 -addr_width 10 -data_width 8 -num_rows 1024 -outdata REGISTERED -memfile /home/ugur/projects/encoder/encoder_304_with_more_bbl_errors/source/rom_encoder.mem -memformat orca -cascade -1 -e - --- Mon Apr 16 15:10:22 2012 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp3; -use ecp3.components.all; --- synopsys translate_on - -entity ROM_Encoder is - port ( - Address : in std_logic_vector(9 downto 0); - OutClock : in std_logic; - OutClockEn : in std_logic; - Reset : in std_logic; - Q : out std_logic_vector(7 downto 0)); -end ROM_Encoder; - -architecture Structure of ROM_Encoder is - - -- internal signal declarations - signal scuba_vhi : std_logic; - signal scuba_vlo : std_logic; - - -- local component declarations - component VHI - port (Z : out std_logic); - end component; - component VLO - port (Z : out std_logic); - end component; - component DP16KC - generic (INITVAL_3F : in string; INITVAL_3E : in string; - INITVAL_3D : in string; INITVAL_3C : in string; - INITVAL_3B : in string; INITVAL_3A : in string; - INITVAL_39 : in string; INITVAL_38 : in string; - INITVAL_37 : in string; INITVAL_36 : in string; - INITVAL_35 : in string; INITVAL_34 : in string; - INITVAL_33 : in string; INITVAL_32 : in string; - INITVAL_31 : in string; INITVAL_30 : in string; - INITVAL_2F : in string; INITVAL_2E : in string; - INITVAL_2D : in string; INITVAL_2C : in string; - INITVAL_2B : in string; INITVAL_2A : in string; - INITVAL_29 : in string; INITVAL_28 : in string; - INITVAL_27 : in string; INITVAL_26 : in string; - INITVAL_25 : in string; INITVAL_24 : in string; - INITVAL_23 : in string; INITVAL_22 : in string; - INITVAL_21 : in string; INITVAL_20 : in string; - INITVAL_1F : in string; INITVAL_1E : in string; - INITVAL_1D : in string; INITVAL_1C : in string; - INITVAL_1B : in string; INITVAL_1A : in string; - INITVAL_19 : in string; INITVAL_18 : in string; - INITVAL_17 : in string; INITVAL_16 : in string; - INITVAL_15 : in string; INITVAL_14 : in string; - INITVAL_13 : in string; INITVAL_12 : in string; - INITVAL_11 : in string; INITVAL_10 : in string; - INITVAL_0F : in string; INITVAL_0E : in string; - INITVAL_0D : in string; INITVAL_0C : in string; - INITVAL_0B : in string; INITVAL_0A : in string; - INITVAL_09 : in string; INITVAL_08 : in string; - INITVAL_07 : in string; INITVAL_06 : in string; - INITVAL_05 : in string; INITVAL_04 : in string; - INITVAL_03 : in string; INITVAL_02 : in string; - INITVAL_01 : in string; INITVAL_00 : in string; - GSR : in string; WRITEMODE_B : in string; - WRITEMODE_A : in string; CSDECODE_B : in string; - CSDECODE_A : in string; REGMODE_B : in string; - REGMODE_A : in string; DATA_WIDTH_B : in integer; - DATA_WIDTH_A : in integer); - port (DIA0 : in std_logic; DIA1 : in std_logic; - DIA2 : in std_logic; DIA3 : in std_logic; - DIA4 : in std_logic; DIA5 : in std_logic; - DIA6 : in std_logic; DIA7 : in std_logic; - DIA8 : in std_logic; DIA9 : in std_logic; - DIA10 : in std_logic; DIA11 : in std_logic; - DIA12 : in std_logic; DIA13 : in std_logic; - DIA14 : in std_logic; DIA15 : in std_logic; - DIA16 : in std_logic; DIA17 : in std_logic; - ADA0 : in std_logic; ADA1 : in std_logic; - ADA2 : in std_logic; ADA3 : in std_logic; - ADA4 : in std_logic; ADA5 : in std_logic; - ADA6 : in std_logic; ADA7 : in std_logic; - ADA8 : in std_logic; ADA9 : in std_logic; - ADA10 : in std_logic; ADA11 : in std_logic; - ADA12 : in std_logic; ADA13 : in std_logic; - CEA : in std_logic; CLKA : in std_logic; OCEA : in std_logic; - WEA : in std_logic; CSA0 : in std_logic; CSA1 : in std_logic; - CSA2 : in std_logic; RSTA : in std_logic; - DIB0 : in std_logic; DIB1 : in std_logic; - DIB2 : in std_logic; DIB3 : in std_logic; - DIB4 : in std_logic; DIB5 : in std_logic; - DIB6 : in std_logic; DIB7 : in std_logic; - DIB8 : in std_logic; DIB9 : in std_logic; - DIB10 : in std_logic; DIB11 : in std_logic; - DIB12 : in std_logic; DIB13 : in std_logic; - DIB14 : in std_logic; DIB15 : in std_logic; - DIB16 : in std_logic; DIB17 : in std_logic; - ADB0 : in std_logic; ADB1 : in std_logic; - ADB2 : in std_logic; ADB3 : in std_logic; - ADB4 : in std_logic; ADB5 : in std_logic; - ADB6 : in std_logic; ADB7 : in std_logic; - ADB8 : in std_logic; ADB9 : in std_logic; - ADB10 : in std_logic; ADB11 : in std_logic; - ADB12 : in std_logic; ADB13 : in std_logic; - CEB : in std_logic; CLKB : in std_logic; OCEB : in std_logic; - WEB : in std_logic; CSB0 : in std_logic; CSB1 : in std_logic; - CSB2 : in std_logic; RSTB : in std_logic; - DOA0 : out std_logic; DOA1 : out std_logic; - DOA2 : out std_logic; DOA3 : out std_logic; - DOA4 : out std_logic; DOA5 : out std_logic; - DOA6 : out std_logic; DOA7 : out std_logic; - DOA8 : out std_logic; DOA9 : out std_logic; - DOA10 : out std_logic; DOA11 : out std_logic; - DOA12 : out std_logic; DOA13 : out std_logic; - DOA14 : out std_logic; DOA15 : out std_logic; - DOA16 : out std_logic; DOA17 : out std_logic; - DOB0 : out std_logic; DOB1 : out std_logic; - DOB2 : out std_logic; DOB3 : out std_logic; - DOB4 : out std_logic; DOB5 : out std_logic; - DOB6 : out std_logic; DOB7 : out std_logic; - DOB8 : out std_logic; DOB9 : out std_logic; - DOB10 : out std_logic; DOB11 : out std_logic; - DOB12 : out std_logic; DOB13 : out std_logic; - DOB14 : out std_logic; DOB15 : out std_logic; - DOB16 : out std_logic; DOB17 : out std_logic); - end component; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute RESETMODE : string; - attribute MEM_LPC_FILE of ROM_Encoder_0_0_0 : label is "ROM_Encoder.lpc"; - attribute MEM_INIT_FILE of ROM_Encoder_0_0_0 : label is "rom_encoder.mem"; - attribute RESETMODE of ROM_Encoder_0_0_0 : label is "SYNC"; - -begin - -- component instantiation statements - scuba_vhi_inst : VHI - port map (Z => scuba_vhi); - - scuba_vlo_inst : VLO - port map (Z => scuba_vlo); - - ROM_Encoder_0_0_0 : DP16KC - generic map (INITVAL_3F => "0x00000000800008000081000000000000000000820000000081000820008200000000000008200083", - INITVAL_3E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000084", - INITVAL_3D => "0x00000000000000000000000000000000000000000000000083000830008300000000000008400084", - INITVAL_3C => "0x00000000000000000000000000000000000000000000000000000840008400000000000008500085", - INITVAL_3B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_39 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000085", - INITVAL_38 => "0x00000000000000000000000000000000000000000000000000000000008500000000000008600086", - INITVAL_37 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_36 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_35 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000085", - INITVAL_34 => "0x00000000000000000000000000000000000000000000000000000000008600000000000008600086", - INITVAL_33 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_32 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_31 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000086", - INITVAL_30 => "0x00000000000000000000000000000000000000000000000000000000008700000000000008700087", - INITVAL_2F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_29 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_28 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_27 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_26 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_25 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_24 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_23 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_22 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_21 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_20 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_19 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_18 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_17 => "0x00086000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_16 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_15 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_14 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_13 => "0x00085000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_12 => "0x00084000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_11 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_10 => "0x00083000000000000000000000000000000000000008200000000000000000081000800000000000", - INITVAL_0F => "0x00087000000000000000000870000000000000000000000000000000000000000000000000000000", - INITVAL_0E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0B => "0x00086000000000000000000860000000000000000000000000000000000000000000000000000000", - INITVAL_0A => "0x00085000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_09 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_08 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_07 => "0x00086000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_06 => "0x00085000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_05 => "0x00085000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_04 => "0x00084000000000000000000840000000000000000000000000000000000000083000830000000000", - INITVAL_03 => "0x00085000000000000000000840000000000000000000000000000000000000000000000000000000", - INITVAL_02 => "0x00084000000000000000000840008400000000000000000000000000000000000000000000000000", - INITVAL_01 => "0x00084000000000000000000830000000000000000000000000000000000000082000820000000000", - INITVAL_00 => "0x00083000000000000000000820008200081000000008200082000810000000081000800008000000", - CSDECODE_B => "0b111", CSDECODE_A => "0b000", WRITEMODE_B => "NORMAL", - WRITEMODE_A => "NORMAL", GSR => "DISABLED", REGMODE_B => "NOREG", - REGMODE_A => "OUTREG", DATA_WIDTH_B => 18, DATA_WIDTH_A => 18) - port map (DIA0 => scuba_vlo, DIA1 => scuba_vlo, DIA2 => scuba_vlo, - DIA3 => scuba_vlo, DIA4 => scuba_vlo, DIA5 => scuba_vlo, - DIA6 => scuba_vlo, DIA7 => scuba_vlo, DIA8 => scuba_vlo, - DIA9 => scuba_vlo, DIA10 => scuba_vlo, DIA11 => scuba_vlo, - DIA12 => scuba_vlo, DIA13 => scuba_vlo, DIA14 => scuba_vlo, - DIA15 => scuba_vlo, DIA16 => scuba_vlo, DIA17 => scuba_vlo, - ADA0 => scuba_vlo, ADA1 => scuba_vlo, ADA2 => scuba_vlo, - ADA3 => scuba_vlo, ADA4 => Address(0), ADA5 => Address(1), - ADA6 => Address(2), ADA7 => Address(3), ADA8 => Address(4), - ADA9 => Address(5), ADA10 => Address(6), ADA11 => Address(7), - ADA12 => Address(8), ADA13 => Address(9), CEA => OutClockEn, - CLKA => OutClock, OCEA => OutClockEn, WEA => scuba_vlo, - CSA0 => scuba_vlo, CSA1 => scuba_vlo, CSA2 => scuba_vlo, - RSTA => Reset, DIB0 => scuba_vlo, DIB1 => scuba_vlo, - DIB2 => scuba_vlo, DIB3 => scuba_vlo, DIB4 => scuba_vlo, - DIB5 => scuba_vlo, DIB6 => scuba_vlo, DIB7 => scuba_vlo, - DIB8 => scuba_vlo, DIB9 => scuba_vlo, DIB10 => scuba_vlo, - DIB11 => scuba_vlo, DIB12 => scuba_vlo, DIB13 => scuba_vlo, - DIB14 => scuba_vlo, DIB15 => scuba_vlo, DIB16 => scuba_vlo, - DIB17 => scuba_vlo, ADB0 => scuba_vlo, ADB1 => scuba_vlo, - ADB2 => scuba_vlo, ADB3 => scuba_vlo, ADB4 => scuba_vlo, - ADB5 => scuba_vlo, ADB6 => scuba_vlo, ADB7 => scuba_vlo, - ADB8 => scuba_vlo, ADB9 => scuba_vlo, ADB10 => scuba_vlo, - ADB11 => scuba_vlo, ADB12 => scuba_vlo, ADB13 => scuba_vlo, - CEB => scuba_vhi, CLKB => scuba_vlo, OCEB => scuba_vhi, - WEB => scuba_vlo, CSB0 => scuba_vlo, CSB1 => scuba_vlo, - CSB2 => scuba_vlo, RSTB => scuba_vlo, DOA0 => Q(0), DOA1 => Q(1), - DOA2 => Q(2), DOA3 => Q(3), DOA4 => Q(4), DOA5 => Q(5), DOA6 => Q(6), - DOA7 => Q(7), DOA8 => open, DOA9 => open, DOA10 => open, DOA11 => open, - DOA12 => open, DOA13 => open, DOA14 => open, DOA15 => open, - DOA16 => open, DOA17 => open, DOB0 => open, DOB1 => open, DOB2 => open, - DOB3 => open, DOB4 => open, DOB5 => open, DOB6 => open, DOB7 => open, - DOB8 => open, DOB9 => open, DOB10 => open, DOB11 => open, - DOB12 => open, DOB13 => open, DOB14 => open, DOB15 => open, - DOB16 => open, DOB17 => open); - -end Structure; - --- synopsys translate_off -library ecp3; -configuration Structure_CON of ROM_Encoder is - for Structure - for all : VHI use entity ecp3.VHI(V); end for; - for all : VLO use entity ecp3.VLO(V); end for; - for all : DP16KC use entity ecp3.DP16KC(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/tdc_releases/tdc_v_stretcher/Readout.vhd b/tdc_releases/tdc_v_stretcher/Readout.vhd deleted file mode 100644 index 3850081..0000000 --- a/tdc_releases/tdc_v_stretcher/Readout.vhd +++ /dev/null @@ -1,1105 +0,0 @@ -------------------------------------------------------------------------------- --- Title : Readout Entity --- Project : -------------------------------------------------------------------------------- --- File : Readout.vhd --- Author : cugur@gsi.de --- Created : 2012-10-25 --- Last update: 2012-11-09 -------------------------------------------------------------------------------- --- Description: -------------------------------------------------------------------------------- --- Copyright (c) 2012 -------------------------------------------------------------------------------- - -library IEEE; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb3_components.all; - -entity Readout is - generic ( - CHANNEL_NUMBER : integer range 2 to 65; - STATUS_REG_NR : integer range 0 to 6); - - port ( - CLK_200 : in std_logic; - RESET_200 : in std_logic; - CLK_100 : in std_logic; - RESET_100 : in std_logic; - RESET_COUNTERS : in std_logic; --- - HIT_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 1); - REFERENCE_TIME : in std_logic; - TRIGGER_TIME_IN : in std_logic_vector(38 downto 0); - TRG_WIN_PRE : in std_logic_vector(10 downto 0); - TRG_WIN_POST : in std_logic_vector(10 downto 0); --- slow control - DEBUG_MODE_EN_IN : in std_logic; - TRIGGER_WIN_EN_IN : in std_logic; - --- from the channels - CH_DATA_IN : in std_logic_vector_array_32(0 to CHANNEL_NUMBER); - CH_EMPTY_IN : in std_logic_vector(CHANNEL_NUMBER downto 0); - CH_FULL_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); - CH_ALMOST_FULL_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); --- from the endpoint - TRG_DATA_VALID_IN : in std_logic; - VALID_TIMING_TRG_IN : in std_logic; - VALID_NOTIMING_TRG_IN : in std_logic; - INVALID_TRG_IN : in std_logic; - TMGTRG_TIMEOUT_IN : in std_logic; - SPIKE_DETECTED_IN : in std_logic; - MULTI_TMG_TRG_IN : in std_logic; - SPURIOUS_TRG_IN : in std_logic; - TRG_NUMBER_IN : in std_logic_vector(15 downto 0); - TRG_CODE_IN : in std_logic_vector(7 downto 0); - TRG_INFORMATION_IN : in std_logic_vector(23 downto 0); - TRG_TYPE_IN : in std_logic_vector(3 downto 0); --- to the endpoint - TRG_RELEASE_OUT : out std_logic; - TRG_STATUSBIT_OUT : out std_logic_vector(31 downto 0); - DATA_OUT : out std_logic_vector(31 downto 0); - DATA_WRITE_OUT : out std_logic; - DATA_FINISHED_OUT : out std_logic; --- to the channels - READOUT_BUSY_OUT : out std_logic; - READ_EN_OUT : out std_logic_vector(CHANNEL_NUMBER-1 downto 0); - TRIGGER_WIN_END_OUT : out std_logic; --- - SLOW_CONTROL_REG_OUT : out std_logic_vector(32*2**STATUS_REG_NR-1 downto 0); - STATUS_REGISTERS_BUS_OUT : out std_logic_vector_array_32(0 to 23); - READOUT_DEBUG : out std_logic_vector(31 downto 0) - ); - -end Readout; - -architecture behavioral of Readout is - -------------------------------------------------------------------------------- --- Signal Declarations -------------------------------------------------------------------------------- - - -- slow control - signal slow_control_ch_empty_i : std_logic_vector(64 downto 0); - - -- trigger window - signal start_trg_win_cnt : std_logic; - signal start_trg_win_cnt_200 : std_logic; - signal start_trg_win_cnt_200_p : std_logic; - signal trg_win_post_200 : std_logic_vector(10 downto 0); - signal trg_win_cnt : std_logic_vector(11 downto 0); - signal trg_win_end_200 : std_logic; - signal trg_win_end_200_p : std_logic; - signal trg_win_end_100 : std_logic; - signal trg_win_end_100_p : std_logic; - signal TW_pre : std_logic_vector(38 downto 0); - signal TW_post : std_logic_vector(38 downto 0); - signal trg_win_l : std_logic; - signal trg_win_r : std_logic; - -- channel signals - signal ch_data_reg : std_logic_vector_array_32(0 to CHANNEL_NUMBER); - signal ch_data_2reg : std_logic_vector_array_32(0 to CHANNEL_NUMBER); - --signal ch_data_3reg : std_logic_vector_array_32(0 to CHANNEL_NUMBER); - signal ch_empty_reg : std_logic_vector(CHANNEL_NUMBER downto 0); - signal ch_empty_2reg : std_logic_vector(CHANNEL_NUMBER downto 0); - signal ch_empty_3reg : std_logic_vector(CHANNEL_NUMBER downto 0); - signal ch_empty_4reg : std_logic_vector(CHANNEL_NUMBER downto 0); - signal ch_hit_time : std_logic_vector(38 downto 0); - signal ch_epoch_cntr_i : std_logic_vector(27 downto 0); - -- readout fsm - type FSM is (IDLE, WAIT_FOR_TRG_WIND_END, WAIT_FOR_LVL1_TRG_A, WAIT_FOR_LVL1_TRG_B, - WAIT_FOR_LVL1_TRG_C, SEND_STATUS, SEND_TRG_RELEASE_A, SEND_TRG_RELEASE_B, - WAIT_FOR_FIFO_NR_A, WAIT_FOR_FIFO_NR_B, WAIT_FOR_FIFO_NR_C, WR_HEADER_A, - APPLY_MASK, RD_CHANNEL_A, RD_CHANNEL_B, RD_CHANNEL_C); - signal FSM_CURRENT, FSM_NEXT : FSM; - signal start_trg_win_cnt_fsm : std_logic; - signal fsm_debug_fsm : std_logic_vector(7 downto 0); - signal updt_index_fsm : std_logic; - signal updt_mask_fsm : std_logic; - signal rd_en_fsm : std_logic_vector(CHANNEL_NUMBER-1 downto 0); - signal data_finished_fsm : std_logic; - signal trg_release_fsm : std_logic; - signal wr_header_fsm : std_logic; - signal wr_ch_data_fsm : std_logic; - signal wr_status_fsm : std_logic; - signal wrong_readout_fsm : std_logic; --- signal wr_trailer_fsm : std_logic; - signal idle_fsm : std_logic; - signal readout_fsm : std_logic; - signal wait_fsm : std_logic; - -- readout busy fsm - type FSM_RDO_BUSY is (NOT_BUSY, BUSY, WAIT_FOR_SILINCE); - signal FSM_RDO_BUSY_CURRENT : FSM_RDO_BUSY; - signal FSM_RDO_BUSY_NEXT : FSM_RDO_BUSY; - signal readout_busy : std_logic; - -- fifo number - type Std_Logic_8_array is array (0 to 8) of std_logic_vector(3 downto 0); - signal updt_index : std_logic; - signal fifo_nr : integer range 0 to CHANNEL_NUMBER := CHANNEL_NUMBER; - signal fifo_nr_reg : integer range 0 to CHANNEL_NUMBER := CHANNEL_NUMBER; - signal fifo_nr_next : integer range 0 to CHANNEL_NUMBER := CHANNEL_NUMBER; - signal fifo_nr_hex : Std_Logic_8_array; - signal empty_channels : std_logic_vector(CHANNEL_NUMBER downto 0); - signal updt_index_reg : std_logic; - signal updt_mask : std_logic; - signal mask : std_logic_vector(71 downto 0); - -- fifo read - signal rd_en : std_logic_vector(CHANNEL_NUMBER-1 downto 0); - -- data mux - signal wr_header : std_logic; - signal wr_ch_data : std_logic; - signal wr_ch_data_reg : std_logic; - signal wr_ch_data_2reg : std_logic; - signal wr_status : std_logic; - signal wr_trailer : std_logic; - signal stop_status_i : std_logic; - -- to endpoint - signal data_out_reg : std_logic_vector(31 downto 0); - signal data_wr_reg : std_logic; - signal data_finished : std_logic; - signal data_finished_reg : std_logic; - signal trg_release_reg : std_logic; - -- statistics - signal trig_number : unsigned(23 downto 0); - signal release_number : unsigned(23 downto 0); - signal valid_tmg_trig_number : unsigned(23 downto 0); - signal valid_NOtmg_trig_number : unsigned(23 downto 0); - signal invalid_trig_number : unsigned(23 downto 0); - signal multi_tmg_trig_number : unsigned(23 downto 0); - signal spurious_trig_number : unsigned(23 downto 0); - signal wrong_readout_number : unsigned(23 downto 0); - signal spike_number : unsigned(23 downto 0); - signal timeout_number : unsigned(23 downto 0); - signal total_empty_channel : unsigned(23 downto 0); - signal idle_time : unsigned(23 downto 0); - signal readout_time : unsigned(23 downto 0); - signal wait_time : unsigned(23 downto 0); - signal valid_timing_trg_p : std_logic; - signal valid_notiming_trg_p : std_logic; - signal invalid_trg_p : std_logic; - signal multi_tmg_trg_p : std_logic; - signal spurious_trg_p : std_logic; - signal spike_detected_p : std_logic; - signal timeout_detected_p : std_logic; - signal idle_time_up : std_logic; - signal readout_time_up : std_logic; - signal wait_time_up : std_logic; - signal wrong_readout_up : std_logic; - -- debug - signal header_error_bits : std_logic_vector(15 downto 0); - signal trailer_error_bits : std_logic_vector(15 downto 0); - signal ch_full_i : std_logic; - signal ch_almost_full_i : std_logic; - signal fsm_debug : std_logic_vector(7 downto 0); - -begin -- behavioral -------------------------------------------------------------------------------- --- Trigger window -------------------------------------------------------------------------------- --- Trigger window start logic - StartTrgWinCntSync : bit_sync - generic map ( - DEPTH => 3) - port map ( - RESET => RESET_200, - CLK0 => CLK_100, - CLK1 => CLK_200, - D_IN => start_trg_win_cnt, - D_OUT => start_trg_win_cnt_200); - - StartTrgWinCntPulse : edge_to_pulse - port map ( - clock => CLK_200, - en_clk => '1', - signal_in => start_trg_win_cnt_200, - pulse => start_trg_win_cnt_200_p); - --- Trigger window end logic - Check_Trg_Win_End_Conrollers : process (CLK_200) - begin - if rising_edge(CLK_200) then - if RESET_200 = '1' then - trg_win_end_200 <= '0'; - trg_win_cnt <= '1' & trg_win_post_200; - elsif start_trg_win_cnt_200_p = '1' then - trg_win_end_200 <= '0'; - trg_win_cnt <= "000000000001"; - elsif trg_win_cnt(10 downto 0) = trg_win_post_200 then - trg_win_end_200 <= '1'; - trg_win_cnt(11) <= '1'; - else - trg_win_end_200 <= '0'; - trg_win_cnt <= std_logic_vector(unsigned(trg_win_cnt) + to_unsigned(1, 1)); - end if; - end if; - end process Check_Trg_Win_End_Conrollers; - - TriggerWinEndPulse200 : edge_to_pulse - port map ( - clock => CLK_200, - en_clk => '1', - signal_in => trg_win_end_200, - pulse => trg_win_end_200_p); - TRIGGER_WIN_END_OUT <= trg_win_end_200_p; - - TriggerWinEndSync : bit_sync - generic map ( - DEPTH => 3) - port map ( - RESET => RESET_100, - CLK0 => CLK_200, - CLK1 => CLK_100, - D_IN => trg_win_end_200, - D_OUT => trg_win_end_100); - - TriggerWinEndPulse100 : edge_to_pulse - port map ( - clock => CLK_100, - en_clk => '1', - signal_in => trg_win_end_100, - pulse => trg_win_end_100_p); - --- Trigger window borders - Trg_Win_Calculation : process (CLK_100, RESET_100) - begin - if rising_edge(CLK_100) then - if RESET_100 = '1' then - TW_pre <= (others => '0'); - TW_post <= (others => '0'); - else - TW_pre <= std_logic_vector(to_unsigned(to_integer(unsigned(TRIGGER_TIME_IN)) - to_integer(unsigned(TRG_WIN_PRE)), 39)); - TW_post <= std_logic_vector(to_unsigned(to_integer(unsigned(TRIGGER_TIME_IN)) + to_integer(unsigned(TRG_WIN_POST)), 39)); - end if; - end if; - end process Trg_Win_Calculation; - --- Channel Hit Time Determination - ChannelEpochCounter : process (CLK_100) - begin - if rising_edge(CLK_100) then - if RESET_100 = '1' then - ch_epoch_cntr_i <= (others => '0'); - elsif ch_empty_3reg(fifo_nr_reg) = '1' and ch_empty_4reg(fifo_nr_reg) = '0' then - ch_epoch_cntr_i <= (others => '0'); - elsif ch_data_reg(fifo_nr_reg)(31 downto 29) = "011" then - ch_epoch_cntr_i <= ch_data_reg(fifo_nr_reg)(27 downto 0); - end if; - end if; - end process ChannelEpochCounter; - - ChannelHitTime : process (CLK_100) - begin - if rising_edge(CLK_100) then - if RESET_100 = '1' then - ch_hit_time <= (others => '0'); - elsif ch_data_reg(fifo_nr_reg)(31) = '1' then - ch_hit_time <= ch_epoch_cntr_i & ch_data_reg(fifo_nr_reg)(10 downto 0); - elsif ch_data_reg(fifo_nr_reg)(31 downto 29) = "011" then - ch_hit_time <= (others => '0'); - end if; - end if; - end process ChannelHitTime; - --- Controls if the data coming from the channel is greater than the trigger window pre-edge - Check_Trg_Win_Left : process (RESET_100, TW_pre, ch_hit_time) - begin - --if rising_edge(CLK_100) then - if RESET_100 = '1' then - trg_win_l <= '0'; - elsif to_integer(unsigned(TW_pre)) <= to_integer(unsigned(ch_hit_time)) then - trg_win_l <= '1'; - else - trg_win_l <= '0'; - end if; - --end if; - end process Check_Trg_Win_Left; - --- Controls if the data coming from the channel is smaller than the trigger window post-edge - Check_Trg_Win_Right : process (RESET_100, TW_post, ch_hit_time) - begin - --if rising_edge(CLK_100) then - if RESET_100 = '1' then - trg_win_r <= '0'; - elsif to_integer(unsigned(ch_hit_time)) <= to_integer(unsigned(TW_post)) then - trg_win_r <= '1'; - else - trg_win_r <= '0'; - end if; - --end if; - end process Check_Trg_Win_Right; - -------------------------------------------------------------------------------- --- Readout -------------------------------------------------------------------------------- --- Readout fsm - FSM_CLK : process (CLK_100, RESET_100) - begin - if rising_edge(CLK_100) then - if RESET_100 = '1' then - FSM_CURRENT <= IDLE; - start_trg_win_cnt <= '0'; - updt_index <= '0'; - updt_mask <= '0'; - rd_en <= (others => '0'); - wr_ch_data <= '0'; - wr_header <= '0'; - wr_status <= '0'; - data_finished <= '0'; - trg_release_reg <= '0'; - wrong_readout_up <= '0'; - idle_time_up <= '0'; - readout_time_up <= '0'; - wait_time_up <= '0'; - fsm_debug <= x"00"; - else - FSM_CURRENT <= FSM_NEXT; - start_trg_win_cnt <= start_trg_win_cnt_fsm; - updt_index <= updt_index_fsm; - updt_mask <= updt_mask_fsm; - rd_en <= rd_en_fsm; - wr_ch_data <= wr_ch_data_fsm; - wr_header <= wr_header_fsm; - wr_status <= wr_status_fsm; - data_finished <= data_finished_fsm; - trg_release_reg <= trg_release_fsm; - wrong_readout_up <= wrong_readout_fsm; - idle_time_up <= idle_fsm; - readout_time_up <= readout_fsm; - wait_time_up <= wait_fsm; - fsm_debug <= fsm_debug_fsm; - end if; - end if; - end process FSM_CLK; - READ_EN_OUT <= rd_en; - - FSM_PROC : process (FSM_CURRENT, VALID_TIMING_TRG_IN, VALID_NOTIMING_TRG_IN, trg_win_end_100_p, fifo_nr_next, - fifo_nr, ch_empty_reg, TRG_DATA_VALID_IN, INVALID_TRG_IN, TMGTRG_TIMEOUT_IN, - TRG_TYPE_IN, SPURIOUS_TRG_IN, stop_status_i, DEBUG_MODE_EN_IN) - begin - - start_trg_win_cnt_fsm <= '0'; - updt_index_fsm <= '0'; - updt_mask_fsm <= '0'; - rd_en_fsm <= (others => '0'); - wr_ch_data_fsm <= '0'; - wr_header_fsm <= '0'; - data_finished_fsm <= '0'; - trg_release_fsm <= '0'; - wrong_readout_fsm <= '0'; - idle_fsm <= '0'; - readout_fsm <= '0'; - wait_fsm <= '0'; - wr_status_fsm <= '0'; - fsm_debug_fsm <= x"00"; - FSM_NEXT <= IDLE; - - case (FSM_CURRENT) is - when IDLE => - if VALID_TIMING_TRG_IN = '1' then - FSM_NEXT <= WAIT_FOR_TRG_WIND_END; - start_trg_win_cnt_fsm <= '1'; - elsif VALID_NOTIMING_TRG_IN = '1' then - if TRG_TYPE_IN = x"E" then - FSM_NEXT <= SEND_STATUS; - else - FSM_NEXT <= SEND_TRG_RELEASE_A; - end if; - wr_header_fsm <= '1'; - elsif INVALID_TRG_IN = '1' then - FSM_NEXT <= SEND_TRG_RELEASE_A; - data_finished_fsm <= '1'; - else - FSM_NEXT <= IDLE; - end if; - idle_fsm <= '1'; - fsm_debug_fsm <= x"01"; - - when WAIT_FOR_TRG_WIND_END => - if trg_win_end_100_p = '1' then - FSM_NEXT <= WR_HEADER_A; - else - FSM_NEXT <= WAIT_FOR_TRG_WIND_END; - end if; - wait_fsm <= '1'; - fsm_debug_fsm <= x"02"; -------------------------------------------------------------------------------- --- Readout process starts - when WR_HEADER_A => - FSM_NEXT <= WAIT_FOR_FIFO_NR_A; - wr_header_fsm <= '1'; - readout_fsm <= '1'; - fsm_debug_fsm <= x"03"; - - when WAIT_FOR_FIFO_NR_A => - FSM_NEXT <= WAIT_FOR_FIFO_NR_B; - updt_index_fsm <= '1'; - wait_fsm <= '1'; - fsm_debug_fsm <= x"04"; - - when WAIT_FOR_FIFO_NR_B => - FSM_NEXT <= APPLY_MASK; - wait_fsm <= '1'; - fsm_debug_fsm <= x"05"; - - when APPLY_MASK => - if fifo_nr_next = CHANNEL_NUMBER then - if DEBUG_MODE_EN_IN = '1' then - FSM_NEXT <= SEND_STATUS; - else - FSM_NEXT <= WAIT_FOR_LVL1_TRG_A; - data_finished_fsm <= '1'; - end if; - else - FSM_NEXT <= RD_CHANNEL_A; - rd_en_fsm(fifo_nr_next) <= '1'; - updt_mask_fsm <= '1'; - end if; - wait_fsm <= '1'; - fsm_debug_fsm <= x"06"; - - when RD_CHANNEL_A => - FSM_NEXT <= RD_CHANNEL_B; - rd_en_fsm(fifo_nr) <= '1'; - readout_fsm <= '1'; - fsm_debug_fsm <= x"07"; - - when RD_CHANNEL_B => - FSM_NEXT <= RD_CHANNEL_C; - rd_en_fsm(fifo_nr) <= '1'; - readout_fsm <= '1'; - fsm_debug_fsm <= x"08"; - - when RD_CHANNEL_C => - if ch_empty_reg(fifo_nr) = '1' then - FSM_NEXT <= WAIT_FOR_FIFO_NR_B; - wr_ch_data_fsm <= '0'; - updt_index_fsm <= '1'; - else - FSM_NEXT <= RD_CHANNEL_C; - wr_ch_data_fsm <= '1'; - rd_en_fsm(fifo_nr) <= '1'; - end if; - readout_fsm <= '1'; - fsm_debug_fsm <= x"09"; -------------------------------------------------------------------------------- - when WAIT_FOR_LVL1_TRG_A => - if TRG_DATA_VALID_IN = '1' then - FSM_NEXT <= WAIT_FOR_LVL1_TRG_B; - elsif TMGTRG_TIMEOUT_IN = '1' then - FSM_NEXT <= IDLE; - else - FSM_NEXT <= WAIT_FOR_LVL1_TRG_A; - end if; - wait_fsm <= '1'; - fsm_debug_fsm <= x"0A"; - - when WAIT_FOR_LVL1_TRG_B => - FSM_NEXT <= WAIT_FOR_LVL1_TRG_C; - wait_fsm <= '1'; - fsm_debug_fsm <= x"0B"; - - when WAIT_FOR_LVL1_TRG_C => - if SPURIOUS_TRG_IN = '1' then - wrong_readout_fsm <= '1'; - end if; - FSM_NEXT <= SEND_TRG_RELEASE_A; - wait_fsm <= '1'; - fsm_debug_fsm <= x"0C"; - - when SEND_STATUS => - if stop_status_i = '1' then - if DEBUG_MODE_EN_IN = '1' then - FSM_NEXT <= WAIT_FOR_LVL1_TRG_A; - else - FSM_NEXT <= SEND_TRG_RELEASE_A; - end if; - data_finished_fsm <= '1'; - else - FSM_NEXT <= SEND_STATUS; - wr_status_fsm <= '1'; - end if; - fsm_debug_fsm <= x"0D"; - - when SEND_TRG_RELEASE_A => - FSM_NEXT <= SEND_TRG_RELEASE_B; - trg_release_fsm <= '1'; - fsm_debug_fsm <= x"0E"; - - when SEND_TRG_RELEASE_B => - FSM_NEXT <= IDLE; - fsm_debug_fsm <= x"0F"; - - when others => - FSM_NEXT <= IDLE; - fsm_debug_fsm <= x"FF"; - end case; - end process FSM_PROC; - --- Readout busy fsm - FSM_READOUT_BUSY_CLK : process (CLK_200) - begin - if rising_edge(CLK_200) then - if RESET_200 = '1' then - FSM_RDO_BUSY_CURRENT <= NOT_BUSY; - else - FSM_RDO_BUSY_CURRENT <= FSM_RDO_BUSY_NEXT; - end if; - end if; - end process FSM_READOUT_BUSY_CLK; - - FSM_READOUT_BUSY : process (FSM_RDO_BUSY_CURRENT, trg_win_end_200_p, data_finished_reg, HIT_IN) - begin - FSM_RDO_BUSY_NEXT <= NOT_BUSY; - readout_busy <= '0'; - - case FSM_RDO_BUSY_CURRENT is - when NOT_BUSY => - if trg_win_end_200_p = '1' then - FSM_RDO_BUSY_NEXT <= BUSY; - else - FSM_RDO_BUSY_NEXT <= NOT_BUSY; - end if; - readout_busy <= '0'; - - when BUSY => - if data_finished_reg = '1' then - FSM_RDO_BUSY_NEXT <= WAIT_FOR_SILINCE; -- waits until the hit input is zero - else - FSM_RDO_BUSY_NEXT <= BUSY; - end if; - readout_busy <= '1'; - - when WAIT_FOR_SILINCE => - if or_all(HIT_IN) = '0' then - FSM_RDO_BUSY_NEXT <= NOT_BUSY; - else - FSM_RDO_BUSY_NEXT <= WAIT_FOR_SILINCE; - end if; - readout_busy <= '1'; - - when others => - FSM_RDO_BUSY_NEXT <= NOT_BUSY; - end case; - end process FSM_READOUT_BUSY; - - READOUT_BUSY_OUT <= readout_busy; - --- Fifo number determination - CREAT_MASK : process (CLK_100) - begin - if rising_edge(CLK_100) then - if RESET_100 = '1' then - mask <= (others => '1'); - empty_channels <= (others => '1'); - elsif trg_win_end_100_p = '1' then - mask(CHANNEL_NUMBER-1 downto 0) <= CH_EMPTY_IN(CHANNEL_NUMBER-1 downto 0); - empty_channels(CHANNEL_NUMBER-1 downto 0) <= CH_EMPTY_IN(CHANNEL_NUMBER-1 downto 0); - elsif updt_mask = '1' then - mask(fifo_nr) <= '1'; - end if; - end if; - end process CREAT_MASK; - - GEN : for i in 0 to 8 generate - ROM : ROM_FIFO - port map ( - Address => mask(8*(i+1)-1 downto 8*i), - OutClock => CLK_100, - OutClockEn => '1', - Reset => RESET_100, - Q => fifo_nr_hex(i)); - end generate GEN; - - CON_FIFO_NR_HEX_TO_INT : process (CLK_100) - begin - if rising_edge(CLK_100) then - if RESET_100 = '1' then - fifo_nr_next <= CHANNEL_NUMBER; - elsif fifo_nr_hex(0)(3) /= '1' then - fifo_nr_next <= to_integer("00000" & unsigned(fifo_nr_hex(0)(2 downto 0))); - elsif fifo_nr_hex(1)(3) /= '1' then - fifo_nr_next <= to_integer("00001" & unsigned(fifo_nr_hex(1)(2 downto 0))); - elsif fifo_nr_hex(2)(3) /= '1' then - fifo_nr_next <= to_integer("00010" & unsigned(fifo_nr_hex(2)(2 downto 0))); - elsif fifo_nr_hex(3)(3) /= '1' then - fifo_nr_next <= to_integer("00011" & unsigned(fifo_nr_hex(3)(2 downto 0))); - elsif fifo_nr_hex(4)(3) /= '1' then - fifo_nr_next <= to_integer("00100" & unsigned(fifo_nr_hex(4)(2 downto 0))); - elsif fifo_nr_hex(5)(3) /= '1' then - fifo_nr_next <= to_integer("00101" & unsigned(fifo_nr_hex(5)(2 downto 0))); - elsif fifo_nr_hex(6)(3) /= '1' then - fifo_nr_next <= to_integer("00110" & unsigned(fifo_nr_hex(6)(2 downto 0))); - elsif fifo_nr_hex(7)(3) /= '1' then - fifo_nr_next <= to_integer("00111" & unsigned(fifo_nr_hex(7)(2 downto 0))); - elsif fifo_nr_hex(8)(3) /= '1' then - fifo_nr_next <= to_integer("01000" & unsigned(fifo_nr_hex(8)(2 downto 0))); - else - fifo_nr_next <= CHANNEL_NUMBER; - end if; - end if; - end process CON_FIFO_NR_HEX_TO_INT; - - UPDATE_INDEX_NR : process (CLK_100) - begin - if rising_edge(CLK_100) then - if RESET_100 = '1' then - fifo_nr <= CHANNEL_NUMBER; - elsif updt_index_reg = '1' then - fifo_nr <= fifo_nr_next; - end if; - end if; - end process UPDATE_INDEX_NR; - -------------------------------------------------------------------------------- --- Data out mux -------------------------------------------------------------------------------- - Data_Out_MUX : process (CLK_100, RESET_100) - variable i : integer := 0; - begin - if rising_edge(CLK_100) then - if RESET_100 = '1' then - data_out_reg <= (others => '1'); - data_wr_reg <= '0'; - stop_status_i <= '0'; - elsif wr_header = '1' then - data_out_reg <= "001" & "00000" & TRG_CODE_IN & header_error_bits; - data_wr_reg <= '1'; - stop_status_i <= '0'; - elsif wr_ch_data_2reg = '1' then - if TRIGGER_WIN_EN_IN = '1' then -- if the trigger window is enabled - if ch_data_2reg(fifo_nr)(31 downto 29) = "011" then - data_out_reg <= ch_data_2reg(fifo_nr); - data_wr_reg <= '1'; - --elsif (TW_pre(10) = '1' and ref_time_coarse(10) = '0') or (TW_post(10) = '0' and ref_time_coarse(10) = '1') then -- if one of the trigger window edges has an overflow - -- if (trg_win_l = '0' and trg_win_r = '1') or (trg_win_l = '1' and trg_win_r = '0') then - -- data_out_reg <= ch_data_2reg(fifo_nr); - -- data_wr_reg <= '1'; - -- else - -- data_out_reg <= (others => '1'); - -- data_wr_reg <= '0'; - -- end if; - else -- if both of the trigger window edges are in the coarse counter boundries - if (trg_win_l = '1' and trg_win_r = '1') then - data_out_reg <= ch_data_2reg(fifo_nr); - data_wr_reg <= '1'; - else - data_out_reg <= (others => '1'); - data_wr_reg <= '0'; - end if; - end if; - stop_status_i <= '0'; - elsif TRIGGER_WIN_EN_IN = '0' then - data_out_reg <= ch_data_2reg(fifo_nr); - data_wr_reg <= '1'; - stop_status_i <= '0'; - end if; - elsif wr_status = '1' then - case i is - when 0 => data_out_reg <= "010" & "00000" & std_logic_vector(trig_number); - when 1 => data_out_reg <= "010" & "00001" & std_logic_vector(release_number); - when 2 => data_out_reg <= "010" & "00010" & std_logic_vector(valid_tmg_trig_number); - when 3 => data_out_reg <= "010" & "00011" & std_logic_vector(valid_NOtmg_trig_number); - when 4 => data_out_reg <= "010" & "00100" & std_logic_vector(invalid_trig_number); - when 5 => data_out_reg <= "010" & "00101" & std_logic_vector(multi_tmg_trig_number); - when 6 => data_out_reg <= "010" & "00110" & std_logic_vector(spurious_trig_number); - when 7 => data_out_reg <= "010" & "00111" & std_logic_vector(wrong_readout_number); - when 8 => data_out_reg <= "010" & "01000" & std_logic_vector(spike_number); - when 9 => data_out_reg <= "010" & "01001" & std_logic_vector(idle_time); - when 10 => data_out_reg <= "010" & "01010" & std_logic_vector(wait_time); - when 11 => data_out_reg <= "010" & "01011" & std_logic_vector(total_empty_channel); - when 12 => data_out_reg <= "010" & "01100" & std_logic_vector(readout_time); - stop_status_i <= '1'; - when 13 => data_out_reg <= "010" & "01101" & std_logic_vector(timeout_number); - i := -1; - when others => null; - end case; - data_wr_reg <= '1'; - i := i+1; - elsif wr_trailer = '1' then - data_out_reg <= "011" & "0000000000000" & trailer_error_bits; - data_wr_reg <= '1'; - stop_status_i <= '0'; - else - data_out_reg <= (others => '1'); - data_wr_reg <= '0'; - stop_status_i <= '0'; - end if; - end if; - end process Data_Out_MUX; - - DATA_OUT <= data_out_reg; - DATA_WRITE_OUT <= data_wr_reg; - DATA_FINISHED_OUT <= data_finished_reg; - TRG_RELEASE_OUT <= trg_release_reg; - TRG_STATUSBIT_OUT <= (others => '0'); - READOUT_DEBUG(7 downto 0) <= fsm_debug; - READOUT_DEBUG(8) <= data_wr_reg; - READOUT_DEBUG(9) <= data_finished_reg; - READOUT_DEBUG(10) <= trg_release_reg; - READOUT_DEBUG(16 downto 11) <= data_out_reg(27 downto 22); - READOUT_DEBUG(31 downto 17) <= (others => '0'); - - -- Error, warning bits set in the header - header_error_bits(15 downto 3) <= (others => '0'); - header_error_bits(0) <= '0'; ---header_error_bits(0) <= lost_hit_i; -- if there is at least one lost hit (can be more if the FIFO is full). - header_error_bits(1) <= ch_full_i; -- if the channel FIFO is full. - header_error_bits(2) <= ch_almost_full_i; -- if the channel FIFO is almost full. - - -- Error, warning bits set in the trailer - trailer_error_bits <= (others => '0'); - -- trailer_error_bits (0) <= wrong_readout_i; -- if there is a wrong readout because of a spurious timing trigger. - - ch_full_i <= or_all(CH_FULL_IN); - ch_almost_full_i <= or_all(CH_ALMOST_FULL_IN); - - - -------------------------------------------------------------------------------- --- Debug and statistics words -------------------------------------------------------------------------------- - - edge_to_pulse_1 : edge_to_pulse - port map ( - clock => CLK_100, - en_clk => '1', - signal_in => VALID_TIMING_TRG_IN, - pulse => valid_timing_trg_p); - - edge_to_pulse_2 : edge_to_pulse - port map ( - clock => CLK_100, - en_clk => '1', - signal_in => VALID_NOTIMING_TRG_IN, - pulse => valid_notiming_trg_p); - - edge_to_pulse_3 : edge_to_pulse - port map ( - clock => CLK_100, - en_clk => '1', - signal_in => INVALID_TRG_IN, - pulse => invalid_trg_p); - - edge_to_pulse_4 : edge_to_pulse - port map ( - clock => CLK_100, - en_clk => '1', - signal_in => MULTI_TMG_TRG_IN, - pulse => multi_tmg_trg_p); - - edge_to_pulse_5 : edge_to_pulse - port map ( - clock => CLK_100, - en_clk => '1', - signal_in => SPURIOUS_TRG_IN, - pulse => spurious_trg_p); - - edge_to_pulse_6 : edge_to_pulse - port map ( - clock => CLK_100, - en_clk => '1', - signal_in => SPIKE_DETECTED_IN, - pulse => spike_detected_p); - - edge_to_pulse_7 : edge_to_pulse - port map ( - clock => CLK_100, - en_clk => '1', - signal_in => TMGTRG_TIMEOUT_IN, - pulse => timeout_detected_p); - --- Internal trigger number counter (only valid triggers) - Statistics_Trigger_Number : process (CLK_100, RESET_100) - begin - if rising_edge(CLK_100) then - if RESET_100 = '1' or RESET_COUNTERS = '1' then - trig_number <= (others => '0'); - elsif valid_timing_trg_p = '1' or valid_notiming_trg_p = '1' then - trig_number <= trig_number + to_unsigned(1, 1); - end if; - end if; - end process Statistics_Trigger_Number; - --- Internal release number counter - Statistics_Release_Number : process (CLK_100, RESET_100) - begin - if rising_edge(CLK_100) then - if RESET_100 = '1' or RESET_COUNTERS = '1' then - release_number <= (others => '0'); - elsif trg_release_reg = '1' then - release_number <= release_number + to_unsigned(1, 1); - end if; - end if; - end process Statistics_Release_Number; - --- Internal valid timing trigger number counter - Statistics_Valid_Timing_Trigger_Number : process (CLK_100, RESET_100) - begin - if rising_edge(CLK_100) then - if RESET_100 = '1' or RESET_COUNTERS = '1' then - valid_tmg_trig_number <= (others => '0'); - elsif valid_timing_trg_p = '1' then - valid_tmg_trig_number <= valid_tmg_trig_number + to_unsigned(1, 1); - end if; - end if; - end process Statistics_Valid_Timing_Trigger_Number; - --- Internal valid NOtiming trigger number counter - Statistics_Valid_NoTiming_Trigger_Number : process (CLK_100, RESET_100) - begin - if rising_edge(CLK_100) then - if RESET_100 = '1' or RESET_COUNTERS = '1' then - valid_NOtmg_trig_number <= (others => '0'); - elsif valid_notiming_trg_p = '1' then - valid_NOtmg_trig_number <= valid_NOtmg_trig_number + to_unsigned(1, 1); - end if; - end if; - end process Statistics_Valid_NoTiming_Trigger_Number; - --- Internal invalid trigger number counter - Statistics_Invalid_Trigger_Number : process (CLK_100, RESET_100) - begin - if rising_edge(CLK_100) then - if RESET_100 = '1' or RESET_COUNTERS = '1' then - invalid_trig_number <= (others => '0'); - elsif invalid_trg_p = '1' then - invalid_trig_number <= invalid_trig_number + to_unsigned(1, 1); - end if; - end if; - end process Statistics_Invalid_Trigger_Number; - --- Internal multi timing trigger number counter - Statistics_Multi_Timing_Trigger_Number : process (CLK_100, RESET_100) - begin - if rising_edge(CLK_100) then - if RESET_100 = '1' or RESET_COUNTERS = '1' then - multi_tmg_trig_number <= (others => '0'); - elsif multi_tmg_trg_p = '1' then - multi_tmg_trig_number <= multi_tmg_trig_number + to_unsigned(1, 1); - end if; - end if; - end process Statistics_Multi_Timing_Trigger_Number; - --- Internal spurious trigger number counter - Statistics_Spurious_Trigger_Number : process (CLK_100, RESET_100) - begin - if rising_edge(CLK_100) then - if RESET_100 = '1' or RESET_COUNTERS = '1' then - spurious_trig_number <= (others => '0'); - elsif spurious_trg_p = '1' then - spurious_trig_number <= spurious_trig_number + to_unsigned(1, 1); - end if; - end if; - end process Statistics_Spurious_Trigger_Number; - --- Number of wrong readout becasue of spurious trigger - Statistics_Wrong_Readout_Number : process (CLK_100, RESET_100) - begin - if rising_edge(CLK_100) then - if RESET_100 = '1' or RESET_COUNTERS = '1' then - wrong_readout_number <= (others => '0'); - elsif wrong_readout_up = '1' then - wrong_readout_number <= wrong_readout_number + to_unsigned(1, 1); - end if; - end if; - end process Statistics_Wrong_Readout_Number; - --- Internal spike number counter - Statistics_Spike_Number : process (CLK_100, RESET_100) - begin - if rising_edge(CLK_100) then - if RESET_100 = '1' or RESET_COUNTERS = '1' then - spike_number <= (others => '0'); - elsif spike_detected_p = '1' then - spike_number <= spike_number + to_unsigned(1, 1); - end if; - end if; - end process Statistics_Spike_Number; - --- Internal timeout number counter - Statistics_Timeout_Number : process (CLK_100, RESET_100) - begin - if rising_edge(CLK_100) then - if RESET_100 = '1' or RESET_COUNTERS = '1' then - timeout_number <= (others => '0'); - elsif timeout_detected_p = '1' then - timeout_number <= timeout_number + to_unsigned(1, 1); - end if; - end if; - end process Statistics_Timeout_Number; - --- IDLE time of the TDC readout - Statistics_Idle_Time : process (CLK_100, RESET_100) - begin - if rising_edge(CLK_100) then - if RESET_100 = '1' or RESET_COUNTERS = '1' then - idle_time <= (others => '0'); - elsif idle_time_up = '1' then - idle_time <= idle_time + to_unsigned(1, 1); - end if; - end if; - end process Statistics_Idle_Time; - --- Readout and Wait time of the TDC readout - Statistics_Readout_Wait_Time : process (CLK_100, RESET_100) - begin - if rising_edge(CLK_100) then - if RESET_100 = '1' or RESET_COUNTERS = '1' then - readout_time <= (others => '0'); - wait_time <= (others => '0'); - elsif readout_time_up = '1' then - readout_time <= readout_time + to_unsigned(1, 1); - elsif wait_time_up = '1' then - wait_time <= wait_time + to_unsigned(1, 1); - end if; - end if; - end process Statistics_Readout_Wait_Time; - --- Empty channel number - Statistics_Empty_Channel_Number : process (CLK_100, RESET_100) - variable i : integer := CHANNEL_NUMBER; - begin - if rising_edge(CLK_100) then - if RESET_100 = '1' or RESET_COUNTERS = '1' then - total_empty_channel <= (others => '0'); - i := CHANNEL_NUMBER; - elsif trg_win_end_100_p = '1' then - i := 0; - elsif i = CHANNEL_NUMBER then - i := i; - elsif empty_channels(i) = '1' then - total_empty_channel <= total_empty_channel + to_unsigned(1, 1); - i := i + 1; - else - i := i + 1; - end if; - end if; - end process Statistics_Empty_Channel_Number; - -------------------------------------------------------------------------------- --- SLOW CONTROL REGISTERS -------------------------------------------------------------------------------- - ----- Register 0x80 --- SLOW_CONTROL_REG_OUT(31 downto 0) <= ----- Register 0x81 --- SLOW_CONTROL_REG_OUT(1*32+31 downto 1*32+0) <= ----- Register 0x82 --- SLOW_CONTROL_REG_OUT(2*32+31 downto 2*32+0) <= ----- Register 0x83 --- SLOW_CONTROL_REG_OUT(3*32+31 downto 3*32+0) <= ----- Register 0x84 --- SLOW_CONTROL_REG_OUT(4*32+31 downto 4*32+0) <= ----- Register 0x85 --- SLOW_CONTROL_REG_OUT(5*32+31 downto 5*32+0) <= ----- Register 0x86 --- SLOW_CONTROL_REG_OUT(6*32+31 downto 6*32+0) <= ----- Register 0x87 --- SLOW_CONTROL_REG_OUT(7*32+31 downto 7*32+0) <= ----- Register 0x88 --- SLOW_CONTROL_REG_OUT(8*32+31 downto 8*32+0) <= ----- Register 0x89 --- SLOW_CONTROL_REG_OUT(9*32+31 downto 9*32+0) <= ----- Register 0x8a --- SLOW_CONTROL_REG_OUT(10*32+31 downto 10*32+0) <= ----- Register 0x8b --- SLOW_CONTROL_REG_OUT(11*32+31 downto 11*32+0) <= ----- Register 0x8c --- SLOW_CONTROL_REG_OUT(12*32+31 downto 12*32+0) <= ----- Register 0x8d --- SLOW_CONTROL_REG_OUT(13*32+31 downto 13*32+0) <= ----- Register 0x8e --- SLOW_CONTROL_REG_OUT(14*32+31 downto 14*32+0) <= ----- Register 0x8f --- SLOW_CONTROL_REG_OUT(15*32+31 downto 15*32+0) <= ----- Register 0x90 --- SLOW_CONTROL_REG_OUT(16*32+31 downto 16*32+0) <= ----- Register 0x91 --- SLOW_CONTROL_REG_OUT(17*32+31 downto 17*32+0) <= ----- Register 0x93 --- SLOW_CONTROL_REG_OUT(19*32+31 downto 19*32+0) <= ----- Register 0x94 --- SLOW_CONTROL_REG_OUT(20*32+31 downto 20*32+0) <= ----- Register 0x95 --- SLOW_CONTROL_REG_OUT(21*32+31 downto 21*32+0) <= ----- Register 0x96 --- SLOW_CONTROL_REG_OUT(22*32+31 downto 22*32+0) <= ----- Register 0x97 --- SLOW_CONTROL_REG_OUT(23*32+31 downto 23*32+0) <= ----- Register 0x98 --- SLOW_CONTROL_REG_OUT(24*32+31 downto 24*32+0) <= ----- Register 0x99 --- SLOW_CONTROL_REG_OUT(25*32+31 downto 25*32+0) <= ----- Register 0x9a --- SLOW_CONTROL_REG_OUT(26*32+31 downto 26*32+0) <= ----- Register 0x9f --- SLOW_CONTROL_REG_OUT(27*32+31 downto 27*32+0) <= - - SLOW_CONTROL_REG_OUT(32*2**STATUS_REG_NR-1 downto 0) <= (others => '0'); - -------------------------------------------------------------------------------- --- STATUS REGISTERS BUS -------------------------------------------------------------------------------- - STATUS_REGISTERS_BUS_OUT(0)(7 downto 0) <= fsm_debug; - STATUS_REGISTERS_BUS_OUT(0)(15 downto 8) <= std_logic_vector(to_unsigned(CHANNEL_NUMBER-1, 8)); - STATUS_REGISTERS_BUS_OUT(0)(16) <= REFERENCE_TIME when rising_edge(CLK_100); - STATUS_REGISTERS_BUS_OUT(0)(31 downto 17) <= (others => '0'); - STATUS_REGISTERS_BUS_OUT(1) <= slow_control_ch_empty_i(31 downto 0); - STATUS_REGISTERS_BUS_OUT(2) <= slow_control_ch_empty_i(63 downto 32); - STATUS_REGISTERS_BUS_OUT(3)(10 downto 0) <= TRG_WIN_PRE; - STATUS_REGISTERS_BUS_OUT(3)(15 downto 11) <= (others => '0'); - STATUS_REGISTERS_BUS_OUT(3)(26 downto 16) <= TRG_WIN_POST; - STATUS_REGISTERS_BUS_OUT(3)(30 downto 27) <= (others => '0'); - STATUS_REGISTERS_BUS_OUT(3)(31) <= TRIGGER_WIN_EN_IN; - STATUS_REGISTERS_BUS_OUT(4)(23 downto 0) <= std_logic_vector(trig_number); - STATUS_REGISTERS_BUS_OUT(5)(23 downto 0) <= std_logic_vector(valid_tmg_trig_number); - STATUS_REGISTERS_BUS_OUT(6)(23 downto 0) <= std_logic_vector(valid_NOtmg_trig_number); - STATUS_REGISTERS_BUS_OUT(7)(23 downto 0) <= std_logic_vector(invalid_trig_number); - STATUS_REGISTERS_BUS_OUT(8)(23 downto 0) <= std_logic_vector(multi_tmg_trig_number); - STATUS_REGISTERS_BUS_OUT(9)(23 downto 0) <= std_logic_vector(spurious_trig_number); - STATUS_REGISTERS_BUS_OUT(10)(23 downto 0) <= std_logic_vector(wrong_readout_number); - STATUS_REGISTERS_BUS_OUT(11)(23 downto 0) <= std_logic_vector(spike_number); - STATUS_REGISTERS_BUS_OUT(12)(23 downto 0) <= std_logic_vector(idle_time); - STATUS_REGISTERS_BUS_OUT(13)(23 downto 0) <= std_logic_vector(wait_time); - STATUS_REGISTERS_BUS_OUT(14)(23 downto 0) <= std_logic_vector(total_empty_channel); - STATUS_REGISTERS_BUS_OUT(15)(23 downto 0) <= std_logic_vector(release_number); - STATUS_REGISTERS_BUS_OUT(16)(23 downto 0) <= std_logic_vector(readout_time); - STATUS_REGISTERS_BUS_OUT(17)(23 downto 0) <= std_logic_vector(timeout_number); - - FILL_BUS1 : for i in 4 to 17 generate - STATUS_REGISTERS_BUS_OUT(i)(31 downto 24) <= (others => '0'); - end generate FILL_BUS1; - - FILL_BUS2 : for i in 18 to 23 generate - STATUS_REGISTERS_BUS_OUT(i) <= (others => '0'); - end generate FILL_BUS2; - - slow_control_ch_empty_i(64 downto CHANNEL_NUMBER-1) <= (others => '1'); - slow_control_ch_empty_i(CHANNEL_NUMBER-2 downto 0) <= ch_empty_2reg(CHANNEL_NUMBER-1 downto 1); - -------------------------------------------------------------------------------- --- Registering -------------------------------------------------------------------------------- --- 100 MHz - updt_index_reg <= updt_index when rising_edge(CLK_100); - wr_ch_data_reg <= wr_ch_data when rising_edge(CLK_100); - wr_ch_data_2reg <= wr_ch_data_reg when rising_edge(CLK_100); - data_finished_reg <= data_finished when rising_edge(CLK_100); - fifo_nr_reg <= fifo_nr when rising_edge(CLK_100); - ch_data_reg <= CH_DATA_IN when rising_edge(CLK_100); - ch_data_2reg <= ch_data_reg when rising_edge(CLK_100); --- ch_data_3reg <= ch_data_2reg when rising_edge(CLK_100); - ch_empty_reg <= CH_EMPTY_IN when rising_edge(CLK_100); - ch_empty_2reg <= ch_empty_reg when rising_edge(CLK_100); - ch_empty_3reg <= ch_empty_2reg when rising_edge(CLK_100); - ch_empty_4reg <= ch_empty_3reg when rising_edge(CLK_100); - --- 200 MHz - trg_win_post_200 <= TRG_WIN_POST when rising_edge(CLK_200); - -end behavioral; diff --git a/tdc_releases/tdc_v_stretcher/Reference_Channel.vhd b/tdc_releases/tdc_v_stretcher/Reference_Channel.vhd deleted file mode 100644 index 57b906e..0000000 --- a/tdc_releases/tdc_v_stretcher/Reference_Channel.vhd +++ /dev/null @@ -1,131 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_UNSIGNED.all; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -use ieee.std_logic_arith.all; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb3_components.all; -use work.version.all; - -entity Reference_Channel is - - generic ( - CHANNEL_ID : integer range 0 to 0); - port ( - RESET_200 : in std_logic; - RESET_100 : in std_logic; - CLK_200 : in std_logic; - CLK_100 : in std_logic; --- - HIT_IN : in std_logic; - READ_EN_IN : in std_logic; - VALID_TMG_TRG_IN : in std_logic; - SPIKE_DETECTED_IN : in std_logic; - MULTI_TMG_TRG_IN : in std_logic; - FIFO_DATA_OUT : out std_logic_vector(31 downto 0); - FIFO_EMPTY_OUT : out std_logic; - FIFO_FULL_OUT : out std_logic; - FIFO_ALMOST_FULL_OUT : out std_logic; - COARSE_COUNTER_IN : in std_logic_vector(10 downto 0); - EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0); - TRIGGER_WINDOW_END_IN : in std_logic; - DATA_FINISHED_IN : in std_logic; -- end of the readout process - RUN_MODE : in std_logic; - TRIGGER_TIME_STAMP_OUT : out std_logic_vector(38 downto 0); -- coarse time of the timing trigger - REF_DEBUG_OUT : out std_logic_vector(31 downto 0) - ); - -end Reference_Channel; - -architecture Reference_Channel of Reference_Channel is -------------------------------------------------------------------------------- --- Signal Declarations -------------------------------------------------------------------------------- - - --hit detection - signal hit_in_i : std_logic; - signal hit_buf : std_logic; - - -- time stamp - signal coarse_cntr_reg : std_logic_vector(10 downto 0); - - -- other - signal trg_win_end_i : std_logic; - signal data_finished_i : std_logic; - signal run_mode_i : std_logic; - - attribute syn_keep : boolean; - attribute syn_keep of hit_buf : signal is true; - attribute NOMERGE : string; - attribute NOMERGE of hit_buf : signal is "true"; - attribute syn_preserve : boolean; - attribute syn_preserve of coarse_cntr_reg : signal is true; - attribute syn_preserve of hit_buf : signal is true; -------------------------------------------------------------------------------- - -begin - - hit_in_i <= HIT_IN; - hit_buf <= not hit_in_i; - - Reference_Channel_200_1 : Reference_Channel_200 - generic map ( - CHANNEL_ID => CHANNEL_ID) - port map ( - CLK_200 => CLK_200, - RESET_200 => RESET_200, - CLK_100 => CLK_100, - RESET_100 => RESET_100, - VALID_TMG_TRG_IN => VALID_TMG_TRG_IN, - SPIKE_DETECTED_IN => SPIKE_DETECTED_IN, - MULTI_TMG_TRG_IN => MULTI_TMG_TRG_IN, - HIT_IN => hit_buf, - READ_EN_IN => READ_EN_IN, - FIFO_DATA_OUT => FIFO_DATA_OUT, - FIFO_EMPTY_OUT => FIFO_EMPTY_OUT, - FIFO_FULL_OUT => FIFO_FULL_OUT, - FIFO_ALMOST_FULL_OUT => FIFO_ALMOST_FULL_OUT, - EPOCH_COUNTER_IN => EPOCH_COUNTER_IN, - TRIGGER_WINDOW_END_IN => trg_win_end_i, - TRIGGER_TIME_STAMP_OUT => TRIGGER_TIME_STAMP_OUT, - DATA_FINISHED_IN => data_finished_i, - RUN_MODE => run_mode_i, - COARSE_COUNTER_IN => coarse_cntr_reg); - - trg_win_end_i <= TRIGGER_WINDOW_END_IN when rising_edge(CLK_200); - data_finished_i <= DATA_FINISHED_IN when rising_edge(CLK_100); - run_mode_i <= RUN_MODE when rising_edge(CLK_100); - - CoarseCounter : ShiftRegisterSISO - generic map ( - DEPTH => 1, - WIDTH => 11) - port map ( - CLK => CLK_200, - RESET => RESET_200, - D_IN => COARSE_COUNTER_IN, - D_OUT => coarse_cntr_reg); - -------------------------------------------------------------------------------- --- Debug signals -------------------------------------------------------------------------------- - --REF_DEBUG_OUT(3 downto 0) <= fsm_debug_i; - --REF_DEBUG_OUT(4) <= HIT_IN; - --REF_DEBUG_OUT(5) <= result_i(2); - --REF_DEBUG_OUT(6) <= result_2_reg; - --REF_DEBUG_OUT(7) <= '0'; --hit_detect_i; - --REF_DEBUG_OUT(8) <= '0'; --hit_detect_reg; - --REF_DEBUG_OUT(9) <= '0'; - --REF_DEBUG_OUT(10) <= '0'; - --REF_DEBUG_OUT(11) <= ff_array_en_i; - --REF_DEBUG_OUT(12) <= encoder_start_i; - --REF_DEBUG_OUT(13) <= encoder_finished_i; - --REF_DEBUG_OUT(14) <= fifo_wr_en_i; - - --REF_DEBUG_OUT(15) <= CLK_200; - - REF_DEBUG_OUT(31 downto 0) <= (others => '0'); -end Reference_Channel; diff --git a/tdc_releases/tdc_v_stretcher/Reference_Channel_200.vhd b/tdc_releases/tdc_v_stretcher/Reference_Channel_200.vhd deleted file mode 100644 index 2069801..0000000 --- a/tdc_releases/tdc_v_stretcher/Reference_Channel_200.vhd +++ /dev/null @@ -1,437 +0,0 @@ -------------------------------------------------------------------------------- --- Title : Reference Channel 200 MHz Part --- Project : -------------------------------------------------------------------------------- --- File : Reference_channel_200.vhd --- Author : c.ugur@gsi.de --- Created : 2012-09-04 --- Last update: 2012-11-14 -------------------------------------------------------------------------------- --- Description: -------------------------------------------------------------------------------- - -library IEEE; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb3_components.all; -use work.version.all; - -entity Reference_Channel_200 is - - generic ( - CHANNEL_ID : integer range 0 to 0); - port ( - CLK_200 : in std_logic; -- 200 MHz clk - RESET_200 : in std_logic; -- reset sync with 200Mhz clk - CLK_100 : in std_logic; -- 100 MHz clk - RESET_100 : in std_logic; -- reset sync with 100Mhz clk --- - VALID_TMG_TRG_IN : in std_logic; - SPIKE_DETECTED_IN : in std_logic; - MULTI_TMG_TRG_IN : in std_logic; --- - HIT_IN : in std_logic; -- hit in - READ_EN_IN : in std_logic; -- read en signal - FIFO_DATA_OUT : out std_logic_vector(31 downto 0); -- fifo data out - FIFO_EMPTY_OUT : out std_logic; -- fifo empty signal - FIFO_FULL_OUT : out std_logic; -- fifo full signal - FIFO_ALMOST_FULL_OUT : out std_logic; -- fifo almost full signal - EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0); - TRIGGER_WINDOW_END_IN : in std_logic; - TRIGGER_TIME_STAMP_OUT : out std_logic_vector(38 downto 0); -- TRIGGER time stamp - DATA_FINISHED_IN : in std_logic; -- end of the readout process - RUN_MODE : in std_logic; - COARSE_COUNTER_IN : in std_logic_vector(10 downto 0)); - -end Reference_Channel_200; - -architecture Reference_Channel_200 of Reference_Channel_200 is - - -- carry chain - signal data_a_i : std_logic_vector(303 downto 0); - signal data_b_i : std_logic_vector(303 downto 0); - signal result_i : std_logic_vector(303 downto 0); - signal ff_array_en_i : std_logic; - - --hit detection - signal hit_detect_i : std_logic; - signal hit_detect_reg : std_logic; - signal hit_detect_2reg : std_logic; - signal result_2_reg : std_logic; - - -- time stamp - signal time_stamp_i : std_logic_vector(10 downto 0); - signal coarse_cntr_reg : std_logic_vector(10 downto 0); - signal time_stamp_epoch_bits : std_logic_vector(27 downto 0); - - -- encoder - signal encoder_start_i : std_logic; - signal encoder_finished_i : std_logic; - signal encoder_data_out_i : std_logic_vector(9 downto 0); - signal encoder_debug_i : std_logic_vector(31 downto 0); - - -- fifo - signal fifo_data_in_i : std_logic_vector(31 downto 0); - signal fifo_data_out_i : std_logic_vector(31 downto 0); - signal fifo_empty_i : std_logic; - signal fifo_full_i : std_logic; - signal fifo_was_full_i : std_logic; - signal fifo_almost_full_i : std_logic; - signal fifo_wr_en_i : std_logic; - signal fifo_rd_en_i : std_logic; - - -- timing trigger - signal valid_tmg_trg_i : std_logic; - signal multi_tmg_trg_i : std_logic; - signal spike_detected_i : std_logic; - - -- coarse counter overflow - signal coarse_cntr_overflow_release : std_logic; - signal coarse_cntr_overflow_flag : std_logic; - signal coarse_cntr_overflow_reset : std_logic; - - -- epoch counter - signal epoch_cntr : std_logic_vector(27 downto 0); - signal epoch_time : std_logic_vector(27 downto 0); - signal epoch_word_first : std_logic_vector(31 downto 0); - signal epoch_cntr_up : std_logic; - signal epoch_capture_time : std_logic_vector(10 downto 0); - - -- other - signal read_en_reg : std_logic; - signal read_en_2reg : std_logic; - signal first_read_i : std_logic; - signal trg_win_end_i : std_logic; - - -- fsm - type FSM is (IDLE, LOOK_FOR_VALIDITY, ENCODER_FINISHED, WAIT_FOR_FALLING_EDGE); - signal FSM_CURRENT, FSM_NEXT : FSM; - signal valid_trigger_i : std_logic; - signal valid_trigger_fsm : std_logic; - signal fsm_debug_i : std_logic_vector(3 downto 0); - signal fsm_debug_fsm : std_logic_vector(3 downto 0); - - attribute syn_keep : boolean; - attribute syn_keep of ff_array_en_i : signal is true; - attribute syn_keep of trg_win_end_i : signal is true; - attribute syn_preserve : boolean; - attribute syn_preserve of trg_win_end_i : signal is true; - - -begin -- Reference_Channel_200 - - trg_win_end_i <= TRIGGER_WINDOW_END_IN when rising_edge(CLK_200); - - --purpose: Tapped Delay Line 304 (Carry Chain) with wave launcher (21) double transition - FC : Adder_304 - port map ( - CLK => CLK_200, - RESET => RESET_200, - DataA => data_a_i, - DataB => data_b_i, - ClkEn => ff_array_en_i, - Result => result_i); - data_a_i <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" & x"7FFFFFF"; - data_b_i <= x"000000000000000000000000000000000000000000000000000000000000000000000" & not(HIT_IN) & x"000000" & "00" & HIT_IN; - ff_array_en_i <= not(hit_detect_i or hit_detect_reg or hit_detect_2reg); - - result_2_reg <= result_i(2) when rising_edge(CLK_200); - hit_detect_i <= (not result_2_reg) and result_i(2); -- detects the hit by - -- comparing the - -- previous state of the - -- hit detection bit - hit_detect_reg <= hit_detect_i when rising_edge(CLK_200); - hit_detect_2reg <= hit_detect_reg when rising_edge(CLK_200); - coarse_cntr_reg <= COARSE_COUNTER_IN when rising_edge(CLK_200); - encoder_start_i <= hit_detect_reg; - - TimeStampCapture : process (CLK_200) - begin - if rising_edge(CLK_200) then - if RESET_200 = '1' then - time_stamp_i <= (others => '0'); - elsif hit_detect_reg = '1' then - time_stamp_i <= coarse_cntr_reg; - end if; - end if; - end process TimeStampCapture; - - epoch_capture_time <= "00000000111"; - - EpochCounterUpdate : process (CLK_200) - begin - if rising_edge(CLK_200) then - if RESET_200 = '1' then - epoch_cntr <= (others => '0'); - epoch_cntr_up <= '0'; - elsif coarse_cntr_reg = epoch_capture_time then - epoch_cntr <= EPOCH_COUNTER_IN; - epoch_cntr_up <= '1'; - end if; - end if; - end process EpochCounterUpdate; - - EpochCounterCapture : process (CLK_200) - begin - if rising_edge(CLK_200) then - if RESET_200 = '1' then - epoch_time <= (others => '0'); - elsif encoder_finished_i = '1' then - epoch_time <= epoch_cntr; - end if; - end if; - end process EpochCounterCapture; - - --purpose: Encoder - Encoder : Encoder_304_Bit - port map ( - RESET => RESET_200, - CLK => CLK_200, - START_IN => encoder_start_i, - THERMOCODE_IN => result_i, - FINISHED_OUT => encoder_finished_i, - BINARY_CODE_OUT => encoder_data_out_i, - ENCODER_DEBUG => encoder_debug_i); - - FIFO : FIFO_32x32_OutReg - port map ( - Data => fifo_data_in_i, - WrClock => CLK_200, - RdClock => CLK_100, - WrEn => fifo_wr_en_i, - RdEn => fifo_rd_en_i, - Reset => RESET_100, - RPReset => RESET_200, - Q => fifo_data_out_i, - Empty => fifo_empty_i, - Full => fifo_full_i, - AlmostFull => fifo_almost_full_i); - - fifo_rd_en_i <= READ_EN_IN or fifo_full_i; - - -- purpose: Sets the Overflow Flag - CoarseCounterOverflowFlag : process (CLK_200) - begin - if rising_edge(CLK_200) then - if RESET_200 = '1' then - coarse_cntr_overflow_flag <= '0'; - elsif epoch_cntr_up = '1' or trg_win_end_i = '1' then - coarse_cntr_overflow_flag <= '1'; - elsif coarse_cntr_overflow_release = '1' then - coarse_cntr_overflow_flag <= '0'; - end if; - end if; - end process CoarseCounterOverflowFlag; - - -- purpose: Generate Fifo Wr Signal - FifoWriteSignal : process (CLK_200) - begin - if rising_edge(CLK_200) then - if RESET_200 = '1' then - fifo_data_in_i <= (others => '0'); - coarse_cntr_overflow_release <= '0'; - fifo_wr_en_i <= '0'; - time_stamp_epoch_bits <= (others => '0'); - elsif valid_trigger_i = '1' then - --if coarse_cntr_overflow_flag = '0' then - -- fifo_data_in_i(31) <= '1'; -- data marker - -- fifo_data_in_i(30 downto 29) <= "00"; -- reserved bits - -- fifo_data_in_i(28 downto 22) <= std_logic_vector(to_unsigned(CHANNEL_ID, 7)); -- channel number - -- fifo_data_in_i(21 downto 12) <= encoder_data_out_i; -- fine time from the encoder - -- fifo_data_in_i(11) <= '1'; --edge_type_i; -- rising '1' or falling '0' edge - -- fifo_data_in_i(10 downto 0) <= time_stamp_reg; -- hit time stamp - -- coarse_cntr_overflow_release <= '0'; - -- fifo_wr_en_i <= '1'; - --else - --if and_all(TIME_STAMP_IN(10 downto 3)) = '1' then - -- fifo_data_in_i(31) <= '1'; -- data marker - -- fifo_data_in_i(30 downto 29) <= "00"; -- reserved bits - -- fifo_data_in_i(28 downto 22) <= std_logic_vector(to_unsigned(CHANNEL_ID, 7)); -- channel number - -- fifo_data_in_i(21 downto 12) <= encoder_data_out_i; -- fine time from the encoder - -- fifo_data_in_i(11) <= '1'; --edge_type_i; -- rising '1' or falling '0' edge - -- fifo_data_in_i(10 downto 0) <= time_stamp_reg; -- hit time stamp - -- coarse_cntr_overflow_release <= '0'; - -- fifo_wr_en_i <= '1'; - --else - - fifo_data_in_i(31 downto 29) <= "011"; - fifo_data_in_i(28) <= '0'; - fifo_data_in_i(27 downto 0) <= epoch_time; - coarse_cntr_overflow_release <= '1'; - fifo_wr_en_i <= '1'; - time_stamp_epoch_bits <= epoch_time; - --end if; - --end if; - elsif coarse_cntr_overflow_release = '1' then - fifo_data_in_i(31) <= '1'; -- data marker - fifo_data_in_i(30 downto 29) <= "00"; -- reserved bits - fifo_data_in_i(28 downto 22) <= std_logic_vector(to_unsigned(CHANNEL_ID, 7)); -- channel number - fifo_data_in_i(21 downto 12) <= encoder_data_out_i; -- fine time from the encoder - fifo_data_in_i(11) <= '1'; --edge_type_i; -- rising '1' or falling '0' edge - fifo_data_in_i(10 downto 0) <= time_stamp_i; -- hit time stamp - coarse_cntr_overflow_release <= '0'; - fifo_wr_en_i <= '1'; - elsif DATA_FINISHED_IN = '1' then - time_stamp_epoch_bits <= (others => '0'); - else - fifo_data_in_i <= (others => '0'); - coarse_cntr_overflow_release <= '0'; - fifo_wr_en_i <= '0'; - end if; - end if; - end process FifoWriteSignal; - - TRIGGER_TIME_STAMP_OUT <= time_stamp_epoch_bits & time_stamp_i; - - EpochCounterCaptureFirstWord : process (CLK_100, RESET_100) - begin - if rising_edge(CLK_100) then - if RESET_100 = '1' then - epoch_word_first <= x"60000000"; - elsif DATA_FINISHED_IN = '1' and RUN_MODE = '0' then - epoch_word_first <= x"60000000"; - elsif fifo_data_out_i(31 downto 29) = "011" then - epoch_word_first <= fifo_data_out_i; - end if; - end if; - end process EpochCounterCaptureFirstWord; - - read_en_reg <= READ_EN_IN when rising_edge(CLK_100); - read_en_2reg <= read_en_reg when rising_edge(CLK_100); - first_read_i <= read_en_reg and not(read_en_2reg) when rising_edge(CLK_100); - - FifoWasFull : process (CLK_100, RESET_100) - begin - if rising_edge(CLK_100) then - if RESET_100 = '1' then - fifo_was_full_i <= '0'; - elsif fifo_full_i = '1' then - fifo_was_full_i <= '1'; - elsif fifo_empty_i = '1' then - fifo_was_full_i <= '0'; - end if; - end if; - end process FifoWasFull; - - RegisterOutputs : process (CLK_100) - begin - if rising_edge(CLK_100) then - if RESET_100 = '1' then - FIFO_DATA_OUT <= (others => '1'); - FIFO_EMPTY_OUT <= '0'; - FIFO_FULL_OUT <= '0'; - FIFO_ALMOST_FULL_OUT <= '0'; - else - if first_read_i = '1' and fifo_was_full_i = '1' then - FIFO_DATA_OUT <= epoch_word_first; - else - FIFO_DATA_OUT <= fifo_data_out_i; - end if; - FIFO_EMPTY_OUT <= fifo_empty_i; - FIFO_FULL_OUT <= fifo_full_i; - FIFO_ALMOST_FULL_OUT <= fifo_almost_full_i; - end if; - end if; - end process RegisterOutputs; - - --purpose: FSM for controlling the validity of the timing signal - FSM_CLK : process (CLK_200, RESET_200) - begin - if rising_edge(CLK_200) then - if RESET_200 = '1' then - FSM_CURRENT <= IDLE; - valid_trigger_i <= '0'; - fsm_debug_i <= (others => '0'); - else - FSM_CURRENT <= FSM_NEXT; - valid_trigger_i <= valid_trigger_fsm; - fsm_debug_i <= fsm_debug_fsm; - end if; - end if; - end process FSM_CLK; - - FSM_PROC : process (FSM_CURRENT, hit_detect_i, encoder_finished_i, valid_tmg_trg_i, multi_tmg_trg_i, - spike_detected_i) - begin - valid_trigger_fsm <= '0'; - fsm_debug_fsm <= (others => '0'); - - case (FSM_CURRENT) is - when IDLE => - if hit_detect_i = '1' then - FSM_NEXT <= ENCODER_FINISHED; - else - FSM_NEXT <= IDLE; - end if; - fsm_debug_fsm <= x"1"; - - when ENCODER_FINISHED => - if encoder_finished_i = '1' then - FSM_NEXT <= LOOK_FOR_VALIDITY; - elsif valid_tmg_trg_i = '1' then - FSM_NEXT <= IDLE; - else - FSM_NEXT <= ENCODER_FINISHED; - end if; - fsm_debug_fsm <= x"2"; - - when LOOK_FOR_VALIDITY => - if valid_tmg_trg_i = '1' then - FSM_NEXT <= IDLE; - valid_trigger_fsm <= '1'; - elsif multi_tmg_trg_i = '1' or spike_detected_i = '1' then - FSM_NEXT <= IDLE; - else - FSM_NEXT <= LOOK_FOR_VALIDITY; - end if; - fsm_debug_fsm <= x"3"; - - --when WAIT_FOR_FALLING_EDGE => - -- if encoder_finished_i = '1' then - -- FSM_NEXT <= IDLE; - -- valid_trigger_fsm <= '1'; - -- fsm_debug_fsm <= x"C"; - -- else - -- FSM_NEXT <= WAIT_FOR_FALLING_EDGE; - -- valid_trigger_fsm <= '0'; - -- fsm_debug_fsm <= x"D"; - -- end if; - - when others => - FSM_NEXT <= IDLE; - end case; - end process FSM_PROC; - - bit_sync_1 : bit_sync - generic map ( - DEPTH => 3) - port map ( - RESET => RESET_200, - CLK0 => CLK_100, - CLK1 => CLK_200, - D_IN => VALID_TMG_TRG_IN, - D_OUT => valid_tmg_trg_i); - bit_sync_2 : bit_sync - generic map ( - DEPTH => 3) - port map ( - RESET => RESET_200, - CLK0 => CLK_100, - CLK1 => CLK_200, - D_IN => SPIKE_DETECTED_IN, - D_OUT => spike_detected_i); - bit_sync_3 : bit_sync - generic map ( - DEPTH => 3) - port map ( - RESET => RESET_200, - CLK0 => CLK_100, - CLK1 => CLK_200, - D_IN => MULTI_TMG_TRG_IN, - D_OUT => multi_tmg_trg_i); - -end Reference_Channel_200; diff --git a/tdc_releases/tdc_v_stretcher/ShiftRegisterSISO.vhd b/tdc_releases/tdc_v_stretcher/ShiftRegisterSISO.vhd deleted file mode 100644 index 497d384..0000000 --- a/tdc_releases/tdc_v_stretcher/ShiftRegisterSISO.vhd +++ /dev/null @@ -1,59 +0,0 @@ -------------------------------------------------------------------------------- --- Title : Register.vhd --- Project : -------------------------------------------------------------------------------- --- File : Register.vhd --- Author : c.ugur@gsi.de --- Created : 2012-10-02 --- Last update: 2012-10-04 -------------------------------------------------------------------------------- --- Description: Used to register signals n levels. -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - - -entity ShiftRegisterSISO is - - generic ( - DEPTH : integer range 1 to 32 := 1; -- defines the number register level - WIDTH : integer range 1 to 32 := 1); -- defines the register size - - port ( - CLK : in std_logic; -- register clock - RESET : in std_logic; -- register reset - D_IN : in std_logic_vector(WIDTH-1 downto 0); -- register input - D_OUT : out std_logic_vector(WIDTH-1 downto 0)); -- register out - -end ShiftRegisterSISO; - -architecture Behavioral of ShiftRegisterSISO is - - type RegisterArray is array (0 to DEPTH) of std_logic_vector(WIDTH-1 downto 0); - signal reg : RegisterArray; - - attribute syn_preserve : boolean; - attribute syn_preserve of reg : signal is true; - -begin -- RTL - - reg(0) <= D_IN; - - GEN_Registers : for i in 1 to DEPTH generate - Registers : process (CLK, RESET) - begin - if rising_edge(CLK) then - if RESET = '1' then - reg(i) <= (others => '0'); - else - reg(i) <= reg(i-1); - end if; - end if; - end process Registers; - end generate GEN_Registers; - - D_OUT <= reg(DEPTH); - -end Behavioral; diff --git a/tdc_releases/tdc_v_stretcher/TDC.vhd b/tdc_releases/tdc_v_stretcher/TDC.vhd deleted file mode 100644 index 2612a31..0000000 --- a/tdc_releases/tdc_v_stretcher/TDC.vhd +++ /dev/null @@ -1,432 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -use ieee.math_real.all; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb3_components.all; -use work.version.all; - -entity TDC is - generic ( - CHANNEL_NUMBER : integer range 2 to 65; - STATUS_REG_NR : integer range 0 to 6; - CONTROL_REG_NR : integer range 0 to 6); - port ( - RESET : in std_logic; - CLK_TDC : in std_logic; - CLK_READOUT : in std_logic; - REFERENCE_TIME : in std_logic; - HIT_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 1); - TRG_WIN_PRE : in std_logic_vector(10 downto 0); - TRG_WIN_POST : in std_logic_vector(10 downto 0); --- - -- Trigger signals from handler - TRG_DATA_VALID_IN : in std_logic; - VALID_TIMING_TRG_IN : in std_logic; - VALID_NOTIMING_TRG_IN : in std_logic; - INVALID_TRG_IN : in std_logic; - TMGTRG_TIMEOUT_IN : in std_logic; - SPIKE_DETECTED_IN : in std_logic; - MULTI_TMG_TRG_IN : in std_logic; - SPURIOUS_TRG_IN : in std_logic; --- - TRG_NUMBER_IN : in std_logic_vector(15 downto 0); - TRG_CODE_IN : in std_logic_vector(7 downto 0); - TRG_INFORMATION_IN : in std_logic_vector(23 downto 0); - TRG_TYPE_IN : in std_logic_vector(3 downto 0); --- - --Response to handler - TRG_RELEASE_OUT : out std_logic; - TRG_STATUSBIT_OUT : out std_logic_vector(31 downto 0); - DATA_OUT : out std_logic_vector(31 downto 0); - DATA_WRITE_OUT : out std_logic; - DATA_FINISHED_OUT : out std_logic; --- - --To Bus Handler - HCB_READ_EN_IN : in std_logic; - HCB_WRITE_EN_IN : in std_logic; - HCB_ADDR_IN : in std_logic_vector(6 downto 0); - HCB_DATA_OUT : out std_logic_vector(31 downto 0); - HCB_DATAREADY_OUT : out std_logic; - HCB_UNKNOWN_ADDR_OUT : out std_logic; - SRB_READ_EN_IN : in std_logic; - SRB_WRITE_EN_IN : in std_logic; - SRB_ADDR_IN : in std_logic_vector(6 downto 0); - SRB_DATA_OUT : out std_logic_vector(31 downto 0); - SRB_DATAREADY_OUT : out std_logic; - SRB_UNKNOWN_ADDR_OUT : out std_logic; - ESB_READ_EN_IN : in std_logic; - ESB_WRITE_EN_IN : in std_logic; - ESB_ADDR_IN : in std_logic_vector(6 downto 0); - ESB_DATA_OUT : out std_logic_vector(31 downto 0); - ESB_DATAREADY_OUT : out std_logic; - ESB_UNKNOWN_ADDR_OUT : out std_logic; - FWB_READ_EN_IN : in std_logic; - FWB_WRITE_EN_IN : in std_logic; - FWB_ADDR_IN : in std_logic_vector(6 downto 0); - FWB_DATA_OUT : out std_logic_vector(31 downto 0); - FWB_DATAREADY_OUT : out std_logic; - FWB_UNKNOWN_ADDR_OUT : out std_logic; - LHB_READ_EN_IN : in std_logic; - LHB_WRITE_EN_IN : in std_logic; - LHB_ADDR_IN : in std_logic_vector(6 downto 0); - LHB_DATA_OUT : out std_logic_vector(31 downto 0); - LHB_DATAREADY_OUT : out std_logic; - LHB_UNKNOWN_ADDR_OUT : out std_logic; --- - SLOW_CONTROL_REG_OUT : out std_logic_vector(32*2**STATUS_REG_NR-1 downto 0); - LOGIC_ANALYSER_OUT : out std_logic_vector(15 downto 0); - CONTROL_REG_IN : in std_logic_vector(32*2**CONTROL_REG_NR-1 downto 0) - ); -end TDC; - -architecture TDC of TDC is - -------------------------------------------------------------------------------- --- Signal Declarations -------------------------------------------------------------------------------- --- Reset Signals - signal reset_tdc : std_logic; --- Coarse counters - signal coarse_cntr : std_logic_vector_array_11(1 to 4); - signal coarse_cntr_reset : std_logic; - signal coarse_cntr_reset_r : std_logic_vector(4 downto 1); --- Slow control - signal logic_anal_control : std_logic_vector(3 downto 0); - signal debug_mode_en_i : std_logic; - signal reset_counters_i : std_logic; - signal run_mode_i : std_logic; -- 1: cc reset every trigger - -- 0: free running mode - signal run_mode_200 : std_logic; - signal trigger_win_en_i : std_logic; - signal ch_en_i : std_logic_vector(64 downto 1); - signal ref_ch_en_i : std_logic; --- Logic analyser - signal logic_anal_data_i : std_logic_vector(3*32-1 downto 0); --- Hit signals - signal hit_in_i : std_logic_vector(CHANNEL_NUMBER-1 downto 1); - signal scaler_in_i : std_logic_vector(CHANNEL_NUMBER-1 downto 1); - signal ref_time_i : std_logic; --- To the channels - signal readout_busy_i : std_logic; - signal rd_en_i : std_logic_vector(CHANNEL_NUMBER-1 downto 0); - signal trg_win_end_i : std_logic; --- From the channels - signal ch_data_i : std_logic_vector_array_32(0 to CHANNEL_NUMBER); - signal ch_empty_i : std_logic_vector(CHANNEL_NUMBER downto 0); - signal ch_full_i : std_logic_vector(CHANNEL_NUMBER-1 downto 0); - signal ch_almost_full_i : std_logic_vector(CHANNEL_NUMBER-1 downto 0); - signal trg_time_i : std_logic_vector(38 downto 0); - signal ch_lost_hit_number_i : std_logic_vector_array_24(0 to CHANNEL_NUMBER-1); - signal ch_hit_detect_number_i : std_logic_vector_array_24(0 to CHANNEL_NUMBER-1); - signal ch_encoder_start_number_i : std_logic_vector_array_24(0 to CHANNEL_NUMBER-1); - signal ch_fifo_wr_number_i : std_logic_vector_array_24(0 to CHANNEL_NUMBER-1); - signal ch_level_hit_number : std_logic_vector_array_32(0 to CHANNEL_NUMBER-1); - signal ch_lost_hit_bus_i : std_logic_vector_array_32(0 to CHANNEL_NUMBER-1); - signal ch_encoder_start_bus_i : std_logic_vector_array_32(0 to CHANNEL_NUMBER-1); - signal ch_fifo_wr_bus_i : std_logic_vector_array_32(0 to CHANNEL_NUMBER-1); --- To the endpoint - signal data_finished_i : std_logic; --- Epoch counter - signal epoch_cntr : std_logic_vector(27 downto 0); - signal epoch_cntr_up_i : std_logic; - signal epoch_cntr_reset_i : std_logic; --- Debug signals - signal ref_debug_i : std_logic_vector(31 downto 0); - signal ch_debug_i : std_logic_vector_array_32(0 to CHANNEL_NUMBER-1); - signal readout_debug_i : std_logic_vector(31 downto 0); --- Bus signals - signal status_registers_bus_i : std_logic_vector_array_32(0 to 23); - - attribute syn_keep : boolean; - attribute syn_keep of reset_tdc : signal is true; - attribute syn_keep of coarse_cntr : signal is true; - attribute syn_preserve : boolean; - attribute syn_preserve of coarse_cntr : signal is true; - -begin - --- Slow control signals - logic_anal_control <= CONTROL_REG_IN(3 downto 0) when rising_edge(CLK_READOUT); - debug_mode_en_i <= CONTROL_REG_IN(4); - reset_counters_i <= CONTROL_REG_IN(8); - run_mode_i <= CONTROL_REG_IN(12); - run_mode_200 <= run_mode_i when rising_edge(CLK_TDC); -- Run mode control register synchronised to the coarse counter clk - trigger_win_en_i <= CONTROL_REG_IN(1*32+31); - ch_en_i <= CONTROL_REG_IN(3*32+31 downto 2*32+0); - ref_ch_en_i <= CONTROL_REG_IN(16); - --- Reset signal - reset_tdc <= RESET; - --- Channel enable signals - GEN_Channel_Enable : for i in 1 to CHANNEL_NUMBER-1 generate - scaler_in_i(i) <= HIT_IN(i) and ch_en_i(i); - hit_in_i(i) <= scaler_in_i(i) and not(readout_busy_i); - end generate GEN_Channel_Enable; - ref_time_i <= REFERENCE_TIME and ref_ch_en_i; - --- Reference channel - The_Reference_Time : Reference_Channel - generic map ( - CHANNEL_ID => 0) - port map ( - RESET_200 => reset_tdc, - RESET_100 => RESET, - CLK_200 => CLK_TDC, - CLK_100 => CLK_READOUT, - HIT_IN => ref_time_i, - READ_EN_IN => rd_en_i(0), - VALID_TMG_TRG_IN => VALID_TIMING_TRG_IN, - SPIKE_DETECTED_IN => SPIKE_DETECTED_IN, - MULTI_TMG_TRG_IN => MULTI_TMG_TRG_IN, - FIFO_DATA_OUT => ch_data_i(0), - FIFO_EMPTY_OUT => ch_empty_i(0), - FIFO_FULL_OUT => ch_full_i(0), - FIFO_ALMOST_FULL_OUT => ch_almost_full_i(0), - COARSE_COUNTER_IN => coarse_cntr(1), - EPOCH_COUNTER_IN => epoch_cntr, - TRIGGER_WINDOW_END_IN => trg_win_end_i, - DATA_FINISHED_IN => data_finished_i, - RUN_MODE => run_mode_i, - TRIGGER_TIME_STAMP_OUT => trg_time_i, - REF_DEBUG_OUT => ref_debug_i); - --- Channels - GEN_Channels : for i in 1 to CHANNEL_NUMBER - 1 generate - Channels : Channel - generic map ( - CHANNEL_ID => i) - port map ( - RESET_200 => reset_tdc, - RESET_100 => RESET, - RESET_COUNTERS => reset_counters_i, - CLK_200 => CLK_TDC, - CLK_100 => CLK_READOUT, - HIT_IN => hit_in_i(i), - SCALER_IN => scaler_in_i(i), - READ_EN_IN => rd_en_i(i), - FIFO_DATA_OUT => ch_data_i(i), - FIFO_EMPTY_OUT => ch_empty_i(i), - FIFO_FULL_OUT => ch_full_i(i), - FIFO_ALMOST_FULL_OUT => ch_almost_full_i(i), - COARSE_COUNTER_IN => coarse_cntr(integer(ceil(real(i)/real(16)))), - EPOCH_COUNTER_IN => epoch_cntr, - TRIGGER_WINDOW_END_IN => trg_win_end_i, - DATA_FINISHED_IN => data_finished_i, - RUN_MODE => run_mode_i, - LOST_HIT_NUMBER => ch_lost_hit_number_i(i), - HIT_DETECT_NUMBER => ch_hit_detect_number_i(i), - ENCODER_START_NUMBER => ch_encoder_start_number_i(i), - FIFO_WR_NUMBER => ch_fifo_wr_number_i(i), - Channel_DEBUG => ch_debug_i(i)); - end generate GEN_Channels; - ch_data_i(CHANNEL_NUMBER) <= x"FFFFFFFF"; - --- Coarse counter - GenCoarseCounter : for i in 1 to 4 generate - TheCoarseCounter : up_counter - generic map ( - NUMBER_OF_BITS => 11) - port map ( - CLK => CLK_TDC, - RESET => coarse_cntr_reset_r(i), - COUNT_OUT => coarse_cntr(i), - UP_IN => '1'); - end generate GenCoarseCounter; - - Coarse_Counter_Reset : process (CLK_TDC, reset_tdc) - begin - if rising_edge(CLK_TDC) then - if reset_tdc = '1' then - coarse_cntr_reset <= '1'; - elsif run_mode_200 = '1' then - coarse_cntr_reset <= '0'; - else - coarse_cntr_reset <= trg_win_end_i; - end if; - end if; - end process Coarse_Counter_Reset; - - GenCoarseCounterReset : for i in 1 to 4 generate - coarse_cntr_reset_r(i) <= coarse_cntr_reset when rising_edge(CLK_TDC); - end generate GenCoarseCounterReset; - --- EPOCH counter - TheEpochCounter : up_counter - generic map ( - NUMBER_OF_BITS => 28) - port map ( - CLK => CLK_TDC, - RESET => epoch_cntr_reset_i, - COUNT_OUT => epoch_cntr, - UP_IN => epoch_cntr_up_i); - epoch_cntr_up_i <= and_all(coarse_cntr(1)); - epoch_cntr_reset_i <= reset_tdc or coarse_cntr_reset; - --- Bus handler entities - TheHitCounterBus : BusHandler - generic map ( - BUS_LENGTH => CHANNEL_NUMBER-1) - port map ( - RESET => RESET, - CLK => CLK_READOUT, - DATA_IN => ch_level_hit_number, - READ_EN_IN => HCB_READ_EN_IN, - WRITE_EN_IN => HCB_WRITE_EN_IN, - ADDR_IN => HCB_ADDR_IN, - DATA_OUT => HCB_DATA_OUT, - DATAREADY_OUT => HCB_DATAREADY_OUT, - UNKNOWN_ADDR_OUT => HCB_UNKNOWN_ADDR_OUT); - - GenHitCounterLevelSignals : for i in 1 to CHANNEL_NUMBER-1 generate - ch_level_hit_number(i) <= scaler_in_i(i) & "0000000" & ch_hit_detect_number_i(i) when rising_edge(CLK_READOUT); - end generate GenHitCounterLevelSignals; - - TheStatusRegistersBus: BusHandler - generic map ( - BUS_LENGTH => 23) - port map ( - RESET => RESET, - CLK => CLK_READOUT, - DATA_IN => status_registers_bus_i, - READ_EN_IN => SRB_READ_EN_IN, - WRITE_EN_IN => SRB_WRITE_EN_IN, - ADDR_IN => SRB_ADDR_IN, - DATA_OUT => SRB_DATA_OUT, - DATAREADY_OUT => SRB_DATAREADY_OUT, - UNKNOWN_ADDR_OUT => SRB_UNKNOWN_ADDR_OUT); - - TheLostHitBus : BusHandler - generic map ( - BUS_LENGTH => CHANNEL_NUMBER-1) - port map ( - RESET => RESET, - CLK => CLK_READOUT, - DATA_IN => ch_lost_hit_bus_i, - READ_EN_IN => LHB_READ_EN_IN, - WRITE_EN_IN => LHB_WRITE_EN_IN, - ADDR_IN => LHB_ADDR_IN, - DATA_OUT => LHB_DATA_OUT, - DATAREADY_OUT => LHB_DATAREADY_OUT, - UNKNOWN_ADDR_OUT => LHB_UNKNOWN_ADDR_OUT); - - GenLostHitBus : for i in 1 to CHANNEL_NUMBER-1 generate - ch_lost_hit_bus_i(i) <= x"00" & ch_lost_hit_number_i(i) when rising_edge(CLK_READOUT); - end generate GenLostHitBus; - - TheEncoderStartBus : BusHandler - generic map ( - BUS_LENGTH => CHANNEL_NUMBER-1) - port map ( - RESET => RESET, - CLK => CLK_READOUT, - DATA_IN => ch_encoder_start_bus_i, - READ_EN_IN => ESB_READ_EN_IN, - WRITE_EN_IN => ESB_WRITE_EN_IN, - ADDR_IN => ESB_ADDR_IN, - DATA_OUT => ESB_DATA_OUT, - DATAREADY_OUT => ESB_DATAREADY_OUT, - UNKNOWN_ADDR_OUT => ESB_UNKNOWN_ADDR_OUT); - - GenEncoderStartBus : for i in 1 to CHANNEL_NUMBER-1 generate - ch_encoder_start_bus_i(i) <= x"00" & ch_encoder_start_number_i(i) when rising_edge(CLK_READOUT); - end generate GenEncoderStartBus; - - TheFifoWriteBus : BusHandler - generic map ( - BUS_LENGTH => CHANNEL_NUMBER-1) - port map ( - RESET => RESET, - CLK => CLK_READOUT, - DATA_IN => ch_fifo_wr_bus_i, - READ_EN_IN => FWB_READ_EN_IN, - WRITE_EN_IN => FWB_WRITE_EN_IN, - ADDR_IN => FWB_ADDR_IN, - DATA_OUT => FWB_DATA_OUT, - DATAREADY_OUT => FWB_DATAREADY_OUT, - UNKNOWN_ADDR_OUT => FWB_UNKNOWN_ADDR_OUT); - - GenFifoWriteBus : for i in 1 to CHANNEL_NUMBER-1 generate - ch_fifo_wr_bus_i(i) <= x"00" & ch_fifo_wr_number_i(i) when rising_edge(CLK_READOUT); - end generate GenFifoWriteBus; - - --- Readout - TheReadout : Readout - generic map ( - CHANNEL_NUMBER => CHANNEL_NUMBER, - STATUS_REG_NR => STATUS_REG_NR) - port map ( - CLK_200 => CLK_TDC, - RESET_200 => reset_tdc, - CLK_100 => CLK_READOUT, - RESET_100 => RESET, - RESET_COUNTERS => reset_counters_i, - HIT_IN => scaler_in_i, - REFERENCE_TIME => REFERENCE_TIME, - TRIGGER_TIME_IN => trg_time_i, - TRG_WIN_PRE => TRG_WIN_PRE, - TRG_WIN_POST => TRG_WIN_POST, - DEBUG_MODE_EN_IN => debug_mode_en_i, - TRIGGER_WIN_EN_IN => trigger_win_en_i, - CH_DATA_IN => ch_data_i, - CH_EMPTY_IN => ch_empty_i, - CH_FULL_IN => ch_full_i, - CH_ALMOST_FULL_IN => ch_almost_full_i, - TRG_DATA_VALID_IN => TRG_DATA_VALID_IN, - VALID_TIMING_TRG_IN => VALID_TIMING_TRG_IN, - VALID_NOTIMING_TRG_IN => VALID_NOTIMING_TRG_IN, - INVALID_TRG_IN => INVALID_TRG_IN, - TMGTRG_TIMEOUT_IN => TMGTRG_TIMEOUT_IN, - SPIKE_DETECTED_IN => SPIKE_DETECTED_IN, - MULTI_TMG_TRG_IN => MULTI_TMG_TRG_IN, - SPURIOUS_TRG_IN => SPURIOUS_TRG_IN, - TRG_NUMBER_IN => TRG_NUMBER_IN, - TRG_CODE_IN => TRG_CODE_IN, - TRG_INFORMATION_IN => TRG_INFORMATION_IN, - TRG_TYPE_IN => TRG_TYPE_IN, - TRG_RELEASE_OUT => TRG_RELEASE_OUT, - TRG_STATUSBIT_OUT => TRG_STATUSBIT_OUT, - DATA_OUT => DATA_OUT, - DATA_WRITE_OUT => DATA_WRITE_OUT, - DATA_FINISHED_OUT => data_finished_i, - READOUT_BUSY_OUT => readout_busy_i, - READ_EN_OUT => rd_en_i, - TRIGGER_WIN_END_OUT => trg_win_end_i, - SLOW_CONTROL_REG_OUT => SLOW_CONTROL_REG_OUT, - STATUS_REGISTERS_BUS_OUT => status_registers_bus_i, - READOUT_DEBUG => readout_debug_i); - DATA_FINISHED_OUT <= data_finished_i; - --- Logic Analyser - TheLogicAnalyser : LogicAnalyser - generic map ( - CHANNEL_NUMBER => CHANNEL_NUMBER, - STATUS_REG_NR => STATUS_REG_NR) - port map ( - CLK => CLK_READOUT, - RESET => RESET, - DATA_IN => logic_anal_data_i, - CONTROL_IN => logic_anal_control, - DATA_OUT => LOGIC_ANALYSER_OUT); - - logic_anal_data_i(7 downto 0) <= readout_debug_i(7 downto 0); - logic_anal_data_i(8) <= REFERENCE_TIME; - logic_anal_data_i(9) <= VALID_TIMING_TRG_IN; - logic_anal_data_i(10) <= VALID_NOTIMING_TRG_IN; - logic_anal_data_i(11) <= INVALID_TRG_IN; - logic_anal_data_i(12) <= TRG_DATA_VALID_IN; - logic_anal_data_i(13) <= readout_debug_i(8); --data_wr_reg; - logic_anal_data_i(14) <= readout_debug_i(9); --data_finished_reg; - logic_anal_data_i(15) <= readout_debug_i(10); --trg_release_reg; - logic_anal_data_i(31 downto 16) <= ref_debug_i(15 downto 0); - logic_anal_data_i(37 downto 32) <= readout_debug_i(16 downto 11); --data_out_reg(27 downto 22); - logic_anal_data_i(47 downto 38) <= (others => '0'); - logic_anal_data_i(63 downto 48) <= ch_debug_i(1)(15 downto 0); - logic_anal_data_i(95 downto 64) <= (others => '0'); - -end TDC; diff --git a/tdc_releases/tdc_v_stretcher/bit_sync.vhd b/tdc_releases/tdc_v_stretcher/bit_sync.vhd deleted file mode 100644 index ba9adb2..0000000 --- a/tdc_releases/tdc_v_stretcher/bit_sync.vhd +++ /dev/null @@ -1,60 +0,0 @@ ---synchronizes a single bit to a different clock domain - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity bit_sync is - generic( - DEPTH : integer := 3 - ); - port( - RESET : in std_logic; --Reset is neceessary to avoid optimization to shift register - CLK0 : in std_logic; --clock for first FF - CLK1 : in std_logic; --Clock for other FF - D_IN : in std_logic; --Data input - D_OUT : out std_logic --Data output - ); -end entity; - -architecture behavioral of bit_sync is - - signal sync_q : std_logic_vector(DEPTH downto 0); - - attribute syn_preserve : boolean; - attribute syn_keep : boolean; - attribute syn_keep of sync_q : signal is true; - attribute syn_preserve of sync_q : signal is true; - - -begin - sync_q(0) <= D_IN; - D_OUT <= sync_q(DEPTH); - - process(CLK0) - begin - if rising_edge(CLK0) then - if RESET = '1' then - sync_q(1) <= '0'; - else - sync_q(1) <= sync_q(0); - end if; - end if; - end process; - - gen_others : if DEPTH > 1 generate - gen_flipflops : for i in 2 to DEPTH generate - process(CLK1) - begin - if rising_edge(CLK1) then - if RESET = '1' then - sync_q(i) <= '0'; - else - sync_q(i) <= sync_q(i-1); - end if; - end if; - end process; - end generate; - end generate; - -end architecture; diff --git a/tdc_releases/tdc_v_stretcher/trb3_periph_constraints.lpf.jan b/tdc_releases/tdc_v_stretcher/trb3_periph_constraints.lpf.jan deleted file mode 100644 index 5beb625..0000000 --- a/tdc_releases/tdc_v_stretcher/trb3_periph_constraints.lpf.jan +++ /dev/null @@ -1,1381 +0,0 @@ -BLOCK RESETPATHS ; -BLOCK ASYNCPATHS ; -BLOCK RD_DURING_WR_PATHS ; - -################################################################# -# Reset Nets -################################################################# -GSR_NET NET "GSR_N"; - -################################################################# -# Locate Serdes and media interfaces -################################################################# -LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ; - -REGION "MEDIA_UPLINK" "R105C104D" 10 27; -REGION "REGION_SPI" "R2C104D" 15 18 DEVSIZE; - -LOCATE UGROUP "THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ; -LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ; - -LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ; - -MULTICYCLE TO CELL "THE_MEDIA_DOWNLINK/SCI_DATA_OUT*" 50 ns; -MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns; -MULTICYCLE TO CELL "THE_RESET_HANDLER/final_reset*" 30 ns; - - -#Jan: Placement of TrbNet components (at least, most of them) -REGION "REGION_TRBNET" "R38C104D" 67 27 DEVSIZE; -#UGROUP "TrbNet" BBOX 77 27 -# BLKNAME THE_ENDPOINT -# BLKNAME THE_ENDPOINT/THE_ENDPOINT -#LOCATE UGROUP "TrbNet" REGION "REGION_TRBNET"; -LOCATE UGROUP "THE_BUS_HANDLER/Bus_handler_group" REGION "REGION_TRBNET"; -LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group" REGION "REGION_TRBNET"; -LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group" REGION "REGION_TRBNET"; -LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_2_gentermbuf_termbuf/TRMBUF_group" REGION "REGION_TRBNET"; -LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group" REGION "REGION_TRBNET"; -LOCATE UGROUP "THE_ENDPOINT/THE_INTERNAL_BUS_HANDLER/Bus_handler_group" REGION "REGION_TRBNET"; -LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/MPLEX/MUX_group" REGION "REGION_TRBNET"; -LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/HUBLOGIC_group" REGION "REGION_TRBNET"; -LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/RegIO_group" REGION "REGION_TRBNET"; -LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/API_group" REGION "REGION_TRBNET"; -LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/API_group" REGION "REGION_TRBNET"; -LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "REGION_TRBNET"; -LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_TRBNET"; -LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "REGION_TRBNET"; -LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_TRBNET"; -LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "REGION_TRBNET"; -LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_TRBNET"; - -################################################################# -# TDC Constraints -################################################################# -############################################################################## -## REGION DECLERATION ## -############################################################################## -#REGION "Region_E&F_1" "R11C120D" 10 44 DEVSIZE; -#REGION "Region_E&F_2" "R24C128D" 5 44 DEVSIZE; -#REGION "Region_E&F_3" "R38C128D" 10 44 DEVSIZE; -#REGION "Region_E&F_4" "R56C128D" 10 44 DEVSIZE; -#REGION "Region_E&F_5" "R74C128D" 10 44 DEVSIZE; -#REGION "Region_E&F_6" "R92C128D" 10 44 DEVSIZE; -#REGION "Region_E&F_7" "R105C128D" 5 44 DEVSIZE; - -#REGION "Region_E&F_8" "R11C69D" 10 44 DEVSIZE; -#REGION "Region_E&F_9" "R24C69D" 5 44 DEVSIZE; -#REGION "Region_E&F_10" "R38C69D" 10 44 DEVSIZE; -#REGION "Region_E&F_11" "R56C69D" 10 44 DEVSIZE; -#REGION "Region_E&F_12" "R74C69D" 10 44 DEVSIZE; -#REGION "Region_E&F_13" "R92C69D" 10 44 DEVSIZE; -#REGION "Region_E&F_14" "R105C69D" 5 44 DEVSIZE; - -#REGION "Region_E&F_15" "R11C10D" 10 44 DEVSIZE; -#REGION "Region_E&F_16" "R24C10D" 5 44 DEVSIZE; -#REGION "Region_E&F_17" "R38C10D" 10 44 DEVSIZE; -#REGION "Region_E&F_18" "R56C10D" 10 44 DEVSIZE; -#REGION "Region_E&F_19" "R74C10D" 10 44 DEVSIZE; - - -PROHIBIT SECONDARY NET "THE_TDC/The_Reference_Time/ff_array_en_i"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels_*_Channels/Channel_200_1/ff_array_en_i"; - - -############################################################################## -## REFERENCE CHANNEL PLACEMENT ## -############################################################################## -UGROUP "Ref_Ch" BBOX 1 51 - BLKNAME THE_TDC/The_Reference_Time/Reference_Channel_200_1/FC; -LOCATE UGROUP "Ref_Ch" SITE "R8C131D" ; -UGROUP "ref_hit" BBOX 1 1 - BLKNAME THE_TDC/The_Reference_Time/hit_buf_RNO; -LOCATE UGROUP "ref_hit" SITE "R9C133D" ; -UGROUP "Ref_ff_en" BBOX 1 1 - BLKNAME THE_TDC/The_Reference_Time/Reference_Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "Ref_ff_en" SITE "R8C156D" ; - -#UGROUP "Ref_Ch" BBOX 1 51 -# BLKNAME THE_TDC/The_Reference_Time/FC; -#LOCATE UGROUP "Ref_Ch" SITE "R8C131D" ; -#UGROUP "ref_hit" BBOX 1 1 -# BLKNAME THE_TDC/The_Reference_Time/hit_buf_RNO; -#LOCATE UGROUP "ref_hit" SITE "R9C133D" ; -#UGROUP "Ref_ff_en" BBOX 1 1 -# BLKNAME THE_TDC/The_Reference_Time/ff_array_en_i_1_i; -#LOCATE UGROUP "Ref_ff_en" SITE "R8C156D" ; - -############################################################################## -## DELAY LINE and HIT BUFFER PLACEMENTS ## -############################################################################## -UGROUP "FC_1" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_1_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_1" SITE "R10C131D" ; -UGROUP "hit_1" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels_1_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_1" SITE "R11C133D" ; -UGROUP "ff_en_1" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels_1_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_1" SITE "R10C156D" ; -# -UGROUP "FC_2" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_2_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_2" SITE "R21C131D" ; -UGROUP "hit_2" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels_2_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_2" SITE "R22C133D" ; -UGROUP "ff_en_2" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels_2_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_2" SITE "R21C156D" ; -# -UGROUP "FC_3" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_3_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_3" SITE "R23C131D" ; -UGROUP "hit_3" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels_3_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_3" SITE "R24C133D" ; -UGROUP "ff_en_3" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels_3_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_3" SITE "R23C156D" ; -# -UGROUP "FC_4" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_4_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_4" SITE "R30C131D" ; -UGROUP "hit_4" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels_4_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_4" SITE "R31C133D" ; -UGROUP "ff_en_4" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels_4_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_4" SITE "R30C156D" ; -# -UGROUP "FC_5" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_5_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_5" SITE "R32C131D" ; -UGROUP "hit_5" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels_5_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_5" SITE "R33C133D" ; -UGROUP "ff_en_5" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels_5_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_5" SITE "R32C156D" ; -# -UGROUP "FC_6" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_6_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_6" SITE "R35C131D" ; -UGROUP "hit_6" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels_6_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_6" SITE "R36C133D" ; -UGROUP "ff_en_6" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels_6_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_6" SITE "R35C156D" ; -# -UGROUP "FC_7" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_7_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_7" SITE "R37C131D" ; -UGROUP "hit_7" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels_7_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_7" SITE "R38C133D" ; -UGROUP "ff_en_7" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels_7_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_7" SITE "R37C156D" ; -# -UGROUP "FC_8" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_8_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_8" SITE "R48C131D" ; -UGROUP "hit_8" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels_8_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_8" SITE "R49C133D" ; -UGROUP "ff_en_8" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels_8_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_8" SITE "R48C156D" ; -# -UGROUP "FC_9" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_9_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_9" SITE "R50C131D" ; -UGROUP "hit_9" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels_9_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_9" SITE "R51C133D" ; -UGROUP "ff_en_9" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels_9_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_9" SITE "R50C156D" ; -# -UGROUP "FC_10" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_10_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_10" SITE "R53C131D" ; -UGROUP "hit_10" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels_10_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_10" SITE "R54C133D" ; -UGROUP "ff_en_10" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels_10_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_10" SITE "R53C156D" ; -# -UGROUP "FC_11" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_11_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_11" SITE "R55C131D" ; -UGROUP "hit_11" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels_11_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_11" SITE "R56C133D" ; -UGROUP "ff_en_11" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels_11_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_11" SITE "R55C156D" ; -# -UGROUP "FC_12" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_12_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_12" SITE "R66C131D" ; -UGROUP "hit_12" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels_12_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_12" SITE "R67C133D" ; -UGROUP "ff_en_12" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels_12_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_12" SITE "R66C156D" ; -# -UGROUP "FC_13" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_13_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_13" SITE "R68C131D" ; -UGROUP "hit_13" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels_13_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_13" SITE "R69C133D" ; -UGROUP "ff_en_13" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels_13_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_13" SITE "R68C156D" ; -# -UGROUP "FC_14" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_14_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_14" SITE "R71C131D" ; -UGROUP "hit_14" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels_14_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_14" SITE "R72C133D" ; -UGROUP "ff_en_14" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels_14_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_14" SITE "R71C156D" ; -# -UGROUP "FC_15" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_15_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_15" SITE "R73C131D" ; -UGROUP "hit_15" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels_15_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_15" SITE "R74C133D" ; -UGROUP "ff_en_15" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels_15_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_15" SITE "R73C156D" ; -# -UGROUP "FC_16" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_16_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_16" SITE "R84C131D" ; -UGROUP "hit_16" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels_16_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_16" SITE "R85C133D" ; -UGROUP "ff_en_16" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels_16_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_16" SITE "R84C156D" ; -# -UGROUP "FC_17" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_17_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_17" SITE "R86C131D" ; -UGROUP "hit_17" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels_17_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_17" SITE "R87C133D" ; -UGROUP "ff_en_17" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels_17_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_17" SITE "R86C156D" ; -# -UGROUP "FC_18" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_18_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_18" SITE "R89C131D" ; -UGROUP "hit_18" - BLKNAME THE_TDC/GEN_Channels_18_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_18" SITE "R90C133D" ; -UGROUP "ff_en_18" - BLKNAME THE_TDC/GEN_Channels_18_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_18" SITE "R89C156D" ; -# -UGROUP "FC_19" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_19_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_19" SITE "R91C131D" ; -UGROUP "hit_19" - BLKNAME THE_TDC/GEN_Channels_19_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_19" SITE "R92C133D" ; -UGROUP "ff_en_19" - BLKNAME THE_TDC/GEN_Channels_19_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_19" SITE "R91C156D" ; -# -UGROUP "FC_20" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_20_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_20" SITE "R102C131D" ; -UGROUP "hit_20" - BLKNAME THE_TDC/GEN_Channels_20_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_20" SITE "R103C133D" ; -UGROUP "ff_en_20" - BLKNAME THE_TDC/GEN_Channels_20_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_20" SITE "R102C156D" ; -# -UGROUP "FC_21" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_21_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_21" SITE "R104C131D" ; -UGROUP "hit_21" - BLKNAME THE_TDC/GEN_Channels_21_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_21" SITE "R105C133D" ; -UGROUP "ff_en_21" - BLKNAME THE_TDC/GEN_Channels_21_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_21" SITE "R104C156D" ; -# -UGROUP "FC_22" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_22_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_22" SITE "R111C131D" ; -UGROUP "hit_22" - BLKNAME THE_TDC/GEN_Channels_22_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_22" SITE "R112C133D" ; -UGROUP "ff_en_22" - BLKNAME THE_TDC/GEN_Channels_22_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_22" SITE "R111C156D" ; -# -UGROUP "FC_23" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_23_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_23" SITE "R113C131D" ; -UGROUP "hit_23" - BLKNAME THE_TDC/GEN_Channels_23_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_23" SITE "R114C133D" ; -UGROUP "ff_en_23" - BLKNAME THE_TDC/GEN_Channels_23_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_23" SITE "R113C156D" ; -# -# -# -UGROUP "FC_24" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_24_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_24" SITE "R8C53D" ; -UGROUP "hit_24" - BLKNAME THE_TDC/GEN_Channels_24_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_24" SITE "R9C55D" ; -UGROUP "ff_en_24" - BLKNAME THE_TDC/GEN_Channels_24_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_24" SITE "R8C78D" ; -# -UGROUP "FC_25" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_25_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_25" SITE "R10C53D" ; -UGROUP "hit_25" - BLKNAME THE_TDC/GEN_Channels_25_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_25" SITE "R11C55D" ; -UGROUP "ff_en_25" - BLKNAME THE_TDC/GEN_Channels_25_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_25" SITE "R10C78D" ; -# -UGROUP "FC_26" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_26_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_26" SITE "R21C53D" ; -UGROUP "hit_26" - BLKNAME THE_TDC/GEN_Channels_26_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_26" SITE "R22C55D" ; -UGROUP "ff_en_26" - BLKNAME THE_TDC/GEN_Channels_26_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_26" SITE "R21C78D" ; -# -UGROUP "FC_27" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_27_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_27" SITE "R23C53D" ; -UGROUP "hit_27" - BLKNAME THE_TDC/GEN_Channels_27_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_27" SITE "R24C55D" ; -UGROUP "ff_en_27" - BLKNAME THE_TDC/GEN_Channels_27_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_27" SITE "R23C78D" ; -# -UGROUP "FC_28" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_28_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_28" SITE "R30C53D" ; -UGROUP "hit_28" - BLKNAME THE_TDC/GEN_Channels_28_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_28" SITE "R31C55D" ; -UGROUP "ff_en_28" - BLKNAME THE_TDC/GEN_Channels_28_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_28" SITE "R30C78D" ; -# -UGROUP "FC_29" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_29_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_29" SITE "R32C53D" ; -UGROUP "hit_29" - BLKNAME THE_TDC/GEN_Channels_29_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_29" SITE "R33C55D" ; -UGROUP "ff_en_29" - BLKNAME THE_TDC/GEN_Channels_29_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_29" SITE "R32C78D" ; -# -UGROUP "FC_30" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_30_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_30" SITE "R35C53D" ; -UGROUP "hit_30" - BLKNAME THE_TDC/GEN_Channels_30_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_30" SITE "R36C55D" ; -UGROUP "ff_en_30" - BLKNAME THE_TDC/GEN_Channels_30_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_30" SITE "R35C78D" ; -# -UGROUP "FC_31" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_31_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_31" SITE "R37C53D" ; -UGROUP "hit_31" - BLKNAME THE_TDC/GEN_Channels_31_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_31" SITE "R38C55D" ; -UGROUP "ff_en_31" - BLKNAME THE_TDC/GEN_Channels_31_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_31" SITE "R37C78D" ; -# -UGROUP "FC_32" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_32_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_32" SITE "R48C53D" ; -UGROUP "hit_32" - BLKNAME THE_TDC/GEN_Channels_32_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_32" SITE "R49C55D" ; -UGROUP "ff_en_32" - BLKNAME THE_TDC/GEN_Channels_32_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_32" SITE "R48C78D" ; -# -UGROUP "FC_33" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_33_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_33" SITE "R50C53D" ; -UGROUP "hit_33" - BLKNAME THE_TDC/GEN_Channels_33_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_33" SITE "R51C55D" ; -UGROUP "ff_en_33" - BLKNAME THE_TDC/GEN_Channels_33_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_33" SITE "R50C78D" ; -# -UGROUP "FC_34" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_34_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_34" SITE "R89C53D" ; -UGROUP "hit_34" - BLKNAME THE_TDC/GEN_Channels_34_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_34" SITE "R90C55D" ; -UGROUP "ff_en_34" - BLKNAME THE_TDC/GEN_Channels_34_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_34" SITE "R89C78D" ; -# -UGROUP "FC_35" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_35_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_35" SITE "R91C53D" ; -UGROUP "hit_35" - BLKNAME THE_TDC/GEN_Channels_35_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_35" SITE "R92C55D" ; -UGROUP "ff_en_35" - BLKNAME THE_TDC/GEN_Channels_35_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_35" SITE "R91C78D" ; -# -UGROUP "FC_36" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_36_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_36" SITE "R102C53D" ; -UGROUP "hit_36" - BLKNAME THE_TDC/GEN_Channels_36_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_36" SITE "R103C55D" ; -UGROUP "ff_en_36" - BLKNAME THE_TDC/GEN_Channels_36_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_36" SITE "R102C78D" ; -# -UGROUP "FC_37" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_37_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_37" SITE "R104C53D" ; -UGROUP "hit_37" - BLKNAME THE_TDC/GEN_Channels_37_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_37" SITE "R105C55D" ; -UGROUP "ff_en_37" - BLKNAME THE_TDC/GEN_Channels_37_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_37" SITE "R104C78D" ; -# -UGROUP "FC_38" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_38_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_38" SITE "R111C53D" ; -UGROUP "hit_38" - BLKNAME THE_TDC/GEN_Channels_38_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_38" SITE "R112C55D" ; -UGROUP "ff_en_38" - BLKNAME THE_TDC/GEN_Channels_38_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_38" SITE "R111C78D" ; -# -UGROUP "FC_39" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_39_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_39" SITE "R113C53D" ; -UGROUP "hit_39" - BLKNAME THE_TDC/GEN_Channels_39_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_39" SITE "R114C55D" ; -UGROUP "ff_en_39" - BLKNAME THE_TDC/GEN_Channels_39_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_39" SITE "R113C78D" ; -# -UGROUP "FC_40" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_40_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_40" SITE "R84C53D" ; -UGROUP "hit_40" - BLKNAME THE_TDC/GEN_Channels_40_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_40" SITE "R85C55D" ; -UGROUP "ff_en_40" - BLKNAME THE_TDC/GEN_Channels_40_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_40" SITE "R84C78D" ; -# -UGROUP "FC_41" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_41_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_41" SITE "R86C2D" ; -UGROUP "hit_41" - BLKNAME THE_TDC/GEN_Channels_41_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_41" SITE "R87C4D" ; -UGROUP "ff_en_41" - BLKNAME THE_TDC/GEN_Channels_41_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_41" SITE "R86C27D" ; -# -UGROUP "FC_42" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_42_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_42" SITE "R89C2D" ; -UGROUP "hit_42" - BLKNAME THE_TDC/GEN_Channels_42_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_42" SITE "R90C4D" ; -UGROUP "ff_en_42" - BLKNAME THE_TDC/GEN_Channels_42_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_42" SITE "R89C27D" ; -# -UGROUP "FC_43" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_43_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_43" SITE "R91C2D" ; -UGROUP "hit_43" - BLKNAME THE_TDC/GEN_Channels_43_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_43" SITE "R92C4D" ; -UGROUP "ff_en_43" - BLKNAME THE_TDC/GEN_Channels_43_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_43" SITE "R91C27D" ; -# -UGROUP "FC_44" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_44_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_44" SITE "R102C2D" ; -UGROUP "hit_44" - BLKNAME THE_TDC/GEN_Channels_44_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_44" SITE "R103C4D" ; -UGROUP "ff_en_44" - BLKNAME THE_TDC/GEN_Channels_44_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_44" SITE "R102C27D" ; -# -UGROUP "FC_45" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_45_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_45" SITE "R104C2D" ; -UGROUP "hit_45" - BLKNAME THE_TDC/GEN_Channels_45_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_45" SITE "R105C4D" ; -UGROUP "ff_en_45" - BLKNAME THE_TDC/GEN_Channels_45_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_45" SITE "R104C27D" ; -# -UGROUP "FC_46" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_46_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_46" SITE "R111C2D" ; -UGROUP "hit_46" - BLKNAME THE_TDC/GEN_Channels_46_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_46" SITE "R112C4D" ; -UGROUP "ff_en_46" - BLKNAME THE_TDC/GEN_Channels_46_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_46" SITE "R111C27D" ; -# -UGROUP "FC_47" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_47_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_47" SITE "R113C2D" ; -UGROUP "hit_47" - BLKNAME THE_TDC/GEN_Channels_47_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_47" SITE "R114C4D" ; -UGROUP "ff_en_47" - BLKNAME THE_TDC/GEN_Channels_47_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_47" SITE "R113C27D" ; -# -# -# -UGROUP "FC_48" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_48_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_48" SITE "R8C2D" ; -UGROUP "hit_48" - BLKNAME THE_TDC/GEN_Channels_48_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_48" SITE "R9C4D" ; -UGROUP "ff_en_48" - BLKNAME THE_TDC/GEN_Channels_48_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_48" SITE "R8C27D" ; -# -UGROUP "FC_49" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_49_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_49" SITE "R10C2D" ; -UGROUP "hit_49" - BLKNAME THE_TDC/GEN_Channels_49_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_49" SITE "R11C4D" ; -UGROUP "ff_en_49" - BLKNAME THE_TDC/GEN_Channels_49_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_49" SITE "R10C27D" ; -# -UGROUP "FC_50" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_50_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_50" SITE "R21C2D" ; -UGROUP "hit_50" - BLKNAME THE_TDC/GEN_Channels_50_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_50" SITE "R22C4D" ; -UGROUP "ff_en_50" - BLKNAME THE_TDC/GEN_Channels_50_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_50" SITE "R21C27D" ; -# -UGROUP "FC_51" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_51_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_51" SITE "R23C2D" ; -UGROUP "hit_51" - BLKNAME THE_TDC/GEN_Channels_51_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_51" SITE "R24C4D" ; -UGROUP "ff_en_51" - BLKNAME THE_TDC/GEN_Channels_51_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_51" SITE "R23C27D" ; -# -UGROUP "FC_52" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_52_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_52" SITE "R30C2D" ; -UGROUP "hit_52" - BLKNAME THE_TDC/GEN_Channels_52_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_52" SITE "R31C4D" ; -UGROUP "ff_en_52" - BLKNAME THE_TDC/GEN_Channels_52_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_52" SITE "R30C27D" ; -# -UGROUP "FC_53" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_53_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_53" SITE "R32C2D" ; -UGROUP "hit_53" - BLKNAME THE_TDC/GEN_Channels_53_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_53" SITE "R33C4D" ; -UGROUP "ff_en_53" - BLKNAME THE_TDC/GEN_Channels_53_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_53" SITE "R32C27D" ; -# -UGROUP "FC_54" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_54_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_54" SITE "R35C2D" ; -UGROUP "hit_54" - BLKNAME THE_TDC/GEN_Channels_54_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_54" SITE "R36C4D" ; -UGROUP "ff_en_54" - BLKNAME THE_TDC/GEN_Channels_54_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_54" SITE "R35C27D" ; -# -UGROUP "FC_55" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_55_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_55" SITE "R37C2D" ; -UGROUP "hit_55" - BLKNAME THE_TDC/GEN_Channels_55_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_55" SITE "R38C4D" ; -UGROUP "ff_en_55" - BLKNAME THE_TDC/GEN_Channels_55_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_55" SITE "R37C27D" ; -# -UGROUP "FC_56" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_56_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_56" SITE "R48C2D" ; -UGROUP "hit_56" - BLKNAME THE_TDC/GEN_Channels_56_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_56" SITE "R49C4D" ; -UGROUP "ff_en_56" - BLKNAME THE_TDC/GEN_Channels_56_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_56" SITE "R48C27D" ; -# -UGROUP "FC_57" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_57_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_57" SITE "R50C2D" ; -UGROUP "hit_57" - BLKNAME THE_TDC/GEN_Channels_57_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_57" SITE "R51C4D" ; -UGROUP "ff_en_57" - BLKNAME THE_TDC/GEN_Channels_57_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_57" SITE "R50C27D" ; -# -UGROUP "FC_58" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_58_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_58" SITE "R53C2D" ; -UGROUP "hit_58" - BLKNAME THE_TDC/GEN_Channels_58_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_58" SITE "R54C4D" ; -UGROUP "ff_en_58" - BLKNAME THE_TDC/GEN_Channels_58_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_58" SITE "R53C27D" ; -# -UGROUP "FC_59" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_59_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_59" SITE "R55C2D" ; -UGROUP "hit_59" - BLKNAME THE_TDC/GEN_Channels_59_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_59" SITE "R56C4D" ; -UGROUP "ff_en_59" - BLKNAME THE_TDC/GEN_Channels_59_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_59" SITE "R55C27D" ; -# -UGROUP "FC_60" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_60_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_60" SITE "R66C2D" ; -UGROUP "hit_60" - BLKNAME THE_TDC/GEN_Channels_60_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_60" SITE "R67C4D" ; -UGROUP "ff_en_60" - BLKNAME THE_TDC/GEN_Channels_60_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_60" SITE "R66C27D" ; -# -UGROUP "FC_61" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_61_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_61" SITE "R68C2D" ; -UGROUP "hit_61" - BLKNAME THE_TDC/GEN_Channels_61_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_61" SITE "R69C4D" ; -UGROUP "ff_en_61" - BLKNAME THE_TDC/GEN_Channels_61_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_61" SITE "R68C27D" ; -# -UGROUP "FC_62" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_62_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_62" SITE "R71C2D" ; -UGROUP "hit_62" - BLKNAME THE_TDC/GEN_Channels_62_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_62" SITE "R72C4D" ; -UGROUP "ff_en_62" - BLKNAME THE_TDC/GEN_Channels_62_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_62" SITE "R71C27D" ; -# -UGROUP "FC_63" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_63_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_63" SITE "R73C2D" ; -UGROUP "hit_63" - BLKNAME THE_TDC/GEN_Channels_63_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_63" SITE "R74C4D" ; -UGROUP "ff_en_63" - BLKNAME THE_TDC/GEN_Channels_63_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_63" SITE "R73C27D" ; -# -UGROUP "FC_64" BBOX 1 51 - BLKNAME THE_TDC/GEN_Channels_64_Channels/Channel_200_1/FC; -LOCATE UGROUP "FC_64" SITE "R84C2D" ; -UGROUP "hit_64" - BLKNAME THE_TDC/GEN_Channels_64_Channels/hit_buf_RNO; -LOCATE UGROUP "hit_64" SITE "R85C4D" ; -UGROUP "ff_en_64" - BLKNAME THE_TDC/GEN_Channels_64_Channels/Channel_200_1/ff_array_en_i_1_i; -LOCATE UGROUP "ff_en_64" SITE "R84C27D" ; - - - -############################################################################## -## CHANNEL PLACEMENTS ## -############################################################################## -UGROUP "E&F_ref" BBOX 6 21 - BLKNAME THE_TDC/The_Reference_Time/Reference_Channel_200_1; -LOCATE UGROUP "E&F_ref" SITE "R11C134D" ; - -#UGROUP "E&F_ref" BBOX 6 21 -# BLKNAME THE_TDC/The_Reference_Time/hit_detect_i -# BLKNAME THE_TDC/The_Reference_Time/hit_detect_reg -# BLKNAME THE_TDC/The_Reference_Time/Start_Encoder_un7_hit_detect_reg -# BLKNAME THE_TDC/The_Reference_Time/result_2_reg -# BLKNAME THE_TDC/The_Reference_Time/FIFO -# BLKNAME THE_TDC/The_Reference_Time/Encoder; -## LOCATE UGROUP "E&F_ref" REGION "Region_E&F_1" ; -#LOCATE UGROUP "E&F_ref" SITE "R11C134D" ; -UGROUP "E&F_1" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_1_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_1_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_1_Channels/Start_Encoder_un7_hit_detect_regdup -# BLKNAME THE_TDC/GEN_Channels_1_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_1_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_1_Channels/Channel_200_1; -# LOCATE UGROUP "E&F_1" REGION "Region_E&F_1" ; -LOCATE UGROUP "E&F_1" SITE "R11C155D" ; -UGROUP "E&F_2" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_2_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_2_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_2_Channels/Start_Encoder_un7_hit_detect_regdup -# BLKNAME THE_TDC/GEN_Channels_2_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_2_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_2_Channels/Channel_200_1; -# LOCATE UGROUP "E&F_2" REGION "Region_E&F_1" ; -LOCATE UGROUP "E&F_2" SITE "R15C134D" ; -UGROUP "E&F_3" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_3_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_3_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_3_Channels/Start_Encoder_un7_hit_detect_regdup -# BLKNAME THE_TDC/GEN_Channels_3_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_3_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_3_Channels/Channel_200_1; -# LOCATE UGROUP "E&F_3" REGION "Region_E&F_1" ; -LOCATE UGROUP "E&F_3" SITE "R15C155D" ; -UGROUP "E&F_4" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_4_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_4_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_4_Channels/Start_Encoder_un7_hit_detect_regdup -# BLKNAME THE_TDC/GEN_Channels_4_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_4_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_4_Channels/Channel_200_1; -# LOCATE UGROUP "E&F_4" REGION "Region_E&F_2" ; -LOCATE UGROUP "E&F_4" SITE "R24C134D" ; -UGROUP "E&F_5" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_5_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_5_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_5_Channels/Start_Encoder_un7_hit_detect_regdup -# BLKNAME THE_TDC/GEN_Channels_5_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_5_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_5_Channels/Channel_200_1; -# LOCATE UGROUP "E&F_5" REGION "Region_E&F_2" ; -LOCATE UGROUP "E&F_5" SITE "R24C155D" ; -UGROUP "E&F_6" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_6_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_6_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_6_Channels/Start_Encoder_un7_hit_detect_regdup -# BLKNAME THE_TDC/GEN_Channels_6_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_6_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_6_Channels/Channel_200_1; -# # LOCATE UGROUP "E&F_6" REGION "Region_E&F_3" ; -LOCATE UGROUP "E&F_6" SITE "R38C134D" ; -UGROUP "E&F_7" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_7_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_7_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_7_Channels/Start_Encoder_un7_hit_detect_regdup -# BLKNAME THE_TDC/GEN_Channels_7_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_7_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_7_Channels/Channel_200_1; -# # LOCATE UGROUP "E&F_7" REGION "Region_E&F_3" ; -LOCATE UGROUP "E&F_7" SITE "R38C155D" ; -UGROUP "E&F_8" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_8_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_8_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_8_Channels/Start_Encoder_un7_hit_detect_regdup -# BLKNAME THE_TDC/GEN_Channels_8_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_8_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_8_Channels/Channel_200_1; -# # LOCATE UGROUP "E&F_8" REGION "Region_E&F_3" ; -LOCATE UGROUP "E&F_8" SITE "R42C134D" ; -UGROUP "E&F_9" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_9_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_9_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_9_Channels/Start_Encoder_un7_hit_detect_regdup -# BLKNAME THE_TDC/GEN_Channels_9_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_9_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_9_Channels/Channel_200_1; -# # LOCATE UGROUP "E&F_9" REGION "Region_E&F_3" ; -LOCATE UGROUP "E&F_9" SITE "R42C155D" ; -UGROUP "E&F_10" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_10_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_10_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_10_Channels/Start_Encoder_un7_hit_detect_regdup -# BLKNAME THE_TDC/GEN_Channels_10_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_10_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_10_Channels/Channel_200_1; -# LOCATE UGROUP "E&F_10" REGION "Region_E&F_4" ; -LOCATE UGROUP "E&F_10" SITE "R56C134D" ; -UGROUP "E&F_11" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_11_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_11_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_11_Channels/Start_Encoder_un7_hit_detect_regdup -# BLKNAME THE_TDC/GEN_Channels_11_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_11_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_11_Channels/Channel_200_1; -# LOCATE UGROUP "E&F_11" REGION "Region_E&F_4" ; -LOCATE UGROUP "E&F_11" SITE "R56C155D" ; -UGROUP "E&F_12" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_12_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_12_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_12_Channels/Start_Encoder_un7_hit_detect_regdup -# BLKNAME THE_TDC/GEN_Channels_12_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_12_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_12_Channels/Channel_200_1; -# LOCATE UGROUP "E&F_12" REGION "Region_E&F_4" ; -LOCATE UGROUP "E&F_12" SITE "R60C134D" ; -UGROUP "E&F_13" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_13_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_13_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_13_Channels/Start_Encoder_un7_hit_detect_regdup -# BLKNAME THE_TDC/GEN_Channels_13_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_13_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_13_Channels/Channel_200_1; -# LOCATE UGROUP "E&F_13" REGION "Region_E&F_4" ; -LOCATE UGROUP "E&F_13" SITE "R60C155D" ; -UGROUP "E&F_14" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_14_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_14_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_14_Channels/Start_Encoder_un7_hit_detect_regdup -# BLKNAME THE_TDC/GEN_Channels_14_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_14_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_14_Channels/Channel_200_1; -# LOCATE UGROUP "E&F_14" REGION "Region_E&F_5" ; -LOCATE UGROUP "E&F_14" SITE "R74C134D" ; -UGROUP "E&F_15" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_15_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_15_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_15_Channels/Start_Encoder_un7_hit_detect_regdup -# BLKNAME THE_TDC/GEN_Channels_15_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_15_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_15_Channels/Channel_200_1; -# LOCATE UGROUP "E&F_15" REGION "Region_E&F_5" ; -LOCATE UGROUP "E&F_15" SITE "R74C155D" ; -UGROUP "E&F_16" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_16_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_16_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_16_Channels/Start_Encoder_un7_hit_detect_regdup -# BLKNAME THE_TDC/GEN_Channels_16_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_16_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_16_Channels/Channel_200_1; -# LOCATE UGROUP "E&F_16" REGION "Region_E&F_5" ; -LOCATE UGROUP "E&F_16" SITE "R78C134D" ; -UGROUP "E&F_17" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_17_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_17_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_17_Channels/Start_Encoder_un7_hit_detect_regdup -# BLKNAME THE_TDC/GEN_Channels_17_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_17_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_17_Channels/Channel_200_1; -# LOCATE UGROUP "E&F_17" REGION "Region_E&F_5" ; -LOCATE UGROUP "E&F_17" SITE "R78C155D" ; -UGROUP "E&F_18" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_18_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_18_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_18_Channels/Start_Encoder_un7_hit_detect_regdup -# BLKNAME THE_TDC/GEN_Channels_18_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_18_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_18_Channels/Channel_200_1; -# LOCATE UGROUP "E&F_18" REGION "Region_E&F_6" ; -LOCATE UGROUP "E&F_18" SITE "R92C134D" ; -UGROUP "E&F_19" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_19_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_19_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_19_Channels/Start_Encoder_un7_hit_detect_regdup -# BLKNAME THE_TDC/GEN_Channels_19_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_19_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_19_Channels/Channel_200_1; -# LOCATE UGROUP "E&F_19" REGION "Region_E&F_6" ; -LOCATE UGROUP "E&F_19" SITE "R92C155D" ; -UGROUP "E&F_20" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_20_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_20_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_20_Channels/Start_Encoder_un7_hit_detect_regdup -# BLKNAME THE_TDC/GEN_Channels_20_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_20_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_20_Channels/Channel_200_1; -# LOCATE UGROUP "E&F_20" REGION "Region_E&F_6" ; -LOCATE UGROUP "E&F_20" SITE "R96C134D" ; -UGROUP "E&F_21" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_21_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_21_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_21_Channels/Start_Encoder_un7_hit_detect_regdup -# BLKNAME THE_TDC/GEN_Channels_21_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_21_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_21_Channels/Channel_200_1; -# LOCATE UGROUP "E&F_21" REGION "Region_E&F_6" ; -LOCATE UGROUP "E&F_21" SITE "R96C155D" ; -UGROUP "E&F_22" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_22_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_22_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_22_Channels/Start_Encoder_un7_hit_detect_regdup -# BLKNAME THE_TDC/GEN_Channels_22_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_22_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_22_Channels/Channel_200_1; -# LOCATE UGROUP "E&F_22" REGION "Region_E&F_7" ; -LOCATE UGROUP "E&F_22" SITE "R105C134D" ; -UGROUP "E&F_23" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_23_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_23_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_23_Channels/Start_Encoder_un7_hit_detect_regdup -# BLKNAME THE_TDC/GEN_Channels_23_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_23_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_23_Channels/Channel_200_1; -# LOCATE UGROUP "E&F_23" REGION "Region_E&F_7" ; -LOCATE UGROUP "E&F_23" SITE "R105C155D" ; -# -# -# -UGROUP "E&F_24" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_24_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_24_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_24_Channels/Start_Encoder_un7_hit_detect_regdup -## BLKNAME THE_TDC/GEN_Channels_24_Channels/Channel_200_1/ff_array_en_i_1_i -# BLKNAME THE_TDC/GEN_Channels_24_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_24_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_24_Channels/Channel_200_1; -LOCATE UGROUP "E&F_24" SITE "R11C57D" ; -UGROUP "E&F_25" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_25_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_25_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_25_Channels/Start_Encoder_un7_hit_detect_regdup -## BLKNAME THE_TDC/GEN_Channels_25_Channels/Channel_200_1/ff_array_en_i_1_i -# BLKNAME THE_TDC/GEN_Channels_25_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_25_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_25_Channels/Channel_200_1; -LOCATE UGROUP "E&F_25" SITE "R11C78D" ; -UGROUP "E&F_26" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_26_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_26_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_26_Channels/Start_Encoder_un7_hit_detect_regdup -## BLKNAME THE_TDC/GEN_Channels_26_Channels/Channel_200_1/ff_array_en_i_1_i -# BLKNAME THE_TDC/GEN_Channels_26_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_26_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_26_Channels/Channel_200_1; -LOCATE UGROUP "E&F_26" SITE "R15C57D" ; -UGROUP "E&F_27" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_27_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_27_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_27_Channels/Start_Encoder_un7_hit_detect_regdup -## BLKNAME THE_TDC/GEN_Channels_27_Channels/Channel_200_1/ff_array_en_i_1_i -# BLKNAME THE_TDC/GEN_Channels_27_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_27_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_27_Channels/Channel_200_1; -LOCATE UGROUP "E&F_27" SITE "R15C78D" ; -UGROUP "E&F_28" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_28_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_28_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_28_Channels/Start_Encoder_un7_hit_detect_regdup -## BLKNAME THE_TDC/GEN_Channels_28_Channels/Channel_200_1/ff_array_en_i_1_i -# BLKNAME THE_TDC/GEN_Channels_28_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_28_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_28_Channels/Channel_200_1; -LOCATE UGROUP "E&F_28" SITE "R24C57D" ; -UGROUP "E&F_29" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_29_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_29_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_29_Channels/Start_Encoder_un7_hit_detect_regdup -## BLKNAME THE_TDC/GEN_Channels_29_Channels/Channel_200_1/ff_array_en_i_1_i -# BLKNAME THE_TDC/GEN_Channels_29_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_29_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_29_Channels/Channel_200_1; -LOCATE UGROUP "E&F_29" SITE "R24C78D" ; -UGROUP "E&F_30" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_30_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_30_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_30_Channels/Start_Encoder_un7_hit_detect_regdup -## BLKNAME THE_TDC/GEN_Channels_30_Channels/Channel_200_1/ff_array_en_i_1_i -# BLKNAME THE_TDC/GEN_Channels_30_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_30_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_30_Channels/Channel_200_1; -LOCATE UGROUP "E&F_30" SITE "R38C57D" ; -UGROUP "E&F_31" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_31_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_31_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_31_Channels/Start_Encoder_un7_hit_detect_regdup -## BLKNAME THE_TDC/GEN_Channels_31_Channels/Channel_200_1/ff_array_en_i_1_i -# BLKNAME THE_TDC/GEN_Channels_31_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_31_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_31_Channels/Channel_200_1; -LOCATE UGROUP "E&F_31" SITE "R38C78D" ; -UGROUP "E&F_32" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_32_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_32_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_32_Channels/Start_Encoder_un7_hit_detect_regdup -## BLKNAME THE_TDC/GEN_Channels_32_Channels/Channel_200_1/ff_array_en_i_1_i -# BLKNAME THE_TDC/GEN_Channels_32_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_32_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_32_Channels/Channel_200_1; -LOCATE UGROUP "E&F_32" SITE "R42C57D" ; -UGROUP "E&F_33" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_33_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_33_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_33_Channels/Start_Encoder_un7_hit_detect_regdup -## BLKNAME THE_TDC/GEN_Channels_33_Channels/Channel_200_1/ff_array_en_i_1_i -# BLKNAME THE_TDC/GEN_Channels_33_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_33_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_33_Channels/Channel_200_1; -LOCATE UGROUP "E&F_33" SITE "R42C78D" ; -UGROUP "E&F_34" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_34_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_34_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_34_Channels/Start_Encoder_un7_hit_detect_regdup -## BLKNAME THE_TDC/GEN_Channels_34_Channels/Channel_200_1/ff_array_en_i_1_i -# BLKNAME THE_TDC/GEN_Channels_34_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_34_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_34_Channels/Channel_200_1; -LOCATE UGROUP "E&F_34" SITE "R92C57D" ; -UGROUP "E&F_35" BBOX 6 25 -# BLKNAME THE_TDC/GEN_Channels_35_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_35_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_35_Channels/Start_Encoder_un7_hit_detect_regdupdup -## BLKNAME THE_TDC/GEN_Channels_35_Channels/Channel_200_1/ff_array_en_i_1_i -# BLKNAME THE_TDC/GEN_Channels_35_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_35_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_35_Channels/Channel_200_1; -LOCATE UGROUP "E&F_35" SITE "R92C78D" ; -UGROUP "E&F_36" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_36_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_36_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_36_Channels/Start_Encoder_un7_hit_detect_regdupdup -## BLKNAME THE_TDC/GEN_Channels_36_Channels/Channel_200_1/ff_array_en_i_1_i -# BLKNAME THE_TDC/GEN_Channels_36_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_36_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_36_Channels/Channel_200_1; -LOCATE UGROUP "E&F_36" SITE "R96C57D" ; -UGROUP "E&F_37" BBOX 6 25 -# BLKNAME THE_TDC/GEN_Channels_37_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_37_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_37_Channels/Start_Encoder_un7_hit_detect_regdupdup -## BLKNAME THE_TDC/GEN_Channels_37_Channels/Channel_200_1/ff_array_en_i_1_i -# BLKNAME THE_TDC/GEN_Channels_37_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_37_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_37_Channels/Channel_200_1; -LOCATE UGROUP "E&F_37" SITE "R96C78D" ; -UGROUP "E&F_38" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_38_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_38_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_38_Channels/Start_Encoder_un7_hit_detect_regdupdup -## BLKNAME THE_TDC/GEN_Channels_38_Channels/Channel_200_1/ff_array_en_i_1_i -# BLKNAME THE_TDC/GEN_Channels_38_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_38_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_38_Channels/Channel_200_1; -LOCATE UGROUP "E&F_38" SITE "R105C57D" ; -UGROUP "E&F_39" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_39_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_39_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_39_Channels/Start_Encoder_un7_hit_detect_regdupdup -## BLKNAME THE_TDC/GEN_Channels_39_Channels/Channel_200_1/ff_array_en_i_1_i -# BLKNAME THE_TDC/GEN_Channels_39_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_39_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_39_Channels/Channel_200_1; -LOCATE UGROUP "E&F_39" SITE "R105C78D" ; -UGROUP "E&F_40" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_40_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_40_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_40_Channels/Start_Encoder_un7_hit_detect_regdupdup -## BLKNAME THE_TDC/GEN_Channels_40_Channels/Channel_200_1/ff_array_en_i_1_i -# BLKNAME THE_TDC/GEN_Channels_40_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_40_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_40_Channels/Channel_200_1; -LOCATE UGROUP "E&F_40" SITE "R78C57D" ; -UGROUP "E&F_41" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_41_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_41_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_41_Channels/Start_Encoder_un7_hit_detect_regdupdup -## BLKNAME THE_TDC/GEN_Channels_41_Channels/Channel_200_1/ff_array_en_i_1_i -# BLKNAME THE_TDC/GEN_Channels_41_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_41_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_41_Channels/Channel_200_1; -LOCATE UGROUP "E&F_41" SITE "R78C29D" ; -UGROUP "E&F_42" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_42_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_42_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_42_Channels/Start_Encoder_un7_hit_detect_regdupdup -## BLKNAME THE_TDC/GEN_Channels_42_Channels/Channel_200_1/ff_array_en_i_1_i -# BLKNAME THE_TDC/GEN_Channels_42_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_42_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_42_Channels/Channel_200_1; -LOCATE UGROUP "E&F_42" SITE "R92C8D" ; -UGROUP "E&F_43" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_43_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_43_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_43_Channels/Start_Encoder_un7_hit_detect_regdupdup -## BLKNAME THE_TDC/GEN_Channels_43_Channels/Channel_200_1/ff_array_en_i_1_i -# BLKNAME THE_TDC/GEN_Channels_43_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_43_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_43_Channels/Channel_200_1; -LOCATE UGROUP "E&F_43" SITE "R92C29D" ; -UGROUP "E&F_44" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_44_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_44_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_44_Channels/Start_Encoder_un7_hit_detect_regdupdup -## BLKNAME THE_TDC/GEN_Channels_44_Channels/Channel_200_1/ff_array_en_i_1_i -# BLKNAME THE_TDC/GEN_Channels_44_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_44_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_44_Channels/Channel_200_1; -LOCATE UGROUP "E&F_44" SITE "R96C8D" ; -UGROUP "E&F_45" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_45_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_45_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_45_Channels/Start_Encoder_un7_hit_detect_regdupdup -## BLKNAME THE_TDC/GEN_Channels_45_Channels/Channel_200_1/ff_array_en_i_1_i -# BLKNAME THE_TDC/GEN_Channels_45_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_45_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_45_Channels/Channel_200_1; -LOCATE UGROUP "E&F_45" SITE "R96C29D" ; -UGROUP "E&F_46" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_46_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_46_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_46_Channels/Start_Encoder_un7_hit_detect_regdupdup -## BLKNAME THE_TDC/GEN_Channels_46_Channels/Channel_200_1/ff_array_en_i_1_i -# BLKNAME THE_TDC/GEN_Channels_46_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_46_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_46_Channels/Channel_200_1; -LOCATE UGROUP "E&F_46" SITE "R105C8D" ; -UGROUP "E&F_47" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_47_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_47_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_47_Channels/Start_Encoder_un7_hit_detect_regdupdup -## BLKNAME THE_TDC/GEN_Channels_47_Channels/Channel_200_1/ff_array_en_i_1_i -# BLKNAME THE_TDC/GEN_Channels_47_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_47_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_47_Channels/Channel_200_1; -LOCATE UGROUP "E&F_47" SITE "R105C29D" ; -# -# -# -UGROUP "E&F_48" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_48_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_48_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_48_Channels/Start_Encoder_un7_hit_detect_regdupdup -## BLKNAME THE_TDC/GEN_Channels_48_Channels/Channel_200_1/ff_array_en_i_1_i -# BLKNAME THE_TDC/GEN_Channels_48_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_48_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_48_Channels/Channel_200_1; -LOCATE UGROUP "E&F_48" SITE "R11C8D" ; -UGROUP "E&F_49" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_49_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_49_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_49_Channels/Start_Encoder_un7_hit_detect_regdupdup -## BLKNAME THE_TDC/GEN_Channels_49_Channels/Channel_200_1/ff_array_en_i_1_i -# BLKNAME THE_TDC/GEN_Channels_49_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_49_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_49_Channels/Channel_200_1; -LOCATE UGROUP "E&F_49" SITE "R11C29D" ; -UGROUP "E&F_50" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_50_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_50_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_50_Channels/Start_Encoder_un7_hit_detect_regdupdup -## BLKNAME THE_TDC/GEN_Channels_50_Channels/Channel_200_1/ff_array_en_i_1_i -# BLKNAME THE_TDC/GEN_Channels_50_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_50_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_50_Channels/Channel_200_1; -LOCATE UGROUP "E&F_50" SITE "R15C8D" ; -UGROUP "E&F_51" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_51_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_51_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_51_Channels/Start_Encoder_un7_hit_detect_regdupdup -## BLKNAME THE_TDC/GEN_Channels_51_Channels/Channel_200_1/ff_array_en_i_1_i -# BLKNAME THE_TDC/GEN_Channels_51_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_51_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_51_Channels/Channel_200_1; -LOCATE UGROUP "E&F_51" SITE "R15C29D" ; -UGROUP "E&F_52" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_52_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_52_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_52_Channels/Start_Encoder_un7_hit_detect_regdupdup -## BLKNAME THE_TDC/GEN_Channels_52_Channels/Channel_200_1/ff_array_en_i_1_i -# BLKNAME THE_TDC/GEN_Channels_52_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_52_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_52_Channels/Channel_200_1; -LOCATE UGROUP "E&F_52" SITE "R24C8D" ; -UGROUP "E&F_53" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_53_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_53_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_53_Channels/Start_Encoder_un7_hit_detect_regdupdup -## BLKNAME THE_TDC/GEN_Channels_53_Channels/Channel_200_1/ff_array_en_i_1_i -# BLKNAME THE_TDC/GEN_Channels_53_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_53_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_53_Channels/Channel_200_1; -LOCATE UGROUP "E&F_53" SITE "R24C29D" ; -UGROUP "E&F_54" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_54_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_54_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_54_Channels/Start_Encoder_un7_hit_detect_regdupdup -## BLKNAME THE_TDC/GEN_Channels_54_Channels/Channel_200_1/ff_array_en_i_1_i -# BLKNAME THE_TDC/GEN_Channels_54_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_54_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_54_Channels/Channel_200_1; -LOCATE UGROUP "E&F_54" SITE "R38C8D" ; -UGROUP "E&F_55" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_55_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_55_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_55_Channels/Start_Encoder_un7_hit_detect_regdupdup -## BLKNAME THE_TDC/GEN_Channels_55_Channels/Channel_200_1/ff_array_en_i_1_i -# BLKNAME THE_TDC/GEN_Channels_55_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_55_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_55_Channels/Channel_200_1; -LOCATE UGROUP "E&F_55" SITE "R38C29D" ; -UGROUP "E&F_56" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_56_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_56_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_56_Channels/Start_Encoder_un7_hit_detect_regdupdup -## BLKNAME THE_TDC/GEN_Channels_56_Channels/Channel_200_1/ff_array_en_i_1_i -# BLKNAME THE_TDC/GEN_Channels_56_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_56_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_56_Channels/Channel_200_1; -LOCATE UGROUP "E&F_56" SITE "R42C8D" ; -UGROUP "E&F_57" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_57_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_57_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_57_Channels/Start_Encoder_un7_hit_detect_regdupdup -## BLKNAME THE_TDC/GEN_Channels_57_Channels/Channel_200_1/ff_array_en_i_1_i -# BLKNAME THE_TDC/GEN_Channels_57_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_57_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_57_Channels/Channel_200_1; -LOCATE UGROUP "E&F_57" SITE "R42C29D" ; -UGROUP "E&F_58" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_58_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_58_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_58_Channels/Start_Encoder_un7_hit_detect_regdupdup -## BLKNAME THE_TDC/GEN_Channels_58_Channels/Channel_200_1/ff_array_en_i_1_i -# BLKNAME THE_TDC/GEN_Channels_58_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_58_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_58_Channels/Channel_200_1; -LOCATE UGROUP "E&F_58" SITE "R56C8D" ; -UGROUP "E&F_59" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_59_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_59_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_59_Channels/Start_Encoder_un7_hit_detect_regdupdup -## BLKNAME THE_TDC/GEN_Channels_59_Channels/Channel_200_1/ff_array_en_i_1_i -# BLKNAME THE_TDC/GEN_Channels_59_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_59_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_59_Channels/Channel_200_1; -LOCATE UGROUP "E&F_59" SITE "R56C29D" ; -UGROUP "E&F_60" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_60_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_60_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_60_Channels/Start_Encoder_un7_hit_detect_regdupdup -## BLKNAME THE_TDC/GEN_Channels_60_Channels/Channel_200_1/ff_array_en_i_1_i -# BLKNAME THE_TDC/GEN_Channels_60_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_60_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_60_Channels/Channel_200_1; -LOCATE UGROUP "E&F_60" SITE "R60C8D" ; -UGROUP "E&F_61" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_61_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_61_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_61_Channels/Start_Encoder_un7_hit_detect_regdupdup -## BLKNAME THE_TDC/GEN_Channels_61_Channels/Channel_200_1/ff_array_en_i_1_i -# BLKNAME THE_TDC/GEN_Channels_61_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_61_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_61_Channels/Channel_200_1; -LOCATE UGROUP "E&F_61" SITE "R60C29D" ; -UGROUP "E&F_62" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_62_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_62_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_62_Channels/Start_Encoder_un7_hit_detect_regdupdup -## BLKNAME THE_TDC/GEN_Channels_62_Channels/Channel_200_1/ff_array_en_i_1_i -# BLKNAME THE_TDC/GEN_Channels_62_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_62_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_62_Channels/Channel_200_1; -LOCATE UGROUP "E&F_62" SITE "R74C8D" ; -UGROUP "E&F_63" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_63_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_63_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_63_Channels/Start_Encoder_un7_hit_detect_regdupdup -## BLKNAME THE_TDC/GEN_Channels_63_Channels/Channel_200_1/ff_array_en_i_1_i -# BLKNAME THE_TDC/GEN_Channels_63_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_63_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_63_Channels/Channel_200_1; -LOCATE UGROUP "E&F_63" SITE "R74C29D" ; -UGROUP "E&F_64" BBOX 6 21 -# BLKNAME THE_TDC/GEN_Channels_64_Channels/hit_detect_i -# BLKNAME THE_TDC/GEN_Channels_64_Channels/hit_detect_reg -# BLKNAME THE_TDC/GEN_Channels_64_Channels/Start_Encoder_un7_hit_detect_regdup -## BLKNAME THE_TDC/GEN_Channels_64_Channels/Channel_200_1/ff_array_en_i_1_i -# BLKNAME THE_TDC/GEN_Channels_64_Channels/result_2_reg -# BLKNAME THE_TDC/GEN_Channels_64_Channels/FIFO - BLKNAME THE_TDC/GEN_Channels_64_Channels/Channel_200_1; -LOCATE UGROUP "E&F_64" SITE "R78C8D" ; - -############################################################################# -## Unimportant Data Lines ## -############################################################################## -#MULTICYCLE TO PORT "TEST_LINE_*" 2.000000 X ; - - -MULTICYCLE TO CELL "THE_TDC/GEN_Channels_*_Channels/lost_hit_cntr_*" 3.000000 X ; -MULTICYCLE TO CELL "THE_TDC/GEN_Channels_*_Channels/hit_detect_cntr_*" 3.000000 X ; -MULTICYCLE TO CELL "THE_TDC/GEN_Channels_*_Channels/encoder_start_cntr_*" 3.000000 X ; -MULTICYCLE TO CELL "THE_TDC/GEN_Channels_*_Channels/fifo_wr_cntr_*" 3.000000 X ; - -# MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" 3.000000 X ; -BLOCK NET "THE_TDC/reset_tdc*" ; - -#MULTICYCLE TO CELL "THE_TDC/GEN_Channels_*_Channels/hit_time_stamp_i_*" 2.000000 X ; -#MULTICYCLE TO CELL "THE_TDC/The_Reference_Time/hit_time_stamp_i_*" 2.000000 X ; - -MULTICYCLE FROM CELL "THE_TDC/GEN_Channels_*_Channels/Channel_200_1/FIFO_FULL_OUT" 2.000000 X ; -MULTICYCLE FROM CELL "THE_TDC/GEN_Channels_*_Channels/Channel_200_1/FIFO_ALMOST_FULL_OUT" 2.000000 X ; - - -MAXDELAY NET "THE_TDC/The_Reference_Time/hit_buf" 0.700000 nS DATAPATH_ONLY ; -MAXDELAY NET "THE_TDC/GEN_Channels_*_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ; - -#Jan: This guy gave timing errors > 7ns, so I removed it for my test -#MAXDELAY NET "TRIGGER_LEFT_c_i" 0.700000 nS DATAPATH_ONLY ; diff --git a/tdc_releases/tdc_v_stretcher/up_counter.vhd b/tdc_releases/tdc_v_stretcher/up_counter.vhd deleted file mode 100644 index 1d8a887..0000000 --- a/tdc_releases/tdc_v_stretcher/up_counter.vhd +++ /dev/null @@ -1,41 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.STD_LOGIC_ARITH.all; -use IEEE.STD_LOGIC_UNSIGNED.all; - -entity up_counter is - - generic ( - NUMBER_OF_BITS : positive); - port ( - CLK : in std_logic; - RESET : in std_logic; - COUNT_OUT : out std_logic_vector(NUMBER_OF_BITS-1 downto 0); - UP_IN : in std_logic); - -end up_counter; - -architecture up_counter of up_counter is - - signal counter : std_logic_vector (NUMBER_OF_BITS-1 downto 0); - attribute syn_preserve : boolean; - attribute syn_preserve of counter : signal is true; - -begin - - COUNTER_PROC : process (CLK, RESET) - begin - if rising_edge(CLK) then - if RESET = '1' then - counter <= (others => '0'); - elsif UP_IN = '1' then - counter <= counter + 1; - else - counter <= counter; - end if; - end if; - end process COUNTER_PROC; - - COUNT_OUT <= counter; - -end up_counter; -- 2.43.0