From cea7349a281f015a8bc14626a4b4275cb8b86d57 Mon Sep 17 00:00:00 2001 From: hadaq Date: Tue, 20 Oct 2009 20:37:22 +0000 Subject: [PATCH] updated RichTrigger, new functions reset and reload --- libtrbnet/trbcmd.c | 91 +++++++++++++++++++++++++++++++++++++++++++++- libtrbnet/trbnet.c | 12 ++++-- 2 files changed, 98 insertions(+), 5 deletions(-) diff --git a/libtrbnet/trbcmd.c b/libtrbnet/trbcmd.c index e3280d3..15677cf 100644 --- a/libtrbnet/trbcmd.c +++ b/libtrbnet/trbcmd.c @@ -16,7 +16,7 @@ static int hexMode = HEXMODE; -static const char trbcmd_version[] = "$Revision: 2.27 $"; +static const char trbcmd_version[] = "$Revision: 2.28 $"; /* ------ MAIN ---------------------------------------------------------- */ @@ -49,6 +49,9 @@ void usage(const char *progName) printf(" TR -> send trigger to " "RICH only\n"); printf(" I -> read IPU data\n"); + printf(" reload -> reload FPGA\n"); + printf(" reset -> reset " + "TRBNetwork\n"); printf(" f -> flush FIFO of " "channel\n"); printf(" R -> " @@ -631,6 +634,92 @@ int main(int argc, char ** argv) fprintf(stderr, "WARNING Status-Bits:\n%s\n", trb_strterm(trb_term)); } + } else if (strncmp(cmd[0], "reset", CMD_SIZE) == 0) { + + /*******************************************/ + /* TRBNet Reset */ + /*******************************************/ + + if (cmdLen != 1) { + if (scriptFile != NULL) { + fprintf(stderr, "Line #%d: Invalid command\n", lineCtr); + } else { + usage(basename(argv[0])); + } + exit(EXIT_FAILURE); + } + + /* DEBUG Info */ + if (trb_debug > 0) { + fprintf(stderr, "Command: RESET:\n"); + } + + if (fpga_register_write(0x10, 0x0000) == -1) { + if (scriptFile != NULL) { + fprintf(stderr, "Line #%d: ", lineCtr); + } + trb_error("fpga_register_write failed"); + exit(EXIT_FAILURE); + } + + if (fpga_register_write(0x10, 0x8000) == -1) { + if (scriptFile != NULL) { + fprintf(stderr, "Line #%d: ", lineCtr); + } + trb_error("fpga_register_write failed"); + exit(EXIT_FAILURE); + } + + if (fpga_register_write(0x10, 0x0000) == -1) { + if (scriptFile != NULL) { + fprintf(stderr, "Line #%d: ", lineCtr); + } + trb_error("fpga_register_write failed"); + exit(EXIT_FAILURE); + } + + } else if (strncmp(cmd[0], "reload", CMD_SIZE) == 0) { + + /*********************************************/ + /* FPGA Reload */ + /*********************************************/ + + if (cmdLen != 2) { + if (scriptFile != NULL) { + fprintf(stderr, "Line #%d: Invalid command\n", lineCtr); + } else { + usage(basename(argv[0])); + } + exit(EXIT_FAILURE); + } + + trb_address = strtoul(cmd[1], NULL, hexMode == 1 ? 16 : 0); + + /* DEBUG Info */ + if (trb_debug > 0) { + fprintf(stderr, + "Command: RELOAD: trb_address: 0x%04x\n", trb_address); + } + + if (trb_register_write(trb_address, 0x0020, 0x8000) == -1) { + if (scriptFile != NULL) { + fprintf(stderr, "Line #%d: ", lineCtr); + } + trb_error("FPGA reload failed"); + if (trb_errno != TRB_ENDPOINT_NOT_REACHED) { + exit(EXIT_FAILURE); + } + } + + /* Check Status-Bits */ + if ((trb_term.status_common != 0x01) || + (trb_term.status_channel != 0)) { + if (scriptFile != NULL) { + fprintf(stderr, "Line #%d: ", lineCtr); + } + fprintf(stderr, "WARNING Status-Bits:\n%s\n", trb_strterm(trb_term)); + } + } else if (strncmp(cmd[0], "TR", CMD_SIZE) == 0) { /*********************************************/ diff --git a/libtrbnet/trbnet.c b/libtrbnet/trbnet.c index 29b2d0c..095c559 100644 --- a/libtrbnet/trbnet.c +++ b/libtrbnet/trbnet.c @@ -1,4 +1,4 @@ -const char trbnet_version[] = "$Revision: 2.45 $"; +const char trbnet_version[] = "$Revision: 2.46 $"; #include #include @@ -1426,6 +1426,10 @@ int trb_send_trigger_rich(uint8_t trg_input, trb_errno = TRB_NONE; + if (trg_input > 3) { + return -1; + } + if (lockPorts() == -1) return -1; /* Init transfer slowcontrol */ @@ -1454,9 +1458,9 @@ int trb_send_trigger_rich(uint8_t trg_input, /* Prepare slowcontrol channel */ write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, 0x0000fffb); /* RICH Subnet only */ write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000); - write32_to_FPGA(CHANNEL_3_SENDER_DATA, (0x8080 | (uint32_t)trg_input)); - write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x0000dead); /* fake data is */ - write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x0000beef); /* discarded at ADCM */ + write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x0020); + write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000 | (0x01 << trg_input)); + write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000); write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000); /* Send both fake trigger and LVL1 information */ -- 2.43.0