From cf216cb32d82fdd5d62644ba6474a34fc912a59c Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Thu, 25 Aug 2011 12:52:59 +0000 Subject: [PATCH] *** empty log message *** --- base/compile_periph_frankfurt.pl | 2 +- base/compile_periph_gsi.pl | 2 +- base/trb3_periph.lpf | 169 +++++++++++++++---------------- base/trb3_periph.p2t | 20 ++++ base/trb3_periph.prj | 63 ++++++++++++ base/trb3_periph.vhd | 169 +++++++++++++++++++++++++++++++ 6 files changed, 338 insertions(+), 87 deletions(-) create mode 100644 base/trb3_periph.p2t create mode 100644 base/trb3_periph.prj diff --git a/base/compile_periph_frankfurt.pl b/base/compile_periph_frankfurt.pl index b7a6271..8d9178c 100755 --- a/base/compile_periph_frankfurt.pl +++ b/base/compile_periph_frankfurt.pl @@ -34,7 +34,7 @@ $ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify; my $FAMILYNAME="LatticeECP3"; my $DEVICENAME="LFE3-150EA"; -my $PACKAGE="FPBGA1156"; +my $PACKAGE="FPBGA672"; my $SPEEDGRADE="7"; diff --git a/base/compile_periph_gsi.pl b/base/compile_periph_gsi.pl index b7a6271..8d9178c 100755 --- a/base/compile_periph_gsi.pl +++ b/base/compile_periph_gsi.pl @@ -34,7 +34,7 @@ $ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify; my $FAMILYNAME="LatticeECP3"; my $DEVICENAME="LFE3-150EA"; -my $PACKAGE="FPBGA1156"; +my $PACKAGE="FPBGA672"; my $SPEEDGRADE="7"; diff --git a/base/trb3_periph.lpf b/base/trb3_periph.lpf index 094de00..50e25de 100644 --- a/base/trb3_periph.lpf +++ b/base/trb3_periph.lpf @@ -46,7 +46,7 @@ LOCATE COMP "FPGA5_COMM_9" SITE "AF4"; LOCATE COMP "FPGA5_COMM_10" SITE "V10"; LOCATE COMP "FPGA5_COMM_11" SITE "W10"; DEFINE PORT GROUP "FPGA_group" "FPGA*" ; -IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=8 SLEW=FAST; +IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=8 ; LOCATE COMP "TEST_LINE_0" SITE "A5"; LOCATE COMP "TEST_LINE_1" SITE "A6"; @@ -65,7 +65,7 @@ LOCATE COMP "TEST_LINE_13" SITE "C10"; LOCATE COMP "TEST_LINE_14" SITE "H10"; LOCATE COMP "TEST_LINE_15" SITE "H11"; DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ; -IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12 SLEW=FAST; +IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12; ################################################################# # Connection to AddOn @@ -74,61 +74,61 @@ IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12 SLEW=FAST; #All DQS are inserted in the DQ lines at position 6 and 7 #DQ 6-9 are shifted to 8-11 #Order per bank is kept, i.e. adjacent numbers have adjacent pins -#all DQ blocks are 6+2+4=12 Pins wide, only DQUL3 is 6+2+2=10. +#all DQ blocks are 6+2+4=12 Pins wide, only DQUL3 and DQUR0 are 6+2+2=10. #even numbers are positive LVDS line, odd numbers are negative LVDS line #DQUL can be switched to 1.8V -LOCATE COMP "DQLL0_0" SITE "P1"; #DQLL0_0 #1 -LOCATE COMP "DQLL0_1" SITE "P2"; #DQLL0_1 #3 -LOCATE COMP "DQLL0_2" SITE "T2"; #DQLL0_2 #5 -LOCATE COMP "DQLL0_3" SITE "U3"; #DQLL0_3 #7 -LOCATE COMP "DQLL0_4" SITE "R1"; #DQLL0_4 #9 -LOCATE COMP "DQLL0_5" SITE "R2"; #DQLL0_5 #11 -LOCATE COMP "DQLL0_6" SITE "N3"; #DQSLL0_T #13 -LOCATE COMP "DQLL0_7" SITE "P3"; #DQSLL0_C #15 -LOCATE COMP "DQLL0_8" SITE "P5"; #DQLL0_6 #17 -LOCATE COMP "DQLL0_9" SITE "P6"; #DQLL0_7 #19 -LOCATE COMP "DQLL0_10" SITE "N5"; #DQLL0_8 #21 -LOCATE COMP "DQLL0_11" SITE "N6"; #DQLL0_9 #23 - -LOCATE COMP "DQLL1_12" SITE "V1"; #DQLL1_0 #26 -LOCATE COMP "DQLL1_13" SITE "U2"; #DQLL1_1 #28 -LOCATE COMP "DQLL1_14" SITE "T1"; #DQLL1_2 #30 -LOCATE COMP "DQLL1_15" SITE "U1"; #DQLL1_3 #32 -LOCATE COMP "DQLL1_16" SITE "P4"; #DQLL1_4 #34 -LOCATE COMP "DQLL1_17" SITE "R3"; #DQLL1_5 #36 -LOCATE COMP "DQLL1_18" SITE "T3"; #DQSLL1_T #38 -LOCATE COMP "DQLL1_19" SITE "R4"; #DQSLL1_C #40 -LOCATE COMP "DQLL1_20" SITE "R5"; #DQLL1_6 #42 -LOCATE COMP "DQLL1_21" SITE "R6"; #DQLL1_7 #44 -LOCATE COMP "DQLL1_22" SITE "T7"; #DQLL1_8 #46 -LOCATE COMP "DQLL1_23" SITE "T8"; #DQLL1_9 #48 - -LOCATE COMP "DQLL2_24" SITE "AC2"; #DQLL2_0 #25 -LOCATE COMP "DQLL2_25" SITE "AC3"; #DQLL2_1 #27 -LOCATE COMP "DQLL2_26" SITE "AB1"; #DQLL2_2 #29 -LOCATE COMP "DQLL2_27" SITE "AC1"; #DQLL2_3 #31 -LOCATE COMP "DQLL2_28" SITE "AA1"; #DQLL2_4 #33 -LOCATE COMP "DQLL2_29" SITE "AA2"; #DQLL2_5 #35 -LOCATE COMP "DQLL2_30" SITE "W7"; #DQLL2_T #37 #should be DQSLL2 -LOCATE COMP "DQLL2_31" SITE "W6"; #DQLL2_C #39 #should be DQSLL2 -LOCATE COMP "DQLL2_32" SITE "Y5"; #DQLL2_6 #41 -LOCATE COMP "DQLL2_33" SITE "AA5"; #DQLL2_7 #43 -LOCATE COMP "DQLL2_34" SITE "V6"; #DQLL2_8 #45 -LOCATE COMP "DQLL2_35" SITE "V7"; #DQLL2_9 #47 - -LOCATE COMP "DQLL3_36" SITE "AD1"; #DQLL3_0 #2 -LOCATE COMP "DQLL3_37" SITE "AD2"; #DQLL3_1 #4 -LOCATE COMP "DQLL3_38" SITE "AB5"; #DQLL3_2 #6 -LOCATE COMP "DQLL3_39" SITE "AB6"; #DQLL3_3 #8 -LOCATE COMP "DQLL3_40" SITE "AB3"; #DQLL3_4 #10 -LOCATE COMP "DQLL3_41" SITE "AB4"; #DQLL3_5 #12 -LOCATE COMP "DQLL3_42" SITE "Y6"; #DQLL3_T #14 #should be DQSLL3 -LOCATE COMP "DQLL3_43" SITE "Y7"; #DQLL3_C #16 #should be DQSLL3 -LOCATE COMP "DQLL3_44" SITE "AA3"; #DQLL3_6 #18 -LOCATE COMP "DQLL3_45" SITE "AA4"; #DQLL3_7 #20 -LOCATE COMP "DQLL3_46" SITE "W8"; #DQLL3_8 #22 -LOCATE COMP "DQLL3_47" SITE "W9"; #DQLL3_9 #24 +LOCATE COMP "DQLL_0" SITE "P1"; #DQLL0_0 #1 +LOCATE COMP "DQLL_1" SITE "P2"; #DQLL0_1 #3 +LOCATE COMP "DQLL_2" SITE "T2"; #DQLL0_2 #5 +LOCATE COMP "DQLL_3" SITE "U3"; #DQLL0_3 #7 +LOCATE COMP "DQLL_4" SITE "R1"; #DQLL0_4 #9 +LOCATE COMP "DQLL_5" SITE "R2"; #DQLL0_5 #11 +LOCATE COMP "DQLL_6" SITE "N3"; #DQSLL0_T #13 +LOCATE COMP "DQLL_7" SITE "P3"; #DQSLL0_C #15 +LOCATE COMP "DQLL_8" SITE "P5"; #DQLL0_6 #17 +LOCATE COMP "DQLL_9" SITE "P6"; #DQLL0_7 #19 +LOCATE COMP "DQLL_10" SITE "N5"; #DQLL0_8 #21 +LOCATE COMP "DQLL_11" SITE "N6"; #DQLL0_9 #23 + +LOCATE COMP "DQLL_12" SITE "V1"; #DQLL1_0 #26 +LOCATE COMP "DQLL_13" SITE "U2"; #DQLL1_1 #28 +LOCATE COMP "DQLL_14" SITE "T1"; #DQLL1_2 #30 +LOCATE COMP "DQLL_15" SITE "U1"; #DQLL1_3 #32 +LOCATE COMP "DQLL_16" SITE "P4"; #DQLL1_4 #34 +LOCATE COMP "DQLL_17" SITE "R3"; #DQLL1_5 #36 +LOCATE COMP "DQLL_18" SITE "T3"; #DQSLL1_T #38 +LOCATE COMP "DQLL_19" SITE "R4"; #DQSLL1_C #40 +LOCATE COMP "DQLL_20" SITE "R5"; #DQLL1_6 #42 +LOCATE COMP "DQLL_21" SITE "R6"; #DQLL1_7 #44 +LOCATE COMP "DQLL_22" SITE "T7"; #DQLL1_8 #46 +LOCATE COMP "DQLL_23" SITE "T8"; #DQLL1_9 #48 + +LOCATE COMP "DQLL_24" SITE "AC2"; #DQLL2_0 #25 +LOCATE COMP "DQLL_25" SITE "AC3"; #DQLL2_1 #27 +LOCATE COMP "DQLL_26" SITE "AB1"; #DQLL2_2 #29 +LOCATE COMP "DQLL_27" SITE "AC1"; #DQLL2_3 #31 +LOCATE COMP "DQLL_28" SITE "AA1"; #DQLL2_4 #33 +LOCATE COMP "DQLL_29" SITE "AA2"; #DQLL2_5 #35 +LOCATE COMP "DQLL_30" SITE "W7"; #DQLL2_T #37 #should be DQSLL2 +LOCATE COMP "DQLL_31" SITE "W6"; #DQLL2_C #39 #should be DQSLL2 +LOCATE COMP "DQLL_32" SITE "Y5"; #DQLL2_6 #41 +LOCATE COMP "DQLL_33" SITE "AA5"; #DQLL2_7 #43 +LOCATE COMP "DQLL_34" SITE "V6"; #DQLL2_8 #45 +LOCATE COMP "DQLL_35" SITE "V7"; #DQLL2_9 #47 + +LOCATE COMP "DQLL_36" SITE "AD1"; #DQLL3_0 #2 +LOCATE COMP "DQLL_37" SITE "AD2"; #DQLL3_1 #4 +LOCATE COMP "DQLL_38" SITE "AB5"; #DQLL3_2 #6 +LOCATE COMP "DQLL_39" SITE "AB6"; #DQLL3_3 #8 +LOCATE COMP "DQLL_40" SITE "AB3"; #DQLL3_4 #10 +LOCATE COMP "DQLL_41" SITE "AB4"; #DQLL3_5 #12 +LOCATE COMP "DQLL_42" SITE "Y6"; #DQLL3_T #14 #should be DQSLL3 +LOCATE COMP "DQLL_43" SITE "Y7"; #DQLL3_C #16 #should be DQSLL3 +LOCATE COMP "DQLL_44" SITE "AA3"; #DQLL3_6 #18 +LOCATE COMP "DQLL_45" SITE "AA4"; #DQLL3_7 #20 +LOCATE COMP "DQLL_46" SITE "W8"; #DQLL3_8 #22 +LOCATE COMP "DQLL_47" SITE "W9"; #DQLL3_9 #24 LOCATE COMP "DQLR_0" SITE "AC26"; #DQLR0_0 #129 LOCATE COMP "DQLR_1" SITE "AC25"; #DQLR0_1 #131 @@ -230,37 +230,36 @@ LOCATE COMP "DQUR_6" SITE "F24"; #DQSUR0_T #117 LOCATE COMP "DQUR_7" SITE "G24"; #DQSUR0_C #119 LOCATE COMP "DQUR_8" SITE "K23"; #DQUR0_6 #121 LOCATE COMP "DQUR_9" SITE "K22"; #DQUR0_7 #123 -LOCATE COMP "DQUR_10" SITE "F25"; #DQUR0_8 #125 #input only -LOCATE COMP "DQUR_11" SITE "E26"; #DQUR0_9 #127 #input only - -LOCATE COMP "DQUR_12" SITE "H24"; #DQUR1_0 #106 -LOCATE COMP "DQUR_13" SITE "G25"; #DQUR1_1 #108 -LOCATE COMP "DQUR_14" SITE "L20"; #DQUR1_2 #110 -LOCATE COMP "DQUR_15" SITE "M21"; #DQUR1_3 #112 -LOCATE COMP "DQUR_16" SITE "K24"; #DQUR1_4 #114 -LOCATE COMP "DQUR_17" SITE "J24"; #DQUR1_5 #116 -LOCATE COMP "DQUR_18" SITE "M23"; #DQSUR1_T #118 -LOCATE COMP "DQUR_19" SITE "M24"; #DQSUR1_C #120 -LOCATE COMP "DQUR_20" SITE "L24"; #DQUR1_6 #122 -LOCATE COMP "DQUR_21" SITE "K25"; #DQUR1_7 #124 -LOCATE COMP "DQUR_22" SITE "M22"; #DQUR1_8 #126 -LOCATE COMP "DQUR_23" SITE "N21"; #DQUR1_9 #128 - -LOCATE COMP "DQUR_24" SITE "J26"; #DQUR2_0 #130 -LOCATE COMP "DQUR_25" SITE "K26"; #DQUR2_1 #132 -LOCATE COMP "DQUR_26" SITE "N23"; #DQUR2_2 #134 -LOCATE COMP "DQUR_27" SITE "N22"; #DQUR2_3 #136 -LOCATE COMP "DQUR_28" SITE "K19"; #DQUR2_4 #138 -LOCATE COMP "DQUR_29" SITE "L19"; #DQUR2_5 #140 -LOCATE COMP "DQUR_30" SITE "P23"; #DQSUR2_T #142 -LOCATE COMP "DQUR_31" SITE "R22"; #DQSUR2_C #144 -LOCATE COMP "DQUR_32" SITE "L25"; #DQUR2_6 #146 -LOCATE COMP "DQUR_33" SITE "L26"; #DQUR2_7 #148 -LOCATE COMP "DQUR_34" SITE "P21"; #DQUR2_8 #150 -LOCATE COMP "DQUR_35" SITE "P22"; #DQUR2_9 #152 +# LOCATE COMP "DQUR_10" SITE "F25"; #DQUR0_8 #125 #input only +# LOCATE COMP "DQUR_11" SITE "E26"; #DQUR0_9 #127 #input only + +LOCATE COMP "DQUR_10" SITE "H24"; #DQUR1_0 #106 +LOCATE COMP "DQUR_11" SITE "G25"; #DQUR1_1 #108 +LOCATE COMP "DQUR_12" SITE "L20"; #DQUR1_2 #110 +LOCATE COMP "DQUR_13" SITE "M21"; #DQUR1_3 #112 +LOCATE COMP "DQUR_14" SITE "K24"; #DQUR1_4 #114 +LOCATE COMP "DQUR_15" SITE "J24"; #DQUR1_5 #116 +LOCATE COMP "DQUR_16" SITE "M23"; #DQSUR1_T #118 +LOCATE COMP "DQUR_17" SITE "M24"; #DQSUR1_C #120 +LOCATE COMP "DQUR_18" SITE "L24"; #DQUR1_6 #122 +LOCATE COMP "DQUR_19" SITE "K25"; #DQUR1_7 #124 +LOCATE COMP "DQUR_20" SITE "M22"; #DQUR1_8 #126 +LOCATE COMP "DQUR_21" SITE "N21"; #DQUR1_9 #128 +LOCATE COMP "DQUR_22" SITE "J26"; #DQUR2_0 #130 +LOCATE COMP "DQUR_23" SITE "K26"; #DQUR2_1 #132 +LOCATE COMP "DQUR_24" SITE "N23"; #DQUR2_2 #134 +LOCATE COMP "DQUR_25" SITE "N22"; #DQUR2_3 #136 +LOCATE COMP "DQUR_26" SITE "K19"; #DQUR2_4 #138 +LOCATE COMP "DQUR_27" SITE "L19"; #DQUR2_5 #140 +LOCATE COMP "DQUR_28" SITE "P23"; #DQSUR2_T #142 +LOCATE COMP "DQUR_29" SITE "R22"; #DQSUR2_C #144 +LOCATE COMP "DQUR_30" SITE "L25"; #DQUR2_6 #146 +LOCATE COMP "DQUR_31" SITE "L26"; #DQUR2_7 #148 +LOCATE COMP "DQUR_32" SITE "P21"; #DQUR2_8 #150 +LOCATE COMP "DQUR_33" SITE "P22"; #DQUR2_9 #152 DEFINE PORT GROUP "DQ_group" "DQ*" ; -IOBUF GROUP "DQ_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12 SLEW=FAST; +IOBUF GROUP "DQ_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12; ################################################################# # Additional Lines to AddOn @@ -305,8 +304,8 @@ IOBUF PORT "CODE_LINE_1" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; IOBUF PORT "CODE_LINE_0" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; #terminated differential pair to pads -LOCATE COMP "N1556417_FPGA__3" SITE "C14"; -LOCATE COMP "N1556429_FPGA__3" SITE "D14"; +LOCATE COMP "SUPPL" SITE "C14"; +IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ; ################################################################# diff --git a/base/trb3_periph.p2t b/base/trb3_periph.p2t new file mode 100644 index 0000000..c037b03 --- /dev/null +++ b/base/trb3_periph.p2t @@ -0,0 +1,20 @@ +-w +-i 15 +-l 5 +-n 1 +-y +-s 12 +-t 12 +-c 1 +-e 2 +-m nodelist.txt +# -w +# -i 6 +# -l 5 +# -n 1 +# -t 1 +# -s 1 +# -c 0 +# -e 0 +# +-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1: diff --git a/base/trb3_periph.prj b/base/trb3_periph.prj new file mode 100644 index 0000000..a594c99 --- /dev/null +++ b/base/trb3_periph.prj @@ -0,0 +1,63 @@ + +# implementation: "workdir" +impl -add workdir -type fpga + +# device options +set_option -technology LATTICE-ECP3 +set_option -part LFE3_150EA +set_option -package FN672C +set_option -speed_grade -7 +set_option -part_companion "" + +# compilation/mapping options +set_option -default_enum_encoding sequential +set_option -symbolic_fsm_compiler 1 +set_option -top_module "trb3_periph" +set_option -resource_sharing true + +# map options +set_option -frequency 200 +set_option -fanout_limit 100 +set_option -disable_io_insertion 0 +set_option -retiming 0 +set_option -pipe 0 +#set_option -force_gsr +set_option -force_gsr false +set_option -fixgatedclocks 3 +set_option -fixgeneratedclocks 3 +set_option -compiler_compatible true + + +# simulation options +set_option -write_verilog 0 +set_option -write_vhdl 1 + +# automatic place and route (vendor) options +set_option -write_apr_constraint 0 + +# set result format/file last +project -result_format "edif" +project -result_file "workdir/trb3_periph.edf" + +#implementation attributes + +set_option -vlog_std v2001 +set_option -project_relative_includes 1 +impl -active "workdir" + +#################### + + + +#add_file options + +add_file -vhdl -lib work "version.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" + +add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd" +add_file -vhdl -lib "work" "./trb3_periph.vhd" +add_file -vhdl -lib "work" "../base/trb3_components.vhd" + + + diff --git a/base/trb3_periph.vhd b/base/trb3_periph.vhd index e69de29..ea90318 100644 --- a/base/trb3_periph.vhd +++ b/base/trb3_periph.vhd @@ -0,0 +1,169 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.version.all; + + + +entity trb3_periph is + port( + --Clocks + CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz + CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK + CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200 MHz <-- For TDC. Same oscillator as GPLL right! + CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200 MHz <-- For TDC. Same oscillator as GPLL right! + + --Trigger + TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out + TRIGGER_RIGHT : in std_logic; --right side trigger input from fan-out + + --Serdes + CLK_SERDES_INT_LEFT : in std_logic; --Clock Manager 1/(1357), off, 125 MHz possible + CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 2/(1357), 200 MHz, only in case of problems + SERDES_INT_TX : out std_logic_vector(3 downto 0); + SERDES_INT_RX : in std_logic_vector(3 downto 0); + SERDES_ADDON_TX : out std_logic_vector(11 downto 0); + SERDES_ADDON_RX : in std_logic_vector(11 downto 0); + + --Inter-FPGA Communication + FPGA5_COMM : inout std_logic_vector(11 downto 0); + --Bit 0/1 input, serial link RX active + --Bit 2/3 output, serial link TX active + --others yet undefined + --Connection to AddOn + SPARE_LINE : inout std_logic_vector(5 downto 0); --inputs only + DQUL : inout std_logic_vector(45 downto 0); + DQLL : inout std_logic_vector(47 downto 0); + DQUR : inout std_logic_vector(33 downto 0); + DQLR : inout std_logic_vector(35 downto 0); + --All DQ groups from one bank are grouped. + --All DQS are inserted in the DQ lines at position 6 and 7, DQ 6-9 are shifted to 8-11 + --Order per bank is kept, i.e. adjacent numbers have adjacent pins + --all DQ blocks are 6+2+4=12 Pins wide, only DQUL3 is 6+2+2=10. + --even numbers are positive LVDS line, odd numbers are negative LVDS line + --DQUL can be switched to 1.8V + --Flash ROM & Reboot + FLASH_CLK : out std_logic; + FLASH_CS : out std_logic; + FLASH_CIN : out std_logic; + FLASH_DOUT : in std_logic; + PROGRAMN : out std_logic; --reboot FPGA + + --Misc + TEMPSENS : inout std_logic; --Temperature Sensor + CODE_LINE : in std_logic_vector(1 downto 0); + LED_GREEN : out std_logic; + LED_ORANGE : out std_logic; + LED_RED : out std_logic; + LED_YELLOW : out std_logic; + SUPPL : in std_logic; --terminated diff pair, PCLK, Pads + + --Test Connectors + TEST_LINE : out std_logic_vector(15 downto 0) + ); + + + attribute syn_useioff : boolean; + --no IO-FF for LEDs relaxes timing constraints + attribute syn_useioff of LED_GREEN : signal is false; + attribute syn_useioff of LED_ORANGE : signal is false; + attribute syn_useioff of LED_RED : signal is false; + attribute syn_useioff of LED_YELLOW : signal is false; + attribute syn_useioff of TEMPSENS : signal is false; + attribute syn_useioff of PROGRAMN : signal is false; + attribute syn_useioff of CODE_LINE : signal is false; + attribute syn_useioff of TRIGGER_LEFT : signal is false; + attribute syn_useioff of TRIGGER_RIGHT : signal is false; + + --important signals _with_ IO-FF + attribute syn_useioff of FLASH_CLK : signal is true; + attribute syn_useioff of FLASH_CS : signal is true; + attribute syn_useioff of FLASH_CIN : signal is true; + attribute syn_useioff of FLASH_DOUT : signal is true; + attribute syn_useioff of FPGA5_COMM : signal is true; + attribute syn_useioff of TEST_LINE : signal is true; + attribute syn_useioff of DQLL : signal is true; + attribute syn_useioff of DQUL : signal is true; + attribute syn_useioff of DQLR : signal is true; + attribute syn_useioff of DQUR : signal is true; + attribute syn_useioff of SPARE_LINE : signal is true; + attribute syn_useioff of FPGA5_COMM : signal is true; + +end entity; + +architecture trb3_periph_arch of trb3_periph is + + signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL + signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL + signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic. + + + --FPGA Test + signal time_counter : unsigned(31 downto 0); +begin + +--------------------------------------------------------------------------- +-- Clock Handling +--------------------------------------------------------------------------- + THE_MAIN_PLL : pll_in200_out100 + port map( + CLK => CLK_GPLL_LEFT, + CLKOP => clk_100_i, + CLKOK => clk_200_i, + LOCK => pll_lock + ); + + +--------------------------------------------------------------------------- +-- FPGA communication +--------------------------------------------------------------------------- + FPGA5_COMM <= (others => '0'); + + +--------------------------------------------------------------------------- +-- AddOn +--------------------------------------------------------------------------- + DQLL <= (others => '0'); + DQUL <= (others => '0'); + DQLR <= (others => '0'); + DQUR <= (others => '0'); + + +--------------------------------------------------------------------------- +-- Flash ROM +--------------------------------------------------------------------------- + FLASH_CLK <= '0'; + FLASH_CS <= '0'; + FLASH_CIN <= '0'; + PROGRAMN <= '1'; + +--------------------------------------------------------------------------- +-- LED +--------------------------------------------------------------------------- + LED_GREEN <= not time_counter(24); + LED_ORANGE <= not time_counter(25); + LED_RED <= not time_counter(26); + LED_YELLOW <= not time_counter(27); + + +--------------------------------------------------------------------------- +-- Test Connector +--------------------------------------------------------------------------- + TEST_LINE <= (others => '0'); + + +--------------------------------------------------------------------------- +-- Test Circuits +--------------------------------------------------------------------------- + process + begin + wait until rising_edge(clk_100_i); + time_counter <= time_counter + 1; + end process; + +end architecture; \ No newline at end of file -- 2.43.0