From cf7013398226f07380688ca726abbf90769cdb30 Mon Sep 17 00:00:00 2001 From: "a.weber" Date: Wed, 8 Aug 2018 10:42:26 +0200 Subject: [PATCH] address in data ; FIFO too slow (<4MB/s) -AW --- combiner_calib/combiner.vhd | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/combiner_calib/combiner.vhd b/combiner_calib/combiner.vhd index 315e32d..ece6c7c 100644 --- a/combiner_calib/combiner.vhd +++ b/combiner_calib/combiner.vhd @@ -208,7 +208,8 @@ architecture arch of combiner is signal DEBUG_EvtLength : unsigned(15 downto 0); signal already_asked : std_logic := '0'; - signal rd_enabled : std_logic := '0'; + signal rd_enabled : std_logic := '0'; + signal my_network_address : std_logic_vector(15 downto 0); component FIFO_36x64 is port ( @@ -579,7 +580,7 @@ back_slave_ready_i <= BACK_SLAVE_READY; FEE_READ_IN => fee_read, --'1' for FEE data receiving (page 49) FEE_STATUS_BITS_OUT => fee_status_bits, FEE_BUSY_OUT => fee_busy, - MY_ADDRESS_IN => timer.network_address, + MY_ADDRESS_IN => my_network_address, COMMON_STAT_REGS => common_stat_reg, --open, COMMON_CTRL_REGS => common_ctrl_reg, --open, ONEWIRE => TEMPSENS, @@ -675,6 +676,7 @@ back_slave_ready_i <= BACK_SLAVE_READY; if (fee_dataready and fee_read) = '1' then pckr_Data_Source <= fee_data; --not necessary pckr_Data(15 downto 0) <= fee_data; + my_network_address <= fee_data; pckr_Data_type <= x"2"; pckr_Data_ready <= '1'; pckr_RX_state <= SSE_DATA_H;--SSE_LENGTH; CHANGED FOR PACKING MODE -- 2.43.0