From d0001b3ed072e73c09ceb9a84fe932426a3b9565 Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Sun, 26 Jun 2022 00:13:13 +0200 Subject: [PATCH] fixes 2 --- gbe_trb/base/gbe_med_interface_5G.vhd | 84 +++++++++++++++++---------- 1 file changed, 52 insertions(+), 32 deletions(-) diff --git a/gbe_trb/base/gbe_med_interface_5G.vhd b/gbe_trb/base/gbe_med_interface_5G.vhd index 5639461..d9ff047 100644 --- a/gbe_trb/base/gbe_med_interface_5G.vhd +++ b/gbe_trb/base/gbe_med_interface_5G.vhd @@ -261,7 +261,10 @@ architecture RTL of gbe_med_interface_5G is signal init_dual : std_logic; signal debug : std_logic_vector(255 downto 0); - + + signal delay_q : std_logic_vector(3 downto 0); + signal pulse : std_logic; + begin -------------------------------------------------------------------- -------------------------------------------------------------------- @@ -307,8 +310,8 @@ begin -- clocks pll_refclki => CLK_125_IN, rxrefclk => CLK_125_IN, - txi_clk => sd_tx_clk(i), -- REALLY? - tx_pclk => sd_tx_clk(i), -- TO BE IMPLEMENTED + txi_clk => CLK_125_IN, -- REALLY? + tx_pclk => sd_tx_clk(i), -- not really needed? rx_pclk => sd_rx_clk(i), -- recovered RX clock -- TX channel txdata => sd_tx_data_q( (i + 1) * 8 - 1 downto i * 8), @@ -399,15 +402,15 @@ begin -- one register between SGMII and SerDes SYNC_TX_PROC : process(CLK_125_IN) begin - if rising_edge(sd_tx_clk(i)) then + if rising_edge(CLK_125_IN) then sd_tx_data_q( (i + 1) * 8 - 1 downto i * 8) <= sd_tx_data( (i + 1) * 8 - 1 downto i * 8); sd_tx_kcntl_q(i) <= sd_tx_kcntl(i); sd_tx_correct_disp_q(i) <= sd_tx_correct_disp(i); end if; end process SYNC_TX_PROC; - -- one register between SewrDes and SGMII - SYNC_RX_PROC : process(sd_rx_clk) + -- one register between SerDes and SGMII + SYNC_RX_PROC : process(sd_rx_clk(i)) begin if rising_edge(sd_rx_clk(i)) then sd_rx_data_q( (i + 1) * 8 - 1 downto i * 8) <= sd_rx_data( (i + 1) * 8 - 1 downto i * 8); @@ -434,13 +437,13 @@ begin ctc_add_flag => open, an_link_ok => open, -- MAC interface - tx_clk_125 => sd_tx_clk(i), -- original clock from SerDes + tx_clk_125 => CLK_125_IN, -- was sd_tx_clk(i) tx_clock_enable_source => tx_clk_en(i), tx_clock_enable_sink => tx_clk_en(i), tx_d => pcs_txd( (i + 1) * 8 - 1 downto i * 8), -- TX data from MAC tx_en => pcs_tx_en(i), -- TX data enable from MAC tx_er => pcs_tx_er(i), -- TX error from MAC - rx_clk_125 => sd_rx_clk(i), + rx_clk_125 => CLK_125_IN, -- was sd_rx_clk(i) rx_clock_enable_source => rx_clk_en(i), rx_clock_enable_sink => rx_clk_en(i), rx_d => pcs_rxd( (i + 1) * 8 - 1 downto i * 8), -- RX data to MAC @@ -465,7 +468,7 @@ begin mr_page_rx => mr_page_rx(i), mr_lp_adv_ability => mr_lp_adv_ability( (i + 1) * 16 - 1 downto i * 16), mr_main_reset => mr_main_reset(i), - mr_an_enable => '1', + mr_an_enable => mr_an_enable(i), --'1', mr_restart_an => mr_restart_an(i), mr_adv_ability => mr_adv_ability( (i + 1) * 16 - 1 downto i * 16) ); @@ -493,30 +496,47 @@ begin non_an_rate => "10", -- 1Gbps is rate when auto-negotiation disabled operational_rate => operational_rate( (i + 1) * 2 - 1 downto i * 2) ); + + --- SIMPLE --- + mr_main_reset(i) <= init_dual; + mr_restart_an(i) <= pulse; + mr_an_enable(i) <= link_rx_ready(i); - u0_ri : register_interface_hb port map( - -- Control Signals - rst_n => synced_rst, - hclk => CLK_125_IN, - gbe_mode => '1', - sgmii_mode => '0', - -- Host Bus - hcs_n => '1', - hwrite_n => '1', - haddr => (others => '0'), - hdatain => (others => '0'), - hdataout => open, - hready_n => open, - -- Register Outputs - mr_an_enable => mr_an_enable(i), - mr_restart_an => mr_restart_an(i), - mr_main_reset => mr_main_reset(i), - mr_adv_ability => mr_adv_ability( (i + 1 ) * 16 - 1 downto i * 16), - -- Register Inputs - mr_an_complete => an_complete(i), - mr_page_rx => mr_page_rx(i), - mr_lp_adv_ability => mr_lp_adv_ability( (i + 1 ) * 16 - 1 downto i * 16) - ); + mr_adv_ability( (i + 1 ) * 16 - 1 downto i * 16) <= x"0020"; + + SYNC_PROC: process( sd_tx_clk(i) ) + begin + if( rising_edge(sd_tx_clk(i)) ) then + delay_q <= delay_q(2 downto 0) & link_rx_ready(i); + end if; + end process SYNC_PROC; + + pulse <= not delay_q(3) and delay_q(2); + --- /SIMPLE --- + +-- u0_ri : register_interface_hb port map( +-- -- Control Signals +-- rst_n => synced_rst, +-- hclk => CLK_125_IN, +-- gbe_mode => '1', +-- sgmii_mode => '0', +-- -- Host Bus +-- hcs_n => '1', +-- hwrite_n => '1', +-- haddr => (others => '0'), +-- hdatain => (others => '0'), +-- hdataout => open, +-- hready_n => open, +-- -- Register Outputs +-- mr_an_enable => mr_an_enable(i), +-- mr_restart_an => mr_restart_an(i), +-- mr_main_reset => mr_main_reset(i), +-- mr_adv_ability => mr_adv_ability( (i + 1 ) * 16 - 1 downto i * 16), +-- -- Register Inputs +-- mr_an_complete => an_complete(i), +-- mr_page_rx => mr_page_rx(i), +-- mr_lp_adv_ability => mr_lp_adv_ability( (i + 1 ) * 16 - 1 downto i * 16) +-- ); MAC: tsmac_gbe port map( -- 2.43.0