From d10bad0b856b49a8a691a7366407af196feb17ef Mon Sep 17 00:00:00 2001
From: hadeshyp <hadeshyp>
Date: Wed, 16 Jan 2008 10:21:28 +0000
Subject: [PATCH] *** empty log message ***

---
 trb_net16_obuf.vhd | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/trb_net16_obuf.vhd b/trb_net16_obuf.vhd
index 046ee8d..f95a998 100644
--- a/trb_net16_obuf.vhd
+++ b/trb_net16_obuf.vhd
@@ -95,6 +95,7 @@ architecture trb_net16_obuf_arch of trb_net16_obuf is
 
   type sending_state_t is (idle, sending_ack);
   signal next_sending_state, sending_state : sending_state_t;
+  signal sending_state_bits : std_logic;
   
 begin
 
@@ -202,7 +203,7 @@ begin
   --full buffers (despite the sbuf) can only occur on the last packet.
   COMB_NEXT_TRANSFER : process(comb_dataready, transfer_counter, current_NOP_word,
                                CURRENT_DATA_COUNT, reg_SEND_ACK_IN, INT_DATAREADY_IN, INT_DATA_IN,
-                               reg_INT_READ_OUT, saved_packet_type,
+                               reg_INT_READ_OUT, saved_packet_type, sending_state,
                                current_DATA_word, send_ACK, send_EOB, sbuf_free, 
                                current_ACK_word, current_EOB_word, 
                                next_TRANSMITTED_BUFFERS, TRANSMITTED_BUFFERS, send_DATA)
@@ -215,6 +216,7 @@ begin
       next_DATA_COUNT    <= CURRENT_DATA_COUNT;
       next_SEND_ACK_IN   <= send_ACK;
       comb_dataready     <= '0';
+      next_sending_state <= sending_state;
 
       if (reg_INT_READ_OUT = '1' and  INT_DATAREADY_IN = '1')  then
                                       --can only happen if idle or sending_data
@@ -236,9 +238,11 @@ begin
           end if;
           if send_ACK = '1' then
               next_INT_READ_OUT       <= '0';
+              next_sending_state <= sending_ack;
           end if;
         end if;
       end if;
+
       if sending_state = sending_ack  then
         next_INT_READ_OUT <= '0';
         current_output_data_buffer <= current_ACK_word;
@@ -250,7 +254,8 @@ begin
           end if;
         end if;
       end if;
-      if send_ACK = '1' and transfer_counter = "00" then
+
+      if send_ACK = '1' and transfer_counter = "00" and (reg_INT_READ_OUT and INT_DATAREADY_IN) = '0' then
         next_sending_state <= sending_ack;
         next_INT_READ_OUT <= '0';
       end if;
@@ -259,6 +264,7 @@ begin
       end if;
     end process;
 
+sending_state_bits <= '1' when sending_state = sending_ack else '0';
 
   REG1 : process(CLK)
     begin
-- 
2.43.0