From d1251f2f772b31c6831a4ccd686113fe1eb188c9 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Wed, 10 May 2017 14:47:17 +0200 Subject: [PATCH] fix names of SPI ports fix mapping of PWM outputs on DAC FPGAs --- pinout/dirich.lpf | 32 ++++++++++++++++---------------- thresholds/thresholds.vhd | 30 ++++++++++++++++++++++++++---- 2 files changed, 42 insertions(+), 20 deletions(-) diff --git a/pinout/dirich.lpf b/pinout/dirich.lpf index a786264..57bf40a 100644 --- a/pinout/dirich.lpf +++ b/pinout/dirich.lpf @@ -156,19 +156,19 @@ DEFINE PORT GROUP "TEST_group" "TEST*" ; IOBUF GROUP "TEST_group" IO_TYPE=LVCMOS25 DRIVE=8 BANK_VCCIO=2.5; -LOCATE COMP "MISO_IN_1" SITE "E7"; #DAC1_CTRL0 -LOCATE COMP "MISO_IN_2" SITE "A17"; #DAC2_CTRL0 -LOCATE COMP "MOSI_OUT_1" SITE "D7"; #DAC1_CTRL1 -LOCATE COMP "MOSI_OUT_2" SITE "A18"; #DAC2_CTRL1 -LOCATE COMP "SCLK_OUT_1" SITE "E6"; #DAC1_CTRL2 -LOCATE COMP "SCLK_OUT_2" SITE "B19"; #DAC2_CTRL2 -LOCATE COMP "CS_OUT_1" SITE "D6"; #DAC1_CTRL3 -LOCATE COMP "CS_OUT_2" SITE "B18"; #DAC2_CTRL3 -IOBUF PORT "MISO_IN_1 " IO_TYPE=LVCMOS25 PULLMODE=UP; -IOBUF PORT "MOSI_OUT_1" IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW; -IOBUF PORT "SCLK_OUT_1" IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW; -IOBUF PORT "CS_OUT_1" IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW; -IOBUF PORT "MISO_IN_2 " IO_TYPE=LVCMOS25 PULLMODE=UP; -IOBUF PORT "MOSI_OUT_2" IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW; -IOBUF PORT "SCLK_OUT_2" IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW; -IOBUF PORT "CS_OUT_2" IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW; +LOCATE COMP "MISO_IN[1]" SITE "E7"; #DAC1_CTRL0 +LOCATE COMP "MISO_IN[2]" SITE "A17"; #DAC2_CTRL0 +LOCATE COMP "MOSI_OUT[1]" SITE "D7"; #DAC1_CTRL1 +LOCATE COMP "MOSI_OUT[2]" SITE "A18"; #DAC2_CTRL1 +LOCATE COMP "SCLK_OUT[1]" SITE "E6"; #DAC1_CTRL2 +LOCATE COMP "SCLK_OUT[2]" SITE "B19"; #DAC2_CTRL2 +LOCATE COMP "CS_OUT[1]" SITE "D6"; #DAC1_CTRL3 +LOCATE COMP "CS_OUT[2]" SITE "B18"; #DAC2_CTRL3 +IOBUF PORT "MISO_IN[1]" IO_TYPE=LVCMOS25 PULLMODE=UP; +IOBUF PORT "MOSI_OUT[1]" IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW; +IOBUF PORT "SCLK_OUT[1]" IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW; +IOBUF PORT "CS_OUT[1]" IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW; +IOBUF PORT "MISO_IN[2]" IO_TYPE=LVCMOS25 PULLMODE=UP; +IOBUF PORT "MOSI_OUT[2]" IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW; +IOBUF PORT "SCLK_OUT[2]" IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW; +IOBUF PORT "CS_OUT[2]" IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW; diff --git a/thresholds/thresholds.vhd b/thresholds/thresholds.vhd index 2a00fa1..58499c1 100644 --- a/thresholds/thresholds.vhd +++ b/thresholds/thresholds.vhd @@ -10,8 +10,8 @@ use work.trb_net_std.all; entity thresholds is port( - ID : in std_logic; - OUTPUT : out std_logic_vector(15 downto 0); + DAC_FLAG : in std_logic; + OUTPUT : out std_logic_vector(15 downto 0); MISO_OUT : out std_logic; MOSI_IN : in std_logic; SCLK_IN : in std_logic; @@ -190,8 +190,30 @@ THE_PWM_GEN : entity work.pwm_generator ); --TODO connect to output according to ID -OUTPUT <= pwm_i; - +process(pwm_i,DAC_FLAG) + begin + if DAC_FLAG = '1' then + OUTPUT <= pwm_i; + else + OUTPUT(1) <= pwm_i(15); + OUTPUT(2) <= pwm_i(13); + OUTPUT(3) <= pwm_i(8); + OUTPUT(4) <= pwm_i(5); + OUTPUT(5) <= pwm_i(16); + OUTPUT(6) <= pwm_i(4); + OUTPUT(7) <= pwm_i(3); + OUTPUT(8) <= pwm_i(6); + OUTPUT(9) <= pwm_i(2); + OUTPUT(10) <= pwm_i(1); + OUTPUT(11) <= pwm_i(7); + OUTPUT(12) <= pwm_i(9); + OUTPUT(13) <= pwm_i(14); + OUTPUT(14) <= pwm_i(12); + OUTPUT(15) <= pwm_i(10); + OUTPUT(16) <= pwm_i(11); + end if; + end process; + --------------------------------------------------------------------------- -- 2.43.0