From d1446233c9b6e590bbbdce363315b61146cb940f Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Wed, 21 Jan 2009 13:54:12 +0000 Subject: [PATCH] first version of ipu_data_hub --- basics/ram_dp_rw.vhd | 41 + basics/wide_adder.vhd | 111 +- basics/wide_adder_17x16.vhd | 113 +++ ...rb_net16_endpoint_1_trg_2_data_1_regio.vhd | 960 ++++++++++++++++++ testbench/wide_adder_testbench.vhd | 44 +- testbenches/testbench_hublogic_ipudata.prj | 35 + testbenches/testbench_hublogic_ipudata.vhd | 558 ++++++++++ trb_net16_hub_ipu_logic.vhd | 541 +++++++--- trb_net16_obuf.vhd | 2 +- trb_net_priority_arbiter.vhd | 3 + trb_net_std.vhd | 29 + 11 files changed, 2220 insertions(+), 217 deletions(-) create mode 100644 basics/ram_dp_rw.vhd create mode 100644 basics/wide_adder_17x16.vhd create mode 100644 oldfiles/trb_net16_endpoint_1_trg_2_data_1_regio.vhd create mode 100644 testbenches/testbench_hublogic_ipudata.prj create mode 100644 testbenches/testbench_hublogic_ipudata.vhd diff --git a/basics/ram_dp_rw.vhd b/basics/ram_dp_rw.vhd new file mode 100644 index 0000000..01f07a7 --- /dev/null +++ b/basics/ram_dp_rw.vhd @@ -0,0 +1,41 @@ +--a pseudo dual ported RAM with one write-only port and one read-only port. + +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.std_logic_ARITH.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; + +entity ram_dp_rw is + generic( + depth : integer := 3; + width : integer := 16 + ); + port( + CLK : in std_logic; + wr1 : in std_logic; + a1 : in std_logic_vector(depth-1 downto 0); + din1 : in std_logic_vector(width-1 downto 0); + a2 : in std_logic_vector(depth-1 downto 0); + dout2 : out std_logic_vector(width-1 downto 0) + ); +end entity; + +architecture ram_dp_rw_arch of ram_dp_rw is + type ram_t is array(0 to 2**depth-1) of std_logic_vector(width-1 downto 0); + SIGNAL ram : ram_t := (others => (others => '0')); +begin + + process(CLK) + begin + if rising_edge(CLK) then + if wr1 = '1' then + ram((conv_integer(a1))) <= din1; + end if; + dout2 <= ram(conv_integer(a2)); + end if; + end process; + +end architecture; diff --git a/basics/wide_adder.vhd b/basics/wide_adder.vhd index b0bdd77..2082d37 100644 --- a/basics/wide_adder.vhd +++ b/basics/wide_adder.vhd @@ -12,9 +12,11 @@ use work.trb_net_std.all; entity wide_adder is generic( +-- FIXED_SETUP : integer := c_YES; --18 inputs, 16 WIDTH, 3 clock cycles WIDTH : integer := 16; - WORDS : integer := 16; --multiples of 2^parallel_adders only - PARALLEL_ADDERS : integer := 2 --2^n + WORDS : integer := 16; + PARALLEL_ADDERS : integer := 1 ; + PSEUDO_WORDS : integer := 16 --the smallest multiple of PARALLEL_ADDERS, greater or equal than WORDS ); port( CLK : in std_logic; @@ -30,60 +32,90 @@ entity wide_adder is end entity; architecture wide_adder_arch of wide_adder is - signal state : integer range 0 to WORDS/2**PARALLEL_ADDERS+2; - signal result : integer range 0 to 2**(WIDTH+PARALLEL_ADDERS)-1; + signal state : integer range 0 to WORDS/(PARALLEL_ADDERS)+2; + signal state_word : integer range 0 to PSEUDO_WORDS; + signal result : std_logic_vector(WIDTH-1 downto 0); signal ready : std_logic; signal overflow : std_logic; + signal last_START_IN : std_logic; + + signal tmp_state : std_logic_vector(3 downto 0); + signal tmp_result : std_logic_vector(WIDTH-1 downto 0); + signal tmp_section: std_logic_vector(WIDTH*(PARALLEL_ADDERS)-1 downto 0); + + signal pseudo_VAL_ENABLE_IN : std_logic_vector(PSEUDO_WORDS-1 downto 0); + signal pseudo_INPUT_IN : std_logic_vector(16*PSEUDO_WORDS-1 downto 0); + + type tmp1_t is array(0 to 8) of integer range 0 to 2**16-1; +-- type tmp11_t is array(0 to 11) of integer range 0 to 2**16-1; - signal tmp_result : std_logic_vector(WIDTH+PARALLEL_ADDERS downto 0); begin +--pad inputs to adder WIDTH + pseudo_VAL_ENABLE_IN(WORDS-1 downto 0) <= VAL_ENABLE_IN(WORDS-1 downto 0); + + pseudo_INPUT_IN(WIDTH*WORDS-1 downto 0) <= INPUT_IN(WIDTH*WORDS-1 downto 0); + + gen_padding : if (WORDS/PARALLEL_ADDERS)*PARALLEL_ADDERS /= WORDS generate + pseudo_VAL_ENABLE_IN(pseudo_VAL_ENABLE_IN'left downto WORDS) <= (others => '0'); + pseudo_INPUT_IN(pseudo_INPUT_IN'left downto WIDTH*WORDS) <= (others => '0'); + end generate; proc_result : process(CLK) - variable erg : integer range 0 to 2**(WIDTH+1)-1; - variable section : std_logic_vector(WIDTH*2**PARALLEL_ADDERS-1 downto 0); + variable erg : integer range 0 to 2**(WIDTH+1)*PARALLEL_ADDERS-1; + constant num : integer := PARALLEL_ADDERS; + variable section : std_logic_vector(WIDTH*(PARALLEL_ADDERS)-1 downto 0); + variable var_result : std_logic_vector(WIDTH+log2(PARALLEL_ADDERS)-1 downto 0); begin if rising_edge(CLK) then if RESET = '1' then - state <= WORDS+PARALLEL_ADDERS; + state <= 0; overflow <= '0'; ready <= '0'; - else + last_START_IN <= '0'; + elsif CLK_EN = '1' then + last_START_IN <= START_IN; if START_IN = '1' then state <= 0; - result <= 0; + result <= (others => '0'); ready <= '0'; overflow <= '0'; end if; - if (state) * 2**PARALLEL_ADDERS < WORDS then - gen_mux : for i in 0 to WIDTH*2**PARALLEL_ADDERS-1 loop - section(i) := INPUT_IN((state*2**PARALLEL_ADDERS)*WIDTH+i); + if (state*num) < WORDS then + section := pseudo_INPUT_IN(state*num*WIDTH+WIDTH*(PARALLEL_ADDERS)-1 downto state*num*WIDTH); + gen_mux0 : for j in 0 to PARALLEL_ADDERS-1 loop --word number + if pseudo_VAL_ENABLE_IN(state*num+j) = '0' then + section((j)*WIDTH+WIDTH-1 downto (j)*WIDTH) := (others => '0'); + end if; end loop; - erg := result; --- if (WORDS/2**PARALLEL_ADDERS)*2**PARALLEL_ADDERS = WORDS then - gen_adders_simple : for i in 0 to 2**PARALLEL_ADDERS-1 loop - if VAL_ENABLE_IN(state*2**PARALLEL_ADDERS+i) = '1' then + tmp_section <= section; + erg := to_integer(unsigned(result)); + if PARALLEL_ADDERS = 3 then + erg := ( to_integer(unsigned(result)) + + to_integer(unsigned(section((0)*WIDTH+WIDTH-1 downto (0)*WIDTH)))) + + (to_integer(unsigned(section((1)*WIDTH+WIDTH-1 downto (1)*WIDTH))) + + to_integer(unsigned(section((2)*WIDTH+WIDTH-1 downto (2)*WIDTH)))); + elsif PARALLEL_ADDERS = 4 then + erg :=((to_integer(unsigned(section((0)*WIDTH+WIDTH-1 downto (0)*WIDTH))) + + to_integer(unsigned(section((1)*WIDTH+WIDTH-1 downto (1)*WIDTH)))) + + (to_integer(unsigned(section((2)*WIDTH+WIDTH-1 downto (2)*WIDTH))) + + to_integer(unsigned(section((3)*WIDTH+WIDTH-1 downto (3)*WIDTH))))) + + to_integer(unsigned(result)); + else + gen_adders_simple : for i in 0 to PARALLEL_ADDERS-1 loop erg := erg + to_integer(unsigned(section((i)*WIDTH+WIDTH-1 downto (i)*WIDTH))); - else - erg := erg; - end if; end loop; --- else --- gen_adders_odd : for i in 0 to 2**PARALLEL_ADDERS-1 loop --- if (state)*2**PARALLEL_ADDERS + i < WORDS then --- erg := erg + to_integer(unsigned(section((i)*WIDTH+WIDTH-1 downto (i)*WIDTH))); --- else --- erg := erg; --- end if; --- end loop; --- end if; - result <= erg; - state <= state + 1; - if (state*2**PARALLEL_ADDERS >= WORDS - 2**PARALLEL_ADDERS) then + end if; + var_result := std_logic_vector(to_unsigned(erg,WIDTH+log2(PARALLEL_ADDERS))); + result <= var_result(WIDTH-1 downto 0); + if state /= 0 or last_START_IN = '1' then + state <= state + 1; + end if; + if (state*num >= WORDS - num) then ready <= '1'; end if; - if erg >= 2**WIDTH then + if or_all(var_result(var_result'left downto WIDTH)) = '1' then overflow <= '1'; end if; end if; @@ -91,12 +123,13 @@ begin end if; end process; -tmp_result <= std_logic_vector(to_unsigned(result,WIDTH+PARALLEL_ADDERS+1)); - - -OVERFLOW_OUT <= overflow; -RESULT_OUT <= tmp_result(WIDTH-1 downto 0); -READY_OUT <= ready; +--Debug Signals + tmp_state <= std_logic_vector(to_unsigned(state,4)); + tmp_result <= result; +--Outputs + OVERFLOW_OUT <= overflow; + RESULT_OUT <= tmp_result(WIDTH-1 downto 0); + READY_OUT <= ready; end architecture; \ No newline at end of file diff --git a/basics/wide_adder_17x16.vhd b/basics/wide_adder_17x16.vhd new file mode 100644 index 0000000..25b8127 --- /dev/null +++ b/basics/wide_adder_17x16.vhd @@ -0,0 +1,113 @@ +--Adds up 17 16bit words in 4 clock cycles + + + +LIBRARY ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; + + +entity wide_adder_17x16 is + generic( + SIZE : integer := 16; + WORDS: integer := 17 --fixed + ); + port( + CLK : in std_logic; + CLK_EN : in std_logic; + RESET : in std_logic; + INPUT_IN : in std_logic_vector(SIZE*WORDS-1 downto 0); + START_IN : in std_logic; + VAL_ENABLE_IN: in std_logic_vector(WORDS-1 downto 0); + RESULT_OUT : out std_logic_vector(SIZE-1 downto 0); + OVERFLOW_OUT : out std_logic; + READY_OUT : out std_logic + ); +end entity; + +architecture wide_adder_17x16_arch of wide_adder_17x16 is + +signal overflow : std_logic; +signal ready : std_logic; +signal result : std_logic_vector(SIZE-1 downto 0); +signal state : integer range 0 to 1; + + +begin + + process(CLK) + variable tmp : integer range 0 to (2**SIZE+1)-1; + variable var_storage : std_logic_vector(8*(SIZE+1)-1 downto 0); + variable var1_storage : std_logic_vector(4*(SIZE+1)-1 downto 0); + variable var2_storage : std_logic_vector(2*(SIZE+1)-1 downto 0); + variable var_result : std_logic_vector(1*(SIZE+1)-1 downto 0); + constant STOR_SIZE : integer := SIZE+1; + begin + if rising_edge(CLK) then + if RESET = '1' then + result <= (others => '0'); + state <= 0; + ready <= '0'; + overflow <= '0'; + elsif CLK_EN = '1' then + case state is + when 0 => + ready <= '0'; + if START_IN = '1' then + state <= 1; + gen_1st : for i in 0 to 7 loop + tmp := 0; + if VAL_ENABLE_IN(i*2) = '1' then + tmp := to_integer(unsigned(INPUT_IN((i*2+1)*SIZE-1 downto i*2*SIZE))); + end if; + if VAL_ENABLE_IN(i*2+1) = '1' then + tmp := tmp + to_integer(unsigned(INPUT_IN((i*2+2)*SIZE-1 downto (i*2+1)*SIZE))); + end if; + var_storage((i+1)*STOR_SIZE-1 downto i*STOR_SIZE) := std_logic_vector(to_unsigned(tmp,STOR_SIZE)); + end loop; + gen_2nd : for i in 0 to 3 loop + var1_storage((i+1)*STOR_SIZE-1 downto (i)*STOR_SIZE) := std_logic_vector(to_unsigned( + to_integer(unsigned(var_storage((i*2+1)*STOR_SIZE-1 downto i*2*STOR_SIZE))) + + to_integer(unsigned(var_storage((i*2+2)*STOR_SIZE-1 downto (i*2+1)*STOR_SIZE))),STOR_SIZE)); + end loop; + overflow <= var_storage(1*STOR_SIZE-1) or var_storage(2*STOR_SIZE-1) or var_storage(3*STOR_SIZE-1) + or var_storage(4*STOR_SIZE-1) or var_storage(5*STOR_SIZE-1) or var_storage(6*STOR_SIZE-1) + or var_storage(7*STOR_SIZE-1) or var_storage(8*STOR_SIZE-1) or var1_storage(1*STOR_SIZE-1) + or var1_storage(2*STOR_SIZE-1) or var1_storage(3*STOR_SIZE-1) or var1_storage(4*STOR_SIZE-1); + end if; + when 1 => + state <= 0; + gen_3rd : for i in 0 to 1 loop + var2_storage((i+1)*STOR_SIZE-1 downto (i)*STOR_SIZE) := std_logic_vector(to_unsigned( + to_integer(unsigned(var1_storage((i*2+1)*STOR_SIZE-1 downto i*2*STOR_SIZE))) + + to_integer(unsigned(var1_storage((i*2+2)*STOR_SIZE-1 downto (i*2+1)*STOR_SIZE))),STOR_SIZE)); + end loop; + if VAL_ENABLE_IN(16) = '0' then + var_result := std_logic_vector(to_unsigned( + to_integer(unsigned(var2_storage((1)*STOR_SIZE-1 downto 0*STOR_SIZE))) + + to_integer(unsigned(var2_storage((2)*STOR_SIZE-1 downto 1*STOR_SIZE))),STOR_SIZE)); + else + var_result := std_logic_vector(to_unsigned( + to_integer(unsigned(var2_storage((1)*STOR_SIZE-1 downto 0*STOR_SIZE))) + + to_integer(unsigned(var2_storage((2)*STOR_SIZE-1 downto 1*STOR_SIZE))) + + to_integer(unsigned(INPUT_IN(INPUT_IN'left downto INPUT_IN'left - SIZE+1))),STOR_SIZE)); + end if; + result <= var_result(SIZE-1 downto 0); + overflow <= overflow or var2_storage(1*STOR_SIZE-1) or var2_storage(2*STOR_SIZE-1) or var_result(1*STOR_SIZE-1); + ready <= '1'; + when others => + state <= 0; + end case; + end if; + end if; + end process; + + +OVERFLOW_OUT <= overflow; +READY_OUT <= ready; +RESULT_OUT <= result; + +end architecture; \ No newline at end of file diff --git a/oldfiles/trb_net16_endpoint_1_trg_2_data_1_regio.vhd b/oldfiles/trb_net16_endpoint_1_trg_2_data_1_regio.vhd new file mode 100644 index 0000000..8aadcaa --- /dev/null +++ b/oldfiles/trb_net16_endpoint_1_trg_2_data_1_regio.vhd @@ -0,0 +1,960 @@ +-- the full endpoint for HADES: trg, data, data, regio + +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.std_logic_ARITH.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; + + + +entity trb_net16_endpoint_1_trg_2_api_1_regio is + generic ( + USE_CHANNEL : channel_config_t := (c_YES,c_YES,c_YES,c_YES); + API_TYPE : channel_config_t := (c_API_PASSIVE,c_API_PASSIVE,c_API_PASSIVE,c_API_PASSIVE); + IBUF_DEPTH : channel_config_t := (0,6,6,6); + FIFO_TO_INT_DEPTH : channel_config_t := (0,6,6,6); + FIFO_TO_APL_DEPTH : channel_config_t := (0,6,6,6); + IBUF_SECURE_MODE : channel_config_t := (c_YES,c_YES,c_YES,c_YES); + API_SECURE_MODE_TO_APL : channel_config_t := (c_YES,c_YES,c_YES,c_YES); + OBUF_DATA_COUNT_WIDTH : integer range 0 to 7 := std_DATA_COUNT_WIDTH; + INIT_CAN_SEND_DATA : channel_config_t := (c_NO,c_NO,c_NO,c_NO); + REPLY_CAN_SEND_DATA : channel_config_t := (c_YES,c_YES,c_YES,c_YES); + SCTR_NUM_STAT_REGS : integer range 0 to 6 := 2; --log2 of number of status registers + SCTR_NUM_CTRL_REGS : integer range 0 to 6 := 2; --log2 of number of ctrl registers + --standard values for output registers + SCTR_INIT_CTRL_REGS : std_logic_vector(2**(3)*32-1 downto 0) := (others => '0'); + --set to 0 for unused ctrl registers to save resources + SCTR_USED_CTRL_REGS : std_logic_vector(2**(3)-1 downto 0) := "00000001"; + --set to 0 for each unused bit in a register + SCTR_USED_CTRL_BITMASK : std_logic_vector(2**(3)*32-1 downto 0) := (others => '1'); + --no data / address out? + SCTR_USE_DATA_PORT : integer := c_NO; + SCTR_USE_1WIRE_INTERFACE : integer := c_YES; + SCTR_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF"; + SCTR_INIT_UNIQUE_ID : std_logic_vector(95 downto 0) := (others => '0'); + SCTR_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; + SCTR_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; + SCTR_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678" + ); + + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + -- Media direction port + MED_DATAREADY_OUT : out std_logic; + MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_IN : in std_logic; + MED_DATAREADY_IN : in std_logic; + MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT : out std_logic; + MED_ERROR_IN : in std_logic_vector (2 downto 0); + MED_STAT_OP : in std_logic_vector (15 downto 0); + MED_CTRL_OP : out std_logic_vector (15 downto 0); + + -- LVL1 trigger APL + LVL1_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); + LVL1_GOT_TRIGGER_OUT : out std_logic; + LVL1_DTYPE_OUT : out std_logic_vector(3 downto 0); + LVL1_SEQNR_OUT : out std_logic_vector(7 downto 0); + LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0) := x"00000000"; + LVL1_RELEASE_IN : in std_logic := '0'; + + -- IPU-Data Channel APL + IPUD_APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0) := x"0000"; + IPUD_APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0) := "00"; + IPUD_APL_DATAREADY_IN : in std_logic := '0'; + IPUD_APL_READ_OUT : out std_logic; + IPUD_APL_SHORT_TRANSFER_IN: in std_logic := '0'; + IPUD_APL_DTYPE_IN : in std_logic_vector (3 downto 0) := x"0"; + IPUD_APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0) := x"00000000"; + IPUD_APL_SEND_IN : in std_logic:= '0'; + IPUD_APL_TARGET_ADDRESS_IN: in std_logic_vector (15 downto 0) := x"0000"; + IPUD_APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + IPUD_APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + IPUD_APL_TYP_OUT : out std_logic_vector (2 downto 0); + IPUD_APL_DATAREADY_OUT : out std_logic; + IPUD_APL_READ_IN : in std_logic:= '0'; + IPUD_APL_RUN_OUT : out std_logic; + IPUD_APL_SEQNR_OUT : out std_logic_vector (7 downto 0); + + -- LVL2-Data Channel APL + LVL2_APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0) := x"0000"; + LVL2_APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0) := "00"; + LVL2_APL_DATAREADY_IN : in std_logic := '0'; + LVL2_APL_READ_OUT : out std_logic; + LVL2_APL_SHORT_TRANSFER_IN: in std_logic := '0'; + LVL2_APL_DTYPE_IN : in std_logic_vector (3 downto 0) := x"0"; + LVL2_APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0) := x"00000000"; + LVL2_APL_SEND_IN : in std_logic:= '0'; + LVL2_APL_TARGET_ADDRESS_IN: in std_logic_vector (15 downto 0) := x"0000"; + LVL2_APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + LVL2_APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + LVL2_APL_TYP_OUT : out std_logic_vector (2 downto 0); + LVL2_APL_DATAREADY_OUT : out std_logic; + LVL2_APL_READ_IN : in std_logic:= '0'; + LVL2_APL_RUN_OUT : out std_logic; + LVL2_APL_SEQNR_OUT : out std_logic_vector (7 downto 0); + + -- Slow Control Data Port + SCTR_COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); + SCTR_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0); + SCTR_REGISTERS_IN : in std_logic_vector(32*2**(SCTR_NUM_STAT_REGS)-1 downto 0) := (others => '0'); + SCTR_REGISTERS_OUT : out std_logic_vector(32*2**(SCTR_NUM_CTRL_REGS)-1 downto 0); + --following ports only used when using internal data port + SCTR_ADDR_OUT : out std_logic_vector(16-1 downto 0); + SCTR_READ_ENABLE_OUT : out std_logic; + SCTR_WRITE_ENABLE_OUT : out std_logic; + SCTR_DATA_OUT : out std_logic_vector(32-1 downto 0); + SCTR_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0'); + SCTR_DATAREADY_IN : in std_logic := '0'; + SCTR_NO_MORE_DATA_IN : in std_logic := '0'; + --IDRAM is used if no 1-wire interface, onewire used otherwise + SCTR_IDRAM_DATA_IN : in std_logic_vector(15 downto 0) := (others => '0'); + SCTR_IDRAM_DATA_OUT : out std_logic_vector(15 downto 0); + SCTR_IDRAM_ADDR_IN : in std_logic_vector(2 downto 0) := "000"; + SCTR_IDRAM_WR_IN : in std_logic := '0'; + SCTR_ONEWIRE_INOUT : inout std_logic; + --Additional r/w access to ctrl registers + SCTR_EXT_REG_DATA_IN : in std_logic_vector(31 downto 0) := (others => '0'); + SCTR_EXT_REG_DATA_OUT : out std_logic_vector(31 downto 0); + SCTR_EXT_REG_WRITE_IN : in std_logic := '0'; + SCTR_EXT_REG_ADDR_IN : in std_logic_vector(7 downto 0) := (others => '0'); + -- Status + MPLEX_CTRL : in std_logic_vector (31 downto 0) := (others => '0'); + STAT_CTRL_INIT_BUFFER : in std_logic_vector (4*32-1 downto 0) := (others => '0'); + STAT_CTRL_GEN : in std_logic_vector (4*32-1 downto 0) := (others => '0'); + STAT_GEN_1 : out std_logic_vector (31 downto 0); -- General Status + STAT_GEN_2 : out std_logic_vector (31 downto 0); -- General Status + CTRL_GEN : in std_logic_vector (4*32-1 downto 0) := (others => '0') + ); +end entity; + + + + + +architecture trb_net16_endpoint_1_trg_2_api_1_regio_arch of trb_net16_endpoint_1_trg_2_api_1_regio is + + component trb_net_onewire is + generic( + USE_TEMPERATURE_READOUT : integer range 0 to 1 := 1; + CLK_PERIOD : integer := 10 --clk period in ns + ); + port( + CLK : in std_logic; + RESET : in std_logic; + --connection to 1-wire interface + ONEWIRE : inout std_logic; + --connection to id ram, according to memory map in TrbNetRegIO + DATA_OUT : out std_logic_vector(15 downto 0); + ADDR_OUT : out std_logic_vector(2 downto 0); + WRITE_OUT: out std_logic; + TEMP_OUT : out std_logic_vector(11 downto 0); + STAT : out std_logic_vector(31 downto 0) + ); + end component; + + component trb_net16_regIO is + generic ( + REGISTER_WIDTH : integer range 32 to 32 := 32; + ADDRESS_WIDTH : integer range 8 to 16 := 16; + NUM_STAT_REGS : integer range 0 to 6 := 1; --log2 of number of status registers + NUM_CTRL_REGS : integer range 0 to 6 := 2; --log2 of number of ctrl registers + --standard values for output registers + INIT_CTRL_REGS : std_logic_vector(2**(3)*32-1 downto 0) := + (others => '0'); + --set to 0 for unused ctrl registers to save resources + USED_CTRL_REGS : std_logic_vector(2**(3)-1 downto 0) := "00000001"; + --set to 0 for each unused bit in a register + USED_CTRL_BITMASK : std_logic_vector(2**(3)*32-1 downto 0) := + (others => '1'); + USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port + + INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF"; + INIT_UNIQUE_ID : std_logic_vector(95 downto 0) := (others => '0'); + COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; + COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; + HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678" + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Port to API + API_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + API_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + API_DATAREADY_OUT : out std_logic; + API_READ_IN : in std_logic; + API_SHORT_TRANSFER_OUT : out std_logic; + API_DTYPE_OUT : out std_logic_vector (3 downto 0); + API_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); + API_SEND_OUT : out std_logic; + API_TARGET_ADDRESS_OUT : out std_logic_vector (15 downto 0); + -- Receiver port + API_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + API_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + API_TYP_IN : in std_logic_vector (2 downto 0); + API_DATAREADY_IN : in std_logic; + API_READ_OUT : out std_logic; + -- APL Control port + API_RUN_IN : in std_logic; + API_SEQNR_IN : in std_logic_vector (7 downto 0); + + --Port to write Unique ID + IDRAM_DATA_IN : in std_logic_vector(15 downto 0); + IDRAM_DATA_OUT : out std_logic_vector(15 downto 0); + IDRAM_ADDR_IN : in std_logic_vector(2 downto 0); + IDRAM_WR_IN : in std_logic; + MY_ADDRESS_OUT : out std_logic_vector(15 downto 0); + + --Common Register in / out + COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0); + COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0); + --Custom Register in / out + REGISTERS_IN : in std_logic_vector(REGISTER_WIDTH*2**(NUM_STAT_REGS)-1 downto 0); + REGISTERS_OUT : out std_logic_vector(REGISTER_WIDTH*2**(NUM_CTRL_REGS)-1 downto 0); + --Internal Data Port + DAT_ADDR_OUT : out std_logic_vector(ADDRESS_WIDTH-1 downto 0); + DAT_READ_ENABLE_OUT : out std_logic; + DAT_WRITE_ENABLE_OUT: out std_logic; + DAT_DATA_OUT : out std_logic_vector(REGISTER_WIDTH-1 downto 0); + --Data input can only be used as reaction on read or write access. write operation should return data + --if successful + DAT_DATA_IN : in std_logic_vector(REGISTER_WIDTH-1 downto 0); + DAT_DATAREADY_IN : in std_logic; + DAT_NO_MORE_DATA_IN : in std_logic; + --finish transmission, when reading from a fifo and it got empty + --Additional write access to ctrl registers + EXT_REG_DATA_IN : in std_logic_vector(31 downto 0); + EXT_REG_DATA_OUT : out std_logic_vector(31 downto 0); + EXT_REG_WRITE_IN : in std_logic; + EXT_REG_ADDR_IN : in std_logic_vector(7 downto 0); + STAT : out std_logic_vector(31 downto 0) + ); + end component; + + component trb_net16_iobuf is + generic ( + IBUF_DEPTH : integer range 0 to 6 := c_FIFO_BRAM;--std_FIFO_DEPTH; + IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;--std_IBUF_SECURE_MODE; + SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; + OBUF_DATA_COUNT_WIDTH : integer range 2 to 7 := std_DATA_COUNT_WIDTH; + USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE; + USE_CHECKSUM : integer range 0 to 1 := c_YES; + USE_VENDOR_CORES : integer range 0 to 1 := c_YES; + INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES; + REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Media direction port + MED_INIT_DATAREADY_OUT: out std_logic; + MED_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_INIT_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_INIT_READ_IN: in std_logic; + + MED_REPLY_DATAREADY_OUT: out std_logic; + MED_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_REPLY_READ_IN: in std_logic; + + + MED_DATAREADY_IN: in std_logic; -- Data word is offered by the Media(the IOBUF MUST read) + MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT: out std_logic; + MED_ERROR_IN: in std_logic_vector (2 downto 0); + + + + -- Internal direction port + + INT_INIT_DATAREADY_OUT: out std_logic; + INT_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_INIT_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_INIT_READ_IN: in std_logic; + + INT_INIT_DATAREADY_IN: in std_logic; + INT_INIT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_INIT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_INIT_READ_OUT: out std_logic; + + INT_REPLY_DATAREADY_OUT: out std_logic; + INT_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_REPLY_READ_IN: in std_logic; + + INT_REPLY_DATAREADY_IN: in std_logic; + INT_REPLY_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_REPLY_PACKET_NUM_IN :in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_REPLY_READ_OUT: out std_logic; + + -- Status and control port + STAT_GEN: out std_logic_vector (31 downto 0); + STAT_IBUF_BUFFER: out std_logic_vector (31 downto 0); + CTRL_GEN: in std_logic_vector (31 downto 0); + STAT_CTRL_IBUF_BUFFER: in std_logic_vector (31 downto 0) + ); + end component; + + component trb_net16_api_base is + generic ( + API_TYPE : integer range 0 to 1 := c_API_ACTIVE; + FIFO_TO_INT_DEPTH : integer range 1 to 6 := 1;--std_FIFO_DEPTH; + FIFO_TO_APL_DEPTH : integer range 1 to 6 := 1;--std_FIFO_DEPTH; + FORCE_REPLY : integer range 0 to 1 := std_FORCE_REPLY; + SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; + USE_VENDOR_CORES : integer range 0 to 1 := c_YES; + SECURE_MODE_TO_APL: integer range 0 to 1 := c_YES; + SECURE_MODE_TO_INT: integer range 0 to 1 := c_YES; + APL_WRITE_4_PACKETS:integer range 0 to 1 := c_NO + ); + + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + -- APL Transmitter port + APL_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "application to network" + APL_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); + APL_DATAREADY_IN: in std_logic; -- Data word is valid and should be transmitted + APL_READ_OUT: out std_logic; -- Stop transfer, the fifo is full + APL_SHORT_TRANSFER_IN: in std_logic; -- + APL_DTYPE_IN: in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr + APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr + APL_SEND_IN: in std_logic; -- Release sending of the data + APL_TARGET_ADDRESS_IN: in std_logic_vector (15 downto 0); -- Address of + -- the target (only for active APIs) + + -- Receiver port + APL_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "network to application" + APL_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); + APL_TYP_OUT: out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM + APL_DATAREADY_OUT: out std_logic; -- Data word is valid and might be read out + APL_READ_IN: in std_logic; -- Read data word + + -- APL Control port + APL_RUN_OUT: out std_logic; -- Data transfer is running + APL_MY_ADDRESS_IN: in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!) + APL_SEQNR_OUT: out std_logic_vector (7 downto 0); + + -- Internal direction port + -- This is just a clone from trb_net_iobuf + + INT_MASTER_DATAREADY_OUT: out std_logic; + INT_MASTER_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_MASTER_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_MASTER_READ_IN: in std_logic; + + INT_MASTER_DATAREADY_IN: in std_logic; + INT_MASTER_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_MASTER_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_MASTER_READ_OUT: out std_logic; + + + INT_SLAVE_HEADER_IN: in std_logic; -- Concentrator kindly asks to resend the last + -- header (only for the SLAVE path) + INT_SLAVE_DATAREADY_OUT: out std_logic; + INT_SLAVE_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_SLAVE_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_SLAVE_READ_IN: in std_logic; + + INT_SLAVE_DATAREADY_IN: in std_logic; + INT_SLAVE_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_SLAVE_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_SLAVE_READ_OUT: out std_logic; + + -- Status and control port + STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0); + STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0) + ); + end component; + + + + component trb_net16_io_multiplexer is + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + -- Media direction port + MED_DATAREADY_IN: in STD_LOGIC; + MED_DATA_IN: in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN: in STD_LOGIC_VECTOR (1 downto 0); + MED_READ_OUT: out STD_LOGIC; + + MED_DATAREADY_OUT: out STD_LOGIC; + MED_DATA_OUT: out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (1 downto 0); + MED_READ_IN: in STD_LOGIC; + + -- Internal direction port + INT_DATA_OUT: out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + INT_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); + INT_DATAREADY_OUT: out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); + INT_READ_IN: in STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); + + INT_DATAREADY_IN: in STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); + INT_DATA_IN: in STD_LOGIC_VECTOR ((c_DATA_WIDTH)*(2**c_MUX_WIDTH)-1 downto 0); + INT_PACKET_NUM_IN: in STD_LOGIC_VECTOR (2*(2**c_MUX_WIDTH)-1 downto 0); + INT_READ_OUT: out STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); + + -- Status and control port + CTRL: in STD_LOGIC_VECTOR (31 downto 0); + STAT: out STD_LOGIC_VECTOR (31 downto 0) + ); + end component; + + component trb_net16_term_buf is + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + MED_INIT_DATAREADY_OUT: out std_logic; + MED_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_INIT_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_INIT_READ_IN: in std_logic; + + MED_REPLY_DATAREADY_OUT: out std_logic; + MED_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_REPLY_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_REPLY_READ_IN: in std_logic; + + MED_DATAREADY_IN: in std_logic; + MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT: out std_logic + ); + end component; + component trb_net16_term is + generic ( + USE_APL_PORT : integer range 0 to 1 := 0; + SECURE_MODE : integer range 0 to 1 := std_TERM_SECURE_MODE + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + INT_DATAREADY_OUT: out std_logic; + INT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_READ_IN: in std_logic; + + INT_DATAREADY_IN: in std_logic; + INT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_READ_OUT: out std_logic; + + -- "mini" APL, just to see the triggers coming in + APL_DTYPE_OUT: out std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr + APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr + APL_SEQNR_OUT: out std_logic_vector (7 downto 0); + APL_GOT_TRM: out std_logic; + APL_RELEASE_TRM: in std_logic; + APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0) -- see NewTriggerBusNetworkDescr + -- Status and control port + ); + end component; +signal apl_to_buf_INIT_DATAREADY: std_logic_vector(3 downto 0); +signal apl_to_buf_INIT_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0); +signal apl_to_buf_INIT_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0); +signal apl_to_buf_INIT_READ : std_logic_vector(3 downto 0); + +signal buf_to_apl_INIT_DATAREADY: std_logic_vector(3 downto 0); +signal buf_to_apl_INIT_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0); +signal buf_to_apl_INIT_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0); +signal buf_to_apl_INIT_READ : std_logic_vector(3 downto 0); + +signal apl_to_buf_REPLY_DATAREADY: std_logic_vector(3 downto 0); +signal apl_to_buf_REPLY_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0); +signal apl_to_buf_REPLY_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0); +signal apl_to_buf_REPLY_READ : std_logic_vector(3 downto 0); + +signal buf_to_apl_REPLY_DATAREADY: std_logic_vector(3 downto 0); +signal buf_to_apl_REPLY_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0); +signal buf_to_apl_REPLY_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0); +signal buf_to_apl_REPLY_READ : std_logic_vector(3 downto 0); + +-- for the connection to the multiplexer +signal MED_IO_DATAREADY_IN : std_logic_vector(3 downto 0); +signal MED_IO_DATA_IN : std_logic_vector (c_DATA_WIDTH-1 downto 0); +signal MED_IO_PACKET_NUM_IN : std_logic_vector (c_NUM_WIDTH-1 downto 0); +signal MED_IO_READ_OUT : std_logic_vector(3 downto 0); + +signal MED_IO_DATAREADY_OUT : std_logic_vector(7 downto 0); +signal MED_IO_DATA_OUT : std_logic_vector (8*c_DATA_WIDTH-1 downto 0); +signal MED_IO_PACKET_NUM_OUT : std_logic_vector (8*c_NUM_WIDTH-1 downto 0); +signal MED_IO_READ_IN : std_logic_vector(7 downto 0); + +signal buf_APL_DATA_IN : std_logic_vector(3*c_DATA_WIDTH-1 downto 0); +signal buf_APL_PACKET_NUM_IN : std_logic_vector(3*c_NUM_WIDTH-1 downto 0); +signal buf_APL_DATAREADY_IN : std_logic_vector(2 downto 0); +signal buf_APL_READ_OUT : std_logic_vector(2 downto 0); +signal buf_APL_SHORT_TRANSFER_IN : std_logic_vector(2 downto 0); +signal buf_APL_DTYPE_IN : std_logic_vector(3*4-1 downto 0); +signal buf_APL_ERROR_PATTERN_IN : std_logic_vector(3*32-1 downto 0); +signal buf_APL_SEND_IN : std_logic_vector(2 downto 0); +signal buf_APL_TARGET_ADDRESS_IN : std_logic_vector(3*16-1 downto 0); +signal buf_APL_DATA_OUT : std_logic_vector(3*c_DATA_WIDTH-1 downto 0); +signal buf_APL_PACKET_NUM_OUT : std_logic_vector(3*c_NUM_WIDTH-1 downto 0); +signal buf_APL_DATAREADY_OUT : std_logic_vector(2 downto 0); +signal buf_APL_READ_IN : std_logic_vector(2 downto 0); +signal buf_APL_TYP_OUT : std_logic_vector(3*3-1 downto 0); +signal buf_APL_RUN_OUT : std_logic_vector(2 downto 0); +signal buf_APL_SEQNR_OUT : std_logic_vector(3*8-1 downto 0); + +signal MY_ADDRESS : std_logic_vector(15 downto 0); + +signal buf_api_stat_fifo_to_apl, buf_api_stat_fifo_to_int : std_logic_vector (4*32-1 downto 0); +signal buf_STAT_GEN : std_logic_vector(32*4-1 downto 0); +signal buf_STAT_INIT_BUFFER : std_logic_vector(32*4-1 downto 0); +signal buf_CTRL_GEN : std_logic_vector(32*4-1 downto 0); +signal buf_STAT_CTRL_INIT_BUFFER : std_logic_vector(32*4-1 downto 0); +signal SCTR_REGIO_STAT : std_logic_vector(31 downto 0); + +signal buf_COMMON_STAT_REG_IN: std_logic_vector(std_COMSTATREG*32-1 downto 0); + +signal buf_IDRAM_DATA_IN : std_logic_vector(15 downto 0); +signal buf_IDRAM_DATA_OUT : std_logic_vector(15 downto 0); +signal buf_IDRAM_ADDR_IN : std_logic_vector(2 downto 0); +signal buf_IDRAM_WR_IN : std_logic; + +begin + + MED_CTRL_OP(15) <= MED_STAT_OP(15); + MED_CTRL_OP(14 downto 0) <= (others => '0'); + + --Connections for data channel + genbuffers : for i in 0 to 3 generate + geniobuf: if USE_CHANNEL(i) = c_YES generate + IOBUF: trb_net16_iobuf + generic map ( + IBUF_DEPTH => IBUF_DEPTH(i), + IBUF_SECURE_MODE => IBUF_SECURE_MODE(i), + SBUF_VERSION => 0, + USE_ACKNOWLEDGE => cfg_USE_ACKNOWLEDGE(i), + USE_VENDOR_CORES => c_YES, + USE_CHECKSUM => cfg_USE_CHECKSUM(i), + INIT_CAN_SEND_DATA => INIT_CAN_SEND_DATA(i), + REPLY_CAN_SEND_DATA => REPLY_CAN_SEND_DATA(i) + ) + port map ( + -- Misc + CLK => CLK , + RESET => RESET, + CLK_EN => CLK_EN, + -- Media direction port + MED_INIT_DATAREADY_OUT => MED_IO_DATAREADY_OUT(i*2), + MED_INIT_DATA_OUT => MED_IO_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*2*c_DATA_WIDTH), + MED_INIT_PACKET_NUM_OUT => MED_IO_PACKET_NUM_OUT((i*2+1)*c_NUM_WIDTH-1 downto i*2*c_NUM_WIDTH), + MED_INIT_READ_IN => MED_IO_READ_IN(i*2), + + MED_DATAREADY_IN => MED_IO_DATAREADY_IN(i), + MED_DATA_IN => MED_IO_DATA_IN, + MED_PACKET_NUM_IN => MED_IO_PACKET_NUM_IN, + MED_READ_OUT => MED_IO_READ_OUT(i), + MED_ERROR_IN => MED_ERROR_IN, + + MED_REPLY_DATAREADY_OUT => MED_IO_DATAREADY_OUT(i*2+1), + MED_REPLY_DATA_OUT => MED_IO_DATA_OUT((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH), + MED_REPLY_PACKET_NUM_OUT=> MED_IO_PACKET_NUM_OUT((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH), + MED_REPLY_READ_IN => MED_IO_READ_IN(i*2+1), + + -- Internal direction port + + INT_INIT_DATAREADY_OUT => buf_to_apl_INIT_DATAREADY(i), + INT_INIT_DATA_OUT => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_INIT_PACKET_NUM_OUT=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_INIT_READ_IN => buf_to_apl_INIT_READ(i), + + INT_INIT_DATAREADY_IN => apl_to_buf_INIT_DATAREADY(i), + INT_INIT_DATA_IN => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_INIT_PACKET_NUM_IN => apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_INIT_READ_OUT => apl_to_buf_INIT_READ(i), + + INT_REPLY_DATAREADY_OUT => buf_to_apl_REPLY_DATAREADY(i), + INT_REPLY_DATA_OUT => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_REPLY_READ_IN => buf_to_apl_REPLY_READ(i), + + INT_REPLY_DATAREADY_IN => apl_to_buf_REPLY_DATAREADY(i), + INT_REPLY_DATA_IN => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_REPLY_PACKET_NUM_IN => apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_REPLY_READ_OUT => apl_to_buf_REPLY_READ(i), + + -- Status and control port + STAT_GEN => buf_STAT_GEN(32*(i+1)-1 downto i*32), + STAT_IBUF_BUFFER => buf_STAT_INIT_BUFFER(32*(i+1)-1 downto i*32), + CTRL_GEN => buf_CTRL_GEN(32*(i+1)-1 downto i*32), + STAT_CTRL_IBUF_BUFFER => buf_STAT_CTRL_INIT_BUFFER(32*(i+1)-1 downto i*32) + ); + genactapi : if API_TYPE(i) = c_API_ACTIVE and i /= 0 generate + DAT_ACTIVE_API: trb_net16_api_base + generic map ( + API_TYPE => API_TYPE(i), + FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH(i), + FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH(i), + FORCE_REPLY => cfg_FORCE_REPLY(i), + SBUF_VERSION => 0 + ) + port map ( + -- Misc + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + -- APL Transmitter port + APL_DATA_IN => buf_APL_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + APL_PACKET_NUM_IN => buf_APL_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + APL_DATAREADY_IN => buf_APL_DATAREADY_IN(i), + APL_READ_OUT => buf_APL_READ_OUT(i), + APL_SHORT_TRANSFER_IN => buf_APL_SHORT_TRANSFER_IN(i), + APL_DTYPE_IN => buf_APL_DTYPE_IN((i+1)*4-1 downto i*4), + APL_ERROR_PATTERN_IN => buf_APL_ERROR_PATTERN_IN((i+1)*32-1 downto i*32), + APL_SEND_IN => buf_APL_SEND_IN(i), + APL_TARGET_ADDRESS_IN => buf_APL_TARGET_ADDRESS_IN((i+1)*16-1 downto i*16), + -- Receiver port + APL_DATA_OUT => buf_APL_DATA_OUT((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + APL_PACKET_NUM_OUT=> buf_APL_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + APL_TYP_OUT => buf_APL_TYP_OUT((i+1)*3-1 downto i*3), + APL_DATAREADY_OUT => buf_APL_DATAREADY_OUT(i), + APL_READ_IN => buf_APL_READ_IN(i), + -- APL Control port + APL_RUN_OUT => buf_APL_RUN_OUT(i), + APL_MY_ADDRESS_IN => MY_ADDRESS, + APL_SEQNR_OUT => buf_APL_SEQNR_OUT((i+1)*8-1 downto i*8), + -- Internal direction port + INT_MASTER_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY(i), + INT_MASTER_DATA_OUT => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_MASTER_READ_IN => apl_to_buf_INIT_READ(i), + INT_MASTER_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i), + INT_MASTER_DATA_IN => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_MASTER_PACKET_NUM_IN => buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_MASTER_READ_OUT => buf_to_apl_INIT_READ(i), + INT_SLAVE_HEADER_IN => '0', + INT_SLAVE_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY(i), + INT_SLAVE_DATA_OUT => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_SLAVE_READ_IN => apl_to_buf_REPLY_READ(i), + INT_SLAVE_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY(i), + INT_SLAVE_DATA_IN => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_SLAVE_READ_OUT => buf_to_apl_REPLY_READ(i), + -- Status and control port + STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int((i+1)*32-1 downto i*32), + STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl((i+1)*32-1 downto i*32) + ); + end generate; + genpasapi : if API_TYPE(i) = c_API_PASSIVE and i /= 0 generate + constant j : integer := i-1; + begin + DAT_PASSIVE_API: trb_net16_api_base + generic map ( + API_TYPE => API_TYPE(i), + FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH(i), + FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH(i), + FORCE_REPLY => cfg_FORCE_REPLY(i), + SBUF_VERSION => 0 + ) + port map ( + -- Misc + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + -- APL Transmitter port + APL_DATA_IN => buf_APL_DATA_IN((j+1)*c_DATA_WIDTH-1 downto j*c_DATA_WIDTH), + APL_PACKET_NUM_IN => buf_APL_PACKET_NUM_IN((j+1)*c_NUM_WIDTH-1 downto j*c_NUM_WIDTH), + APL_DATAREADY_IN => buf_APL_DATAREADY_IN(j), + APL_READ_OUT => buf_APL_READ_OUT(j), + APL_SHORT_TRANSFER_IN => buf_APL_SHORT_TRANSFER_IN(j), + APL_DTYPE_IN => buf_APL_DTYPE_IN((j+1)*4-1 downto j*4), + APL_ERROR_PATTERN_IN => buf_APL_ERROR_PATTERN_IN((j+1)*32-1 downto j*32), + APL_SEND_IN => buf_APL_SEND_IN(j), + APL_TARGET_ADDRESS_IN => buf_APL_TARGET_ADDRESS_IN((j+1)*16-1 downto j*16), + -- Receiver port + APL_DATA_OUT => buf_APL_DATA_OUT((j+1)*c_DATA_WIDTH-1 downto j*c_DATA_WIDTH), + APL_PACKET_NUM_OUT=> buf_APL_PACKET_NUM_OUT((j+1)*c_NUM_WIDTH-1 downto j*c_NUM_WIDTH), + APL_TYP_OUT => buf_APL_TYP_OUT((j+1)*3-1 downto j*3), + APL_DATAREADY_OUT => buf_APL_DATAREADY_OUT(j), + APL_READ_IN => buf_APL_READ_IN(j), + -- APL Control port + APL_RUN_OUT => buf_APL_RUN_OUT(j), + APL_MY_ADDRESS_IN => MY_ADDRESS, + APL_SEQNR_OUT => buf_APL_SEQNR_OUT((j+1)*8-1 downto j*8), + -- Internal direction port + INT_MASTER_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY(i), + INT_MASTER_DATA_OUT => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_MASTER_READ_IN => apl_to_buf_REPLY_READ(i), + INT_MASTER_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY(i), + INT_MASTER_DATA_IN => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_MASTER_PACKET_NUM_IN => buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_MASTER_READ_OUT => buf_to_apl_REPLY_READ(i), + INT_SLAVE_HEADER_IN => '0', + INT_SLAVE_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY(i), + INT_SLAVE_DATA_OUT => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_SLAVE_READ_IN => apl_to_buf_INIT_READ(i), + INT_SLAVE_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i), + INT_SLAVE_DATA_IN => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_SLAVE_READ_OUT => buf_to_apl_INIT_READ(i), + -- Status and control port + STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int((i+1)*32-1 downto i*32), + STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl((i+1)*32-1 downto i*32) + ); + end generate; + gentrgapi : if i = 0 generate + apl_to_buf_INIT_DATAREADY(0) <= '0'; + apl_to_buf_INIT_DATA(15 downto 0) <= (others => '0'); + apl_to_buf_INIT_PACKET_NUM(1 downto 0) <= "00"; + buf_to_apl_REPLY_READ(0) <= '1'; + trglvl1 : trb_net16_term + generic map( + USE_APL_PORT => c_YES, + SECURE_MODE => std_TERM_SECURE_MODE + ) + port map( + -- Misc + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + + INT_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY(i), + INT_DATA_OUT => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_PACKET_NUM_OUT=> apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_READ_IN => apl_to_buf_REPLY_READ(i), + + INT_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i), + INT_DATA_IN => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_PACKET_NUM_IN=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_READ_OUT => buf_to_apl_INIT_READ(i), + + -- "mini" APL, just to see the triggers coming in + APL_DTYPE_OUT => LVL1_DTYPE_OUT, + APL_ERROR_PATTERN_OUT => LVL1_ERROR_PATTERN_OUT, + APL_SEQNR_OUT => LVL1_SEQNR_OUT, + APL_GOT_TRM => LVL1_GOT_TRIGGER_OUT, + APL_RELEASE_TRM => LVL1_RELEASE_IN, + APL_ERROR_PATTERN_IN => LVL1_ERROR_PATTERN_IN + ); + end generate; + end generate; + gentermbuf: if USE_CHANNEL(i) = c_NO generate + termbuf: trb_net16_term_buf + port map( + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + MED_DATAREADY_IN => MED_IO_DATAREADY_IN(i), + MED_DATA_IN => MED_IO_DATA_IN, + MED_PACKET_NUM_IN => MED_IO_PACKET_NUM_IN, + MED_READ_OUT => MED_IO_READ_OUT(i), + + MED_INIT_DATAREADY_OUT => MED_IO_DATAREADY_OUT(i*2), + MED_INIT_DATA_OUT => MED_IO_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*2*c_DATA_WIDTH), + MED_INIT_PACKET_NUM_OUT => MED_IO_PACKET_NUM_OUT((i*2+1)*c_NUM_WIDTH-1 downto i*2*c_NUM_WIDTH), + MED_INIT_READ_IN => MED_IO_READ_IN(i*2), + MED_REPLY_DATAREADY_OUT => MED_IO_DATAREADY_OUT(i*2+1), + MED_REPLY_DATA_OUT => MED_IO_DATA_OUT((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH), + MED_REPLY_PACKET_NUM_OUT=> MED_IO_PACKET_NUM_OUT((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH), + MED_REPLY_READ_IN => MED_IO_READ_IN(i*2+1) + ); + end generate; + end generate; + + + buf_APL_DATA_IN(1*c_DATA_WIDTH-1 downto 0*c_DATA_WIDTH) <= IPUD_APL_DATA_IN; + buf_APL_DATA_IN(2*c_DATA_WIDTH-1 downto 1*c_DATA_WIDTH) <= LVL2_APL_DATA_IN; + buf_APL_PACKET_NUM_IN(1*c_NUM_WIDTH-1 downto 0*c_NUM_WIDTH) <= IPUD_APL_PACKET_NUM_IN; + buf_APL_PACKET_NUM_IN(2*c_NUM_WIDTH-1 downto 1*c_NUM_WIDTH) <= LVL2_APL_PACKET_NUM_IN; + buf_APL_DATAREADY_IN(0) <= IPUD_APL_DATAREADY_IN; + buf_APL_DATAREADY_IN(1) <= LVL2_APL_DATAREADY_IN; + IPUD_APL_READ_OUT <= buf_APL_READ_OUT(0); + LVL2_APL_READ_OUT <= buf_APL_READ_OUT(1); + buf_APL_SHORT_TRANSFER_IN(0) <= IPUD_APL_SHORT_TRANSFER_IN; + buf_APL_SHORT_TRANSFER_IN(1) <= LVL2_APL_SHORT_TRANSFER_IN; + buf_APL_DTYPE_IN(1*4-1 downto 0*4) <= IPUD_APL_DTYPE_IN; + buf_APL_DTYPE_IN(2*4-1 downto 1*4) <= LVL2_APL_DTYPE_IN; + buf_APL_ERROR_PATTERN_IN(1*32-1 downto 0*32) <= IPUD_APL_ERROR_PATTERN_IN; + buf_APL_ERROR_PATTERN_IN(2*32-1 downto 1*32) <= LVL2_APL_ERROR_PATTERN_IN; + buf_APL_SEND_IN(0) <= IPUD_APL_SEND_IN; + buf_APL_SEND_IN(1) <= LVL2_APL_SEND_IN; + buf_APL_TARGET_ADDRESS_IN(1*16-1 downto 0*16) <= IPUD_APL_TARGET_ADDRESS_IN; + buf_APL_TARGET_ADDRESS_IN(2*16-1 downto 1*16) <= LVL2_APL_TARGET_ADDRESS_IN; + + IPUD_APL_DATA_OUT <= buf_APL_DATA_OUT(1*c_DATA_WIDTH-1 downto 0*c_DATA_WIDTH); + LVL2_APL_DATA_OUT <= buf_APL_DATA_OUT(2*c_DATA_WIDTH-1 downto 1*c_DATA_WIDTH); + IPUD_APL_PACKET_NUM_OUT <= buf_APL_DATA_OUT(1*c_NUM_WIDTH-1 downto 0*c_NUM_WIDTH); + LVL2_APL_PACKET_NUM_OUT <= buf_APL_DATA_OUT(2*c_NUM_WIDTH-1 downto 1*c_NUM_WIDTH); + IPUD_APL_DATAREADY_OUT <= buf_APL_DATAREADY_OUT(0); + LVL2_APL_DATAREADY_OUT <= buf_APL_DATAREADY_OUT(1); + buf_APL_READ_IN(0) <= IPUD_APL_READ_IN; + buf_APL_READ_IN(1) <= LVL2_APL_READ_IN; + IPUD_APL_TYP_OUT <= buf_APL_TYP_OUT(2 downto 0); + LVL2_APL_TYP_OUT <= buf_APL_TYP_OUT(5 downto 3); + + buf_APL_DTYPE_IN(1*4-1 downto 0*4) <= IPUD_APL_DTYPE_IN; + buf_APL_DTYPE_IN(2*4-1 downto 1*4) <= LVL2_APL_DTYPE_IN; + IPUD_APL_RUN_OUT <= buf_APL_RUN_OUT(0); + LVL2_APL_RUN_OUT <= buf_APL_RUN_OUT(1); + IPUD_APL_SEQNR_OUT <= buf_APL_SEQNR_OUT(1*8-1 downto 0*8); + LVL2_APL_SEQNR_OUT <= buf_APL_SEQNR_OUT(2*8-1 downto 1*8); + + gen_regio : if USE_CHANNEL(c_SLOW_CTRL_CHANNEL) = c_YES generate + regIO : trb_net16_regIO + generic map( + REGISTER_WIDTH => 32, + ADDRESS_WIDTH => 16, + NUM_STAT_REGS => SCTR_NUM_STAT_REGS, + NUM_CTRL_REGS => SCTR_NUM_CTRL_REGS, + --standard values for output registers + INIT_CTRL_REGS => SCTR_INIT_CTRL_REGS, + --set to 0 for unused ctrl registers to save resources + USED_CTRL_REGS => SCTR_USED_CTRL_REGS, + --set to 0 for each unused bit in a register + USED_CTRL_BITMASK => SCTR_USED_CTRL_BITMASK, + --no data / address out? + USE_DAT_PORT => SCTR_USE_DATA_PORT, + INIT_ADDRESS => SCTR_INIT_ADDRESS, + INIT_UNIQUE_ID => SCTR_INIT_UNIQUE_ID, + COMPILE_TIME => SCTR_COMPILE_TIME, + COMPILE_VERSION => SCTR_COMPILE_VERSION, + HARDWARE_VERSION => SCTR_HARDWARE_VERSION + ) + port map( + -- Misc + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + -- Port to API + API_DATA_OUT => buf_APL_DATA_IN(3*c_DATA_WIDTH-1 downto 2*c_DATA_WIDTH), + API_PACKET_NUM_OUT => buf_APL_PACKET_NUM_IN(3*c_NUM_WIDTH-1 downto 2*c_NUM_WIDTH), + API_DATAREADY_OUT => buf_APL_DATAREADY_IN(2), + API_READ_IN => buf_APL_READ_OUT(2), + API_SHORT_TRANSFER_OUT => buf_APL_SHORT_TRANSFER_IN(2), + API_DTYPE_OUT => buf_APL_DTYPE_IN(3*4-1 downto 2*4), + API_ERROR_PATTERN_OUT => buf_APL_ERROR_PATTERN_IN(3*32-1 downto 2*32), + API_SEND_OUT => buf_APL_SEND_IN(2), + API_TARGET_ADDRESS_OUT => buf_APL_TARGET_ADDRESS_IN(3*16-1 downto 2*16), + API_DATA_IN => buf_APL_DATA_OUT(3*c_DATA_WIDTH-1 downto 2*c_DATA_WIDTH), + API_PACKET_NUM_IN => buf_APL_PACKET_NUM_OUT(3*c_NUM_WIDTH-1 downto 2*c_NUM_WIDTH), + API_TYP_IN => buf_APL_TYP_OUT(3*3-1 downto 2*3), + API_DATAREADY_IN => buf_APL_DATAREADY_OUT(2), + API_READ_OUT => buf_APL_READ_IN(2), + API_RUN_IN => buf_APL_RUN_OUT(2), + API_SEQNR_IN => buf_APL_SEQNR_OUT(3*8-1 downto 2*8), + --Port to write Unique ID + IDRAM_DATA_IN => buf_IDRAM_DATA_IN, + IDRAM_DATA_OUT => buf_IDRAM_DATA_OUT, + IDRAM_ADDR_IN => buf_IDRAM_ADDR_IN, + IDRAM_WR_IN => buf_IDRAM_WR_IN, + MY_ADDRESS_OUT => MY_ADDRESS, + --Common Register in / out + COMMON_STAT_REG_IN => buf_COMMON_STAT_REG_IN, + COMMON_CTRL_REG_OUT => SCTR_COMMON_CTRL_REG_OUT, + --Custom Register in / out + REGISTERS_IN => SCTR_REGISTERS_IN, + REGISTERS_OUT => SCTR_REGISTERS_OUT, + --following ports only used when no internal register is accessed + DAT_ADDR_OUT => SCTR_ADDR_OUT, + DAT_READ_ENABLE_OUT => SCTR_READ_ENABLE_OUT, + DAT_WRITE_ENABLE_OUT => SCTR_WRITE_ENABLE_OUT, + DAT_DATA_OUT => SCTR_DATA_OUT, + DAT_DATA_IN => SCTR_DATA_IN, + DAT_DATAREADY_IN => SCTR_DATAREADY_IN, + DAT_NO_MORE_DATA_IN => SCTR_NO_MORE_DATA_IN, + EXT_REG_DATA_IN => SCTR_EXT_REG_DATA_IN, + EXT_REG_DATA_OUT => SCTR_EXT_REG_DATA_OUT, + EXT_REG_WRITE_IN => SCTR_EXT_REG_WRITE_IN, + EXT_REG_ADDR_IN => SCTR_EXT_REG_ADDR_IN, + STAT => SCTR_REGIO_STAT + ); + end generate; + + gen_no1wire : if SCTR_USE_1WIRE_INTERFACE = 0 generate + buf_IDRAM_DATA_IN <= SCTR_IDRAM_DATA_IN; + buf_IDRAM_ADDR_IN <= SCTR_IDRAM_ADDR_IN; + buf_IDRAM_WR_IN <= SCTR_IDRAM_WR_IN; + SCTR_IDRAM_DATA_OUT <= buf_IDRAM_DATA_OUT; + SCTR_ONEWIRE_INOUT <= '0'; + buf_COMMON_STAT_REG_IN <= SCTR_COMMON_STAT_REG_IN; + end generate; + gen_1wire : if SCTR_USE_1WIRE_INTERFACE = 1 generate + buf_COMMON_STAT_REG_IN(19 downto 0) <= SCTR_COMMON_STAT_REG_IN(19 downto 0); + buf_COMMON_STAT_REG_IN(SCTR_COMMON_STAT_REG_IN'left downto 32) <= SCTR_COMMON_STAT_REG_IN(SCTR_COMMON_STAT_REG_IN'left downto 32); + + SCTR_IDRAM_DATA_OUT <= (others => '0'); + + onewire_interface : trb_net_onewire + generic map( + USE_TEMPERATURE_READOUT => c_YES, + CLK_PERIOD => 10 + ) + port map( + CLK => CLK, + RESET => RESET, + --connection to 1-wire interface + ONEWIRE => SCTR_ONEWIRE_INOUT, + --connection to id ram, according to memory map in TrbNetRegIO + DATA_OUT => buf_IDRAM_DATA_IN, + ADDR_OUT => buf_IDRAM_ADDR_IN, + WRITE_OUT=> buf_IDRAM_WR_IN, + TEMP_OUT => buf_COMMON_STAT_REG_IN(31 downto 20), + STAT => open + ); + end generate; + + + MPLEX: trb_net16_io_multiplexer + port map ( + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + MED_DATAREADY_IN => MED_DATAREADY_IN, + MED_DATA_IN => MED_DATA_IN, + MED_PACKET_NUM_IN => MED_PACKET_NUM_IN, + MED_READ_OUT => MED_READ_OUT, + MED_DATAREADY_OUT => MED_DATAREADY_OUT, + MED_DATA_OUT => MED_DATA_OUT, + MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT, + MED_READ_IN => MED_READ_IN, + INT_DATAREADY_OUT => MED_IO_DATAREADY_IN, + INT_DATA_OUT => MED_IO_DATA_IN, + INT_PACKET_NUM_OUT => MED_IO_PACKET_NUM_IN, + INT_READ_IN => MED_IO_READ_OUT, + INT_DATAREADY_IN => MED_IO_DATAREADY_OUT, + INT_DATA_IN => MED_IO_DATA_OUT, + INT_PACKET_NUM_IN => MED_IO_PACKET_NUM_OUT, + INT_READ_OUT => MED_IO_READ_IN, + CTRL => MPLEX_CTRL + ); + + +buf_STAT_CTRL_INIT_BUFFER <= STAT_CTRL_INIT_BUFFER; +buf_CTRL_GEN <= CTRL_GEN; +STAT_GEN_1 <= (others => '0'); +STAT_GEN_2 <= (others => '0'); + +end architecture; + diff --git a/testbench/wide_adder_testbench.vhd b/testbench/wide_adder_testbench.vhd index 00ff5e8..a062447 100644 --- a/testbench/wide_adder_testbench.vhd +++ b/testbench/wide_adder_testbench.vhd @@ -15,8 +15,9 @@ architecture test_arch of testbench is component wide_adder is generic( WIDTH : integer := 16; - WORDS : integer := 16; - PARALLEL_ADDERS : integer := 2 --2^n + WORDS : integer := 18; + PARALLEL_ADDERS : integer := 3; + PSEUDO_WORDS : integer := 16 --the smallest multiple of PARALLEL_ADDERS, greater or equal than WORDS ); port( CLK : in std_logic; @@ -31,6 +32,25 @@ architecture test_arch of testbench is ); end component; + +component wide_adder_17x16 is + generic( + SIZE : integer := 16; + WORDS: integer := 17 --fixed + ); + port( + CLK : in std_logic; + CLK_EN : in std_logic; + RESET : in std_logic; + INPUT_IN : in std_logic_vector(SIZE*WORDS-1 downto 0); + START_IN : in std_logic; + VAL_ENABLE_IN: in std_logic_vector(WORDS-1 downto 0); + RESULT_OUT : out std_logic_vector(SIZE-1 downto 0); + OVERFLOW_OUT : out std_logic; + READY_OUT : out std_logic + ); +end component; + signal CLK : std_logic := '1'; signal CLK_EN : std_logic := '1'; signal RESET : std_logic := '1'; @@ -39,22 +59,24 @@ signal start : std_logic := '0'; signal overflow : std_logic := '0'; signal ready : std_logic := '0'; signal result : std_logic_vector(15 downto 0); -signal input : std_logic_vector(255 downto 0); -signal enable : std_logic_vector(15 downto 0); +signal input : std_logic_vector(255+16 downto 0); +signal enable : std_logic_vector(16 downto 0); begin RESET <= '0' after 100 ns; CLK <= not CLK after 5 ns; -start <= '1' after 145 ns, '0' after 155 ns, '1' after 295 ns, '0' after 305 ns; -input <= x"8000_4000_2000_1000_0800_0400_0200_0100_0010_0020_0040_0080_0001_0002_0004_0001"; -enable <= "0111111111111111"; +start <= '1' after 141 ns, '0' after 151 ns, '1' after 291 ns, '0' after 301 ns; +input <= x"0001_0800_4000_2000_1000_8000_0400_0200_0100_0010_0020_0040_0080_0001_0002_0004_0001"; +enable <= "10111111111111111"; - the_adder : wide_adder + the_adder : wide_adder_17x16 generic map( - WIDTH => 16, - WORDS => 16, - PARALLEL_ADDERS => 2 + SIZE => 16 +-- WIDTH => 16, +-- WORDS => 16, +-- PARALLEL_ADDERS => 4, +-- PSEUDO_WORDS => 16 ) port map( CLK => CLK, diff --git a/testbenches/testbench_hublogic_ipudata.prj b/testbenches/testbench_hublogic_ipudata.prj new file mode 100644 index 0000000..b4f47ca --- /dev/null +++ b/testbenches/testbench_hublogic_ipudata.prj @@ -0,0 +1,35 @@ +vhdl work "../trb_net_std.vhd" +vhdl work "../trb_net16_term_buf.vhd" +vhdl work "../xilinx/shift_lut_x16.vhd" +vhdl work "../xilinx/xilinx_fifo_lut.vhd" +vhdl work "../xilinx/virtex2/simulation/xilinx_fifo_18x1k.vhd" +vhdl work "../xilinx/virtex2/trb_net16_fifo_arch.vhd" +vhdl work "../basics/ram_dp_rw.vhd" +vhdl work "../basics/ram_dp.vhd" +vhdl work "../trb_net16_term.vhd" +-- vhdl work "../trb_net16_term_buf.vhd" +vhdl work "../trb_net_sbuf.vhd" +vhdl work "../trb_net16_sbuf.vhd" +vhdl work "../trb_net_priority_encoder.vhd" +vhdl work "../trb_net_dummy_fifo.vhd" +vhdl work "../trb_net16_dummy_fifo.vhd" +-- vhdl work "../trb_net16_term_ibuf.vhd" +vhdl work "../trb_net_priority_arbiter.vhd" +vhdl work "../trb_net_pattern_gen.vhd" +-- vhdl work "../trb_net16_obuf_nodata.vhd" +-- vhdl work "../trb_net16_obuf.vhd" +-- vhdl work "../trb_net16_ibuf.vhd" +vhdl work "../trb_net16_api_base.vhd" +-- vhdl work "../trb_net16_iobuf.vhd" +-- vhdl work "../trb_net16_io_multiplexer.vhd" +vhdl work "../testbench/trb_net16_dummy_apl.vhd" +vhdl work "../trb_net16_ipudata.vhd" +-- vhdl work "../trb_net16_trigger.vhd" +-- vhdl work "../trb_net16_endpoint_hades_full.vhd" +-- vhdl work "../trb_net16_endpoint_active_4_channel.vhd" +-- vhdl work "../trb_net_med_8bit_slow.vhd" +vhdl work "../trb_net16_hub_func.vhd" +-- vhdl work "../trb_net16_hub_base.vhd" +vhdl work "../basics/wide_adder_17x16.vhd" +vhdl work "../trb_net16_hub_ipu_logic.vhd" +vhdl work "testbench_hublogic_ipudata.vhd" \ No newline at end of file diff --git a/testbenches/testbench_hublogic_ipudata.vhd b/testbenches/testbench_hublogic_ipudata.vhd new file mode 100644 index 0000000..9b291aa --- /dev/null +++ b/testbenches/testbench_hublogic_ipudata.vhd @@ -0,0 +1,558 @@ +LIBRARY ieee; +use ieee.std_logic_1164.all; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net16_hub_func.all; + + +entity testbench is +end entity testbench; + +architecture testbench_arch of testbench is + + constant POINT_NUMBER : integer := 4; + + component trb_net16_hub_ipu_logic is + generic ( + --media interfaces + POINT_NUMBER : integer range 2 to 17 := POINT_NUMBER + ); + port ( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + --Internal interfaces to IOBufs + INIT_DATAREADY_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); + INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); + INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); + INIT_READ_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); + + INIT_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); + INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); + INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); + INIT_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); + + REPLY_DATAREADY_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); + REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); + REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); + REPLY_READ_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); + + REPLY_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); + REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); + REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); + REPLY_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); + + MY_ADDRESS_IN : in std_logic_vector (15 downto 0); + --Status ports + STAT_DEBUG : out std_logic_vector (31 downto 0); + STAT_POINTS_locked : out std_logic_vector (31 downto 0); + STAT_ERRORBITS : out std_logic_vector (31 downto 0); + CTRL : in std_logic_vector (15 downto 0); + CTRL_activepoints : in std_logic_vector (31 downto 0) := (others => '1') + ); + end component; + + component trb_net16_api_base is + generic ( + API_TYPE : integer range 0 to 1 := c_API_PASSIVE; + FIFO_TO_INT_DEPTH : integer range 0 to 6 := 6;--std_FIFO_DEPTH; + FIFO_TO_APL_DEPTH : integer range 1 to 6 := 6;--std_FIFO_DEPTH; + FORCE_REPLY : integer range 0 to 1 := std_FORCE_REPLY; + SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; + USE_VENDOR_CORES : integer range 0 to 1 := c_YES; + SECURE_MODE_TO_APL: integer range 0 to 1 := c_YES; + SECURE_MODE_TO_INT: integer range 0 to 1 := c_YES; + APL_WRITE_ALL_WORDS:integer range 0 to 1 := c_NO; + BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF" + ); + + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + -- APL Transmitter port + APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + APL_DATAREADY_IN : in std_logic; + APL_READ_OUT : out std_logic; + APL_SHORT_TRANSFER_IN : in std_logic; + APL_DTYPE_IN : in std_logic_vector (3 downto 0); + APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); + APL_SEND_IN : in std_logic; + APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0);-- the target (only for active APIs) + + -- Receiver port + APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + APL_TYP_OUT : out std_logic_vector (2 downto 0); + APL_DATAREADY_OUT : out std_logic; + APL_READ_IN : in std_logic; + + -- APL Control port + APL_RUN_OUT : out std_logic; + APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); + APL_SEQNR_OUT : out std_logic_vector (7 downto 0); + APL_LENGTH_IN : in std_logic_vector (15 downto 0); + + -- Internal direction port + -- the ports with master or slave in their name are to be mapped by the active api + -- to the init respectivly the reply path and vice versa in the passive api. + -- lets define: the "master" path is the path that I send data on. + -- master_data_out and slave_data_in are only used in active API for termination + INT_MASTER_DATAREADY_OUT : out std_logic; + INT_MASTER_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_MASTER_READ_IN : in std_logic; + + INT_MASTER_DATAREADY_IN : in std_logic; + INT_MASTER_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_MASTER_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_MASTER_READ_OUT : out std_logic; + + INT_SLAVE_DATAREADY_OUT : out std_logic; + INT_SLAVE_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_SLAVE_READ_IN : in std_logic; + + INT_SLAVE_DATAREADY_IN : in std_logic; + INT_SLAVE_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_SLAVE_READ_OUT : out std_logic; + + -- Status and control port + STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0); + STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0) + ); + end component; + + + component trb_net16_dummy_apl is + generic ( + TARGET_ADDRESS : std_logic_vector (15 downto 0) := x"F001"; + PREFILL_LENGTH : integer := 1; + TRANSFER_LENGTH : integer := 1 -- length of dummy data + -- might not work with transfer_length > api_fifo + -- because of incorrect handling of fifo_full_in! + + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- APL Transmitter port + APL_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); + APL_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); + APL_DATAREADY_OUT : out std_logic; + APL_READ_IN : in std_logic; + APL_SHORT_TRANSFER_OUT: out std_logic; + APL_DTYPE_OUT: out std_logic_vector (3 downto 0); + APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); + APL_SEND_OUT: out std_logic; + APL_TARGET_ADDRESS_OUT: out std_logic_vector (15 downto 0); + -- Receiver port + APL_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); + APL_PACKET_NUM_IN:in std_logic_vector (c_NUM_WIDTH-1 downto 0); + APL_TYP_IN: in std_logic_vector (2 downto 0); + APL_DATAREADY_IN: in std_logic; + APL_READ_OUT: out std_logic; + -- APL Control port + APL_RUN_IN: in std_logic; + APL_SEQNR_IN: in std_logic_vector (7 downto 0) + ); + end component; + + component trb_net16_ipudata is + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Port to API + API_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + API_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + API_DATAREADY_OUT : out std_logic; + API_READ_IN : in std_logic; + API_SHORT_TRANSFER_OUT : out std_logic; + API_DTYPE_OUT : out std_logic_vector (3 downto 0); + API_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); + API_SEND_OUT : out std_logic; + -- Receiver port + API_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + API_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + API_TYP_IN : in std_logic_vector (2 downto 0); + API_DATAREADY_IN : in std_logic; + API_READ_OUT : out std_logic; + -- APL Control port + API_RUN_IN : in std_logic; + API_SEQNR_IN : in std_logic_vector (7 downto 0); + API_LENGTH_OUT : out std_logic_vector (15 downto 0); + + --Information received with request + IPU_NUMBER_OUT : out std_logic_vector (15 downto 0); + IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0); + --start strobe + IPU_START_READOUT_OUT: out std_logic; + --detector data, equipped with DHDR + IPU_DATA_IN : in std_logic_vector (31 downto 0); + IPU_DATAREADY_IN : in std_logic; + --no more data, end transfer, send TRM + IPU_READOUT_FINISHED_IN : in std_logic; + --will be low every second cycle due to 32bit -> 16bit conversion + IPU_READ_OUT : out std_logic; + IPU_LENGTH_IN : in std_logic_vector (15 downto 0); + IPU_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); + + + STAT_DEBUG : out std_logic_vector(31 downto 0) + ); + end component; + + signal CLK : std_logic := '1'; + signal RESET : std_logic := '1'; + signal CLK_EN : std_logic := '1'; + + signal INIT_DATAREADY_IN : std_logic_vector (POINT_NUMBER-1 downto 0); + signal INIT_DATA_IN : std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); + signal INIT_PACKET_NUM_IN : std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); + signal INIT_READ_OUT : std_logic_vector (POINT_NUMBER-1 downto 0); + + signal INIT_DATAREADY_OUT : std_logic_vector (POINT_NUMBER-1 downto 0); + signal INIT_DATA_OUT : std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); + signal INIT_PACKET_NUM_OUT : std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); + signal INIT_READ_IN : std_logic_vector (POINT_NUMBER-1 downto 0); + + signal REPLY_DATAREADY_IN : std_logic_vector (POINT_NUMBER-1 downto 0); + signal REPLY_DATA_IN : std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); + signal REPLY_PACKET_NUM_IN : std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); + signal REPLY_READ_OUT : std_logic_vector (POINT_NUMBER-1 downto 0); + + signal REPLY_DATAREADY_OUT : std_logic_vector (POINT_NUMBER-1 downto 0); + signal REPLY_DATA_OUT : std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); + signal REPLY_PACKET_NUM_OUT : std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); + signal REPLY_READ_IN : std_logic_vector (POINT_NUMBER-1 downto 0); + + + signal APL_DATA_IN : std_logic_vector(POINT_NUMBER*c_DATA_WIDTH-1 downto 0); + signal APL_PACKET_NUM_IN : std_logic_vector(POINT_NUMBER*c_NUM_WIDTH-1 downto 0); + signal APL_DATAREADY_IN : std_logic_vector(POINT_NUMBER-1 downto 0); + signal APL_READ_OUT : std_logic_vector(POINT_NUMBER-1 downto 0); + signal APL_SHORT_TRANSFER_IN : std_logic_vector(POINT_NUMBER-1 downto 0); + signal APL_DTYPE_IN : std_logic_vector(POINT_NUMBER*4-1 downto 0); + signal APL_ERROR_PATTERN_IN : std_logic_vector(POINT_NUMBER*32-1 downto 0); + signal APL_SEND_IN : std_logic_vector(POINT_NUMBER-1 downto 0); + signal APL_TARGET_ADDRESS_IN : std_logic_vector(POINT_NUMBER*c_DATA_WIDTH-1 downto 0); + signal APL_DATA_OUT : std_logic_vector(POINT_NUMBER*c_DATA_WIDTH-1 downto 0); + signal APL_PACKET_NUM_OUT : std_logic_vector(POINT_NUMBER*c_NUM_WIDTH-1 downto 0); + signal APL_TYP_OUT : std_logic_vector(POINT_NUMBER*3-1 downto 0); + signal APL_DATAREADY_OUT : std_logic_vector(POINT_NUMBER-1 downto 0); + signal APL_READ_IN : std_logic_vector(POINT_NUMBER-1 downto 0); + signal APL_RUN_OUT : std_logic_vector(POINT_NUMBER-1 downto 0); + signal APL_SEQNR_OUT : std_logic_vector(POINT_NUMBER*8-1 downto 0); + signal APL_LENGTH_IN : std_logic_vector(POINT_NUMBER*16-1 downto 0); + signal APL_MY_ADDRESS_IN : std_logic_vector(POINT_NUMBER*16-1 downto 0); + + signal IPU_NUMBER_OUT : std_logic_vector(4*16-1 downto 16); + signal IPU_INFORMATION_OUT : std_logic_vector(4*8-1 downto 8); + signal IPU_START_READOUT_OUT : std_logic_vector(4-1 downto 1); + signal IPU_DATA_IN : std_logic_vector(4*32-1 downto 32); + signal IPU_DATAREADY_IN : std_logic_vector(4*1-1 downto 1); + signal IPU_READOUT_FINISHED_IN : std_logic_vector(4*1-1 downto 1); + signal IPU_READ_OUT : std_logic_vector(4*1-1 downto 1); + signal IPU_LENGTH_IN : std_logic_vector(4*16-1 downto 16); + signal IPU_ERROR_PATTERN_IN : std_logic_vector(4*32-1 downto 32); + + type state_t is array(1 to 3) of integer range 0 to 15; + signal state : state_t; + signal counter : state_t; + signal state_vec : std_logic_vector(15 downto 0); + signal counter_vec : std_logic_vector(15 downto 0); + +begin + CLK <= not CLK after 5 ns; + RESET <= '0' after 50 ns; + CLK_EN <= '1'; + + + THE_HUB_LOGIC : trb_net16_hub_ipu_logic + port map( + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + + --Internal interfaces to IOBufs + INIT_DATAREADY_IN => INIT_DATAREADY_IN, + INIT_DATA_IN => INIT_DATA_IN, + INIT_PACKET_NUM_IN => INIT_PACKET_NUM_IN, + INIT_READ_OUT => INIT_READ_OUT, + + INIT_DATAREADY_OUT => INIT_DATAREADY_OUT, + INIT_DATA_OUT => INIT_DATA_OUT, + INIT_PACKET_NUM_OUT => INIT_PACKET_NUM_OUT, + INIT_READ_IN => INIT_READ_IN, + + REPLY_DATAREADY_IN => REPLY_DATAREADY_IN, + REPLY_DATA_IN => REPLY_DATA_IN, + REPLY_PACKET_NUM_IN => REPLY_PACKET_NUM_IN, + REPLY_READ_OUT => REPLY_READ_OUT, + + REPLY_DATAREADY_OUT => REPLY_DATAREADY_OUT, + REPLY_DATA_OUT => REPLY_DATA_OUT, + REPLY_PACKET_NUM_OUT => REPLY_PACKET_NUM_OUT, + REPLY_READ_IN => REPLY_READ_IN, + + MY_ADDRESS_IN => x"F00E", + --Status ports + CTRL => (others => '0'), + CTRL_activepoints => (others => '1') + ); + + THE_ACTIVE_API : trb_net16_api_base + generic map( + API_TYPE => c_API_ACTIVE + ) + port map( + -- Misc + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + APL_DATA_IN => APL_DATA_IN(15 downto 0), + APL_PACKET_NUM_IN => APL_PACKET_NUM_IN(2 downto 0), + APL_DATAREADY_IN => APL_DATAREADY_IN(0), + APL_READ_OUT => APL_READ_OUT(0), + APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN(0), + APL_DTYPE_IN => APL_DTYPE_IN(3 downto 0), + APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN(31 downto 0), + APL_SEND_IN => APL_SEND_IN(0), + APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN(15 downto 0), + APL_DATA_OUT => APL_DATA_OUT(c_DATA_WIDTH-1 downto 0), + APL_PACKET_NUM_OUT => APL_PACKET_NUM_OUT (c_NUM_WIDTH-1 downto 0), + APL_TYP_OUT => APL_TYP_OUT(2 downto 0), + APL_DATAREADY_OUT => APL_DATAREADY_OUT(0), + APL_READ_IN => APL_READ_IN(0), + APL_RUN_OUT => APL_RUN_OUT(0), + APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN(15 downto 0), + APL_SEQNR_OUT => APL_SEQNR_OUT(7 downto 0), + APL_LENGTH_IN => APL_LENGTH_IN(15 downto 0), + INT_MASTER_DATAREADY_OUT => INIT_DATAREADY_IN(0), + INT_MASTER_DATA_OUT => INIT_DATA_IN(c_DATA_WIDTH-1 downto 0), + INT_MASTER_PACKET_NUM_OUT => INIT_PACKET_NUM_IN(c_NUM_WIDTH-1 downto 0), + INT_MASTER_READ_IN => INIT_READ_OUT(0), + INT_MASTER_DATAREADY_IN => INIT_DATAREADY_OUT(0), + INT_MASTER_DATA_IN => INIT_DATA_OUT(15 downto 0), + INT_MASTER_PACKET_NUM_IN => INIT_PACKET_NUM_OUT(c_NUM_WIDTH-1 downto 0), + INT_MASTER_READ_OUT => INIT_READ_IN(0), + INT_SLAVE_DATAREADY_OUT => REPLY_DATAREADY_IN(0), + INT_SLAVE_DATA_OUT => REPLY_DATA_IN(c_DATA_WIDTH-1 downto 0), + INT_SLAVE_PACKET_NUM_OUT => REPLY_PACKET_NUM_IN(c_NUM_WIDTH-1 downto 0), + INT_SLAVE_READ_IN => REPLY_READ_OUT(0), + INT_SLAVE_DATAREADY_IN => REPLY_DATAREADY_OUT(0), + INT_SLAVE_DATA_IN => REPLY_DATA_OUT(15 downto 0), + INT_SLAVE_PACKET_NUM_IN => REPLY_PACKET_NUM_OUT(c_NUM_WIDTH-1 downto 0), + INT_SLAVE_READ_OUT => REPLY_READ_IN(0) + ); + REPLY_DATAREADY_IN(0) <= '0'; + + + + gen_passive_apis : for i in 1 to 3 generate + A_PASSIVE_API : trb_net16_api_base + generic map( + API_TYPE => c_API_PASSIVE + ) + port map( + -- Misc + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + APL_DATA_IN => APL_DATA_IN(i*16+15 downto i*16), + APL_PACKET_NUM_IN => APL_PACKET_NUM_IN(i*3+2 downto i*3), + APL_DATAREADY_IN => APL_DATAREADY_IN(i), + APL_READ_OUT => APL_READ_OUT(i), + APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN(i), + APL_DTYPE_IN => APL_DTYPE_IN(i*4+3 downto i*4), + APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN(i*32+31 downto i*32), + APL_SEND_IN => APL_SEND_IN(i), + APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN(i*16+15 downto i*16), + APL_DATA_OUT => APL_DATA_OUT((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + APL_PACKET_NUM_OUT => APL_PACKET_NUM_OUT ((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + APL_TYP_OUT => APL_TYP_OUT((i+1)*3-1 downto i*3), + APL_DATAREADY_OUT => APL_DATAREADY_OUT(i), + APL_READ_IN => APL_READ_IN(i), + APL_RUN_OUT => APL_RUN_OUT(i), + APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN(i*16+15 downto i*16), + APL_SEQNR_OUT => APL_SEQNR_OUT(i*8+7 downto i*8), + APL_LENGTH_IN => APL_LENGTH_IN(i*16+15 downto i*16), + INT_MASTER_DATAREADY_OUT => REPLY_DATAREADY_IN(i), + INT_MASTER_DATA_OUT => REPLY_DATA_IN(i*16+15 downto i*16), + INT_MASTER_PACKET_NUM_OUT=> REPLY_PACKET_NUM_IN(i*3+2 downto i*3), + INT_MASTER_READ_IN => REPLY_READ_OUT(i), + INT_MASTER_DATAREADY_IN => REPLY_DATAREADY_OUT(i), + INT_MASTER_DATA_IN => REPLY_DATA_OUT(i*16+15 downto i*16), + INT_MASTER_PACKET_NUM_IN => REPLY_PACKET_NUM_OUT(i*3+2 downto i*3), + INT_MASTER_READ_OUT => REPLY_READ_IN(i), + INT_SLAVE_DATAREADY_OUT => INIT_DATAREADY_IN(i), + INT_SLAVE_DATA_OUT => INIT_DATA_IN(i*16+15 downto i*16), + INT_SLAVE_PACKET_NUM_OUT => INIT_PACKET_NUM_IN(i*3+2 downto i*3), + INT_SLAVE_READ_IN => INIT_READ_OUT(i), + INT_SLAVE_DATAREADY_IN => INIT_DATAREADY_OUT(i), + INT_SLAVE_DATA_IN => INIT_DATA_OUT(i*16+15 downto i*16), + INT_SLAVE_PACKET_NUM_IN => INIT_PACKET_NUM_OUT(i*3+2 downto i*3), + INT_SLAVE_READ_OUT => INIT_READ_IN(i) + ); + end generate; + + + THE_SENDER : trb_net16_dummy_apl + generic map( + TARGET_ADDRESS => x"FFFF", + PREFILL_LENGTH => 1, + TRANSFER_LENGTH => 1 + ) + port map( + -- Misc + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + -- APL Transmitter port + APL_DATA_OUT => APL_DATA_IN(15 downto 0), + APL_PACKET_NUM_OUT => APL_PACKET_NUM_IN(2 downto 0), + APL_DATAREADY_OUT => open, + APL_READ_IN => APL_READ_OUT(0), + APL_SHORT_TRANSFER_OUT => open, + APL_DTYPE_OUT => open, + APL_ERROR_PATTERN_OUT => open, + APL_SEND_OUT => open, --APL_SEND_IN(0), + APL_TARGET_ADDRESS_OUT => APL_TARGET_ADDRESS_IN(15 downto 0), + -- Receiver port + APL_DATA_IN => APL_DATA_OUT(15 downto 0), + APL_PACKET_NUM_IN => APL_PACKET_NUM_OUT(2 downto 0), + APL_TYP_IN => APL_TYP_OUT(2 downto 0), + APL_DATAREADY_IN => APL_DATAREADY_OUT(0), + APL_READ_OUT => APL_READ_IN(0), + -- APL Control port + APL_RUN_IN => APL_RUN_OUT(0), + APL_SEQNR_IN => APL_SEQNR_OUT(7 downto 0) + ); + +APL_ERROR_PATTERN_IN(31 downto 0) <= x"0055" & x"EFE0"; +APL_DTYPE_IN(3 downto 0) <= x"9"; +APL_SHORT_TRANSFER_IN(0) <= '1'; +APL_DATAREADY_IN(0) <= '0'; +APL_SEND_IN(0) <= not APL_RUN_OUT(0); + + + gen_ipudatas : for i in 1 to 3 generate + A_IPUDATA : trb_net16_ipudata + port map( + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + API_DATA_OUT => APL_DATA_IN(i*16+15 downto i*16), + API_PACKET_NUM_OUT => APL_PACKET_NUM_IN(i*3+2 downto i*3), + API_DATAREADY_OUT => APL_DATAREADY_IN(i), + API_READ_IN => APL_READ_OUT(i), + API_SHORT_TRANSFER_OUT => APL_SHORT_TRANSFER_IN(i), + API_DTYPE_OUT => APL_DTYPE_IN((i+1)*4-1 downto i*4), + API_ERROR_PATTERN_OUT => APL_ERROR_PATTERN_IN((i+1)*32-1 downto i*32), + API_SEND_OUT => APL_SEND_IN(i), + -- Receiver port + API_DATA_IN => APL_DATA_OUT((i+1)*16-1 downto i*16), + API_PACKET_NUM_IN => APL_PACKET_NUM_OUT((i+1)*3-1 downto i*3), + API_TYP_IN => APL_TYP_OUT((i+1)*3-1 downto i*3), + API_DATAREADY_IN => APL_DATAREADY_OUT(i), + API_READ_OUT => APL_READ_IN(i), + -- APL Control port + API_RUN_IN => APL_RUN_OUT(i), + API_SEQNR_IN => APL_SEQNR_OUT((i+1)*8-1 downto i*8), + API_LENGTH_OUT => APL_LENGTH_IN((i+1)*16-1 downto i*16), + --Information received with request + IPU_NUMBER_OUT => IPU_NUMBER_OUT((i+1)*16-1 downto i*16), + IPU_INFORMATION_OUT => IPU_INFORMATION_OUT((i+1)*8-1 downto i*8), + --start strobe + IPU_START_READOUT_OUT => IPU_START_READOUT_OUT(i), + --detector data, equipped with DHDR + IPU_DATA_IN => IPU_DATA_IN((i+1)*32-1 downto i*32), + IPU_DATAREADY_IN => IPU_DATAREADY_IN(i), + --no more data, end transfer, send TRM + IPU_READOUT_FINISHED_IN=> IPU_READOUT_FINISHED_IN(i), + --will be low every second cycle due to 32bit -> 16bit conversion + IPU_READ_OUT => IPU_READ_OUT(i), + IPU_LENGTH_IN => IPU_LENGTH_IN((i+1)*16-1 downto i*16), + IPU_ERROR_PATTERN_IN => IPU_ERROR_PATTERN_IN((i+1)*32-1 downto i*32), + STAT_DEBUG => open + ); + + IPU_ERROR_PATTERN_IN((i+1)*32-1 downto i*32) <= (others => '0'); + + counter_vec(i*4+3 downto i*4) <= std_logic_vector(to_unsigned(counter(i),4)); + state_vec(i*4+3 downto i*4) <= std_logic_vector(to_unsigned(state(i),4)); + + process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + IPU_LENGTH_IN((i*16+15) downto i*16) <= (others => '0'); + IPU_DATA_IN((i*32+31) downto i*32) <= (others => '0'); + IPU_READOUT_FINISHED_IN(i) <= '0'; + else + case state(i) is + when 0 => + if IPU_START_READOUT_OUT(i) = '1' then + state(i) <= 1; + counter(i) <= 0; + IPU_DATAREADY_IN(i) <= '0'; + IPU_READOUT_FINISHED_IN(i) <= '0'; + end if; + when 1 => + counter(i) <= counter(i) + 1; + if counter(i) = 8-2*i then + counter(i) <= counter(i); + if IPU_READ_OUT(i) = '1' then + state(i) <= 2; + counter(i) <= 1; + end if; + IPU_DATAREADY_IN(i) <= '1'; + IPU_LENGTH_IN((i*16+15) downto i*16) <= std_logic_vector(to_unsigned(i+2,16)); + IPU_DATA_IN((i*32+31) downto i*32) <= "0001100101010101" & x"EFE0"; + end if; + when 2 => + IPU_DATAREADY_IN(i) <= '1'; + if IPU_READ_OUT(i) = '1' and IPU_DATAREADY_IN(i) = '1' then + counter(i) <= counter(i) + 1; + end if; + case counter(i) is + when 1 => + IPU_DATA_IN((i*32+31) downto i*32) <= std_logic_vector(to_unsigned(i,16)) & APL_MY_ADDRESS_IN(i*16+15 downto i*16); + when others => + IPU_DATA_IN((i*32+31) downto i*32) <= std_logic_vector(to_unsigned(counter(i)+1000,16)) & std_logic_vector(to_unsigned(counter(i),16)); + end case; + if counter(i) = i+2 then + IPU_DATAREADY_IN(i) <= '0'; + IPU_READOUT_FINISHED_IN(i) <= '1'; + state(i) <= 3; + end if; + when 3 => + if IPU_START_READOUT_OUT(i) = '0' then + state(i) <= 0; + end if; + when others => state(i) <= 0; + end case; + end if; + end if; + end process; + end generate; + + + + +APL_MY_ADDRESS_IN <= x"F00C_F00B_F00A_F000"; + + +end architecture; \ No newline at end of file diff --git a/trb_net16_hub_ipu_logic.vhd b/trb_net16_hub_ipu_logic.vhd index 1bf0e2d..108b43a 100644 --- a/trb_net16_hub_ipu_logic.vhd +++ b/trb_net16_hub_ipu_logic.vhd @@ -1,7 +1,6 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.std_logic_ARITH.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; +LIBRARY ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; library work; use work.trb_net_std.all; @@ -10,7 +9,7 @@ use work.trb_net_std.all; entity trb_net16_hub_ipu_logic is generic ( --media interfaces - POINT_NUMBER : integer range 2 to 32 := 3 + POINT_NUMBER : integer range 2 to 17 := 11 ); port ( CLK : in std_logic; @@ -90,7 +89,7 @@ architecture trb_net16_hub_ipu_logic_arch of trb_net16_hub_ipu_logic is ); end component; - component trb_net_ram_dp + component ram_dp_rw generic( depth : integer := 3; width : integer := 16 @@ -99,27 +98,25 @@ architecture trb_net16_hub_ipu_logic_arch of trb_net16_hub_ipu_logic is CLK : in std_logic; wr1 : in std_logic; a1 : in std_logic_vector(depth-1 downto 0); - dout1 : out std_logic_vector(width-1 downto 0); din1 : in std_logic_vector(width-1 downto 0); a2 : in std_logic_vector(depth-1 downto 0); dout2 : out std_logic_vector(width-1 downto 0) ); end component; - component wide_adder is + component wide_adder_17x16 is generic( - WIDTH : integer := 16; - WORDS : integer := 16; --multiples of 2^parallel_adders only - PARALLEL_ADDERS : integer := 2 --2^n + SIZE : integer := 16; + WORDS: integer := 17 --fixed ); port( CLK : in std_logic; CLK_EN : in std_logic; RESET : in std_logic; - INPUT_IN : in std_logic_vector(WIDTH*WORDS-1 downto 0); + INPUT_IN : in std_logic_vector(SIZE*WORDS-1 downto 0); START_IN : in std_logic; VAL_ENABLE_IN: in std_logic_vector(WORDS-1 downto 0); - RESULT_OUT : out std_logic_vector(WIDTH-1 downto 0); + RESULT_OUT : out std_logic_vector(SIZE-1 downto 0); OVERFLOW_OUT : out std_logic; READY_OUT : out std_logic ); @@ -141,10 +138,12 @@ architecture trb_net16_hub_ipu_logic_arch of trb_net16_hub_ipu_logic is signal REPLY_POOL_DATA : std_logic_vector(c_DATA_WIDTH-1 downto 0); signal REPLY_POOL_PACKET_NUM : std_logic_vector(c_NUM_WIDTH-1 downto 0); - signal current_reply_packet_type : std_logic_vector(2 downto 0); - signal saved_reply_packet_type : std_logic_vector(2 downto 0); - signal last_reply_packet_type : std_logic_vector(2 downto 0); + signal current_reply_packet_type : std_logic_vector(POINT_NUMBER*3-1 downto 0); + signal saved_reply_packet_type : std_logic_vector(POINT_NUMBER*3-1 downto 0); + signal last_reply_packet_type : std_logic_vector(POINT_NUMBER*3-1 downto 0); + signal last_reply_packet_number : std_logic_vector(POINT_NUMBER*3-1 downto 0); signal current_reply_reading_trm : std_logic_vector(POINT_NUMBER-1 downto 0); + signal reply_reading_H0 : std_logic_vector(POINT_NUMBER-1 downto 0); signal reply_reading_F0 : std_logic_vector(POINT_NUMBER-1 downto 0); signal reply_reading_F1 : std_logic_vector(POINT_NUMBER-1 downto 0); signal reply_reading_F2 : std_logic_vector(POINT_NUMBER-1 downto 0); @@ -152,20 +151,19 @@ architecture trb_net16_hub_ipu_logic_arch of trb_net16_hub_ipu_logic is signal reply_combined_trm_F1 : std_logic_vector(c_DATA_WIDTH-1 downto 0); signal reply_combined_trm_F2 : std_logic_vector(c_DATA_WIDTH-1 downto 0); signal reply_combined_trm_F3 : std_logic_vector(c_DATA_WIDTH-1 downto 0); - signal REPLY_MUX_real_reading : std_logic; signal real_activepoints : std_logic_vector(POINT_NUMBER-1 downto 0); signal hdrram_write_enable : std_logic_vector(POINT_NUMBER-1 downto 0); signal hdrram_address : std_logic_vector(3*POINT_NUMBER-1 downto 0); signal current_waiting_for_reply : std_logic_vector(POINT_NUMBER-1 downto 0); signal next_current_waiting_for_reply : std_logic_vector(POINT_NUMBER-1 downto 0); - signal reply_reading_HDR : std_logic_vector(POINT_NUMBER-1 downto 0); - signal reply_reading_DHDR : std_logic_vector(POINT_NUMBER-1 downto 0); - signal next_REPLY_reading_hdr : std_logic_vector(POINT_NUMBER-1 downto 0); +-- signal reply_reading_HDR : std_logic_vector(POINT_NUMBER-1 downto 0); +-- signal reply_reading_DHDR : std_logic_vector(POINT_NUMBER-1 downto 0); + signal current_reply_reading_DHDR : std_logic_vector(POINT_NUMBER-1 downto 0); + signal current_reply_auto_reading_DHDR : std_logic_vector(POINT_NUMBER-1 downto 0); +-- signal reply_reading_trm : std_logic_vector(POINT_NUMBER-1 downto 0); signal current_REPLY_reading_hdr : std_logic_vector(POINT_NUMBER-1 downto 0); - signal last_header_addr : std_logic_vector(c_NUM_WIDTH-1 downto 0); - signal last_header_data : std_logic_vector(POINT_NUMBER*c_DATA_WIDTH-1 downto 0); - signal reading_last_hdr,next_reading_last_hdr : std_logic_vector(POINT_NUMBER-1 downto 0); + signal current_muxed_reading_DAT : std_logic; --general signals signal locked, next_locked : std_logic; @@ -178,31 +176,37 @@ architecture trb_net16_hub_ipu_logic_arch of trb_net16_hub_ipu_logic is signal get_init_locked, release_init_locked: std_logic; signal REPLY_MUX_reading : std_logic_vector(POINT_NUMBER-1 downto 0); - signal reply_arbiter_result,last_reply_arbiter_result : std_logic_vector(POINT_NUMBER-1 downto 0); + signal reply_arbiter_result : std_logic_vector(POINT_NUMBER-1 downto 0); - type state_type is (IDLE, CHECK_DHDR, SENDING_DATA, SENDING_REPLY_TRM); + type state_type is (IDLE, WAIT_FOR_HDR_DATA, GEN_LENGTH, CHECK_DHDR, SENDING_DATA, SENDING_REPLY_TRM, SEND_PADDING, WAITING_FOR_INIT); signal current_state, next_state : state_type; signal packet_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0); - signal data_counter : std_logic_vector(7 downto 0); - signal SEQ_NR : std_logic_vector(7 downto 0); + signal reply_data_counter : unsigned(15 downto 0); + signal reply_data_counter_reset : std_logic; signal comb_REPLY_POOL_DATAREADY : std_logic; signal comb_REPLY_POOL_DATA : std_logic_vector(c_DATA_WIDTH-1 downto 0); signal comb_REPLY_POOL_PACKET_NUM : std_logic_vector(c_NUM_WIDTH-1 downto 0); signal REPLY_POOL_next_read : std_logic; signal comb_REPLY_POOL_next_read : std_logic; - - signal reply_point_lock, next_point_lock : std_logic; + signal evt_random_code : std_logic_vector(7 downto 0); + signal evt_number : std_logic_vector(15 downto 0); + signal evt_dtype : std_logic_vector(3 downto 0); + signal evt_seqnr : std_logic_vector(7 downto 0); signal comb_REPLY_muxed_DATAREADY : std_logic; signal comb_REPLY_muxed_DATA : std_logic_vector(c_DATA_WIDTH-1 downto 0); signal comb_REPLY_muxed_PACKET_NUM : std_logic_vector(c_NUM_WIDTH-1 downto 0); - signal reply_arbiter_CLK_EN : std_logic; + signal init_arbiter_CLK_EN : std_logic; signal init_arbiter_ENABLE : std_logic; signal init_arbiter_read_out : std_logic_vector(POINT_NUMBER-1 downto 0); + signal reply_arbiter_input : std_logic_vector(POINT_NUMBER-1 downto 0); signal reply_arbiter_enable : std_logic; + signal reply_arbiter_CLK_EN : std_logic; + signal reply_arbiter_reset : std_logic; + signal saved_reply_arbiter_CLK_EN : std_logic; signal INIT_muxed_DATAREADY : std_logic; signal INIT_muxed_DATA : std_logic_vector(c_DATA_WIDTH-1 downto 0); @@ -211,17 +215,35 @@ architecture trb_net16_hub_ipu_logic_arch of trb_net16_hub_ipu_logic is signal comb_INIT_next_read : std_logic; signal reply_fsm_state : std_logic_vector(7 downto 0); - signal waiting_for_init_finish, next_waiting_for_init_finish : std_logic; +-- signal waiting_for_init_finish, next_waiting_for_init_finish : std_logic; signal waiting_for_DHDR_word : std_logic_vector(POINT_NUMBER-1 downto 0); signal next_waiting_for_DHDR_word : std_logic_vector(POINT_NUMBER-1 downto 0); + signal reply_adder_input : std_logic_vector(17*16-1 downto 0); signal reply_adder_start : std_logic; signal reply_adder_overflow : std_logic; signal reply_adder_ready : std_logic; - signal reply_adder_val_enable : std_logic_vector(POINT_NUMBER-1 downto 0); + signal reply_adder_val_enable : std_logic_vector(17-1 downto 0); signal reply_adder_result : std_logic_vector(15 downto 0); + signal reply_compare_start : std_logic; + signal reply_compare_finished : std_logic; + signal reply_compare_result : std_logic_vector(17-1 downto 0); + signal reply_compare_flag : std_logic; + signal reply_compare_input : std_logic_vector(17-1 downto 0); + + signal last_dhdr_addr : std_logic_vector(2 downto 0); + signal last_dhdr_data : std_logic_vector(16*POINT_NUMBER-1 downto 0); + + signal current_point_length : unsigned(15 downto 0); + signal reply_mux_number : integer range 0 to POINT_NUMBER-1; + signal start_read_padding : std_logic_vector(POINT_NUMBER-1 downto 0); + signal saved_reading_padding : std_logic_vector(POINT_NUMBER-1 downto 0); + signal reading_padding : std_logic_vector(POINT_NUMBER-1 downto 0); + signal got_all_DHDR : std_logic; + signal got_all_reply_starts : std_logic; + signal not_reading_HDR : std_logic; begin @@ -371,13 +393,21 @@ begin current_INIT_TYPE <= INIT_muxed_DATA(2 downto 0) when INIT_muxed_DATAREADY = '1' and INIT_muxed_PACKET_NUM = c_H0 else saved_INIT_TYPE; - save_SEQ_NR : process(CLK) + + + save_INIT_PACKET : process(CLK) begin if rising_edge(CLK) then if RESET = '1' then - SEQ_NR <= (others => '0'); - elsif INIT_POOL_PACKET_NUM = c_F3 and current_INIT_TYPE = TYPE_HDR then - SEQ_NR <= INIT_POOL_DATA(11 downto 4); + elsif INIT_POOL_DATAREADY = '1' then + case INIT_POOL_PACKET_NUM is + when c_F0 => null; + when c_F1 => evt_random_code <= INIT_POOL_DATA(7 downto 0); + when c_F2 => evt_number <= INIT_POOL_DATA; + when c_F3 => evt_dtype <= INIT_POOL_DATA(3 downto 0); + evt_seqnr <= INIT_POOL_DATA(11 downto 4); + when others => null; + end case; end if; end if; end process; @@ -385,22 +415,43 @@ begin + + + + + + + + + + + + ------------------------------ --REPLY----------------------- ------------------------------ - buf_REPLY_READ_OUT <= reply_reading_trm or reply_reading_HDR or reply_reading_DHDR or reply_mux_reading - when REPLY_POOL_next_read = '1' - else reply_reading_trm or reply_reading_HDR or reply_real_reading_DHDR; + gen_read_out : for i in 0 to POINT_NUMBER-1 generate + buf_REPLY_READ_OUT(i) <= current_reply_reading_TRM(i) + or current_reply_reading_HDR(i) + or current_reply_auto_reading_DHDR(i) + or saved_reading_padding(i) + or (reply_mux_reading(i) and REPLY_POOL_next_read and not packet_counter(2)) + or (reply_fsm_state(4) and reply_reading_H0(i)); + + + end generate; REPLY_READ_OUT <= buf_REPLY_READ_OUT; send_reply_trm <= and_all(got_trm); ---save current packet type & number ------------------------------------ +--save current packet type & set markers for special words +---------------------------------------------------------- - gen_reading_trmFn : for i in 0 to POINT_NUMBER-1 generate + gen_reading_Fn : for i in 0 to POINT_NUMBER-1 generate + reply_reading_H0(i) <= not REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH+1) and not REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH) + and REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH+2) and REPLY_DATAREADY_IN(i); reply_reading_F0(i) <= not REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH+1) and not REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH) and not REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH+2) and REPLY_DATAREADY_IN(i); reply_reading_F1(i) <= not REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH+1) and REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH) @@ -415,13 +466,20 @@ begin if rising_edge(CLK) then if RESET = '1' then saved_reply_packet_type((i+1)*3-1 downto i*3) <= TYPE_ILLEGAL; - last_reply_packet_type((i+1)*3-1 downto i*3) <= TYPE_ILLEGAL; - elsif REPLY_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) = c_H0 then - saved_reply_packet_type((i+1)*3-1 downto i*3) <= REPLY_DATA_IN(2 downto 0); - last_reply_packet_type((i+1)*3-1 downto i*3) <= saved_reply_packet_type; + last_reply_packet_type ((i+1)*3-1 downto i*3) <= TYPE_ILLEGAL; + last_reply_packet_number((i+1)*3-1 downto i*3) <= c_F3; + elsif REPLY_DATAREADY_IN(i) = '1' then + last_reply_packet_number((i+1)*3-1 downto i*3) <= REPLY_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH); + if REPLY_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) = c_H0 then + saved_reply_packet_type((i+1)*3-1 downto i*3) <= REPLY_DATA_IN(i*c_DATA_WIDTH+2 downto i*c_DATA_WIDTH); + if last_reply_packet_number((i+1)*3-1 downto i*3) /= c_H0 then + last_reply_packet_type ((i+1)*3-1 downto i*3) <= saved_reply_packet_type((i+1)*3-1 downto i*3); + end if; + end if; end if; end if; end process; + current_reply_packet_type((i+1)*3-1 downto i*3) <= REPLY_DATA_IN(i*c_DATA_WIDTH+2 downto i*c_DATA_WIDTH) when (REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH+2 downto i*c_NUM_WIDTH) = c_H0) else saved_reply_packet_type((i+1)*3-1 downto i*3); @@ -430,17 +488,36 @@ begin current_reply_reading_DHDR(i) <= '1' when current_reply_packet_type((i+1)*3-1 downto i*3) = TYPE_DAT and last_reply_packet_type((i+1)*3-1 downto i*3) = TYPE_HDR else '0'; current_reply_reading_TRM(i) <= '1' when current_reply_packet_type((i+1)*3-1 downto i*3) = TYPE_TRM else '0'; + current_reply_auto_reading_DHDR(i) <= '1' when current_reply_reading_DHDR(i) = '1' and REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH+1) = '0' + else '0'; end generate; + + process(current_reply_packet_type, reply_arbiter_result) + begin + current_muxed_reading_DAT <= '0'; + gen_current_reading_dat : for i in 0 to POINT_NUMBER-1 loop + if reply_arbiter_result(i) = '1' then + if current_reply_packet_type((i+1)*3-1 downto i*3) = TYPE_DAT then + current_muxed_reading_DAT <= '1'; + end if; + end if; + end loop; + end process; + --saving (D)HDR ------------------------- gen_saving_dhdr : for i in 0 to POINT_NUMBER-1 generate - hdrram_write_enable(i) <= current_reply_reading_HDR(i) and - (reply_reading_F0(i) or reply_reading_F1(i) or reply_reading_F2(i) or reply_reading_F3(i)); - hdrram_address(i*3+2 downto i*3) <= REPLY_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH); - hdrram_address(i*3+3) <= '1' when current_reply_reading_DHDR(i) else '0'; - - the_last_HDR_RAM : trb_net_ram_dp + hdrram_write_enable(i) <= (current_reply_reading_HDR(i) and + (reply_reading_F0(i) or reply_reading_F1(i) or reply_reading_F2(i) or reply_reading_F3(i))) or + (current_reply_reading_DHDR(i) and + (reply_reading_F0(i) or reply_reading_F1(i) or (REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH+1) and not + REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH) and not REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH+2)))); + --read normal HDR_F0 to DHDR_F1 and DHDR_F2 without read='1' + hdrram_address(i*3+1 downto i*3) <= REPLY_PACKET_NUM_IN((i)*c_NUM_WIDTH+1 downto i*c_NUM_WIDTH); + hdrram_address(i*3+2) <= '1' when current_reply_reading_DHDR(i)='1' else '0'; + + the_last_HDR_RAM : ram_dp_rw generic map( depth => 3, width => 16 @@ -450,34 +527,50 @@ begin wr1 => hdrram_write_enable(i), a1 => hdrram_address(i*3+2 downto i*3), din1 => REPLY_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), - dout1 => open, a2 => last_dhdr_addr, dout2 => last_dhdr_data((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) ); end generate; - the_ram_output_adder : wide_adder + the_ram_output_adder : wide_adder_17x16 generic map( - WIDTH => 16, - WORDS => POINT_NUMBER, - PARALLEL_ADDERS => 2 + SIZE => 16, + WORDS => 17 ) port map( CLK => CLK, CLK_EN => CLK_EN, RESET => RESET, - INPUT_IN => last_dhdr_data, - START_IN => adder_start, - RESULT_OUT => adder_result, - OVERFLOW_OUT => adder_overflow, - READY_OUT => adder_ready + INPUT_IN => reply_adder_input, + VAL_ENABLE_IN=> reply_adder_val_enable, + START_IN => reply_adder_start, + RESULT_OUT => reply_adder_result, + OVERFLOW_OUT => reply_adder_overflow, + READY_OUT => reply_adder_ready ); + reply_adder_input(POINT_NUMBER*16-1 downto 0) <= last_dhdr_data; + reply_adder_input(reply_adder_input'left downto POINT_NUMBER*16) <= (others => '0'); ---reading and merging TRM ----------------------------------- + process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + current_point_length <= (others => '0'); + else + gen_current_length : for i in 0 to POINT_NUMBER-1 loop + if reply_arbiter_result(i) = '1' then + current_point_length <= unsigned(last_dhdr_data((i)*c_DATA_WIDTH+c_DATA_WIDTH-1 downto i*c_DATA_WIDTH)); + end if; + end loop; + end if; + end if; + end process; + +--reading and merging TRM +---------------------------------- gen_combining_trm : for j in 0 to c_DATA_WIDTH-1 generate process(CLK) variable tmpF1, tmpF2, tmpF3 : std_logic; @@ -492,9 +585,9 @@ begin tmpF2 := '0'; tmpF3 := '0'; for i in 0 to POINT_NUMBER-1 loop - tmpF1 := tmpF1 or (REPLY_DATA_IN(i*c_DATA_WIDTH+j) and reply_reading_F1(i) and reply_reading_trm(i)); - tmpF2 := tmpF2 or (REPLY_DATA_IN(i*c_DATA_WIDTH+j) and reply_reading_F2(i) and reply_reading_trm(i)); - tmpF3 := tmpF3 or (REPLY_DATA_IN(i*c_DATA_WIDTH+j) and reply_reading_F3(i) and reply_reading_trm(i)); + tmpF1 := tmpF1 or (REPLY_DATA_IN(i*c_DATA_WIDTH+j) and reply_reading_F1(i) and current_reply_reading_TRM(i)); + tmpF2 := tmpF2 or (REPLY_DATA_IN(i*c_DATA_WIDTH+j) and reply_reading_F2(i) and current_reply_reading_TRM(i)); + tmpF3 := tmpF3 or (REPLY_DATA_IN(i*c_DATA_WIDTH+j) and reply_reading_F3(i) and current_reply_reading_TRM(i)); end loop; reply_combined_trm_F1(j) <= reply_combined_trm_F1(j) or tmpF1; reply_combined_trm_F2(j) <= reply_combined_trm_F2(j) or tmpF2; @@ -504,6 +597,39 @@ begin end process; end generate; +--read overhead data +-------------------- + + process(RESET, send_reply_trm, REPLY_PACKET_NUM_IN, REPLY_DATAREADY_IN, REPLY_DATA_IN, start_read_padding, + saved_reading_padding) + begin + if RESET = '1' or send_reply_trm = '1' then + reading_padding <= (others => '0'); + else + for i in 0 to POINT_NUMBER-1 loop + if REPLY_DATAREADY_IN(i) = '1' and REPLY_PACKET_NUM_IN(i*3+2 downto i*3) = c_H0 and REPLY_DATA_IN(i*16+2 downto i*16) = TYPE_TRM then + reading_padding(i) <= '0'; + elsif start_read_padding(i) = '1' and REPLY_PACKET_NUM_IN(i*3+2 downto i*3) /= c_F3 then + reading_padding(i) <= '1'; + else + reading_padding(i) <= saved_reading_padding(i); + end if; + end loop; + end if; + end process; + + gen_saved_padding : process (CLK) + begin + if rising_edge(CLK) then + if locked = '0' then + saved_reading_padding <= (others => '0'); + else + saved_reading_padding <= reading_padding; + end if; + end if; + end process; + + --real_activepoints can be set between transfers only, but can be cleared at any time ---------------------------------- @@ -527,7 +653,18 @@ begin if RESET = '1' or send_reply_trm = '1' or locked = '0' then got_trm <= (others => '0'); else - got_trm <= got_trm or locking_point or reading_trmF2 or not real_activepoints; + got_trm <= got_trm or locking_point or (reply_reading_F3 and current_reply_reading_TRM) or not real_activepoints; + end if; + end if; + end process; + + gen_got_dhdr : process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' or locked = '0' then + got_all_DHDR <= '0'; + else + got_all_DHDR <= or_all(waiting_for_DHDR_word); end if; end if; end process; @@ -545,20 +682,20 @@ begin if packet_counter = c_max_word_number then packet_counter <= (others => '0'); else - packet_counter <= packet_counter + 1; + packet_counter <= std_logic_vector(to_unsigned(to_integer(unsigned(packet_counter)) + 1 ,packet_counter'length )); end if; end if; end if; end process; - --counts data packets only + --counts 32bit words gen_data_counter : process(CLK) begin if rising_edge(CLK) then - if RESET = '1' or reply_point_lock = '0' then - data_counter <= (others => '0'); - elsif comb_REPLY_POOL_DATAREADY = '1' and comb_REPLY_POOL_DATA(2 downto 0) = TYPE_DAT then - data_counter <= data_counter + 1; + if RESET = '1' or reply_data_counter_reset = '1' then + reply_data_counter <= (others => '1'); + elsif comb_REPLY_POOL_DATAREADY = '1' and comb_REPLY_POOL_PACKET_NUM(0) = '0' and comb_REPLY_POOL_PACKET_NUM(2) = '0' then + reply_data_counter <= reply_data_counter + 1; end if; end if; end process; @@ -571,7 +708,7 @@ begin ) port map ( CLK => CLK, - RESET => RESET, + RESET => reply_arbiter_reset, CLK_EN => reply_arbiter_CLK_EN, INPUT_IN => reply_arbiter_input, RESULT_OUT => reply_arbiter_result, @@ -579,106 +716,97 @@ begin CTRL => (others => '0') ); - reply_arbiter_input <= REPLY_DATAREADY_IN and not reply_reading_trm and not reply_reading_HDR and not reply_reading_DHDR; - reply_arbiter_CLK_EN <= not next_point_lock; + reply_arbiter_reset <= RESET or not locked; + reply_arbiter_input <= REPLY_DATAREADY_IN and not current_reply_reading_TRM and current_reply_reading_DHDR and not saved_reading_padding and not start_read_padding; +-- reply_arbiter_CLK_EN <= not next_point_lock; REPLY_MUX_reading <= reply_arbiter_result; - -- release is done after first packet of TRM - gen_reply_point_lock : process(reply_point_lock, comb_REPLY_muxed_PACKET_NUM, - REPLY_DATAREADY_IN, comb_REPLY_muxed_DATA, REPLY_MUX_reading) - begin - next_point_lock <= reply_point_lock; - --release lock if TRM is read - if comb_REPLY_muxed_PACKET_NUM = c_H0 and or_all(REPLY_MUX_reading and REPLY_DATAREADY_IN) = '1' then - if comb_REPLY_muxed_DATA(2 downto 0) = TYPE_TRM then - next_point_lock <= '0'; - else - next_point_lock <= '1'; - end if; - end if; - end process; - - gen_point_lock : process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - reply_point_lock <= '0'; - else - reply_point_lock <=next_point_lock; - end if; - end if; - end process; - - - - --REPLY mux ---------------------------------- gen_reply_mux1 : for i in 0 to c_DATA_WIDTH-1 generate - data_mux : process(REPLY_DATA_IN, REPLY_MUX_reading,last_header_data, reading_last_hdr) + data_mux : process(REPLY_DATA_IN, REPLY_MUX_reading) variable tmp_data : std_logic; begin tmp_data := '0'; gen_data_mux : for j in 0 to POINT_NUMBER-1 loop - tmp_data := tmp_data or (REPLY_DATA_IN(j*c_DATA_WIDTH+i) and REPLY_MUX_reading(j)) - or (last_header_data(j*c_DATA_WIDTH+i) and reading_last_hdr(j)); + tmp_data := tmp_data or (REPLY_DATA_IN(j*c_DATA_WIDTH+i) and REPLY_MUX_reading(j)); end loop; comb_REPLY_muxed_DATA(i) <= tmp_data; end process; end generate; gen_reply_mux2 : for i in 0 to c_NUM_WIDTH-1 generate - packet_num_mux : process(REPLY_PACKET_NUM_IN, REPLY_MUX_reading,packet_counter, reading_last_hdr) + packet_num_mux : process(REPLY_PACKET_NUM_IN, REPLY_MUX_reading,packet_counter) variable tmp_pm : std_logic; begin tmp_pm := '0'; gen_pm_mux : for j in 0 to POINT_NUMBER-1 loop - tmp_pm := tmp_pm or (REPLY_PACKET_NUM_IN(j*c_NUM_WIDTH+i) and REPLY_MUX_reading(j)) - or (packet_counter(i) and reading_last_hdr(j)); + tmp_pm := tmp_pm or (REPLY_PACKET_NUM_IN(j*c_NUM_WIDTH+i) and REPLY_MUX_reading(j)); end loop; comb_REPLY_muxed_PACKET_NUM(i) <= tmp_pm; end process; end generate; - comb_REPLY_muxed_DATAREADY <= (or_all(reply_arbiter_result and REPLY_DATAREADY_IN and not current_reply_reading_trm and not current_reply_reading_hdr) or or_all(reading_last_hdr)) and REPLY_POOL_next_read; + comb_REPLY_muxed_DATAREADY <= or_all(reply_arbiter_result and REPLY_DATAREADY_IN and not current_reply_reading_trm + and not reply_reading_H0 and not saved_reading_padding and not start_read_padding) + and REPLY_POOL_next_read; +--temporary! +reply_compare_finished <= reply_compare_start; --REPLY POOL state machine ---------------------------------- - reply_state_machine : process(REPLY_POOL_next_READ, current_state, packet_counter, REPLY_combined_trm_F0, - send_reply_trm, SEQ_NR, REPLY_combined_trm_F1, REPLY_combined_trm_F2, - comb_REPLY_muxed_DATAREADY, comb_REPLY_muxed_DATA, init_locked, - comb_REPLY_muxed_PACKET_NUM, waiting_for_init_finish, waiting_for_DHDR_word) + reply_state_machine : process(REPLY_POOL_next_READ, current_state, packet_counter, reply_reading_F1, + send_reply_trm, REPLY_combined_trm_F1, REPLY_combined_trm_F2, got_all_DHDR, + comb_REPLY_muxed_DATAREADY, comb_REPLY_muxed_DATA, init_locked, not_reading_HDR, + comb_REPLY_muxed_PACKET_NUM, waiting_for_DHDR_word, got_all_reply_starts, + current_waiting_for_reply, current_REPLY_reading_hdr, locking_point, + real_activepoints, locked, MY_ADDRESS_IN, reply_adder_ready, reply_adder_result, + reply_combined_trm_F3, reply_compare_finished, reply_adder_ready, + reply_adder_overflow, reply_adder_result, current_reply_reading_DHDR, + evt_seqnr, evt_dtype, evt_random_code, evt_number, start_read_padding, + current_muxed_reading_DAT,reply_data_counter, current_point_length, + reply_arbiter_result, REPLY_DATAREADY_IN, saved_reply_arbiter_CLK_EN) begin release_locked <= '0'; next_state <= current_state; comb_REPLY_POOL_DATAREADY <= '0'; comb_REPLY_POOL_PACKET_NUM <= packet_counter; comb_REPLY_POOL_DATA <= (others => '0'); - next_waiting_for_init_finish <= waiting_for_init_finish; - next_waiting_for_DHDR_word <= waiting_for_DHDR_word; - hdrram_address <= "000"; - next_current_waiting_for_reply <= current_waiting_for_reply and not current_reply_reading_HDR; + next_waiting_for_DHDR_word <= waiting_for_DHDR_word and real_activepoints + and not (current_reply_reading_DHDR and reply_reading_F1); + last_dhdr_addr <= "000"; + next_current_waiting_for_reply <= current_waiting_for_reply and not current_reply_reading_HDR and real_activepoints; reply_adder_start <= '0'; - reply_adder_val_enable <= (not locking_point and real_activepoints); + reply_adder_val_enable(POINT_NUMBER-1 downto 0) <= (not locking_point and real_activepoints); + reply_adder_val_enable(reply_adder_val_enable'left downto POINT_NUMBER) <= (others => '0'); + reply_arbiter_enable <= '0'; + reply_compare_start <= '0'; + reply_arbiter_CLK_EN <= '0'; + reply_data_counter_reset <= '0'; + start_read_padding <= (others => '0'); + case current_state is when IDLE => --wait for init transfer + next_waiting_for_DHDR_word <= not (locking_point or not real_activepoints); + reply_arbiter_enable <= '0'; + next_current_waiting_for_reply <= not (locking_point or not real_activepoints); next_waiting_for_DHDR_word <= not (locking_point or not real_activepoints); if locked = '1' then - next_current_waiting_for_reply <= (others => '1'); next_state <= WAIT_FOR_HDR_DATA; end if; when WAIT_FOR_HDR_DATA => --start writing HDR when first reply is received, stop waiting for length + last_dhdr_addr <= "010"; case packet_counter is when c_H0 => comb_REPLY_POOL_DATA <= (others => '0'); comb_REPLY_POOL_DATA(2 downto 0) <= TYPE_HDR; - comb_REPLY_POOL_DATAREADY <= REPLY_POOL_next_read and not or_all(current_waiting_for_reply); + comb_REPLY_POOL_DATAREADY <= REPLY_POOL_next_read and got_all_reply_starts; when c_F0 => comb_REPLY_POOL_DATA <= MY_ADDRESS_IN; comb_REPLY_POOL_DATAREADY <= REPLY_POOL_next_read; @@ -687,53 +815,120 @@ begin comb_REPLY_POOL_DATAREADY <= REPLY_POOL_next_read; when c_F2 => comb_REPLY_POOL_DATAREADY <= '0'; - hdrram_address <= "011"; - if or_all(current_reply_reading_HDR or current_waiting_for_reply) = '0' then + if not_reading_HDR = '1' then --implicit not waiting_for_reply next_state <= GEN_LENGTH; reply_adder_start <= '1'; end if; - when others => - null; + when others => null; end case; when GEN_LENGTH => --now, all HDR are stored, calc sum of HDR lengths - hdrram_address <= "011"; - if reply_adder_ready = '1' then - case packet_counter is - when c_F2 => + last_dhdr_addr <= "010"; + comb_REPLY_POOL_DATAREADY <= '0'; + if reply_adder_ready = '1' then --packet_counter = c_F2 + comb_REPLY_POOL_DATAREADY <= REPLY_POOL_next_read; + comb_REPLY_POOL_DATA <= reply_adder_result; + end if; + if packet_counter = c_F3 then + last_dhdr_addr <= "100"; + comb_REPLY_POOL_DATA <= "0000" & evt_seqnr & evt_dtype; + comb_REPLY_POOL_DATAREADY <= REPLY_POOL_next_read; + if REPLY_POOL_next_read = '1' then + next_state <= CHECK_DHDR; + end if; + end if; + + when CHECK_DHDR => + comb_REPLY_POOL_DATAREADY <= '0'; + case packet_counter is + when c_H0 => + last_dhdr_addr <= "100"; + if got_all_DHDR = '1' then comb_REPLY_POOL_DATAREADY <= REPLY_POOL_next_read; - comb_REPLY_POOL_DATA <= reply_adder_result; - when c_F3 => + end if; + comb_REPLY_POOL_DATA(2 downto 0) <= TYPE_DAT; + comb_REPLY_POOL_DATA(c_DATA_WIDTH-1 downto 3) <= (others => '0'); + when c_F0 => + last_dhdr_addr <= "100"; + reply_compare_start <= '1'; + if reply_compare_finished = '1' then comb_REPLY_POOL_DATAREADY <= REPLY_POOL_next_read; - comb_REPLY_POOL_DATA <= ????????????????????????????????????????????????????; - if REPLY_POOL_next_read = '1' then - next_state <= CHECK_DHDR_0; - end if; - end case; - end if; + comb_REPLY_POOL_DATA <= "0001" & evt_dtype & evt_random_code; + last_dhdr_addr <= "101"; + end if; + when c_F1 => + last_dhdr_addr <= "101"; + reply_compare_start <= '1'; + if reply_compare_finished = '1' then + comb_REPLY_POOL_DATAREADY <= REPLY_POOL_next_read; + comb_REPLY_POOL_DATA <= evt_number; + last_dhdr_addr <= "110"; + end if; + when c_F2 => + reply_adder_start <= '1'; + last_dhdr_addr <= "110"; + if reply_adder_ready = '1' then + reply_adder_start <= '0'; + comb_REPLY_POOL_DATAREADY <= REPLY_POOL_next_read; + comb_REPLY_POOL_DATA <= std_logic_vector(unsigned(reply_adder_result) + + to_unsigned(count_ones(real_activepoints and not locking_point),16)); + end if; + when others => --c_F3 + comb_REPLY_POOL_DATA <= MY_ADDRESS_IN; + comb_REPLY_POOL_DATAREADY <= REPLY_POOL_next_read; + if REPLY_POOL_next_read = '1' then + next_state <= SENDING_DATA; + reply_arbiter_CLK_EN <= '1'; + reply_arbiter_enable <= '1'; + last_dhdr_addr <= "110"; + reply_data_counter_reset <= '1'; + end if; + end case; - when CHECK_DHDR_0 => - if or_all(waiting_for_DHDR_word) = '0' and REPLY_POOL_next_read = '1' then - comb_REPLY_POOL_DATAREADY <= '1'; - comb_REPLY_POOL_DATA <= combined_DHDR_word; - comb_REPLY_POOL_PACKET_NUM <= c_F0; - next_waiting_for_DHDR_word <= not (locking_point or not real_activepoints); + when SENDING_DATA => + reply_arbiter_enable <= '1'; + last_dhdr_addr <= "110"; --length + if packet_counter = c_H0 + and not (comb_REPLY_muxed_PACKET_NUM = c_H0 and comb_REPLY_muxed_DATA(2 downto 0) = TYPE_TRM) + and current_muxed_reading_DAT = '1' then + comb_REPLY_POOL_DATAREADY <= REPLY_POOL_next_read; + comb_REPLY_POOL_DATA(2 downto 0) <= TYPE_DAT; + comb_REPLY_POOL_DATA(15 downto 3) <= (others => '0'); + comb_REPLY_POOL_PACKET_NUM <= packet_counter; + else + comb_REPLY_POOL_DATAREADY <= comb_REPLY_muxed_DATAREADY; + comb_REPLY_POOL_DATA <= comb_REPLY_muxed_DATA; + comb_REPLY_POOL_PACKET_NUM <= packet_counter; + end if; + if packet_counter(0) = '0' and reply_data_counter = current_point_length then + reply_arbiter_CLK_EN <= '1'; + reply_data_counter_reset <= '1'; + start_read_padding <= reply_arbiter_result; + elsif or_all(reply_arbiter_result and REPLY_DATAREADY_IN)='1' then + reply_arbiter_CLK_EN <= '0'; + else + reply_arbiter_CLK_EN <= saved_reply_arbiter_CLK_EN; end if; - when SENDING_DATA => - comb_REPLY_POOL_DATAREADY <= comb_REPLY_muxed_DATAREADY; - comb_REPLY_POOL_DATA <= comb_REPLY_muxed_DATA; - comb_REPLY_POOL_PACKET_NUM <= comb_REPLY_muxed_PACKET_NUM; + if send_reply_trm = '1' then + if packet_counter /= c_H0 then + next_state <= SEND_PADDING; + else + next_state <= SENDING_REPLY_TRM; + end if; + end if; + + when SEND_PADDING => + comb_REPLY_POOL_DATAREADY <= REPLY_POOL_next_read; + comb_REPLY_POOL_DATA <= (others => '0'); + if packet_counter = c_F3 then next_state <= SENDING_REPLY_TRM; end if; + when SENDING_REPLY_TRM => - comb_REPLY_POOL_DATAREADY <= REPLY_POOL_next_read and not waiting_for_init_finish; - if waiting_for_init_finish = '1' and init_locked = '1' then - release_locked <= '1'; --release only when init has finished too - next_state <= SENDING_DATA; - next_waiting_for_init_finish <= '0'; - end if; + comb_REPLY_POOL_DATAREADY <= REPLY_POOL_next_read; + case packet_counter is when c_F0 => comb_REPLY_POOL_DATA <= (others => '0'); @@ -747,35 +942,49 @@ begin release_locked <= '1'; --release only when init has finished too next_state <= IDLE; elsif REPLY_POOL_next_read = '1' and init_locked = '0' then - next_waiting_for_init_finish <= '1'; + next_state <= WAITING_FOR_INIT; end if; - when c_H0 | others => + when others => -- | c_H0 => comb_REPLY_POOL_DATA <= (others => '0'); comb_REPLY_POOL_DATA(2 downto 0) <= TYPE_TRM; end case; + when WAITING_FOR_INIT => + comb_REPLY_POOL_DATAREADY <= '0'; + if init_locked = '1' then + release_locked <= '1'; --release only when init has finished too + next_state <= IDLE; + end if; end case; end process; reply_fsm_state(0) <= '1' when current_state = IDLE else '0'; - reply_fsm_state(1) <= '1' when current_state = CHECK_DHDR else '0'; - reply_fsm_state(2) <= '1' when current_state = SENDING_DATA else '0'; - reply_fsm_state(3) <= '1' when current_state = SENDING_REPLY_TRM else '0'; + reply_fsm_state(1) <= '1' when current_state = WAIT_FOR_HDR_DATA else '0'; + reply_fsm_state(2) <= '1' when current_state = GEN_LENGTH else '0'; + reply_fsm_state(3) <= '1' when current_state = CHECK_DHDR else '0'; + reply_fsm_state(4) <= '1' when current_state = SENDING_DATA else '0'; --do not change + reply_fsm_state(5) <= '1' when current_state = SEND_PADDING else '0'; + reply_fsm_state(6) <= '1' when current_state = SENDING_REPLY_TRM else '0'; + reply_fsm_state(7) <= '1' when current_state = WAITING_FOR_INIT else '0'; + + process(CLK) begin if rising_edge(CLK) then if RESET = '1' then - current_state <= SENDING_DATA; + current_state <= IDLE; REPLY_POOL_next_read <= '0'; - waiting_for_init_finish <= '0'; - waiting_for_DHDR_word <= (others => '0'); + waiting_for_DHDR_word <= (others => '1'); current_waiting_for_reply <= (others => '1'); + got_all_reply_starts <= '0'; else current_state <= next_state; REPLY_POOL_next_read <= comb_REPLY_POOL_next_read; - waiting_for_init_finish <= next_waiting_for_init_finish; waiting_for_DHDR_word <= next_waiting_for_DHDR_word; current_waiting_for_reply <= next_current_waiting_for_reply; + saved_reply_arbiter_CLK_EN <= reply_arbiter_CLK_EN; + got_all_reply_starts <= not or_all(current_waiting_for_reply); + not_reading_HDR <= not or_all(current_reply_reading_HDR); end if; end if; end process; @@ -832,7 +1041,7 @@ begin STAT_DEBUG(8) <= '0';--REPLY_DATA_IN(46); STAT_DEBUG(9) <= locked; STAT_DEBUG(13 downto 10) <= reply_fsm_state(3 downto 0); - STAT_DEBUG(15 downto 14) <= (others => '0'); + STAT_DEBUG(31 downto 14) <= (others => '0'); --STAT(15 downto 8) <= data_counter; STAT_POINTS_locked(POINT_NUMBER-1 downto 0) <= not got_trm; STAT_POINTS_locked(31 downto POINT_NUMBER) <= (others => '0'); diff --git a/trb_net16_obuf.vhd b/trb_net16_obuf.vhd index 6e28936..93fa046 100644 --- a/trb_net16_obuf.vhd +++ b/trb_net16_obuf.vhd @@ -203,7 +203,7 @@ begin current_DATA_word <= INT_DATA_IN; if transfer_counter = c_F0 then current_EOB_word <= CRC; - if saved_packet_type = TYPE_TRM then + if saved_packet_type = TYPE_TRM and USE_CHECKSUM = c_YES then current_DATA_word <= CRC; end if; elsif transfer_counter = c_F1 then diff --git a/trb_net_priority_arbiter.vhd b/trb_net_priority_arbiter.vhd index a2a4ed5..4f7abeb 100755 --- a/trb_net_priority_arbiter.vhd +++ b/trb_net_priority_arbiter.vhd @@ -169,6 +169,9 @@ architecture trb_net_priority_arbiter_arch of trb_net_priority_arbiter is current_rr_mask <= next_rr_mask; current_final_pattern <= next_final_pattern; current_rr_mask <= next_rr_mask; +-- if ENABLE = '0' then +-- current_final_pattern <= (others => '0'); +-- end if; end if; end if; end process; diff --git a/trb_net_std.vhd b/trb_net_std.vhd index bcb711e..e90ed72 100644 --- a/trb_net_std.vhd +++ b/trb_net_std.vhd @@ -149,6 +149,9 @@ package trb_net_std is function MAX(x : integer; y : integer) return integer; + function Log2( input:integer ) return integer; + function count_ones( input:std_logic_vector ) return integer; + end package trb_net_std; package body trb_net_std is @@ -242,5 +245,31 @@ package body trb_net_std is end if; end MAX; + + function Log2( input:integer ) return integer is + variable temp,log:integer; + begin + temp:=input; + log:=0; + while (temp /= 0) loop + temp:=temp/2; + log:=log+1; + end loop; + return log; + end function log2; + + function count_ones( input:std_logic_vector ) return integer is + variable temp:integer; + begin + temp := 0; + for i in input'range loop + if input(i) = '1' then + temp := temp + 1; + end if; + end loop; + return temp; + end function count_ones; + + end package body trb_net_std; -- 2.43.0