From d16b6d495c68fc8f32b28d0ec6e7141dd304b2d1 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Thu, 19 Nov 2020 17:46:44 +0100 Subject: [PATCH] add trigger box files --- pinout/trb3sc_triggerbox.lpf | 379 +++++ triggerbox/code/coincidence.vhd | 58 + triggerbox/code/groups.vhd | 40 + triggerbox/code/input_processor.vhd | 171 +++ triggerbox/code/monitor_output.vhd | 43 + triggerbox/code/multiplicity.vhd | 85 ++ triggerbox/code/scalers.vhd | 97 ++ triggerbox/code/tb_triggerbox.vhd | 54 + triggerbox/code/triggerbox.vhd | 484 +++++++ triggerbox/code/triggerbox_pkg.vhd | 39 + triggerbox/compile.pl | 1 + triggerbox/config.vhd | 113 ++ triggerbox/config_compile_frankfurt.pl | 20 + triggerbox/cores/delay_shift_reg.ipx | 10 + triggerbox/cores/delay_shift_reg.lpc | 44 + triggerbox/cores/delay_shift_reg.vhd | 696 +++++++++ triggerbox/par.p2t | 21 + triggerbox/sim/triggerbox.mpf | 1805 ++++++++++++++++++++++++ triggerbox/trb3sc_triggerbox.lpf | 181 +++ triggerbox/trb3sc_triggerbox.prj | 256 ++++ triggerbox/trb3sc_triggerbox.sdc | 5 + triggerbox/trb3sc_triggerbox.vhd | 450 ++++++ 22 files changed, 5052 insertions(+) create mode 100644 pinout/trb3sc_triggerbox.lpf create mode 100644 triggerbox/code/coincidence.vhd create mode 100644 triggerbox/code/groups.vhd create mode 100644 triggerbox/code/input_processor.vhd create mode 100644 triggerbox/code/monitor_output.vhd create mode 100644 triggerbox/code/multiplicity.vhd create mode 100644 triggerbox/code/scalers.vhd create mode 100644 triggerbox/code/tb_triggerbox.vhd create mode 100644 triggerbox/code/triggerbox.vhd create mode 100644 triggerbox/code/triggerbox_pkg.vhd create mode 120000 triggerbox/compile.pl create mode 100644 triggerbox/config.vhd create mode 100644 triggerbox/config_compile_frankfurt.pl create mode 100644 triggerbox/cores/delay_shift_reg.ipx create mode 100644 triggerbox/cores/delay_shift_reg.lpc create mode 100644 triggerbox/cores/delay_shift_reg.vhd create mode 100644 triggerbox/par.p2t create mode 100644 triggerbox/sim/triggerbox.mpf create mode 100644 triggerbox/trb3sc_triggerbox.lpf create mode 100644 triggerbox/trb3sc_triggerbox.prj create mode 100644 triggerbox/trb3sc_triggerbox.sdc create mode 100644 triggerbox/trb3sc_triggerbox.vhd diff --git a/pinout/trb3sc_triggerbox.lpf b/pinout/trb3sc_triggerbox.lpf new file mode 100644 index 0000000..3b4dd17 --- /dev/null +++ b/pinout/trb3sc_triggerbox.lpf @@ -0,0 +1,379 @@ +################################################################# +# Clock I/O +################################################################# +LOCATE COMP "CLK_SUPPL_PLL_RIGHT" SITE "Y28"; #was SUPPL_CLOCK1_P +LOCATE COMP "CLK_SUPPL_PLL_LEFT" SITE "Y9"; #was SUPPL_CLOCK2_P +LOCATE COMP "CLK_SUPPL_PCLK" SITE "V9"; #was SUPPL_CLOCK3_P +LOCATE COMP "CLK_CORE_PCLK" SITE "U9"; #was "CORE_CLOCK0_P" +LOCATE COMP "CLK_CORE_PLL_LEFT" SITE "U6"; #was "CORE_CLOCK1_P" +LOCATE COMP "CLK_CORE_PLL_RIGHT" SITE "V34"; #was "CORE_CLOCK2_P" +LOCATE COMP "CLK_EXT_PCLK" SITE "U28"; #was "EXT_CLOCK0_P" +LOCATE COMP "CLK_EXT_PLL_RIGHT" SITE "P30"; #was "EXT_CLOCK1_P" +LOCATE COMP "CLK_EXT_PLL_LEFT" SITE "N7"; #was "EXT_CLOCK2_P" +DEFINE PORT GROUP "CLK_group" "CLK*" ; +IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 DIFFRESISTOR=100; + + +LOCATE COMP "TRIG_PLL" SITE "AJ34"; +LOCATE COMP "TRIG_RIGHT" SITE "P34"; +LOCATE COMP "TRIG_LEFT" SITE "T6"; +DEFINE PORT GROUP "TRIG_group" "TRIG*" ; +IOBUF GROUP "TRIG_group" IO_TYPE=LVDS25 DIFFRESISTOR=100; + + + + +################################################################# +# Backplane I/O +################################################################# +LOCATE COMP "BACK_GPIO_0" SITE "C26"; +LOCATE COMP "BACK_GPIO_1" SITE "D26"; +LOCATE COMP "BACK_GPIO_2" SITE "B27"; +LOCATE COMP "BACK_GPIO_3" SITE "C27"; +LOCATE COMP "BACK_GPIO_4" SITE "D27"; +LOCATE COMP "BACK_GPIO_5" SITE "E27"; +LOCATE COMP "BACK_GPIO_6" SITE "B28"; +LOCATE COMP "BACK_GPIO_7" SITE "A28"; +LOCATE COMP "BACK_GPIO_8" SITE "A26"; +LOCATE COMP "BACK_GPIO_9" SITE "A27"; +LOCATE COMP "BACK_GPIO_10" SITE "A29"; +LOCATE COMP "BACK_GPIO_11" SITE "A30"; +LOCATE COMP "BACK_GPIO_12" SITE "H26"; +LOCATE COMP "BACK_GPIO_13" SITE "H25"; +LOCATE COMP "BACK_GPIO_14" SITE "A31"; +LOCATE COMP "BACK_GPIO_15" SITE "B31"; +DEFINE PORT GROUP "BACK_GPIO_group" "BACK_GPIO*" ; +IOBUF GROUP "BACK_GPIO_group" IO_TYPE=LVCMOS25 PULLMODE=UP; + +LOCATE COMP "BACK_LVDS_0" SITE "V2"; +LOCATE COMP "BACK_LVDS_1" SITE "T4"; +# LOCATE COMP "BACK_LVDS_0_N" SITE "V1"; +# LOCATE COMP "BACK_LVDS_1_N" SITE "T3"; +DEFINE PORT GROUP "BACK_LVDS_group" "BACK_LVDS*" ; +IOBUF GROUP "BACK_LVDS_group" IO_TYPE=LVDS25; + +LOCATE COMP "BACK_3V3_0" SITE "E11"; +LOCATE COMP "BACK_3V3_1" SITE "F12"; +LOCATE COMP "BACK_3V3_2" SITE "F10"; +LOCATE COMP "BACK_3V3_3" SITE "E10"; +DEFINE PORT GROUP "BACK_3V3_group" "BACK_3V3*" ; +IOBUF GROUP "BACK_3V3_group" IO_TYPE=LVTTL33 PULLMODE=DOWN; + +################################################################# +# AddOn Connector +################################################################# +LOCATE COMP "INP_28" SITE "AA2"; #was "DQLL0_0_P" 1 +LOCATE COMP "INP_12" SITE "AB2"; #was "DQLL0_1_P" 5 +LOCATE COMP "INP_15" SITE "AA4"; #was "DQLL0_2_P" 9 +LOCATE COMP "INP_29" SITE "AA10"; #was "DQSLL0_T" 13 +LOCATE COMP "INP_24" SITE "AA5"; #was "DQLL0_3_P" 17 +LOCATE COMP "INP_14" SITE "Y7"; #was "DQLL0_4_P" 21 +LOCATE COMP "INP_30" SITE "AC5"; #was "DQLL2_0_P" 25 +LOCATE COMP "INP_9" SITE "AC2"; #was "DQLL2_1_P" 29 +LOCATE COMP "INP_31" SITE "AB4"; #was "DQLL2_2_P" 33 +LOCATE COMP "INP_13" SITE "AD5"; #was "DQSLL2_T" 37 +LOCATE COMP "INP_25" SITE "AA9"; #was "DQLL2_3_P" 41 +LOCATE COMP "INP_8" SITE "AB7"; #was "DQLL2_4_P" 45 +LOCATE COMP "INP_26" SITE "N4"; #was "DQUL3_0_P" 49 +LOCATE COMP "INP_27" SITE "N2"; #was "DQUL3_1_P" 53 +LOCATE COMP "INP_11" SITE "M5"; #was "DQUL3_2_P" 57 +LOCATE COMP "INP_10" SITE "M10"; #was "DQSUL3_T" 61 +LOCATE COMP "INP_7" SITE "AE4"; #was "DQLL3_0_P" 2 +LOCATE COMP "INP_20" SITE "AB10"; #was "DQLL3_1_P" 6 +LOCATE COMP "INP_21" SITE "AE2"; #was "DQLL3_2_P" 10 +LOCATE COMP "INP_5" SITE "AJ1"; #was "DQSLL3_T" 14 +LOCATE COMP "INP_6" SITE "AD4"; #was "DQLL3_3_P" 18 +LOCATE COMP "INP_4" SITE "AC9"; #was "DQLL3_4_P" 22 +LOCATE COMP "INP_22" SITE "Y2"; #was "DQLL1_0_P" 26 +LOCATE COMP "INP_16" SITE "W4"; #was "DQLL1_1_P" 30 +LOCATE COMP "INP_23" SITE "W2"; #was "DQLL1_2_P" 34 +LOCATE COMP "INP_17" SITE "W6"; #was "DQSLL1_T" 38 +LOCATE COMP "INP_3" SITE "W8"; #was "DQLL1_3_P" 42 +LOCATE COMP "INP_1" SITE "Y8"; #was "DQLL1_4_P" 46 +LOCATE COMP "INP_2" SITE "F2"; #was "DQUL2_0_P" 50 +LOCATE COMP "INP_0" SITE "F3"; #was "DQUL2_1_P" 54 +LOCATE COMP "X_1" SITE "G2"; #was "DQUL2_2_P" 58 +LOCATE COMP "INP_18" SITE "G3"; #was "DQSUL2_T" 62 +LOCATE COMP "INP_19" SITE "N9"; #was "DQSUL0_T" 86 +LOCATE COMP "X_2" SITE "M4"; #was "DQUL0_1_P" 78 +LOCATE COMP "X_3" SITE "K6"; #was "DQUL0_2_P" 82 +LOCATE COMP "X_4" SITE "M7"; #was "DQUL0_4_P" 94 + +LOCATE COMP "INP_60" SITE "L26"; #was "DQUR0_0_P" 105 +LOCATE COMP "INP_44" SITE "L32"; #was "DQUR0_1_P" 109 +LOCATE COMP "INP_47" SITE "M26"; #was "DQSUR0_T" 113 +LOCATE COMP "INP_61" SITE "L34"; #was "DQUR0_2_P" 117 +LOCATE COMP "INP_56" SITE "K29"; #was "DQUR0_3_P" 121 +LOCATE COMP "INP_46" SITE "K34"; #was "DQUR0_4_P" 125 +LOCATE COMP "INP_62" SITE "AB34"; #was "DQLR0_0_P" 129 +LOCATE COMP "INP_41" SITE "AA25"; #was "DQLR0_1_P" 133 +LOCATE COMP "INP_63" SITE "AC34"; #was "DQLR0_2_P" 137 +LOCATE COMP "INP_45" SITE "AB30"; #was "DQSLR0_T" 141 +LOCATE COMP "INP_57" SITE "AA31"; #was "DQLR0_3_P" 145 +LOCATE COMP "INP_40" SITE "AA28"; #was "DQLR0_4_P" 149 +LOCATE COMP "INP_58" SITE "AD31"; #was "DQLR1_0_P" 169 +LOCATE COMP "INP_59" SITE "AB32"; #was "DQLR1_1_P" 173 +LOCATE COMP "INP_43" SITE "AE34"; #was "DQLR1_2_P" 177 +LOCATE COMP "INP_42" SITE "AB26"; #was "DQSLR1_T" 181 +LOCATE COMP "INP_39" SITE "N30"; #was "DQUR1_0_P" 106 +LOCATE COMP "INP_52" SITE "N26"; #was "DQUR1_1_P" 110 +LOCATE COMP "INP_53" SITE "N32"; #was "DQUR1_2_P" 114 +LOCATE COMP "INP_37" SITE "N27"; #was "DQSUR1_T" 118 +LOCATE COMP "INP_38" SITE "N34"; #was "DQUR1_3_P" 122 +LOCATE COMP "INP_36" SITE "P28"; #was "DQUR1_4_P" 126 +LOCATE COMP "INP_54" SITE "T32"; #was "DQUR2_0_P" 130 +LOCATE COMP "INP_48" SITE "T26"; #was "DQUR2_1_P" 134 +LOCATE COMP "INP_55" SITE "U32"; #was "DQUR2_2_P" 138 +LOCATE COMP "INP_49" SITE "T30"; #was "DQSUR2_T" 142 +LOCATE COMP "INP_35" SITE "T34"; #was "DQUR2_3_P" 146 +LOCATE COMP "INP_33" SITE "U26"; #was "DQUR2_4_P" 150 +LOCATE COMP "INP_34" SITE "W30"; #was "DQLR2_0_P" 170 +LOCATE COMP "INP_32" SITE "W27"; #was "DQLR2_1_P" 174 +LOCATE COMP "X_5" SITE "W34"; #was "DQLR2_2_P" 178 +LOCATE COMP "INP_50" SITE "Y30"; #was "DQSLR2_T" 182 +LOCATE COMP "INP_51" SITE "AF34"; #was "DQLR1_4_P" 189 +LOCATE COMP "X_6" SITE "AD33"; #was "DQLR1_3_P" 185 +LOCATE COMP "X_7" SITE "Y34"; #was "DQLR2_3_P" 186 +LOCATE COMP "X_8" SITE "Y26"; #was "DQLR2_4_P" 190 + +#on KEL1 +LOCATE COMP "INP_64" SITE "AP5"; +LOCATE COMP "INP_65" SITE "AP2"; +LOCATE COMP "INP_66" SITE "AN1"; +LOCATE COMP "INP_67" SITE "AN3"; +LOCATE COMP "INP_68" SITE "AL5"; +LOCATE COMP "INP_69" SITE "AM6"; +LOCATE COMP "INP_70" SITE "AL4"; +LOCATE COMP "INP_71" SITE "AJ5"; +LOCATE COMP "INP_72" SITE "AJ2"; +LOCATE COMP "INP_73" SITE "AL3"; +LOCATE COMP "INP_74" SITE "AD9"; +LOCATE COMP "INP_75" SITE "AJ4"; +LOCATE COMP "INP_76" SITE "V4"; +LOCATE COMP "INP_77" SITE "V5"; +LOCATE COMP "INP_78" SITE "T9"; +LOCATE COMP "INP_79" SITE "T2"; + #on KEL2 +LOCATE COMP "INP_80" SITE "AP29"; +LOCATE COMP "INP_81" SITE "AP33"; +LOCATE COMP "INP_82" SITE "AN34"; +LOCATE COMP "INP_83" SITE "AP31"; +LOCATE COMP "INP_84" SITE "AN32"; +LOCATE COMP "INP_85" SITE "AM29"; +LOCATE COMP "INP_86" SITE "AL31"; +LOCATE COMP "INP_87" SITE "AL30"; +LOCATE COMP "INP_88" SITE "AL34"; +LOCATE COMP "INP_89" SITE "AJ31"; +LOCATE COMP "INP_90" SITE "AH33"; +LOCATE COMP "INP_91" SITE "AL32"; +LOCATE COMP "INP_92" SITE "AF32"; +LOCATE COMP "INP_93" SITE "AE32"; +LOCATE COMP "INP_94" SITE "AE30"; +LOCATE COMP "INP_95" SITE "AD26"; + +DEFINE PORT GROUP "INP_group" "INP*" ; +IOBUF GROUP "INP_group" IO_TYPE=LVDS25 DIFFRESISTOR=100; +DEFINE PORT GROUP "X_group" "X*" ; +IOBUF GROUP "X_group" IO_TYPE=LVDS25; + + +################################################################# +# SPI +################################################################# +LOCATE COMP "DAC_IN_SDI_5" SITE "P7"; +LOCATE COMP "DAC_IN_SDI_6" SITE "M29"; + +DEFINE PORT GROUP "IN_group" "DAC_IN*" ; +IOBUF GROUP "IN_group" IO_TYPE=LVDS25 DIFFRESISTOR=100; + +LOCATE COMP "DAC_OUT_SDO_5" SITE "R8"; +LOCATE COMP "DAC_OUT_SCK_5" SITE "R2"; +LOCATE COMP "DAC_OUT_CS_5" SITE "P9"; +LOCATE COMP "DAC_OUT_SDO_6" SITE "AC28"; +LOCATE COMP "DAC_OUT_SCK_6" SITE "M34"; +LOCATE COMP "DAC_OUT_CS_6" SITE "L28"; + +DEFINE PORT GROUP "OUT_group" "DAC_OUT*" ; +IOBUF GROUP "OUT_group" IO_TYPE=LVDS25 DIFFRESISTOR=OFF; + + +################################################################# +# Pin-header IO +################################################################# +LOCATE COMP "HDR_IO_1" SITE "AP28"; +LOCATE COMP "HDR_IO_2" SITE "AN28"; +LOCATE COMP "HDR_IO_3" SITE "AP27"; +LOCATE COMP "HDR_IO_4" SITE "AN27"; +LOCATE COMP "HDR_IO_5" SITE "AM27"; +LOCATE COMP "HDR_IO_6" SITE "AL27"; +LOCATE COMP "HDR_IO_7" SITE "AH26"; +LOCATE COMP "HDR_IO_8" SITE "AG26"; +LOCATE COMP "HDR_IO_9" SITE "AM28"; +LOCATE COMP "HDR_IO_10" SITE "AL28"; +DEFINE PORT GROUP "HDR_group" "HDR*" ; +IOBUF GROUP "HDR_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN ; + + +################################################################# +# Many LED +################################################################# +LOCATE COMP "LED_RJ_GREEN_0" SITE "C25"; +LOCATE COMP "LED_RJ_RED_0" SITE "D25"; +LOCATE COMP "LED_GREEN" SITE "D24"; +LOCATE COMP "LED_ORANGE" SITE "E24"; +LOCATE COMP "LED_RED" SITE "K23"; +LOCATE COMP "LED_RJ_GREEN_1" SITE "G26"; +LOCATE COMP "LED_RJ_RED_1" SITE "G25"; +LOCATE COMP "LED_YELLOW" SITE "K24"; +IOBUF PORT "LED_RJ_GREEN_0" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_RJ_RED_0" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_GREEN" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_ORANGE" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_RED" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_RJ_GREEN_1" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_RJ_RED_1" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_YELLOW" IO_TYPE=LVCMOS25 ; + +LOCATE COMP "LED_SFP_GREEN_0" SITE "B4"; +LOCATE COMP "LED_SFP_GREEN_1" SITE "A6"; +LOCATE COMP "LED_SFP_RED_0" SITE "A3"; +LOCATE COMP "LED_SFP_RED_1" SITE "A8"; +DEFINE PORT GROUP "LED_SFP_group" "LED_SFP*" ; +IOBUF GROUP "LED_SFP_group" IO_TYPE=LVTTL33 ; + +LOCATE COMP "LED_WHITE_0" SITE "A32"; +LOCATE COMP "LED_WHITE_1" SITE "A33"; +DEFINE PORT GROUP "LED_WHITE_group" "LED_WHITE*" ; +IOBUF GROUP "LED_WHITE_group" IO_TYPE=LVTTL33 ; + +################################################################# +# SFP Control Signals +################################################################# +LOCATE COMP "SFP_LOS_0" SITE "B6"; +LOCATE COMP "SFP_LOS_1" SITE "C9"; +LOCATE COMP "SFP_MOD0_0" SITE "A5"; +LOCATE COMP "SFP_MOD0_1" SITE "K11"; +LOCATE COMP "SFP_MOD1_0" SITE "B7"; +LOCATE COMP "SFP_MOD1_1" SITE "J11"; +LOCATE COMP "SFP_MOD2_0" SITE "A7"; +LOCATE COMP "SFP_MOD2_1" SITE "D9"; +# LOCATE COMP "SFP_RATE_SEL_0" SITE "A4"; +# LOCATE COMP "SFP_RATE_SEL_1" SITE "C8"; +LOCATE COMP "SFP_TX_DIS_0" SITE "D6"; +LOCATE COMP "SFP_TX_DIS_1" SITE "A9"; +# LOCATE COMP "SFP_TX_FAULT_0" SITE "C5"; +# LOCATE COMP "SFP_TX_FAULT_1" SITE "B8"; +DEFINE PORT GROUP "SFP_group" "SFP*" ; +IOBUF GROUP "SFP_group" IO_TYPE=LVTTL33 ; + + + +################################################################# +# Serdes Output Switch +################################################################# +LOCATE COMP "PCSSW_ENSMB" SITE "B3"; +LOCATE COMP "PCSSW_EQ_0" SITE "B1"; +LOCATE COMP "PCSSW_EQ_1" SITE "B2"; +LOCATE COMP "PCSSW_EQ_2" SITE "E4"; +LOCATE COMP "PCSSW_EQ_3" SITE "D4"; +LOCATE COMP "PCSSW_PE_0" SITE "C3"; +LOCATE COMP "PCSSW_PE_1" SITE "C4"; +LOCATE COMP "PCSSW_PE_2" SITE "D3"; +LOCATE COMP "PCSSW_PE_3" SITE "C2"; +LOCATE COMP "PCSSW_1" SITE "D5"; +LOCATE COMP "PCSSW_0" SITE "A2"; +LOCATE COMP "PCSSW_2" SITE "E13"; +LOCATE COMP "PCSSW_3" SITE "F13"; +LOCATE COMP "PCSSW_4" SITE "G13"; +LOCATE COMP "PCSSW_5" SITE "H14"; +LOCATE COMP "PCSSW_6" SITE "A13"; +LOCATE COMP "PCSSW_7" SITE "B13"; +DEFINE PORT GROUP "PCSSW_group" "PCSSW*" ; +IOBUF GROUP "PCSSW_group" IO_TYPE=LVTTL33 PULLMODE=DOWN ; + + +################################################################# +# ADC +################################################################# +LOCATE COMP "ADC_CLK" SITE "A14"; +LOCATE COMP "ADC_CS" SITE "B14"; +LOCATE COMP "ADC_DIN" SITE "G17"; +LOCATE COMP "ADC_DOUT" SITE "G16"; +IOBUF PORT "ADC_CLK" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=4 ; +IOBUF PORT "ADC_CS" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=4 ; +IOBUF PORT "ADC_DIN" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=4 ; +IOBUF PORT "ADC_DOUT" IO_TYPE=LVTTL33 PULLMODE=UP ; + + + +################################################################# +# RJ-45 connectors +################################################################# +LOCATE COMP "RJ_IO_0" SITE "R28"; +LOCATE COMP "RJ_IO_1" SITE "R31"; +LOCATE COMP "RJ_IO_2" SITE "R26"; +LOCATE COMP "RJ_IO_3" SITE "R34"; +#LOCATE COMP "RJ_IO_1_N" SITE "R27"; +#LOCATE COMP "RJ_IO_2_N" SITE "R30"; +#LOCATE COMP "RJ_IO_3_N" SITE "R25"; +#LOCATE COMP "RJ_IO_4_N" SITE "R33"; +IOBUF PORT "RJ_IO_0" IO_TYPE=LVDS25 ; +IOBUF PORT "RJ_IO_1" IO_TYPE=LVDS25 ; +IOBUF PORT "RJ_IO_2" IO_TYPE=LVDS25E ; +IOBUF PORT "RJ_IO_3" IO_TYPE=LVDS25E ; + + +LOCATE COMP "SPARE_IN_0" SITE "K31"; +LOCATE COMP "SPARE_IN_1" SITE "R4"; +#LOCATE COMP "SPARE_IN0_N" SITE "K32"; +#LOCATE COMP "SPARE_IN1_N" SITE "R3"; +IOBUF PORT "SPARE_IN_1" IO_TYPE=LVDS25 DIFFRESISTOR=100 ; +IOBUF PORT "SPARE_IN_2" IO_TYPE=LVDS25 DIFFRESISTOR=100 ; + + + +################################################################# +# Flash ROM and Reboot +################################################################# +LOCATE COMP "FLASH_CLK" SITE "F34"; #was "SPI_CLK" +LOCATE COMP "FLASH_CS" SITE "D34"; #was "SPI_CS" +LOCATE COMP "FLASH_IN" SITE "F33"; #was "SPI_IN" +LOCATE COMP "FLASH_OUT" SITE "F32"; #was "SPI_OUT" +LOCATE COMP "PROGRAMN" SITE "C31"; + +DEFINE PORT GROUP "FLASH_group" "FLASH*" ; +IOBUF GROUP "FLASH_group" IO_TYPE=LVTTL33 PULLMODE=NONE; +IOBUF PORT "PROGRAMN" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8 ; + +LOCATE COMP "ENPIRION_CLOCK" SITE "H23"; +IOBUF PORT "ENPIRION_CLOCK" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; + + +################################################################# +# Misc +################################################################# +LOCATE COMP "TEMPSENS" SITE "J13"; #was TEMP_OWB +IOBUF PORT "TEMPSENS" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8 ; + + +################################################################# +# Trigger I/O +################################################################# +LOCATE COMP "TEST_LINE_0" SITE "A19"; +LOCATE COMP "TEST_LINE_1" SITE "B19"; +LOCATE COMP "TEST_LINE_2" SITE "K20"; +LOCATE COMP "TEST_LINE_3" SITE "L19"; +LOCATE COMP "TEST_LINE_4" SITE "C19"; +LOCATE COMP "TEST_LINE_5" SITE "D19"; +LOCATE COMP "TEST_LINE_6" SITE "J19"; +LOCATE COMP "TEST_LINE_7" SITE "K19"; +LOCATE COMP "TEST_LINE_8" SITE "A20"; +LOCATE COMP "TEST_LINE_9" SITE "B20"; +LOCATE COMP "TEST_LINE_10" SITE "G20"; +LOCATE COMP "TEST_LINE_11" SITE "G21"; +LOCATE COMP "TEST_LINE_12" SITE "C20"; +LOCATE COMP "TEST_LINE_13" SITE "D20"; +LOCATE COMP "TEST_LINE_14" SITE "F21"; +LOCATE COMP "TEST_LINE_15" SITE "F22"; +DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ; +IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=8; diff --git a/triggerbox/code/coincidence.vhd b/triggerbox/code/coincidence.vhd new file mode 100644 index 0000000..9c09ee4 --- /dev/null +++ b/triggerbox/code/coincidence.vhd @@ -0,0 +1,58 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.trb_net_std.all; + use work.config.all; + use work.triggerbox_pkg.all; + + +entity coincidence is + generic ( + NUM_INPUTS : integer range 1 to 256 := 32 + ); + port ( + CLK : in std_logic; + INP : in std_logic_vector(NUM_INPUTS-1 downto 0); + OUTP : out std_logic; + CONF : in CONF_coincidence_t + ); +end entity; + + +architecture arch of coincidence is + +attribute syn_hier : string; +attribute syn_hier of arch : architecture is "fixed"; + +attribute HGROUP: string; +attribute HGROUP of arch : architecture is "coinc_proc"; +attribute BBOX: string; +attribute BBOX of arch: architecture is "7,7"; + +signal reg_inp : std_logic_vector(INP'range); +signal sel1,sel2,sel3 : std_logic; + + attribute syn_preserve : boolean; + attribute syn_preserve of reg_inp : signal is true; + + attribute syn_keep : boolean; + attribute syn_keep of reg_inp : signal is true; + +-- (1 or 2) and 3 +begin +reg_inp <= INP when rising_edge(CLK); + +sel1 <= reg_inp(CONF.mux_input1); +sel2 <= reg_inp(CONF.mux_input2); +sel3 <= reg_inp(CONF.mux_input3); + +OUTP <= (((sel1 xor CONF.invert(0)) and CONF.enable(0)) + or ((sel2 xor CONF.invert(1)) and CONF.enable(1))) + + and ((sel3 xor CONF.invert(2)) or not CONF.enable(2)) + and CONF.module_enable + when rising_edge(CLK); + +end architecture; diff --git a/triggerbox/code/groups.vhd b/triggerbox/code/groups.vhd new file mode 100644 index 0000000..848013f --- /dev/null +++ b/triggerbox/code/groups.vhd @@ -0,0 +1,40 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.trb_net_std.all; + use work.config.all; + use work.triggerbox_pkg.all; + + +entity groups is + generic ( + NUM_INPUTS : integer range 0 to 256 := 128 + ); + port ( + CLK : in std_logic; + INP : in std_logic_vector(NUM_INPUTS-1 downto 0); + OUTP : out std_logic; + CONF : in std_logic_vector(NUM_INPUTS-1 downto 0) + ); +end entity; + + +architecture arch of groups is +attribute syn_hier : string; +attribute syn_hier of arch : architecture is "fixed"; + +attribute HGROUP: string; +attribute BBOX: string; +attribute HGROUP of arch : architecture is "groups"; +attribute BBOX of arch: architecture is "5,5"; + + +begin + + + OUTP <= or (CONF and INP) when rising_edge(CLK); + + +end architecture; diff --git a/triggerbox/code/input_processor.vhd b/triggerbox/code/input_processor.vhd new file mode 100644 index 0000000..ed77355 --- /dev/null +++ b/triggerbox/code/input_processor.vhd @@ -0,0 +1,171 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.trb_net_std.all; + use work.config.all; + use work.triggerbox_pkg.all; + + +entity input_processor is + port ( + CLK : in std_logic; + RESET : in std_logic; + INP : in std_logic; + OUTP : out std_logic; + TICK_MS : in std_logic; + TICK_US : in std_logic; + CONF : in CONF_input_processor_t + ); +end entity; + + +architecture arch of input_processor is +attribute syn_hier : string; +attribute syn_hier of arch : architecture is "fixed"; + +attribute HGROUP: string; +attribute BBOX: string; +attribute HGROUP of arch : architecture is "input_proc"; +attribute BBOX of arch: architecture is "4,16"; + +signal reg_inp, gated_inp, edged_inp, stretched_inp, reg_stretched_inp, delayed_inp, downscaled_inp : std_logic; +signal temp_edged_inp, temp_downscaled_inp, temp_stretched_inp, temp_delayed_inp : std_logic; +signal reg_gated_inp,reg2_gated_inp : std_logic; + +signal reg_tick_us, reg_tick_ms : std_logic; +signal timer : unsigned(11 downto 0); +signal counter : unsigned(15 downto 0); + + + attribute syn_preserve : boolean; + attribute syn_preserve of reg_tick_us : signal is true; + attribute syn_preserve of reg_tick_ms : signal is true; + + attribute syn_keep : boolean; + attribute syn_keep of reg_tick_us : signal is true; + attribute syn_keep of reg_tick_ms : signal is true; + + attribute syn_maxfan : integer; + attribute syn_maxfan of OUTP : signal is 5; + +begin + + reg_tick_us <= TICK_US when rising_edge(CLK); + reg_tick_ms <= TICK_MS when rising_edge(CLK); + + PROC_REG : process begin + wait until rising_edge(CLK); + reg_inp <= INP; + end process; + + --TODO: add async stretcher option + +-------------------------------- +-- Gate / Invert +-------------------------------- + + gated_inp <= reg_INP when CONF.enable = '1' and CONF.invert = '0' else + not reg_INP when CONF.enable = '1' and CONF.invert = '1' else + '0'; + + reg_gated_inp <= gated_inp when rising_edge(CLK); +-- reg2_gated_inp <= reg_gated_inp when rising_edge(CLK); + +-------------------------------- +-- Edge Detect +-------------------------------- + PROC_EDGE : process(CLK) + begin + if rising_edge(CLK) then + temp_edged_inp <= not reg_gated_inp and gated_inp; + end if; + end process; + + edged_inp <= gated_inp when CONF.edge_detect = '0' else --and CONF.downscale = x"0" + temp_edged_inp; + + +-- -------------------------------- +-- -- Downscale +-- -------------------------------- +-- PROC_DOWNSCALE : process(CLK) +-- variable countmax : unsigned(15 downto 0); +-- begin +-- if rising_edge(CLK) then +-- temp_downscaled_inp <= '0'; +-- if RESET = '1' then +-- counter <= (others => '0'); +-- else +-- if reg_gated_inp = '0' and gated_inp = '1' then +-- if counter > 0 then +-- counter <= counter - 1; +-- else +-- countmax := (others => '0'); +-- countmax(to_integer(unsigned(CONF.downscale))) := '1'; +-- counter <= countmax-1; +-- temp_downscaled_inp <= '1'; +-- end if; +-- end if; +-- end if; +-- end if; +-- end process; +-- +-- downscaled_inp <= edged_inp when CONF.downscale = x"0" else +-- temp_downscaled_inp; + +-------------------------------- +-- Stretch +-------------------------------- + PROC_STRETCH : process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + timer <= (others => '0'); + temp_stretched_inp <= '0'; + elsif (edged_inp = '1') then + timer <= unsigned(CONF.stretch_value); + temp_stretched_inp <= '1'; + elsif timer = 0 then + temp_stretched_inp <= '0'; + elsif CONF.stretch_unit = "01" + or (CONF.stretch_unit = "10" and reg_tick_us = '1') + or (CONF.stretch_unit = "11" and reg_tick_ms = '1') then + timer <= timer - 1; + end if; + end if; + end process; + + stretched_inp <= edged_inp when CONF.stretch_unit = "00" else + temp_stretched_inp; + + + +-------------------------------- +-- Delay +-------------------------------- + reg_stretched_inp <= stretched_inp when rising_edge(CLK); + + THE_SHIFT: entity work.delay_shift_reg + port map( + Din(0) => reg_stretched_inp, + Addr => CONF.delay(7 downto 0), + Clock => CLK, + ClockEn => '1', + Reset => RESET, + Q(0) => temp_delayed_inp + ); + + delayed_inp <= stretched_inp when CONF.delay(7 downto 0) = x"00" else + temp_delayed_inp; + + + +-------------------------------- +-- Output +-------------------------------- + + OUTP <= delayed_inp when rising_edge(CLK); + +end architecture; diff --git a/triggerbox/code/monitor_output.vhd b/triggerbox/code/monitor_output.vhd new file mode 100644 index 0000000..9f56e49 --- /dev/null +++ b/triggerbox/code/monitor_output.vhd @@ -0,0 +1,43 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.trb_net_std.all; + use work.config.all; + use work.triggerbox_pkg.all; + + +entity monitor_output is + generic ( + NUM_INPUTS : integer range 1 to 512 := 32 + ); + port ( + CLK : in std_logic; + INP : in std_logic_vector(NUM_INPUTS-1 downto 0); + OUTP : out std_logic; + CONF : in integer range 0 to 511 + ); +end entity; + + +architecture arch of monitor_output is + +attribute syn_hier : string; +attribute syn_hier of arch : architecture is "fixed"; + +attribute HGROUP: string; +attribute HGROUP of arch : architecture is "monitor_output"; + +signal reg_inp : std_logic_vector(INP'range); + +begin + + reg_inp <= INP when rising_edge(CLK); + OUTP <= reg_inp(CONF) when rising_edge(CLK); + + +end architecture; + + + diff --git a/triggerbox/code/multiplicity.vhd b/triggerbox/code/multiplicity.vhd new file mode 100644 index 0000000..7b449ce --- /dev/null +++ b/triggerbox/code/multiplicity.vhd @@ -0,0 +1,85 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.trb_net_std.all; + use work.config.all; + use work.triggerbox_pkg.all; + + +entity multiplicity is + generic ( + NUM_INPUTS : integer range 1 to 96 := 96 + ); + port ( + CLK : in std_logic; + INP : in std_logic_vector(NUM_INPUTS-1 downto 0); + OUTP : out std_logic; + CONF : in CONF_multiplicity_t + ); +end entity; + + +architecture arch of multiplicity is + +attribute syn_hier : string; +attribute syn_hier of arch : architecture is "fixed"; + +-- attribute HGROUP: string; +-- attribute HGROUP of arch : architecture is "mult_proc"; +attribute BBOX: string; +attribute BBOX of arch: architecture is "8,7"; + +signal reg_inp : std_logic_vector(INP'range); +signal mult_gated : std_logic_vector(95 downto 0) := (others => '0'); +type mult_arr is array(0 to 5) of unsigned(4 downto 0); +signal current_multiplicity : mult_arr; +signal out_reg : std_logic; +signal result : unsigned(4 downto 0); + attribute syn_preserve : boolean; + attribute syn_preserve of reg_inp : signal is true; + attribute syn_preserve of out_reg : signal is true; + + attribute syn_keep : boolean; + attribute syn_keep of reg_inp : signal is true; + attribute syn_keep of out_reg : signal is true; + attribute syn_keep of OUTP : signal is true; + + attribute syn_maxfan : integer; + attribute syn_maxfan of out_reg : signal is 1; + +begin + reg_inp <= INP; + mult_gated(INP'range) <= reg_INP and CONF.enable(INP'range) when rising_edge(CLK); + + PROC_MULT : process + variable m,n : integer range 0 to 20; + begin + wait until rising_edge(CLK); + + for j in 0 to 3 loop + m := 0; n := 0; + for i in 20*j+0 to 20*j+9 loop + if mult_gated(i) = '1' then + m := m + 1; + end if; + end loop; + for i in 20*j+10 to 20*j+19 loop + if mult_gated(i) = '1' then + n := n + 1; + end if; + end loop; + current_multiplicity(j) <= to_unsigned(m+n,5); + end loop; + -- + (current_multiplicity(4) + current_multiplicity(5)) + result <= (current_multiplicity(0) + current_multiplicity(1)) + (current_multiplicity(2) + current_multiplicity(3)); + if result >= CONF.multiplicity and CONF.multiplicity > 0 then + out_reg <= '1'; + else + out_reg <= '0'; + end if; + end process; +OUTP <= out_reg; --'1' when result >= CONF.multiplicity and CONF.multiplicity > 0 else '0' ; + +end architecture; diff --git a/triggerbox/code/scalers.vhd b/triggerbox/code/scalers.vhd new file mode 100644 index 0000000..0b7f9c5 --- /dev/null +++ b/triggerbox/code/scalers.vhd @@ -0,0 +1,97 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.trb_net_std.all; + use work.config.all; + use work.triggerbox_pkg.all; + + +entity scalers is + generic ( + NUM_INPUTS : integer range 1 to 512 := 32 + ); + port ( + CLK_SYS : in std_logic; + CLK_FULL : in std_logic; + RESET : in std_logic; + INP : in std_logic_vector(NUM_INPUTS-1 downto 0); + + BUS_RX : in CTRLBUS_RX; + BUS_TX : out CTRLBUS_TX + ); +end entity; + + +architecture arch of scalers is + +attribute syn_hier : string; +attribute syn_hier of arch : architecture is "fixed"; + +attribute HGROUP: string; +attribute HGROUP of arch : architecture is "scalers"; + +signal reg_inp, reg2_inp, reg3_inp : std_logic_vector(INP'range); + + attribute syn_preserve : boolean; + attribute syn_preserve of reg_inp : signal is true; + + attribute syn_keep : boolean; + attribute syn_keep of reg_inp : signal is true; + +type cnt_arr is array (0 to NUM_INPUTS-1) of unsigned(27 downto 0); +signal cnt : cnt_arr; + +signal reset_cnt : std_logic := '0'; +signal send_ack, reg_send_ack, reg2_send_ack, reg3_send_ack : std_logic := '0'; +signal muxreg : std_logic_vector(31 downto 0); +begin +reg_inp <= INP when rising_edge(CLK_FULL); +reg2_inp <= reg_inp when rising_edge(CLK_FULL); +reg3_inp <= reg2_inp when rising_edge(CLK_FULL); + +gen_scalers : for i in 0 to NUM_INPUTS-1 generate + process begin + wait until rising_edge(CLK_FULL); + if reg2_inp(i) = '1' and reg3_inp(i) = '0' then + cnt(i) <= cnt(i) + 1; + end if; + if RESET = '1' then + cnt(i) <= (others => '0'); + end if; + end process; +end generate; + +muxreg(27 downto 0) <= cnt(to_integer(unsigned(BUS_RX.addr(8 downto 0)))) when rising_edge(CLK_SYS); + +THE_REGS : process + variable slice : integer range 0 to 511; +begin + wait until rising_edge(CLK_SYS); + BUS_TX.ack <= reg2_send_ack; + BUS_TX.nack <= '0'; + BUS_TX.unknown <= '0'; + BUS_TX.data <= muxreg; + + send_ack <= '0'; + reg_send_ack <= send_ack; + reg2_send_ack <= reg_send_ack; + reg3_send_ack <= reg2_send_ack; + + if BUS_RX.read = '1' then + if BUS_RX.addr(9) = '0' then + slice := to_integer(unsigned(BUS_RX.addr(8 downto 0))); + if slice < NUM_INPUTS then + send_ack <= '1'; + else + BUS_TX.unknown <= '1'; + end if; + end if; + end if; +end process; + +end architecture; + + + diff --git a/triggerbox/code/tb_triggerbox.vhd b/triggerbox/code/tb_triggerbox.vhd new file mode 100644 index 0000000..d777d6e --- /dev/null +++ b/triggerbox/code/tb_triggerbox.vhd @@ -0,0 +1,54 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.trb_net_std.all; + use work.config.all; + use work.triggerbox_pkg.all; +entity tb is +end entity; + +architecture arch of tb is + +signal clk_100, clk_200, reset : std_logic := '1'; +signal inputs : std_logic_vector(7 downto 0); +signal busrx : CTRLBUS_RX; + +signal test : std_logic; +begin + +reset <= '0' after 20 ns; +clk_200 <= not clk_200 after 2.5 ns; +clk_100 <= not clk_100 after 5 ns; + +inputs(7 downto 1) <= (others => '0'); +inputs(0) <= '0', '1' after 254 ns, '0' after 273 ns, '0' after 500 ns; + + +THE_DUT : entity work.triggerbox + generic map( + NUM_INPUTS => 8, + NUM_VIRTUALIN => 8, + NUM_OUTPUTS => 2, + NUM_GROUPS => 2, + NUM_COINC => 2, + NUM_MULT => 2 + ) + port map( + CLK_SYS => clk_100, + CLK_FULL => clk_200, + RESET => reset, + + INP => inputs, + OUTP => open, + + BUS_RX => busrx, + BUS_TX => open, + + BUSRDO_RX => ('0','0','0','0',(others => '0'),(others => '0'),(others => '0'),(others => '0'),(others => '0'),'0','0','0','0','0','0'), + BUSRDO_TX => open + ); + + +end architecture; diff --git a/triggerbox/code/triggerbox.vhd b/triggerbox/code/triggerbox.vhd new file mode 100644 index 0000000..d241190 --- /dev/null +++ b/triggerbox/code/triggerbox.vhd @@ -0,0 +1,484 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.trb_net_std.all; + use work.config.all; + use work.triggerbox_pkg.all; + +entity triggerbox is + generic ( + NUM_PHYS_INPUTS : integer range 32 to 128 := 96; + NUM_INPUTS : integer range 16 to 128 := 48; + NUM_VIRTUALIN : integer range 16 to 32 := 32; + NUM_OUTPUTS : integer range 1 to 16 := 8; + NUM_GROUPS : integer range 16 to 32 := 16; + NUM_COINC : integer range 16 to 32 := 16; + NUM_MULT : integer range 0 to 32 := 8 + ); + port ( + CLK_SYS : in std_logic; + CLK_FULL : in std_logic; + RESET : in std_logic; + + INP : in std_logic_vector(NUM_PHYS_INPUTS-1 downto 0); + OUTP : out std_logic_vector(NUM_OUTPUTS-1 downto 0); + MONITOR_OUT : out std_logic_vector(15 downto 0); + + BUS_RX : in CTRLBUS_RX; + BUS_TX : out CTRLBUS_TX; + BUSSCALER_RX : in CTRLBUS_RX; + BUSSCALER_TX : out CTRLBUS_TX; + + + BUSRDO_RX : in READOUT_RX; + BUSRDO_TX : out READOUT_TX + ); +end entity; + + +architecture arch of triggerbox is +constant NUM_SCALER : integer := NUM_OUTPUTS + NUM_MULT + NUM_COINC + NUM_GROUPS + NUM_VIRTUALIN + NUM_INPUTS + NUM_PHYS_INPUTS; +signal reg_inp : std_logic_vector(INP'range); +signal selected_inp, processed_inp, reg_processed_inp, temp_processed_inp : std_logic_vector(NUM_INPUTS+NUM_VIRTUALIN-1 downto 0); +signal muxed_inp : std_logic_vector(NUM_VIRTUALIN-1 downto 0); +signal list_of_inp : std_logic_vector(255 downto 0); +signal reset_processor : std_logic; +signal groups, reg_groups : std_logic_vector(NUM_GROUPS-1 downto 0); +signal coincs, reg_coincs : std_logic_vector(NUM_COINC-1 downto 0); +signal multis, reg_multis : std_logic_vector(NUM_MULT-1 downto 0); +signal out1_i, out2_i, reg_out : std_logic_vector(OUTP'range); +signal list_of_scaler : std_logic_vector(NUM_SCALER-1 downto 0); + +type CONF_input_processor_arr is array(0 to NUM_INPUTS+NUM_VIRTUALIN-1) of CONF_input_processor_t; +signal CONF_input_processor : CONF_input_processor_arr; + +type CONF_input_mux_arr is array(0 to NUM_VIRTUALIN-1) of std_logic_vector(7 downto 0); +signal CONF_input_mux : CONF_input_mux_arr; + +type CONF_coincidence_arr is array(0 to NUM_COINC-1) of CONF_coincidence_t; +signal CONF_coincidence : CONF_coincidence_arr; + +type CONF_multiplicity_arr is array(0 to NUM_MULT-1) of CONF_multiplicity_t; +signal CONF_multiplicity : CONF_multiplicity_arr; + +type CONF_outputs_arr is array(0 to 1) of std_logic_vector(255 downto 0); +type CONF_outputs_arr2 is array(0 to NUM_OUTPUTS-1) of CONF_outputs_arr; +signal CONF_outputs : CONF_outputs_arr2; + +type CONF_groups_arr is array(0 to NUM_GROUPS-1) of std_logic_vector(127 downto 0); +signal CONF_groups : CONF_groups_arr; + +type CONF_monitor_arr is array(0 to 15) of integer range 0 to 511; +signal CONF_monitor : CONF_monitor_arr; + +type config_mem_t is array(0 to 1023) of std_logic_vector(31 downto 0); +signal config_mem : config_mem_t; + +signal config_mem_out : std_logic_vector(31 downto 0); +signal read_mem : std_logic; +signal coinc_inputs : std_logic_vector(255 downto 0) := (others => '0'); +signal list_of_outp : std_logic_vector(255 downto 0) := (others => '0'); +signal list_of_monitor, temp_list_of_monitor : std_logic_vector(511 downto 0) := (others => '0'); +signal mult_inputs : std_logic_vector(79 downto 0) := (others => '0'); + +signal timer_us, timer_ms : integer range 0 to 1000; +signal tick_us, tick_ms : std_logic; + + attribute syn_preserve : boolean; + attribute syn_preserve of tick_us : signal is true; + attribute syn_preserve of tick_ms : signal is true; + attribute syn_preserve of reg_processed_inp : signal is true; + attribute syn_preserve of temp_processed_inp : signal is true; + attribute syn_preserve of reg_groups : signal is true; + attribute syn_preserve of reg_multis : signal is true; + attribute syn_preserve of reg_coincs : signal is true; + attribute syn_preserve of list_of_monitor : signal is true; + attribute syn_preserve of list_of_scaler : signal is true; + + attribute syn_keep : boolean; + attribute syn_keep of tick_us : signal is true; + attribute syn_keep of tick_ms : signal is true; +-- attribute syn_keep of reg_processed_inp : signal is true; +-- attribute syn_keep of temp_processed_inp : signal is true; +-- attribute syn_keep of reg_groups : signal is true; +-- attribute syn_keep of reg_multis : signal is true; +-- attribute syn_keep of reg_coincs : signal is true; +-- attribute syn_keep of list_of_monitor : signal is true; +-- attribute syn_keep of list_of_scaler : signal is true; + + attribute syn_maxfan : integer; + attribute syn_maxfan of tick_us : signal is 10000; + attribute syn_maxfan of tick_ms : signal is 10000; + attribute syn_maxfan of reset_processor : signal is 10000; + +-- attribute syn_maxfan of list_of_inp : signal is 16; + attribute syn_maxfan of reg_processed_inp : signal is 1; + attribute syn_maxfan of temp_processed_inp : signal is 2; + attribute syn_maxfan of reg_groups : signal is 1; + attribute syn_maxfan of reg_multis : signal is 1; + attribute syn_maxfan of reg_coincs : signal is 1; + attribute syn_maxfan of list_of_monitor : signal is 1; + attribute syn_maxfan of temp_list_of_monitor : signal is 1; + + attribute HGROUP : string; + attribute HGROUP of gen_input_muxes : label is "muxes_group"; + +begin + +TIMER_PROC: process begin + wait until rising_edge(CLK_FULL); + tick_us <= '0'; + tick_ms <= '0'; + + timer_us <= timer_us + 1; + if timer_us >= 199 then + timer_us <= 0; + tick_us <= '1'; + end if; + if tick_us = '1' then + timer_ms <= timer_ms + 1; + end if; + if timer_ms >= 1000 then + timer_ms <= 0; + tick_ms <= '1'; + end if; + +end process; + +-------------------------------- +-- Register input +-------------------------------- + PROC_REG : process begin + wait until rising_edge(CLK_FULL); + reg_inp <= INP; + end process; + + --TODO: add async stretcher option + + + +-------------------------------- +-- Select Inputs +-------------------------------- +list_of_inp(NUM_PHYS_INPUTS-1 downto 0) <= inp; +gen_input_muxes : for i in 0 to NUM_VIRTUALIN-1 generate + muxed_inp(i) <= list_of_inp(to_integer(unsigned(CONF_input_mux(i))));-- when rising_edge(CLK_FULL); +end generate; + +selected_inp <= muxed_inp & inp(NUM_INPUTS-1 downto 0); + + +-------------------------------- +-- Input Stage +-------------------------------- +gen_input_processor : for i in 0 to NUM_INPUTS+NUM_VIRTUALIN-1 generate + THE_INP_PROC : entity work.input_processor + port map( + CLK => CLK_FULL, + RESET => reset_processor, + INP => selected_inp(i), + OUTP => processed_inp(i), + TICK_MS => tick_ms, + TICK_US => tick_us, + CONF => CONF_input_processor(i) + ); +end generate; + +temp_processed_inp <= processed_inp when rising_edge(CLK_FULL); +reg_processed_inp <= temp_processed_inp when rising_edge(CLK_FULL); + + +-------------------------------- +-- Or Groups +-------------------------------- +gen_groups : for i in 0 to NUM_GROUPS-1 generate + THE_GROUPS : entity work.groups + generic map ( + NUM_INPUTS => NUM_INPUTS+NUM_VIRTUALIN + ) + port map( + CLK => CLK_FULL, + INP => reg_processed_inp, + OUTP => groups(i), + CONF => CONF_groups(i)(reg_processed_inp'range) + ); +end generate; +reg_groups <= groups when rising_edge(CLK_FULL); + +-------------------------------- +-- Coincidences +-------------------------------- + +coinc_inputs(NUM_MULT + NUM_GROUPS + NUM_INPUTS + NUM_VIRTUALIN -1 downto 0) <= reg_multis & reg_groups & reg_processed_inp; +gen_coincs : for i in 0 to NUM_COINC-1 generate + THE_COINC : entity work.coincidence + generic map ( + NUM_INPUTS => NUM_COINC + NUM_GROUPS + NUM_INPUTS + NUM_VIRTUALIN + ) + port map( + CLK => CLK_FULL, + INP => coinc_inputs(NUM_COINC + NUM_GROUPS + NUM_INPUTS + NUM_VIRTUALIN-1 downto 0), + OUTP => coincs(i), + CONF => CONF_coincidence(i) + ); +end generate; +reg_coincs <= coincs when rising_edge(CLK_FULL); + +-------------------------------- +-- Multiplicities +-------------------------------- + +mult_inputs <= reg_processed_inp(63 downto 48) & reg_processed_inp(31 downto 0) & reg_coincs(15 downto 0) & reg_groups(15 downto 0); +gen_multis : for i in 0 to NUM_MULT-1 generate + THE_MULTIPLICITY : entity work.multiplicity + generic map( + NUM_INPUTS => 80 + ) + port map( + CLK => CLK_FULL, + INP => mult_inputs, + CONF => CONF_multiplicity(i), + OUTP => multis(i) + ); +end generate; +reg_multis <= multis when rising_edge(CLK_FULL); + +-------------------------------- +-- Outputs +-------------------------------- +--TODO: add a bit of stretching to the OUTPUT +list_of_outp(NUM_MULT + NUM_COINC + NUM_VIRTUALIN + NUM_INPUTS-1 downto 0) <= reg_multis & reg_coincs & reg_processed_inp ;--when rising_edge(CLK_FULL); +gen_outputs : for i in 0 to NUM_OUTPUTS-1 generate + out1_i(i) <= or (list_of_outp and CONF_outputs(i)(0)) when rising_edge(CLK_FULL); + out2_i(i) <= or (list_of_outp and CONF_outputs(i)(1)) when rising_edge(CLK_FULL); +end generate; +OUTP <= reg_out; +reg_out <= out1_i and out2_i when rising_edge(CLK_FULL); + +-------------------------------- +-- Registers +-------------------------------- + +proc_REGS : process + variable slice : integer range 0 to 127; +begin + wait until rising_edge(CLK_SYS); + BUS_TX.ack <= read_mem; + BUS_TX.data <= config_mem_out; + BUS_TX.nack <= '0'; + BUS_TX.unknown <= '0'; + read_mem <= '0'; + config_mem_out <= config_mem(to_integer(unsigned(BUS_RX.addr(9 downto 0)))); + reset_processor <= '0'; + + if BUS_RX.write = '1' then + if BUS_RX.addr(11 downto 10) = "00" then + config_mem(to_integer(unsigned(BUS_RX.addr(9 downto 0)))) <= BUS_RX.data; + end if; + if BUS_RX.addr(11 downto 7) = "00000" then + slice := to_integer(unsigned(BUS_RX.addr(6 downto 0))); + if slice < NUM_INPUTS + NUM_VIRTUALIN then + BUS_TX.ack <= '1'; + reset_processor <= '1'; + CONF_input_processor(slice).async <= BUS_RX.data(0); + CONF_input_processor(slice).enable <= BUS_RX.data(1); + CONF_input_processor(slice).invert <= BUS_RX.data(2); + CONF_input_processor(slice).edge_detect <= BUS_RX.data(3); + CONF_input_processor(slice).stretch_unit <= BUS_RX.data(5 downto 4); + CONF_input_processor(slice).stretch_value <= BUS_RX.data(17 downto 6); + CONF_input_processor(slice).delay <= BUS_RX.data(27 downto 18); + CONF_input_processor(slice).downscale <= BUS_RX.data(31 downto 28); + else + BUS_TX.unknown <= '1'; + end if; + + elsif BUS_RX.addr(11 downto 7) = "00001" then + slice := to_integer(unsigned(BUS_RX.addr(6 downto 2))); + if slice < NUM_GROUPS then + BUS_TX.ack <= '1'; + case BUS_RX.addr(1 downto 0) is + when "00" => CONF_groups(slice)(31 downto 0) <= BUS_RX.data(31 downto 0); + when "01" => CONF_groups(slice)(63 downto 32) <= BUS_RX.data(31 downto 0); + when "10" => CONF_groups(slice)(95 downto 64) <= BUS_RX.data(31 downto 0); + when "11" => CONF_groups(slice)(127 downto 96) <= BUS_RX.data(31 downto 0); + when others => null; + end case; + else + BUS_TX.unknown <= '1'; + end if; + + elsif BUS_RX.addr(11 downto 5) = "0001000" then + slice := to_integer(unsigned(BUS_RX.addr(4 downto 0))); + if slice < NUM_VIRTUALIN then + BUS_TX.ack <= '1'; + CONF_input_mux(slice) <= BUS_RX.data(7 downto 0); + else + BUS_TX.unknown <= '1'; + end if; + + elsif BUS_RX.addr(11 downto 5) = "0001001" then + slice := to_integer(unsigned(BUS_RX.addr(4 downto 0))); + if slice < NUM_COINC then + BUS_TX.ack <= '1'; + CONF_coincidence(slice).mux_input1 <= to_integer(unsigned(BUS_RX.data(7 downto 0))); + CONF_coincidence(slice).mux_input2 <= to_integer(unsigned(BUS_RX.data(15 downto 8))); + CONF_coincidence(slice).mux_input3 <= to_integer(unsigned(BUS_RX.data(23 downto 16))); + CONF_coincidence(slice).invert <= BUS_RX.data(26 downto 24); + CONF_coincidence(slice).enable <= BUS_RX.data(29 downto 27); + CONF_coincidence(slice).module_enable <= BUS_RX.data(30); + else + BUS_TX.unknown <= '1'; + end if; + + elsif BUS_RX.addr(11 downto 5) = "0001010" then + slice := to_integer(unsigned(BUS_RX.addr(4 downto 0))); + if slice < NUM_MULT then + BUS_TX.ack <= '1'; + CONF_multiplicity(slice).multiplicity <= unsigned(BUS_RX.data(4 downto 0)); + else + BUS_TX.unknown <= '1'; + end if; + + elsif BUS_RX.addr(11 downto 4) = "00010110" then + BUS_TX.ack <= '1'; + slice := to_integer(unsigned(BUS_RX.addr(3 downto 0))); + CONF_monitor(slice) <= to_integer(unsigned(BUS_RX.data(8 downto 0))); +-- end if; + + elsif BUS_RX.addr(11 downto 7) = "00011" then + slice := to_integer(unsigned(BUS_RX.addr(6 downto 2))); + if slice < NUM_MULT then + BUS_TX.ack <= '1'; + if(BUS_RX.addr(1 downto 0) = "00") then + CONF_multiplicity(slice).enable(31 downto 0) <= BUS_RX.data; + elsif(BUS_RX.addr(1 downto 0) = "01") then + CONF_multiplicity(slice).enable(63 downto 32) <= BUS_RX.data; + elsif(BUS_RX.addr(1 downto 0) = "11") then + CONF_multiplicity(slice).enable(95 downto 64) <= BUS_RX.data; + end if; + else + BUS_TX.unknown <= '1'; + end if; + + elsif BUS_RX.addr(11 downto 7) = "00100" then + slice := to_integer(unsigned(BUS_RX.addr(6 downto 3))); + if slice < NUM_OUTPUTS then + BUS_TX.ack <= '1'; + case BUS_RX.addr(2 downto 0) is + when "000" => CONF_outputs(slice)(0)( 31 downto 0) <= BUS_RX.data; + when "001" => CONF_outputs(slice)(0)( 63 downto 32) <= BUS_RX.data; + when "010" => CONF_outputs(slice)(0)( 95 downto 64) <= BUS_RX.data; + when "011" => CONF_outputs(slice)(0)(127 downto 96) <= BUS_RX.data; + when "100" => CONF_outputs(slice)(0)(159 downto 128) <= BUS_RX.data; + when "101" => CONF_outputs(slice)(0)(191 downto 160) <= BUS_RX.data; + when "110" => CONF_outputs(slice)(0)(223 downto 192) <= BUS_RX.data; + when "111" => CONF_outputs(slice)(0)(255 downto 224) <= BUS_RX.data; + when others => null; + end case; + end if; + elsif BUS_RX.addr(11 downto 7) = "00110" then + slice := to_integer(unsigned(BUS_RX.addr(6 downto 3))); + if slice < NUM_OUTPUTS then + BUS_TX.ack <= '1'; + case BUS_RX.addr(2 downto 0) is + when "000" => CONF_outputs(slice)(1)( 31 downto 0) <= BUS_RX.data; + when "001" => CONF_outputs(slice)(1)( 63 downto 32) <= BUS_RX.data; + when "010" => CONF_outputs(slice)(1)( 95 downto 64) <= BUS_RX.data; + when "011" => CONF_outputs(slice)(1)(127 downto 96) <= BUS_RX.data; + when "100" => CONF_outputs(slice)(1)(159 downto 128) <= BUS_RX.data; + when "101" => CONF_outputs(slice)(1)(191 downto 160) <= BUS_RX.data; + when "110" => CONF_outputs(slice)(1)(223 downto 192) <= BUS_RX.data; + when "111" => CONF_outputs(slice)(1)(255 downto 224) <= BUS_RX.data; + end case; + else + BUS_TX.unknown <= '1'; + end if; + + else + BUS_TX.unknown <= '1'; + end if; + + elsif BUS_RX.read = '1' then + if (BUS_RX.addr(11 downto 7) = "00000" and to_integer(unsigned(BUS_RX.addr(6 downto 0))) < NUM_INPUTS + NUM_VIRTUALIN) + or (BUS_RX.addr(11 downto 7) = "00001" and to_integer(unsigned(BUS_RX.addr(6 downto 2))) < NUM_GROUPS) + or (BUS_RX.addr(11 downto 5) = "0001000" and to_integer(unsigned(BUS_RX.addr(4 downto 0))) < NUM_VIRTUALIN) + or (BUS_RX.addr(11 downto 5) = "0001001" and to_integer(unsigned(BUS_RX.addr(4 downto 0))) < NUM_COINC) + or (BUS_RX.addr(11 downto 5) = "0001010" and to_integer(unsigned(BUS_RX.addr(4 downto 0))) < NUM_MULT) + or (BUS_RX.addr(11 downto 4) = "00010110"and to_integer(unsigned(BUS_RX.addr(3 downto 0))) < 16) + or (BUS_RX.addr(11 downto 7) = "00011" and to_integer(unsigned(BUS_RX.addr(6 downto 2))) < NUM_MULT) + or (BUS_RX.addr(11 downto 7) = "00100" and to_integer(unsigned(BUS_RX.addr(6 downto 3))) < NUM_OUTPUTS) + or (BUS_RX.addr(11 downto 7) = "00110" and to_integer(unsigned(BUS_RX.addr(6 downto 3))) < NUM_OUTPUTS) + then + read_mem <= '1'; + + elsif BUS_RX.addr(11 downto 0) = x"F00" then + BUS_TX.data <= x"00" + & std_logic_vector(to_unsigned(NUM_PHYS_INPUTS,8)) + & std_logic_vector(to_unsigned(NUM_VIRTUALIN,8)) + & std_logic_vector(to_unsigned(NUM_INPUTS,8)); + BUS_TX.ack <= '1'; + + elsif BUS_RX.addr(11 downto 0) = x"F01" then + BUS_TX.data <= x"00" + & std_logic_vector(to_unsigned(NUM_MULT,8)) + & std_logic_vector(to_unsigned(NUM_COINC,8)) + & std_logic_vector(to_unsigned(NUM_GROUPS,8)); + BUS_TX.ack <= '1'; + elsif BUS_RX.addr(11 downto 0) = x"F02" then + BUS_TX.data <= std_logic_vector(to_unsigned(NUM_SCALER,16)) + & std_logic_vector(to_unsigned(16,8)) --NUM_MONITORS + & std_logic_vector(to_unsigned(NUM_OUTPUTS,8)); + BUS_TX.ack <= '1'; + else + BUS_TX.unknown <= '1'; + end if; + end if; +end process; + +-------------------------------- +-- Scaler +-------------------------------- +list_of_scaler <= reg_out & reg_multis & reg_coincs & reg_groups & reg_processed_inp & reg_inp when rising_edge(CLK_FULL); +THE_SCALER : entity work.scalers + generic map( + NUM_INPUTS => NUM_SCALER + ) + port map( + CLK_SYS => CLK_SYS, + CLK_FULL => CLK_FULL, + RESET => RESET, + INP => list_of_scaler, + BUS_RX => BUSSCALER_RX, + BUS_TX => BUSSCALER_TX + ); + + +-------------------------------- +-- Monitor +-------------------------------- +list_of_monitor(NUM_SCALER-1 downto 0) <= reg_out & reg_multis & reg_coincs & reg_groups & reg_processed_inp & reg_inp when rising_edge(CLK_FULL); +--list_of_monitor <= temp_list_of_monitor when rising_edge(CLK_FULL); +gen_monitors : for i in MONITOR_OUT'range generate + THE_MONITOR : entity work.monitor_output + generic map( + NUM_INPUTS => NUM_SCALER + ) + port map( + CLK => CLK_FULL, + INP => list_of_monitor(NUM_SCALER-1 downto 0), + OUTP => MONITOR_OUT(i), + CONF => CONF_monitor(i) + ); +end generate; + + +-------------------------------- +-- Readout +-------------------------------- +BUSRDO_TX.data_finished <= '1'; +BUSRDO_TX.data_write <= '0'; +BUSRDO_TX.busy_release <= '1'; + +end architecture; diff --git a/triggerbox/code/triggerbox_pkg.vhd b/triggerbox/code/triggerbox_pkg.vhd new file mode 100644 index 0000000..88cc8b2 --- /dev/null +++ b/triggerbox/code/triggerbox_pkg.vhd @@ -0,0 +1,39 @@ +library ieee; +USE IEEE.std_logic_1164.ALL; +use ieee.numeric_std.all; +use work.trb_net_std.all; + +package triggerbox_pkg is + + type CONF_input_processor_t is record + async : std_logic; + enable : std_logic; + invert : std_logic; + edge_detect : std_logic; + downscale : std_logic_vector(3 downto 0); + stretch_unit : std_logic_vector(1 downto 0); + stretch_value : std_logic_vector(11 downto 0); + delay : std_logic_vector(9 downto 0); + end record; + + + type CONF_coincidence_t is record + mux_input1 : integer range 0 to 255; + mux_input2 : integer range 0 to 255; + mux_input3 : integer range 0 to 255; + invert : std_logic_vector(2 downto 0); + enable : std_logic_vector(2 downto 0); + module_enable: std_logic; + end record; + + type CONF_multiplicity_t is record + multiplicity : unsigned(4 downto 0); + enable : std_logic_vector(95 downto 0); + end record; + +end; + +package body triggerbox_pkg is + + +end package body; diff --git a/triggerbox/compile.pl b/triggerbox/compile.pl new file mode 120000 index 0000000..4456748 --- /dev/null +++ b/triggerbox/compile.pl @@ -0,0 +1 @@ +../scripts/compile.pl \ No newline at end of file diff --git a/triggerbox/config.vhd b/triggerbox/config.vhd new file mode 100644 index 0000000..fd7b98e --- /dev/null +++ b/triggerbox/config.vhd @@ -0,0 +1,113 @@ +library ieee; +USE IEEE.std_logic_1164.ALL; +use ieee.numeric_std.all; +use work.trb_net_std.all; + +package config is + + +------------------------------------------------------------------------------ +--Begin of design configuration +------------------------------------------------------------------------------ + + constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 10; -- size of the event buffer, 2**N + constant EVENT_MAX_SIZE : integer := 500; --maximum event size. Should not exceed EVENT_BUFFER_SIZE/2 + + constant FPGA_TYPE : integer := 3; +--Runs with 120 MHz instead of 100 MHz + constant USE_120_MHZ : integer := c_NO; + constant USE_200MHZOSCILLATOR : integer := c_YES; + constant USE_EXTERNAL_CLOCK : integer := c_YES; --'no' not implemented. + constant CLOCK_FAST_SELECT : integer := c_NO; --fast clock select (135us) or slow (280ms)? + +--Use sync mode, RX clock for all parts of the FPGA + constant USE_RXCLOCK : integer := c_NO; + +--Address settings + constant INIT_ADDRESS : std_logic_vector := x"F3B0"; + constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"69"; + +--set to 0 for backplane serdes, set to 3 for front SFP serdes + constant SERDES_NUM : integer := 3; + + constant INCLUDE_UART : integer := c_NO; + constant INCLUDE_SPI : integer := c_YES; + constant INCLUDE_LCD : integer := c_NO; + constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; + + --input monitor and trigger generation logic + constant INCLUDE_TRIGGER_LOGIC : integer := c_NO; + constant INCLUDE_STATISTICS : integer := c_NO; + constant TRIG_GEN_INPUT_NUM : integer := 64; + constant TRIG_GEN_OUTPUT_NUM : integer := 4; + constant MONITOR_INPUT_NUM : integer := 64; + + constant USE_GBE : integer := c_NO; + +------------------------------------------------------------------------------ +--End of design configuration +------------------------------------------------------------------------------ + + + type data_t is array (0 to 1023) of std_logic_vector(7 downto 0); + constant LCD_DATA : data_t := ( + x"36",x"48",x"3A",x"55",x"29",x"2A",x"00",x"00", --config don't touch + x"00",x"EF",x"2B",x"00",x"00",x"01",x"3F",x"2C", --config don't touch + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", --config don't touch + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", --config don't touch + + x"54", x"72", x"62", x"33", x"73", x"63", x"0a", + x"0a", + x"41", x"64", x"64", x"72", x"65", x"73", x"73", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"80", x"0a", + x"55", x"49", x"44", x"20", x"20", x"89", x"88", x"87", x"86", x"0a", + x"43", x"6f", x"6d", x"70", x"69", x"6c", x"65", x"54", x"69", x"6d", x"65", x"20", x"20", x"84", x"83", x"0a", + x"54", x"69", x"6d", x"65", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"82", x"81", x"0a", + x"54", x"65", x"6d", x"70", x"65", x"72", x"61", x"74", x"75", x"72", x"65", x"20", x"20", x"20", x"20", x"20", x"20", x"85", x"0a", + others => x"00"); + +------------------------------------------------------------------------------ +--Select settings by configuration +------------------------------------------------------------------------------ + type intlist_t is array(0 to 7) of integer; + type hw_info_t is array(0 to 7) of unsigned(31 downto 0); + constant HW_INFO_BASE : unsigned(31 downto 0) := x"95000000"; + + constant CLOCK_FREQUENCY_ARR : intlist_t := (100,120, others => 0); + constant MEDIA_FREQUENCY_ARR : intlist_t := (200,240, others => 0); + + --declare constants, filled in body + constant HARDWARE_INFO : std_logic_vector(31 downto 0); + constant CLOCK_FREQUENCY : integer; + constant MEDIA_FREQUENCY : integer; + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0); + constant BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF"; --(7 => (not std_logic_vector(to_unsigned(USE_GBE,1))(0)), others => '1'); + +end; + +package body config is +--compute correct configuration mode + + constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector( + HW_INFO_BASE ); + constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ); + constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ); + +function generateIncludedFeatures return std_logic_vector is + variable t : std_logic_vector(63 downto 0); + begin + t := (others => '0'); + t(63 downto 56) := std_logic_vector(to_unsigned(1,8)); --table version 1 + t(28 downto 28) := std_logic_vector(to_unsigned(3-SERDES_NUM,1)); + t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1)); + t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1)); + t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1)); + t(45 downto 45) := std_logic_vector(to_unsigned(USE_GBE,1)); + t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1)); + t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1)); + t(54 downto 54) := std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1)); + return t; + end function; + + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures; + +end package body; diff --git a/triggerbox/config_compile_frankfurt.pl b/triggerbox/config_compile_frankfurt.pl new file mode 100644 index 0000000..1fd06a9 --- /dev/null +++ b/triggerbox/config_compile_frankfurt.pl @@ -0,0 +1,20 @@ +TOPNAME => "trb3sc_triggerbox", +lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; +lm_license_file_for_par => "1702\@hadeb05.gsi.de", +lattice_path => '/d/jspc29/lattice/diamond/3.11_x64', +synplify_path => '/d/jspc29/lattice/synplify/P-2019.09-SP1/', +#synplify_command => "/d/jspc29/lattice/diamond/3.6_x64/bin/lin64/synpwrap -fg -options", +# synplify_command => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp", + +nodelist_file => 'nodelist_frankfurt.txt', + + +#Include only necessary lpf files #trb3sc_rj_bynumbers - for Hades trigger gen +pinout_file => 'trb3sc_triggerbox', #name of pin-out file, if not equal TOPNAME +include_TDC => 0, +include_GBE => 1, + +#Report settings +firefox_open => 0, +twr_number_of_errors => 50, +mapper_options => ' -hier -tdm -td_pack', diff --git a/triggerbox/cores/delay_shift_reg.ipx b/triggerbox/cores/delay_shift_reg.ipx new file mode 100644 index 0000000..9083f46 --- /dev/null +++ b/triggerbox/cores/delay_shift_reg.ipx @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/triggerbox/cores/delay_shift_reg.lpc b/triggerbox/cores/delay_shift_reg.lpc new file mode 100644 index 0000000..09ceeff --- /dev/null +++ b/triggerbox/cores/delay_shift_reg.lpc @@ -0,0 +1,44 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN1156C +SpeedGrade=8 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=RAM_Based_Shift_Register +CoreRevision=5.2 +ModuleName=delay_shift_reg +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=11/06/2020 +Time=15:50:54 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=None +Order=Big Endian [MSB:LSB] +IO=0 +DataWidth=1 +Type=VarLossless +NoOfShifts=16 +MaxLossyShifts=256 +MaxLosslessShifts=256 +EOR=1 +MemFile= +MemFormat=orca +RamType=dram + +[FilesGenerated] +=mem + +[Command] +cmd_line= -w -n delay_shift_reg -lang vhdl -synth synplify -bb -arch ep5c00 -type shiftreg -width 1 -depth 256 -mode 2 -pipe_final_output diff --git a/triggerbox/cores/delay_shift_reg.vhd b/triggerbox/cores/delay_shift_reg.vhd new file mode 100644 index 0000000..8d15135 --- /dev/null +++ b/triggerbox/cores/delay_shift_reg.vhd @@ -0,0 +1,696 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.11.2.446 +-- Module Version: 5.2 +--/d/jspc29/lattice/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n delay_shift_reg -lang vhdl -synth synplify -bb -arch ep5c00 -type shiftreg -width 1 -depth 256 -mode 2 -pipe_final_output + +-- Fri Nov 6 15:50:54 2020 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity delay_shift_reg is + port ( + Din: in std_logic_vector(0 downto 0); + Addr: in std_logic_vector(7 downto 0); + Clock: in std_logic; + ClockEn: in std_logic; + Reset: in std_logic; + Q: out std_logic_vector(0 downto 0)); +end delay_shift_reg; + +architecture Structure of delay_shift_reg is + + -- internal signal declarations + signal func_and_inet: std_logic; + signal func_and_inet_1: std_logic; + signal func_and_inet_2: std_logic; + signal func_and_inet_3: std_logic; + signal func_and_inet_4: std_logic; + signal func_and_inet_5: std_logic; + signal func_and_inet_6: std_logic; + signal shreg_addr_w7_inv: std_logic; + signal func_and_inet_7: std_logic; + signal func_and_inet_8: std_logic; + signal func_and_inet_9: std_logic; + signal func_and_inet_10: std_logic; + signal shreg_addr_w6_inv: std_logic; + signal func_and_inet_11: std_logic; + signal func_and_inet_12: std_logic; + signal shreg_addr_w5_inv: std_logic; + signal func_and_inet_13: std_logic; + signal shreg_addr_w4_inv: std_logic; + signal func_and_inet_14: std_logic; + signal Reset_inv: std_logic; + signal func_and_inet_15: std_logic; + signal scuba_vhi: std_logic; + signal ishreg_addr_w0: std_logic; + signal ishreg_addr_w1: std_logic; + signal sreg_0_ctr_1_ci: std_logic; + signal ishreg_addr_w2: std_logic; + signal ishreg_addr_w3: std_logic; + signal co0: std_logic; + signal ishreg_addr_w4: std_logic; + signal ishreg_addr_w5: std_logic; + signal co1: std_logic; + signal ishreg_addr_w6: std_logic; + signal ishreg_addr_w7: std_logic; + signal co3: std_logic; + signal co2: std_logic; + signal precin: std_logic; + signal low_inv: std_logic; + signal co0_1: std_logic; + signal co1_1: std_logic; + signal shreg_addr_w4: std_logic; + signal co2_1: std_logic; + signal shreg_addr_w5: std_logic; + signal shreg_addr_w6: std_logic; + signal co3_1: std_logic; + signal shreg_addr_w7: std_logic; + signal Q0_ffin: std_logic; + signal shreg_addr_r7: std_logic; + signal shreg_addr_r6: std_logic; + signal shreg_addr_r5: std_logic; + signal shreg_addr_r4: std_logic; + signal mdL0_0_0: std_logic; + signal dec0_wre3: std_logic; + signal mdL0_1_0: std_logic; + signal dec1_wre7: std_logic; + signal mdL0_2_0: std_logic; + signal dec2_wre11: std_logic; + signal mdL0_3_0: std_logic; + signal dec3_wre15: std_logic; + signal mdL0_4_0: std_logic; + signal dec4_wre19: std_logic; + signal mdL0_5_0: std_logic; + signal dec5_wre23: std_logic; + signal mdL0_6_0: std_logic; + signal dec6_wre27: std_logic; + signal mdL0_7_0: std_logic; + signal dec7_wre31: std_logic; + signal mdL0_8_0: std_logic; + signal dec8_wre35: std_logic; + signal mdL0_9_0: std_logic; + signal dec9_wre39: std_logic; + signal mdL0_10_0: std_logic; + signal dec10_wre43: std_logic; + signal mdL0_11_0: std_logic; + signal dec11_wre47: std_logic; + signal mdL0_12_0: std_logic; + signal dec12_wre51: std_logic; + signal mdL0_13_0: std_logic; + signal dec13_wre55: std_logic; + signal mdL0_14_0: std_logic; + signal dec14_wre59: std_logic; + signal mdL0_15_0: std_logic; + signal shreg_addr_r3: std_logic; + signal shreg_addr_r2: std_logic; + signal shreg_addr_r1: std_logic; + signal shreg_addr_r0: std_logic; + signal dec15_wre63: std_logic; + signal shreg_addr_w3: std_logic; + signal shreg_addr_w2: std_logic; + signal shreg_addr_w1: std_logic; + signal shreg_addr_w0: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FSUB2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; BI: in std_logic; BOUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component MUX161 + port (D0: in std_logic; D1: in std_logic; D2: in std_logic; + D3: in std_logic; D4: in std_logic; D5: in std_logic; + D6: in std_logic; D7: in std_logic; D8: in std_logic; + D9: in std_logic; D10: in std_logic; D11: in std_logic; + D12: in std_logic; D13: in std_logic; D14: in std_logic; + D15: in std_logic; SD1: in std_logic; SD2: in std_logic; + SD3: in std_logic; SD4: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component DPR16X4C + generic (INITVAL : in String); + port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; + DI3: in std_logic; WCK: in std_logic; WRE: in std_logic; + RAD0: in std_logic; RAD1: in std_logic; + RAD2: in std_logic; RAD3: in std_logic; + WAD0: in std_logic; WAD1: in std_logic; + WAD2: in std_logic; WAD3: in std_logic; + DO0: out std_logic; DO1: out std_logic; + DO2: out std_logic; DO3: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + attribute GSR : string; + attribute MEM_INIT_FILE : string; + attribute MEM_LPC_FILE : string; + attribute COMP : string; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute MEM_INIT_FILE of sram_1_0_0 : label is "(0-15)(0-0)"; + attribute MEM_LPC_FILE of sram_1_0_0 : label is "delay_shift_reg.lpc"; + attribute COMP of sram_1_0_0 : label is "sram_1_0_0"; + attribute MEM_INIT_FILE of sram_1_1_0 : label is "(16-31)(0-0)"; + attribute MEM_LPC_FILE of sram_1_1_0 : label is "delay_shift_reg.lpc"; + attribute COMP of sram_1_1_0 : label is "sram_1_1_0"; + attribute MEM_INIT_FILE of sram_1_2_0 : label is "(32-47)(0-0)"; + attribute MEM_LPC_FILE of sram_1_2_0 : label is "delay_shift_reg.lpc"; + attribute COMP of sram_1_2_0 : label is "sram_1_2_0"; + attribute MEM_INIT_FILE of sram_1_3_0 : label is "(48-63)(0-0)"; + attribute MEM_LPC_FILE of sram_1_3_0 : label is "delay_shift_reg.lpc"; + attribute COMP of sram_1_3_0 : label is "sram_1_3_0"; + attribute MEM_INIT_FILE of sram_1_4_0 : label is "(64-79)(0-0)"; + attribute MEM_LPC_FILE of sram_1_4_0 : label is "delay_shift_reg.lpc"; + attribute COMP of sram_1_4_0 : label is "sram_1_4_0"; + attribute MEM_INIT_FILE of sram_1_5_0 : label is "(80-95)(0-0)"; + attribute MEM_LPC_FILE of sram_1_5_0 : label is "delay_shift_reg.lpc"; + attribute COMP of sram_1_5_0 : label is "sram_1_5_0"; + attribute MEM_INIT_FILE of sram_1_6_0 : label is "(96-111)(0-0)"; + attribute MEM_LPC_FILE of sram_1_6_0 : label is "delay_shift_reg.lpc"; + attribute COMP of sram_1_6_0 : label is "sram_1_6_0"; + attribute MEM_INIT_FILE of sram_1_7_0 : label is "(112-127)(0-0)"; + attribute MEM_LPC_FILE of sram_1_7_0 : label is "delay_shift_reg.lpc"; + attribute COMP of sram_1_7_0 : label is "sram_1_7_0"; + attribute MEM_INIT_FILE of sram_1_8_0 : label is "(128-143)(0-0)"; + attribute MEM_LPC_FILE of sram_1_8_0 : label is "delay_shift_reg.lpc"; + attribute COMP of sram_1_8_0 : label is "sram_1_8_0"; + attribute MEM_INIT_FILE of sram_1_9_0 : label is "(144-159)(0-0)"; + attribute MEM_LPC_FILE of sram_1_9_0 : label is "delay_shift_reg.lpc"; + attribute COMP of sram_1_9_0 : label is "sram_1_9_0"; + attribute MEM_INIT_FILE of sram_1_10_0 : label is "(160-175)(0-0)"; + attribute MEM_LPC_FILE of sram_1_10_0 : label is "delay_shift_reg.lpc"; + attribute COMP of sram_1_10_0 : label is "sram_1_10_0"; + attribute MEM_INIT_FILE of sram_1_11_0 : label is "(176-191)(0-0)"; + attribute MEM_LPC_FILE of sram_1_11_0 : label is "delay_shift_reg.lpc"; + attribute COMP of sram_1_11_0 : label is "sram_1_11_0"; + attribute MEM_INIT_FILE of sram_1_12_0 : label is "(192-207)(0-0)"; + attribute MEM_LPC_FILE of sram_1_12_0 : label is "delay_shift_reg.lpc"; + attribute COMP of sram_1_12_0 : label is "sram_1_12_0"; + attribute MEM_INIT_FILE of sram_1_13_0 : label is "(208-223)(0-0)"; + attribute MEM_LPC_FILE of sram_1_13_0 : label is "delay_shift_reg.lpc"; + attribute COMP of sram_1_13_0 : label is "sram_1_13_0"; + attribute MEM_INIT_FILE of sram_1_14_0 : label is "(224-239)(0-0)"; + attribute MEM_LPC_FILE of sram_1_14_0 : label is "delay_shift_reg.lpc"; + attribute COMP of sram_1_14_0 : label is "sram_1_14_0"; + attribute MEM_INIT_FILE of sram_1_15_0 : label is "(240-255)(0-0)"; + attribute MEM_LPC_FILE of sram_1_15_0 : label is "delay_shift_reg.lpc"; + attribute COMP of sram_1_15_0 : label is "sram_1_15_0"; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + INV_5: INV + port map (A=>Reset, Z=>Reset_inv); + + INV_4: INV + port map (A=>scuba_vlo, Z=>low_inv); + + INV_3: INV + port map (A=>shreg_addr_w4, Z=>shreg_addr_w4_inv); + + INV_2: INV + port map (A=>shreg_addr_w5, Z=>shreg_addr_w5_inv); + + INV_1: INV + port map (A=>shreg_addr_w6, Z=>shreg_addr_w6_inv); + + INV_0: INV + port map (A=>shreg_addr_w7, Z=>shreg_addr_w7_inv); + + LUT4_31: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>Reset_inv, AD2=>ClockEn, AD1=>shreg_addr_w4_inv, + AD0=>shreg_addr_w5_inv, DO0=>func_and_inet); + + LUT4_30: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet, AD2=>shreg_addr_w6_inv, + AD1=>shreg_addr_w7_inv, AD0=>scuba_vhi, DO0=>dec0_wre3); + + LUT4_29: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>Reset_inv, AD2=>ClockEn, AD1=>shreg_addr_w4, + AD0=>shreg_addr_w5_inv, DO0=>func_and_inet_1); + + LUT4_28: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_1, AD2=>shreg_addr_w6_inv, + AD1=>shreg_addr_w7_inv, AD0=>scuba_vhi, DO0=>dec1_wre7); + + LUT4_27: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>Reset_inv, AD2=>ClockEn, AD1=>shreg_addr_w4_inv, + AD0=>shreg_addr_w5, DO0=>func_and_inet_2); + + LUT4_26: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_2, AD2=>shreg_addr_w6_inv, + AD1=>shreg_addr_w7_inv, AD0=>scuba_vhi, DO0=>dec2_wre11); + + LUT4_25: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>Reset_inv, AD2=>ClockEn, AD1=>shreg_addr_w4, + AD0=>shreg_addr_w5, DO0=>func_and_inet_3); + + LUT4_24: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_3, AD2=>shreg_addr_w6_inv, + AD1=>shreg_addr_w7_inv, AD0=>scuba_vhi, DO0=>dec3_wre15); + + LUT4_23: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>Reset_inv, AD2=>ClockEn, AD1=>shreg_addr_w4_inv, + AD0=>shreg_addr_w5_inv, DO0=>func_and_inet_4); + + LUT4_22: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_4, AD2=>shreg_addr_w6, + AD1=>shreg_addr_w7_inv, AD0=>scuba_vhi, DO0=>dec4_wre19); + + LUT4_21: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>Reset_inv, AD2=>ClockEn, AD1=>shreg_addr_w4, + AD0=>shreg_addr_w5_inv, DO0=>func_and_inet_5); + + LUT4_20: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_5, AD2=>shreg_addr_w6, + AD1=>shreg_addr_w7_inv, AD0=>scuba_vhi, DO0=>dec5_wre23); + + LUT4_19: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>Reset_inv, AD2=>ClockEn, AD1=>shreg_addr_w4_inv, + AD0=>shreg_addr_w5, DO0=>func_and_inet_6); + + LUT4_18: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_6, AD2=>shreg_addr_w6, + AD1=>shreg_addr_w7_inv, AD0=>scuba_vhi, DO0=>dec6_wre27); + + LUT4_17: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>Reset_inv, AD2=>ClockEn, AD1=>shreg_addr_w4, + AD0=>shreg_addr_w5, DO0=>func_and_inet_7); + + LUT4_16: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_7, AD2=>shreg_addr_w6, + AD1=>shreg_addr_w7_inv, AD0=>scuba_vhi, DO0=>dec7_wre31); + + LUT4_15: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>Reset_inv, AD2=>ClockEn, AD1=>shreg_addr_w4_inv, + AD0=>shreg_addr_w5_inv, DO0=>func_and_inet_8); + + LUT4_14: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_8, AD2=>shreg_addr_w6_inv, + AD1=>shreg_addr_w7, AD0=>scuba_vhi, DO0=>dec8_wre35); + + LUT4_13: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>Reset_inv, AD2=>ClockEn, AD1=>shreg_addr_w4, + AD0=>shreg_addr_w5_inv, DO0=>func_and_inet_9); + + LUT4_12: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_9, AD2=>shreg_addr_w6_inv, + AD1=>shreg_addr_w7, AD0=>scuba_vhi, DO0=>dec9_wre39); + + LUT4_11: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>Reset_inv, AD2=>ClockEn, AD1=>shreg_addr_w4_inv, + AD0=>shreg_addr_w5, DO0=>func_and_inet_10); + + LUT4_10: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_10, AD2=>shreg_addr_w6_inv, + AD1=>shreg_addr_w7, AD0=>scuba_vhi, DO0=>dec10_wre43); + + LUT4_9: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>Reset_inv, AD2=>ClockEn, AD1=>shreg_addr_w4, + AD0=>shreg_addr_w5, DO0=>func_and_inet_11); + + LUT4_8: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_11, AD2=>shreg_addr_w6_inv, + AD1=>shreg_addr_w7, AD0=>scuba_vhi, DO0=>dec11_wre47); + + LUT4_7: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>Reset_inv, AD2=>ClockEn, AD1=>shreg_addr_w4_inv, + AD0=>shreg_addr_w5_inv, DO0=>func_and_inet_12); + + LUT4_6: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_12, AD2=>shreg_addr_w6, + AD1=>shreg_addr_w7, AD0=>scuba_vhi, DO0=>dec12_wre51); + + LUT4_5: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>Reset_inv, AD2=>ClockEn, AD1=>shreg_addr_w4, + AD0=>shreg_addr_w5_inv, DO0=>func_and_inet_13); + + LUT4_4: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_13, AD2=>shreg_addr_w6, + AD1=>shreg_addr_w7, AD0=>scuba_vhi, DO0=>dec13_wre55); + + LUT4_3: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>Reset_inv, AD2=>ClockEn, AD1=>shreg_addr_w4_inv, + AD0=>shreg_addr_w5, DO0=>func_and_inet_14); + + LUT4_2: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_14, AD2=>shreg_addr_w6, + AD1=>shreg_addr_w7, AD0=>scuba_vhi, DO0=>dec14_wre59); + + LUT4_1: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>Reset_inv, AD2=>ClockEn, AD1=>shreg_addr_w4, + AD0=>shreg_addr_w5, DO0=>func_and_inet_15); + + LUT4_0: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_15, AD2=>shreg_addr_w6, + AD1=>shreg_addr_w7, AD0=>scuba_vhi, DO0=>dec15_wre63); + + FF_8: FD1P3DX + port map (D=>ishreg_addr_w0, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>shreg_addr_w0); + + FF_7: FD1P3DX + port map (D=>ishreg_addr_w1, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>shreg_addr_w1); + + FF_6: FD1P3DX + port map (D=>ishreg_addr_w2, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>shreg_addr_w2); + + FF_5: FD1P3DX + port map (D=>ishreg_addr_w3, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>shreg_addr_w3); + + FF_4: FD1P3DX + port map (D=>ishreg_addr_w4, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>shreg_addr_w4); + + FF_3: FD1P3DX + port map (D=>ishreg_addr_w5, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>shreg_addr_w5); + + FF_2: FD1P3DX + port map (D=>ishreg_addr_w6, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>shreg_addr_w6); + + FF_1: FD1P3DX + port map (D=>ishreg_addr_w7, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>shreg_addr_w7); + + FF_0: FD1P3DX + port map (D=>Q0_ffin, SP=>ClockEn, CK=>Clock, CD=>Reset, Q=>Q(0)); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + sreg_0_ctr_1_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>sreg_0_ctr_1_ci, + S0=>open, S1=>open); + + sreg_0_ctr_1_0: CU2 + port map (CI=>sreg_0_ctr_1_ci, PC0=>shreg_addr_w0, + PC1=>shreg_addr_w1, CO=>co0, NC0=>ishreg_addr_w0, + NC1=>ishreg_addr_w1); + + sreg_0_ctr_1_1: CU2 + port map (CI=>co0, PC0=>shreg_addr_w2, PC1=>shreg_addr_w3, + CO=>co1, NC0=>ishreg_addr_w2, NC1=>ishreg_addr_w3); + + sreg_0_ctr_1_2: CU2 + port map (CI=>co1, PC0=>shreg_addr_w4, PC1=>shreg_addr_w5, + CO=>co2, NC0=>ishreg_addr_w4, NC1=>ishreg_addr_w5); + + sreg_0_ctr_1_3: CU2 + port map (CI=>co2, PC0=>shreg_addr_w6, PC1=>shreg_addr_w7, + CO=>co3, NC0=>ishreg_addr_w6, NC1=>ishreg_addr_w7); + + precin_inst46: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>scuba_vlo, COUT=>precin, S0=>open, + S1=>open); + + raddr_sub_1_0: FSUB2B + port map (A0=>scuba_vlo, A1=>shreg_addr_w0, B0=>low_inv, + B1=>Addr(0), BI=>precin, BOUT=>co0_1, S0=>open, + S1=>shreg_addr_r0); + + raddr_sub_1_1: FSUB2B + port map (A0=>shreg_addr_w1, A1=>shreg_addr_w2, B0=>Addr(1), + B1=>Addr(2), BI=>co0_1, BOUT=>co1_1, S0=>shreg_addr_r1, + S1=>shreg_addr_r2); + + raddr_sub_1_2: FSUB2B + port map (A0=>shreg_addr_w3, A1=>shreg_addr_w4, B0=>Addr(3), + B1=>Addr(4), BI=>co1_1, BOUT=>co2_1, S0=>shreg_addr_r3, + S1=>shreg_addr_r4); + + raddr_sub_1_3: FSUB2B + port map (A0=>shreg_addr_w5, A1=>shreg_addr_w6, B0=>Addr(5), + B1=>Addr(6), BI=>co2_1, BOUT=>co3_1, S0=>shreg_addr_r5, + S1=>shreg_addr_r6); + + raddr_sub_1_4: FSUB2B + port map (A0=>shreg_addr_w7, A1=>scuba_vlo, B0=>Addr(7), + B1=>scuba_vlo, BI=>co3_1, BOUT=>open, S0=>shreg_addr_r7, + S1=>open); + + mux_0: MUX161 + port map (D0=>mdL0_0_0, D1=>mdL0_1_0, D2=>mdL0_2_0, D3=>mdL0_3_0, + D4=>mdL0_4_0, D5=>mdL0_5_0, D6=>mdL0_6_0, D7=>mdL0_7_0, + D8=>mdL0_8_0, D9=>mdL0_9_0, D10=>mdL0_10_0, D11=>mdL0_11_0, + D12=>mdL0_12_0, D13=>mdL0_13_0, D14=>mdL0_14_0, + D15=>mdL0_15_0, SD1=>shreg_addr_r4, SD2=>shreg_addr_r5, + SD3=>shreg_addr_r6, SD4=>shreg_addr_r7, Z=>Q0_ffin); + + sram_1_0_0: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Din(0), DI1=>scuba_vlo, DI2=>scuba_vlo, + DI3=>scuba_vlo, WCK=>Clock, WRE=>dec0_wre3, + RAD0=>shreg_addr_r0, RAD1=>shreg_addr_r1, + RAD2=>shreg_addr_r2, RAD3=>shreg_addr_r3, + WAD0=>shreg_addr_w0, WAD1=>shreg_addr_w1, + WAD2=>shreg_addr_w2, WAD3=>shreg_addr_w3, DO0=>mdL0_0_0, + DO1=>open, DO2=>open, DO3=>open); + + sram_1_1_0: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Din(0), DI1=>scuba_vlo, DI2=>scuba_vlo, + DI3=>scuba_vlo, WCK=>Clock, WRE=>dec1_wre7, + RAD0=>shreg_addr_r0, RAD1=>shreg_addr_r1, + RAD2=>shreg_addr_r2, RAD3=>shreg_addr_r3, + WAD0=>shreg_addr_w0, WAD1=>shreg_addr_w1, + WAD2=>shreg_addr_w2, WAD3=>shreg_addr_w3, DO0=>mdL0_1_0, + DO1=>open, DO2=>open, DO3=>open); + + sram_1_2_0: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Din(0), DI1=>scuba_vlo, DI2=>scuba_vlo, + DI3=>scuba_vlo, WCK=>Clock, WRE=>dec2_wre11, + RAD0=>shreg_addr_r0, RAD1=>shreg_addr_r1, + RAD2=>shreg_addr_r2, RAD3=>shreg_addr_r3, + WAD0=>shreg_addr_w0, WAD1=>shreg_addr_w1, + WAD2=>shreg_addr_w2, WAD3=>shreg_addr_w3, DO0=>mdL0_2_0, + DO1=>open, DO2=>open, DO3=>open); + + sram_1_3_0: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Din(0), DI1=>scuba_vlo, DI2=>scuba_vlo, + DI3=>scuba_vlo, WCK=>Clock, WRE=>dec3_wre15, + RAD0=>shreg_addr_r0, RAD1=>shreg_addr_r1, + RAD2=>shreg_addr_r2, RAD3=>shreg_addr_r3, + WAD0=>shreg_addr_w0, WAD1=>shreg_addr_w1, + WAD2=>shreg_addr_w2, WAD3=>shreg_addr_w3, DO0=>mdL0_3_0, + DO1=>open, DO2=>open, DO3=>open); + + sram_1_4_0: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Din(0), DI1=>scuba_vlo, DI2=>scuba_vlo, + DI3=>scuba_vlo, WCK=>Clock, WRE=>dec4_wre19, + RAD0=>shreg_addr_r0, RAD1=>shreg_addr_r1, + RAD2=>shreg_addr_r2, RAD3=>shreg_addr_r3, + WAD0=>shreg_addr_w0, WAD1=>shreg_addr_w1, + WAD2=>shreg_addr_w2, WAD3=>shreg_addr_w3, DO0=>mdL0_4_0, + DO1=>open, DO2=>open, DO3=>open); + + sram_1_5_0: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Din(0), DI1=>scuba_vlo, DI2=>scuba_vlo, + DI3=>scuba_vlo, WCK=>Clock, WRE=>dec5_wre23, + RAD0=>shreg_addr_r0, RAD1=>shreg_addr_r1, + RAD2=>shreg_addr_r2, RAD3=>shreg_addr_r3, + WAD0=>shreg_addr_w0, WAD1=>shreg_addr_w1, + WAD2=>shreg_addr_w2, WAD3=>shreg_addr_w3, DO0=>mdL0_5_0, + DO1=>open, DO2=>open, DO3=>open); + + sram_1_6_0: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Din(0), DI1=>scuba_vlo, DI2=>scuba_vlo, + DI3=>scuba_vlo, WCK=>Clock, WRE=>dec6_wre27, + RAD0=>shreg_addr_r0, RAD1=>shreg_addr_r1, + RAD2=>shreg_addr_r2, RAD3=>shreg_addr_r3, + WAD0=>shreg_addr_w0, WAD1=>shreg_addr_w1, + WAD2=>shreg_addr_w2, WAD3=>shreg_addr_w3, DO0=>mdL0_6_0, + DO1=>open, DO2=>open, DO3=>open); + + sram_1_7_0: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Din(0), DI1=>scuba_vlo, DI2=>scuba_vlo, + DI3=>scuba_vlo, WCK=>Clock, WRE=>dec7_wre31, + RAD0=>shreg_addr_r0, RAD1=>shreg_addr_r1, + RAD2=>shreg_addr_r2, RAD3=>shreg_addr_r3, + WAD0=>shreg_addr_w0, WAD1=>shreg_addr_w1, + WAD2=>shreg_addr_w2, WAD3=>shreg_addr_w3, DO0=>mdL0_7_0, + DO1=>open, DO2=>open, DO3=>open); + + sram_1_8_0: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Din(0), DI1=>scuba_vlo, DI2=>scuba_vlo, + DI3=>scuba_vlo, WCK=>Clock, WRE=>dec8_wre35, + RAD0=>shreg_addr_r0, RAD1=>shreg_addr_r1, + RAD2=>shreg_addr_r2, RAD3=>shreg_addr_r3, + WAD0=>shreg_addr_w0, WAD1=>shreg_addr_w1, + WAD2=>shreg_addr_w2, WAD3=>shreg_addr_w3, DO0=>mdL0_8_0, + DO1=>open, DO2=>open, DO3=>open); + + sram_1_9_0: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Din(0), DI1=>scuba_vlo, DI2=>scuba_vlo, + DI3=>scuba_vlo, WCK=>Clock, WRE=>dec9_wre39, + RAD0=>shreg_addr_r0, RAD1=>shreg_addr_r1, + RAD2=>shreg_addr_r2, RAD3=>shreg_addr_r3, + WAD0=>shreg_addr_w0, WAD1=>shreg_addr_w1, + WAD2=>shreg_addr_w2, WAD3=>shreg_addr_w3, DO0=>mdL0_9_0, + DO1=>open, DO2=>open, DO3=>open); + + sram_1_10_0: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Din(0), DI1=>scuba_vlo, DI2=>scuba_vlo, + DI3=>scuba_vlo, WCK=>Clock, WRE=>dec10_wre43, + RAD0=>shreg_addr_r0, RAD1=>shreg_addr_r1, + RAD2=>shreg_addr_r2, RAD3=>shreg_addr_r3, + WAD0=>shreg_addr_w0, WAD1=>shreg_addr_w1, + WAD2=>shreg_addr_w2, WAD3=>shreg_addr_w3, DO0=>mdL0_10_0, + DO1=>open, DO2=>open, DO3=>open); + + sram_1_11_0: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Din(0), DI1=>scuba_vlo, DI2=>scuba_vlo, + DI3=>scuba_vlo, WCK=>Clock, WRE=>dec11_wre47, + RAD0=>shreg_addr_r0, RAD1=>shreg_addr_r1, + RAD2=>shreg_addr_r2, RAD3=>shreg_addr_r3, + WAD0=>shreg_addr_w0, WAD1=>shreg_addr_w1, + WAD2=>shreg_addr_w2, WAD3=>shreg_addr_w3, DO0=>mdL0_11_0, + DO1=>open, DO2=>open, DO3=>open); + + sram_1_12_0: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Din(0), DI1=>scuba_vlo, DI2=>scuba_vlo, + DI3=>scuba_vlo, WCK=>Clock, WRE=>dec12_wre51, + RAD0=>shreg_addr_r0, RAD1=>shreg_addr_r1, + RAD2=>shreg_addr_r2, RAD3=>shreg_addr_r3, + WAD0=>shreg_addr_w0, WAD1=>shreg_addr_w1, + WAD2=>shreg_addr_w2, WAD3=>shreg_addr_w3, DO0=>mdL0_12_0, + DO1=>open, DO2=>open, DO3=>open); + + sram_1_13_0: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Din(0), DI1=>scuba_vlo, DI2=>scuba_vlo, + DI3=>scuba_vlo, WCK=>Clock, WRE=>dec13_wre55, + RAD0=>shreg_addr_r0, RAD1=>shreg_addr_r1, + RAD2=>shreg_addr_r2, RAD3=>shreg_addr_r3, + WAD0=>shreg_addr_w0, WAD1=>shreg_addr_w1, + WAD2=>shreg_addr_w2, WAD3=>shreg_addr_w3, DO0=>mdL0_13_0, + DO1=>open, DO2=>open, DO3=>open); + + sram_1_14_0: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Din(0), DI1=>scuba_vlo, DI2=>scuba_vlo, + DI3=>scuba_vlo, WCK=>Clock, WRE=>dec14_wre59, + RAD0=>shreg_addr_r0, RAD1=>shreg_addr_r1, + RAD2=>shreg_addr_r2, RAD3=>shreg_addr_r3, + WAD0=>shreg_addr_w0, WAD1=>shreg_addr_w1, + WAD2=>shreg_addr_w2, WAD3=>shreg_addr_w3, DO0=>mdL0_14_0, + DO1=>open, DO2=>open, DO3=>open); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + sram_1_15_0: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Din(0), DI1=>scuba_vlo, DI2=>scuba_vlo, + DI3=>scuba_vlo, WCK=>Clock, WRE=>dec15_wre63, + RAD0=>shreg_addr_r0, RAD1=>shreg_addr_r1, + RAD2=>shreg_addr_r2, RAD3=>shreg_addr_r3, + WAD0=>shreg_addr_w0, WAD1=>shreg_addr_w1, + WAD2=>shreg_addr_w2, WAD3=>shreg_addr_w3, DO0=>mdL0_15_0, + DO1=>open, DO2=>open, DO3=>open); + +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of delay_shift_reg is + for Structure + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FSUB2B use entity ecp3.FSUB2B(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:MUX161 use entity ecp3.MUX161(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:DPR16X4C use entity ecp3.DPR16X4C(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/triggerbox/par.p2t b/triggerbox/par.p2t new file mode 100644 index 0000000..3324919 --- /dev/null +++ b/triggerbox/par.p2t @@ -0,0 +1,21 @@ +-w +-i 15 +-l 5 +-n 1 +-y +-s 12 +-t 26 +-c 1 +-e 4 +#-g guidefile.ncd +#-m nodelist.txt +# -w +# -i 6 +# -l 5 +# -n 1 +# -t 1 +# -s 1 +# -c 0 +# -e 0 +# +-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1 diff --git a/triggerbox/sim/triggerbox.mpf b/triggerbox/sim/triggerbox.mpf new file mode 100644 index 0000000..24a3713 --- /dev/null +++ b/triggerbox/sim/triggerbox.mpf @@ -0,0 +1,1805 @@ +; Copyright 1991-2012 Mentor Graphics Corporation +; +; All Rights Reserved. +; +; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF +; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. +; + +[Library] +std = $MODEL_TECH/../std +ieee = $MODEL_TECH/../ieee +vital2000 = $MODEL_TECH/../vital2000 +; +; VITAL concerns: +; +; The library ieee contains (among other packages) the packages of the +; VITAL 2000 standard. When a design uses VITAL 2000 exclusively, it should use +; the physical library ieee (recommended), or use the physical library +; vital2000, but not both. The design can use logical library ieee and/or +; vital2000 as long as each of these maps to the same physical library, either +; ieee or vital2000. +; +; A design using the 1995 version of the VITAL packages, whether or not +; it also uses the 2000 version of the VITAL packages, must have logical library +; name ieee mapped to physical library vital1995. (A design cannot use library +; vital1995 directly because some packages in this library use logical name ieee +; when referring to the other packages in the library.) The design source +; should use logical name ieee when referring to any packages there except the +; VITAL 2000 packages. Any VITAL 2000 present in the design must use logical +; name vital2000 (mapped to physical library vital2000) to refer to those +; packages. +; ieee = $MODEL_TECH/../vital1995 +; +; For compatiblity with previous releases, logical library name vital2000 maps +; to library vital2000 (a different library than library ieee, containing the +; same packages). +; A design should not reference VITAL from both the ieee library and the +; vital2000 library because the vital packages are effectively different. +; A design that references both the ieee and vital2000 libraries must have +; both logical names ieee and vital2000 mapped to the same library, either of +; these: +; $MODEL_TECH/../ieee +; $MODEL_TECH/../vital2000 +; +verilog = $MODEL_TECH/../verilog +std_developerskit = $MODEL_TECH/../std_developerskit +synopsys = $MODEL_TECH/../synopsys +modelsim_lib = $MODEL_TECH/../modelsim_lib +sv_std = $MODEL_TECH/../sv_std +mtiAvm = $MODEL_TECH/../avm +mtiOvm = $MODEL_TECH/../ovm-2.1.2 +mtiUvm = $MODEL_TECH/../uvm-1.1c +mtiUPF = $MODEL_TECH/../upf_lib +mtiPA = $MODEL_TECH/../pa_lib +floatfixlib = $MODEL_TECH/../floatfixlib +mc2_lib = $MODEL_TECH/../mc2_lib +;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release +;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release +;mvc_lib = $MODEL_TECH/../mvc_lib + +work = work +ecp3 = /d/jspc29/lattice/diamond/3.10_x64/ispfpga/vhdl/data/ecp3/mti/work +[vcom] +; VHDL93 variable selects language version as the default. +; Default is VHDL-2002. +; Value of 0 or 1987 for VHDL-1987. +; Value of 1 or 1993 for VHDL-1993. +; Default or value of 2 or 2002 for VHDL-2002. +; Value of 3 or 2008 for VHDL-2008 +VHDL93 = 2008 + +; Ignore VHDL-2008 declaration of REAL_VECTOR in package STANDARD. Default is off. +; ignoreStandardRealVector = 1 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; The .ini file has Explicit enabled so that std_logic_signed/unsigned +; will match the behavior of synthesis tools. +Explicit = 1 + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = 0 + +; Turn off PSL assertion warning messages. Default is to show warnings. +; Show_PslChecksWarnings = 0 + +; Enable parsing of embedded PSL assertions. Default is enabled. +; EmbeddedPsl = 0 + +; Keep silent about case statement static warnings. +; Default is to give a warning. +; NoCaseStaticError = 1 + +; Keep silent about warnings caused by aggregates that are not locally static. +; Default is to give a warning. +; NoOthersStaticError = 1 + +; Treat as errors: +; case statement static warnings +; warnings caused by aggregates that are not locally static +; Overrides NoCaseStaticError, NoOthersStaticError settings. +; PedanticErrors = 1 + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. +; RequireConfigForAllDefaultBinding = 1 + +; Perform default binding at compile time. +; Default is to do default binding at load time. +; BindAtCompile = 1; + +; Inhibit range checking on subscripts of arrays. Range checking on +; scalars defined with subtypes is inhibited by default. +; NoIndexCheck = 1 + +; Inhibit range checks on all (implicit and explicit) assignments to +; scalar objects defined with subtypes. +; NoRangeCheck = 1 + +; Run the 0-in compiler on the VHDL source files +; Default is off. +; ZeroIn = 1 + +; Set the options to be passed to the 0-in compiler. +; Default is "". +; ZeroInOptions = "" + +; Set the prefix to be honored for synthesis/coverage pragma recognition. +; Default is "". +; AddPragmaPrefix = "" + +; Ignore synthesis and coverage pragmas with this prefix. +; Default is "". +; IgnorePragmaPrefix = "" + +; Turn on code coverage in VHDL design units. Default is off. +; Coverage = sbceft + +; Turn off code coverage in VHDL subprograms. Default is on. +; CoverSub = 0 + +; Automatically exclude VHDL case statement OTHERS choice branches. +; This includes OTHERS choices in selected signal assigment statements. +; Default is to not exclude. +; CoverExcludeDefault = 1 + +; Control compiler and VOPT optimizations that are allowed when +; code coverage is on. Refer to the comment for this in the [vlog] area. +; CoverOpt = 3 + +; Turn on or off clkOpt optimization for code coverage. Default is on. +; CoverClkOpt = 1 + +; Turn on or off clkOpt optimization builtins for code coverage. Default is on. +; CoverClkOptBuiltins = 0 + +; Inform code coverage optimizations to respect VHDL 'H' and 'L' +; values on signals in conditions and expressions, and to not automatically +; convert them to '1' and '0'. Default is to not convert. +; CoverRespectHandL = 0 + +; Increase or decrease the maximum number of rows allowed in a FEC table, implementing +; a condition coverage or expression coverage expression, by changing FecEffort. +; Higher FecEffort leads to a longer compile time, but more expressions covered. +; This is a number from 1 to 3, with the following meanings (the default is 1): +; 3 -- High FecEffort, Allows large expressions to be covered, will cause longer compile time. +; 2 -- Medium FecEffort, Allows more number of inputs per expression than Low FecEffort to be covered. +; 1 -- Low FecEffort, Covers only small expressions or conditions and skips larger ones. +; FecEffort = 2 + +; Enable or disable Focused Expression Coverage analysis for conditions and +; expressions. Focused Expression Coverage data is provided by default when +; expression and/or condition coverage is active. +; CoverFEC = 0 + +; Enable or disable UDP Coverage analysis for conditions and expressions. +; UDP Coverage data is disabled by default when expression and/or condition +; coverage is active. +; CoverUDP = 1 + +; Enable or disable short circuit evaluation of conditions and expressions when +; condition or expression coverage is active. Short circuit evaluation is enabled +; by default. +; CoverShortCircuit = 0 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Use this directory for compiler temporary files instead of "work/_temp" +; CompilerTempDir = /tmp + +; Set this to cause the compilers to force data to be committed to disk +; when the files are closed. +; SyncCompilerFiles = 1 + +; Add VHDL-AMS declarations to package STANDARD +; Default is not to add +; AmsStandard = 1 + +; Range and length checking will be performed on array indices and discrete +; ranges, and when violations are found within subprograms, errors will be +; reported. Default is to issue warnings for violations, because subprograms +; may not be invoked. +; NoDeferSubpgmCheck = 0 + +; Turn ON detection of FSMs having single bit current state variable. +; FsmSingle = 1 + +; Turn off reset state transitions in FSM. +; FsmResetTrans = 0 + +; Turn ON detection of FSM Implicit Transitions. +; FsmImplicitTrans = 1 + +; Controls whether or not to show immediate assertions with constant expressions +; in GUI/report/UCDB etc. By default, immediate assertions with constant +; expressions are shown in GUI/report/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Controls how VHDL basic identifiers are stored with the design unit. +; Does not make the language case-sensitive, affects only how declarations +; declared with basic identifiers have their names stored and printed +; (in the GUI, examine, etc.). +; Default is to preserve the case as originally depicted in the VHDL source. +; Value of 0 indicates to change all basic identifiers to lower case. +; PreserveCase = 0 + +; For Configuration Declarations, controls the effect that USE clauses have +; on visibility inside the configuration items being configured. If 1 +; (the default), then use pre-10.0 behavior. If 0, then for stricter LRM-compliance, +; extend the visibility of objects made visible through USE clauses into nested +; component configurations. +; OldVHDLConfigurationVisibility = 0 + +; Allows VHDL configuration declarations to be in a different library from +; the corresponding configured entity. Default is to not allow this for +; stricter LRM-compliance. +; SeparateConfigLibrary = 1; + +; Determine how mode OUT subprogram parameters of type array and record are treated. +; If 0 (the default), then only VHDL 2008 will do this initialization. +; If 1, always initialize the mode OUT parameter to its default value. +; If 2, do not initialize the mode OUT out parameter. +; Note that prior to release 10.1, all language versions did not initialize mode +; OUT array and record type parameters, unless overridden here via this mechanism. +; In release 10.1 and later, only files compiled with VHDL 2008 will cause this +; initialization, unless overridden here. +; InitOutCompositeParam = 0 + +[vlog] +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn on `protect compiler directive processing. +; Default is to ignore `protect directives. +; Protect = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn on bad option warning. Default is off. +; Show_BadOptionWarning = 1 + +; Revert back to IEEE 1364-1995 syntax, default is 0 (off). +; vlog95compat = 1 + +; Turn off PSL warning messages. Default is to show warnings. +; Show_PslChecksWarnings = 0 + +; Enable parsing of embedded PSL assertions. Default is enabled. +; EmbeddedPsl = 0 + +; Set the threshold for automatically identifying sparse Verilog memories. +; A memory with depth equal to or more than the sparse memory threshold gets +; marked as sparse automatically, unless specified otherwise in source code +; or by +nosparse commandline option of vlog or vopt. +; The default is 1M. (i.e. memories with depth equal +; to or greater than 1M are marked as sparse) +; SparseMemThreshold = 1048576 + +; Run the 0-in compiler on the Verilog source files +; Default is off. +; ZeroIn = 1 + +; Set the options to be passed to the 0-in compiler. +; Default is "". +; ZeroInOptions = "" + +; Set the prefix to be honored for synthesis and coverage pragma recognition. +; Default is "". +; AddPragmaPrefix = "" + +; Ignore synthesis and coverage pragmas with this prefix. +; Default is "". +; IgnorePragmaPrefix = "" + +; Set the option to treat all files specified in a vlog invocation as a +; single compilation unit. The default value is set to 0 which will treat +; each file as a separate compilation unit as specified in the P1800 draft standard. +; MultiFileCompilationUnit = 1 + +; Turn on code coverage in Verilog design units. Default is off. +; Coverage = sbceft + +; Automatically exclude Verilog case statement default branches. +; Default is to not automatically exclude defaults. +; CoverExcludeDefault = 1 + +; Increase or decrease the maximum number of rows allowed in a FEC table, implementing +; a condition coverage or expression coverage expression, by changing FecEffort. +; Higher FecEffort leads to a longer compile time, but more expressions covered. +; This is a number from 1 to 3, with the following meanings (the default is 1): +; 3 -- High FecEffort, Allows large expressions to be covered, will cause longer compile time. +; 2 -- Medium FecEffort, Allows more number of inputs per expression than Low FecEffort to be covered. +; 1 -- Low FecEffort, Covers only small expressions or conditions and skips larger ones. +; FecEffort = 2 + +; Enable or disable Focused Expression Coverage analysis for conditions and +; expressions. Focused Expression Coverage data is provided by default when +; expression and/or condition coverage is active. +; CoverFEC = 0 + +; Enable or disable UDP Coverage analysis for conditions and expressions. +; UDP Coverage data is disabled by default when expression and/or condition +; coverage is active. +; CoverUDP = 1 + +; Enable or disable short circuit evaluation of conditions and expressions when +; condition or expression coverage is active. Short circuit evaluation is enabled +; by default. +; CoverShortCircuit = 0 + + +; Turn on code coverage in VLOG `celldefine modules, modules containing +; specify blocks, and modules included using vlog -v and -y. Default is off. +; CoverCells = 1 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Control compiler and VOPT optimizations that are allowed when +; code coverage is on. This is a number from 0 to 5, with the following +; meanings (the default is 3): +; 5 -- All allowable optimizations are on. +; 4 -- Turn off removing unreferenced code. +; 3 -- Turn off process, always block and if statement merging. +; 2 -- Turn off expression optimization, converting primitives +; to continuous assignments, VHDL subprogram inlining. +; and VHDL clkOpt (converting FF's to builtins). +; 1 -- Turn off continuous assignment optimizations and clock suppression. +; 0 -- Turn off Verilog module inlining and VHDL arch inlining. +; HOWEVER, if fsm coverage is turned on, optimizations will be forced to +; level 3, with also turning off converting primitives to continuous assigns. +; CoverOpt = 3 + +; Specify the override for the default value of "cross_num_print_missing" +; option for the Cross in Covergroups. If not specified then LRM default +; value of 0 (zero) is used. This is a compile time option. +; SVCrossNumPrintMissingDefault = 0 + +; Setting following to 1 would cause creation of variables which +; would represent the value of Coverpoint expressions. This is used +; in conjunction with "SVCoverpointExprVariablePrefix" option +; in the modelsim.ini +; EnableSVCoverpointExprVariable = 0 + +; Specify the override for the prefix used in forming the variable names +; which represent the Coverpoint expressions. This is used in conjunction with +; "EnableSVCoverpointExprVariable" option of the modelsim.ini +; The default prefix is "expr". +; The variable name is +; variable name => _ +; SVCoverpointExprVariablePrefix = expr + +; Override for the default value of the SystemVerilog covergroup, +; coverpoint, and cross option.goal (defined to be 100 in the LRM). +; NOTE: It does not override specific assignments in SystemVerilog +; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal" +; in the [vsim] section can override this value. +; SVCovergroupGoalDefault = 100 + +; Override for the default value of the SystemVerilog covergroup, +; coverpoint, and cross type_option.goal (defined to be 100 in the LRM) +; NOTE: It does not override specific assignments in SystemVerilog +; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal" +; in the [vsim] section can override this value. +; SVCovergroupTypeGoalDefault = 100 + +; Specify the override for the default value of "strobe" option for the +; Covergroup Type. This is a compile time option which forces "strobe" to +; a user specified default value and supersedes SystemVerilog specified +; default value of '0'(zero). NOTE: This can be overriden by a runtime +; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section. +; SVCovergroupStrobeDefault = 0 + +; Specify the override for the default value of "merge_instances" option for +; the Covergroup Type. This is a compile time option which forces +; "merge_instances" to a user specified default value and supersedes +; SystemVerilog specified default value of '0'(zero). +; SVCovergroupMergeInstancesDefault = 0 + +; Specify the override for the default value of "per_instance" option for the +; Covergroup variables. This is a compile time option which forces "per_instance" +; to a user specified default value and supersedes SystemVerilog specified +; default value of '0'(zero). +; SVCovergroupPerInstanceDefault = 0 + +; Specify the override for the default value of "get_inst_coverage" option for the +; Covergroup variables. This is a compile time option which forces +; "get_inst_coverage" to a user specified default value and supersedes +; SystemVerilog specified default value of '0'(zero). +; SVCovergroupGetInstCoverageDefault = 0 + +; +; A space separated list of resource libraries that contain precompiled +; packages. The behavior is identical to using the "-L" switch. +; +; LibrarySearchPath = [ ...] +LibrarySearchPath = mtiAvm mtiOvm mtiUvm mtiUPF + +; The behavior is identical to the "-mixedansiports" switch. Default is off. +; MixedAnsiPorts = 1 + +; Enable SystemVerilog 3.1a $typeof() function. Default is off. +; EnableTypeOf = 1 + +; Only allow lower case pragmas. Default is disabled. +; AcceptLowerCasePragmaOnly = 1 + +; Set the maximum depth permitted for a recursive include file nesting. +; IncludeRecursionDepthMax = 5 + +; Turn ON detection of FSMs having single bit current state variable. +; FsmSingle = 1 + +; Turn off reset state transitions in FSM. +; FsmResetTrans = 0 + +; Turn off detections of FSMs having x-assignment. +; FsmXAssign = 0 + +; Turn ON detection of FSM Implicit Transitions. +; FsmImplicitTrans = 1 + +; List of file suffixes which will be read as SystemVerilog. White space +; in extensions can be specified with a back-slash: "\ ". Back-slashes +; can be specified with two consecutive back-slashes: "\\"; +; SVFileExtensions = sv svp svh + +; This setting is the same as the vlog -sv command line switch. +; Enables SystemVerilog features and keywords when true (1). +; When false (0), the rules of IEEE Std 1364-2001 are followed and +; SystemVerilog keywords are ignored. +; Svlog = 0 + +; Prints attribute placed upon SV packages during package import +; when true (1). The attribute will be ignored when this +; entry is false (0). The attribute name is "package_load_message". +; The value of this attribute is a string literal. +; Default is true (1). +; PrintSVPackageLoadingAttribute = 1 + +; Do not show immediate assertions with constant expressions in +; GUI/reports/UCDB etc. By default immediate assertions with constant +; expressions are shown in GUI/reports/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Controls if untyped parameters that are initialized with values greater +; than 2147483647 are mapped to generics of type INTEGER or ignored. +; If mapped to VHDL Integers, values greater than 2147483647 +; are mapped to negative values. +; Default is to map these parameter to generic of type INTEGER +; ForceUnsignedToVHDLInteger = 1 + +; Enable AMS wreal (wired real) extensions. Default is 0. +; WrealType = 1 + +; Controls SystemVerilog Language Extensions. These options enable +; some non-LRM compliant behavior. Valid extensions are "feci", +; "pae", "uslt" and "spsl". +; SVExtensions = uslt,spsl + +[sccom] +; Enable use of SCV include files and library. Default is off. +; UseScv = 1 + +; Add C++ compiler options to the sccom command line by using this variable. +; CppOptions = -g + +; Use custom C++ compiler located at this path rather than the default path. +; The path should point directly at a compiler executable. +; CppPath = /usr/bin/g++ + +; Enable verbose messages from sccom. Default is off. +; SccomVerbose = 1 + +; sccom logfile. Default is no logfile. +; SccomLogfile = sccom.log + +; Enable use of SC_MS include files and library. Default is off. +; UseScMs = 1 + +[vopt] +; Turn on code coverage in vopt. Default is off. +; Coverage = sbceft + +; Control compiler optimizations that are allowed when +; code coverage is on. Refer to the comment for this in the [vlog] area. +; CoverOpt = 3 + +; Increase or decrease the maximum number of rows allowed in a FEC table, implementing +; a condition coverage or expression coverage expression, by changing FecEffort. +; Higher FecEffort leads to a longer compile time, but more expressions covered. +; This is a number from 1 to 3, with the following meanings (the default is 1): +; 3 -- High FecEffort, Allows large expressions to be covered, will cause longer compile time. +; 2 -- Medium FecEffort, Allows more number of inputs per expression than Low FecEffort to be covered. +; 1 -- Low FecEffort, Covers only small expressions or conditions and skips larger ones. +; FecEffort = 2 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Do not show immediate assertions with constant expressions in +; GUI/reports/UCDB etc. By default immediate assertions with constant +; expressions are shown in GUI/reports/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Set the maximum number of iterations permitted for a generate loop. +; Restricting this permits the implementation to recognize infinite +; generate loops. +; GenerateLoopIterationMax = 100000 + +; Set the maximum depth permitted for a recursive generate instantiation. +; Restricting this permits the implementation to recognize infinite +; recursions. +; GenerateRecursionDepthMax = 200 + +; Set the number of processes created during the code generation phase. +; By default a heuristic is used to set this value. This may be set to 0 +; to disable this feature completely. +; ParallelJobs = 0 + +; Controls SystemVerilog Language Extensions. These options enable +; some non-LRM compliant behavior. Valid extensions are "feci", +; "pae", "uslt" and "spsl". +; SVExtensions = uslt,spsl + +[vsim] +; vopt flow +; Set to turn on automatic optimization of a design. +; Default is on +VoptFlow = 1 + +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +Resolution = ns + +; Disable certain code coverage exclusions automatically. +; Assertions and FSM are exluded from the code coverage by default +; Set AutoExclusionsDisable = fsm to enable code coverage for fsm +; Set AutoExclusionsDisable = assertions to enable code coverage for assertions +; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions +; Or specify comma or space separated list +;AutoExclusionsDisable = fsm,assertions + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +; Should generally be set to default. +UserTimeUnit = default + +; Default run length +RunLength = 1 us + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 5000 + +; Control PSL and Verilog Assume directives during simulation +; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts +; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts +; SimulateAssumeDirectives = 1 + +; Control the simulation of PSL and SVA +; These switches can be overridden by the vsim command line switches: +; -psl, -nopsl, -sva, -nosva. +; Set SimulatePSL = 0 to disable PSL simulation +; Set SimulatePSL = 1 to enable PSL simulation (default) +; SimulatePSL = 1 +; Set SimulateSVA = 0 to disable SVA simulation +; Set SimulateSVA = 1 to enable concurrent SVA simulation (default) +; SimulateSVA = 1 + +; Control SVA and VHDL immediate assertion directives during simulation +; Set SimulateImmedAsserts = 0 to disable simulation of immediate asserts +; Set SimulateImmedAsserts = 1 to enable simulation of immediate asserts +; SimulateImmedAsserts = 1 + +; Directives to license manager can be set either as single value or as +; space separated multi-values: +; vhdl Immediately reserve a VHDL license +; vlog Immediately reserve a Verilog license +; plus Immediately reserve a VHDL and Verilog license +; noqueue Do not wait in the license queue when a license is not available +; viewsim Try for viewer license but accept simulator license(s) instead +; of queuing for viewer license (PE ONLY) +; noviewer Disable checkout of msimviewer and vsim-viewer license +; features (PE ONLY) +; noslvhdl Disable checkout of qhsimvh and vsim license features +; noslvlog Disable checkout of qhsimvl and vsimvlog license features +; nomix Disable checkout of msimhdlmix and hdlmix license features +; nolnl Disable checkout of msimhdlsim and hdlsim license features +; mixedonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog license +; features +; lnlonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog,msimhdlmix, +; hdlmix license features +; Single value: +; License = plus +; Multi-value: +; License = noqueue plus + +; Severity level of a VHDL assertion message or of a SystemVerilog immediate assertion +; which will cause a running simulation to stop. +; VHDL assertions and SystemVerilog immediate assertions that occur with the +; given severity or higher will cause a running simulation to stop. +; This value is ignored during elaboration. +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; The class debug feature enables more visibility and tracking of class instances +; during simulation. By default this feature is 0 (disabled). To enable this +; feature set ClassDebug to 1. +; ClassDebug = 1 + +; Message Format conversion specifications: +; %S - Severity Level of message/assertion +; %R - Text of message +; %T - Time of message +; %D - Delta value (iteration number) of Time +; %K - Kind of path: Instance/Region/Signal/Process/Foreign Process/Unknown/Protected +; %i - Instance/Region/Signal pathname with Process name (if available) +; %I - shorthand for one of these: +; " %K: %i" +; " %K: %i File: %F" (when path is not Process or Signal) +; except that the %i in this case does not report the Process name +; %O - Process name +; %P - Instance/Region path without leaf process +; %F - File name +; %L - Line number; if assertion message, then line number of assertion or, if +; assertion is in a subprogram, line from which the call is made +; %u - Design unit name in form library.primary +; %U - Design unit name in form library.primary(secondary) +; %% - The '%' character itself +; +; If specific format for Severity Level is defined, use that format. +; Else, for a message that occurs during elaboration: +; -- Failure/Fatal message in VHDL region that is not a Process, and in +; certain non-VHDL regions, uses MessageFormatBreakLine; +; -- Failure/Fatal message otherwise uses MessageFormatBreak; +; -- Note/Warning/Error message uses MessageFormat. +; Else, for a message that occurs during runtime and triggers a breakpoint because +; of the BreakOnAssertion setting: +; -- if in a VHDL region that is not a Process, uses MessageFormatBreakLine; +; -- otherwise uses MessageFormatBreak. +; Else (a runtime message that does not trigger a breakpoint) uses MessageFormat. +; +; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n" +; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" + +; Error File - alternate file for storing error messages +; ErrorFile = error.log + +; Simulation Breakpoint messages +; This flag controls the display of function names when reporting the location +; where the simulator stops because of a breakpoint or fatal error. +; Example with function name: # Break in Process ctr at counter.vhd line 44 +; Example without function name: # Break at counter.vhd line 44 +; Default value is 1. +ShowFunctions = 1 + +; Default radix for all windows and commands. +; Radix may be one of: symbolic, ascii, binary, octal, decimal, hex, unsigned +; Flags may be one of: enumnumeric, showbase +DefaultRadix = symbolic +;DefaultRadixFlags = showbase + +; VSIM Startup command +; Startup = do startup.do + +; VSIM Shutdown file +; Filename to save u/i formats and configurations. +; ShutdownFile = restart.do +; To explicitly disable auto save: +; ShutdownFile = --disable-auto-save + +; File for saving command transcript +TranscriptFile = transcript + +; File for saving command history +; CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. +; For VHDL, PathSeparator = / +; For Verilog, PathSeparator = . +; Must not be the same character as DatasetSeparator. +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example: sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Specify a unique path separator for the Signal Spy set of functions. +; The default will be to use the PathSeparator variable. +; Must not be the same character as DatasetSeparator. +; SignalSpyPathSeparator = / + +; Used to control parsing of HDL identifiers input to the tool. +; This includes CLI commands, vsim/vopt/vlog/vcom options, +; string arguments to FLI/VPI/DPI calls, etc. +; If set to 1, accept either Verilog escaped Id syntax or +; VHDL extended id syntax, regardless of source language. +; If set to 0, the syntax of the source language must be used. +; Each identifier in a hierarchical name may need different syntax, +; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or +; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom" +; GenerousIdentifierParsing = 1 + +; Disable VHDL assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Disable SystemVerilog assertion messages +; IgnoreSVAInfo = 1 +; IgnoreSVAWarning = 1 +; IgnoreSVAError = 1 +; IgnoreSVAFatal = 1 + +; Do not print any additional information from Severity System tasks. +; Only the message provided by the user is printed along with severity +; information. +; SVAPrintOnlyUserMessage = 1; + +; Default force kind. May be freeze, drive, deposit, or default +; or in other terms, fixed, wired, or charged. +; A value of "default" will use the signal kind to determine the +; force kind, drive for resolved signals, freeze for unresolved signals +; DefaultForceKind = freeze + +; Control the iteration of events when a VHDL signal is forced to a value +; This flag can be set to honour the signal update event in next iteration, +; the default is to update and propagate in the same iteration. +; ForceSigNextIter = 1 + + +; If zero, open files when elaborated; otherwise, open files on +; first read or write. Default is 0. +; DelayFileOpen = 1 + +; Control VHDL files opened for write. +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control the number of VHDL files open concurrently. +; This number should always be less than the current ulimit +; setting for max file descriptors. +; 0 = unlimited +ConcurrentFileLimit = 40 + +; Control the number of hierarchical regions displayed as +; part of a signal name shown in the Wave window. +; A value of zero tells VSIM to display the full name. +; The default is 0. +; WaveSignalNameWidth = 0 + +; Turn off warnings when changing VHDL constants and generics +; Default is 1 to generate warning messages +; WarnConstantChange = 0 + +; Turn off warnings from accelerated versions of the std_logic_arith, +; std_logic_unsigned, and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from accelerated versions of the IEEE numeric_std +; and numeric_bit packages. +; NumericStdNoWarnings = 1 + +; Use old-style (pre-6.6) VHDL FOR generate statement iteration names +; in the design hierarchy. +; This style is controlled by the value of the GenerateFormat +; value described next. Default is to use new-style names, which +; comprise the generate statement label, '(', the value of the generate +; parameter, and a closing ')'. +; Uncomment this to use old-style names. +; OldVhdlForGenNames = 1 + +; Control the format of the old-style VHDL FOR generate statement region +; name for each iteration. Do not quote it. +; The format string here must contain the conversion codes %s and %d, +; in that order, and no other conversion codes. The %s represents +; the generate statement label; the %d represents the generate parameter value +; at a particular iteration (this is the position number if the generate parameter +; is of an enumeration type). Embedded whitespace is allowed (but discouraged); +; leading and trailing whitespace is ignored. +; Application of the format must result in a unique region name over all +; loop iterations for a particular immediately enclosing scope so that name +; lookup can function properly. The default is %s__%d. +; GenerateFormat = %s__%d + +; Enable changes in VHDL elaboration to allow for Variable Logging +; This trades off simulation performance for the ability to log variables +; efficiently. By default this is disable for maximum simulation performance +; VhdlVariableLogging = 1 + +; Specify whether checkpoint files should be compressed. +; The default is 1 (compressed). +; CheckpointCompressMode = 0 + +; Specify gcc compiler used in the compilation of automatically generated DPI exportwrapper. +; Use custom gcc compiler located at this path rather than the default path. +; The path should point directly at a compiler executable. +; DpiCppPath = /bin/gcc + +; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls. +; The term "out-of-the-blue" refers to SystemVerilog export function calls +; made from C functions that don't have the proper context setup +; (as is the case when running under "DPI-C" import functions). +; When this is enabled, one can call a DPI export function +; (but not task) from any C code. +; the setting of this variable can be one of the following values: +; 0 : dpioutoftheblue call is disabled (default) +; 1 : dpioutoftheblue call is enabled, but export call debug support is not available. +; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available. +; DpiOutOfTheBlue = 1 + +; Specify whether continuous assignments are run before other normal priority +; processes scheduled in the same iteration. This event ordering minimizes race +; differences between optimized and non-optimized designs, and is the default +; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set +; ImmediateContinuousAssign to 0. +; The default is 1 (enabled). +; ImmediateContinuousAssign = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + +; Which default VPI object model should the tool conform to? +; The 1364 modes are Verilog-only, for backwards compatibility with older +; libraries, and SystemVerilog objects are not available in these modes. +; +; In the absence of a user-specified default, the tool default is the +; latest available LRM behavior. +; Options for PliCompatDefault are: +; VPI_COMPATIBILITY_VERSION_1364v1995 +; VPI_COMPATIBILITY_VERSION_1364v2001 +; VPI_COMPATIBILITY_VERSION_1364v2005 +; VPI_COMPATIBILITY_VERSION_1800v2005 +; VPI_COMPATIBILITY_VERSION_1800v2008 +; +; Synonyms for each string are also recognized: +; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995) +; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001) +; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005) +; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005) +; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008) + + +; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005 + +; Specify whether the Verilog system task $fopen or vpi_mcd_open() +; will create directories that do not exist when opening the file +; in "a" or "w" mode. +; The default is 0 (do not create non-existent directories) +; CreateDirForFileAccess = 1 + +; Specify default options for the restart command. Options can be one +; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions +; DefaultRestartOptions = -force + + +; Specify default UVM-aware debug options if the vsim -uvmcontrol switch is not used. +; Valid options include: all, none, verbose, disable, struct, msglog, trlog, certe. +; Options can be enabled by just adding the name, or disabled by prefixing the option with a "-". +; The list of options must be delimited by commas, without spaces or tabs. +; The default is UVMControl = struct + +; Some examples +; To turn on all available UVM-aware debug features: +; UVMControl = all +; To turn on the struct window, mesage logging, and transaction logging: +; UVMControl = struct,msglog,trlog +; To turn on all options except certe: +; UVMControl = all,-certe +; To completely disable all UVM-aware debug functionality: +; UVMControl = disable + + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Specify whether or not a WLF file should be optimized during +; simulation. If set to 0, the WLF file will not be optimized. +; The default is 1, optimize the WLF file. +; WLFOptimize = 0 + +; Specify the name of the WLF file. +; The default is vsim.wlf +; WLFFilename = vsim.wlf + +; Specify whether to lock the WLF file. +; Locking the file prevents other invocations of ModelSim/Questa tools from +; inadvertently overwriting the WLF file. +; The default is 1, lock the WLF file. +; WLFFileLock = 0 + +; Specify the update interval for the WLF file. +; Value is the number of seconds between updated. After at least the +; interval number of seconds, the wlf file is flushed, ensuring that the data +; is correct when viewed from a separate live viewer. Setting to 0 means no +; updating. Default is 10 seconds, which has a tiny performance impact +; WLFUpdateInterval = 10 + +; Specify the WLF reader cache size limit for each open WLF file. +; The size is giving in megabytes. A value of 0 turns off the +; WLF cache. +; WLFSimCacheSize allows a different cache size to be set for +; simulation WLF file independent of post-simulation WLF file +; viewing. If WLFSimCacheSize is not set it defaults to the +; WLFCacheSize setting. +; The default WLFCacheSize setting is enabled to 2000M per open WLF file on most +; platforms; on Windows, the setting is 1000M to help avoid filling process memory. +; WLFCacheSize = 2000 +; WLFSimCacheSize = 500 + +; Specify the WLF file event collapse mode. +; 0 = Preserve all events and event order. (same as -wlfnocollapse) +; 1 = Only record values of logged objects at the end of a simulator iteration. +; (same as -wlfcollapsedelta) +; 2 = Only record values of logged objects at the end of a simulator time step. +; (same as -wlfcollapsetime) +; The default is 1. +; WLFCollapseMode = 0 + +; Specify whether WLF file logging can use threads on multi-processor machines +; if 0, no threads will be used, if 1, threads will be used if the system has +; more than one processor +; WLFUseThreads = 1 + +; Specify the relative size of logged objects that will trigger "large object" +; messages at log/wave/list time. This size value is an approximation of +; the number of bytes needed to store the value of the object before compression +; and optimization. +; The default LargeObjectSize size is 500k +; LargeObjectSize = 500000 + +; Specify whether to output "large object" warning messages. +; The default is 0 which means the warning messages will come out. +; LargeObjectSilent = 0 + +; Turn on/off undebuggable SystemC type warnings. Default is on. +; ShowUndebuggableScTypeWarning = 0 + +; Turn on/off unassociated SystemC name warnings. Default is off. +; ShowUnassociatedScNameWarning = 1 + +; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off. +; ScShowIeeeDeprecationWarnings = 1 + +; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off. +; ScEnableScSignalWriteCheck = 1 + +; Set SystemC default time unit. +; Set to fs, ps, ns, us, ms, or sec with optional +; prefix of 1, 10, or 100. The default is 1 ns. +; The ScTimeUnit value is honored if it is coarser than Resolution. +; If ScTimeUnit is finer than Resolution, it is set to the value +; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns, +; then the default time unit will be 1 ns. However if Resolution +; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns. +ScTimeUnit = ns + +; Set SystemC sc_main stack size. The stack size is set as an integer +; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or +; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends +; on the amount of data on the sc_main() stack and the memory required +; to succesfully execute the longest function call chain of sc_main(). +ScMainStackSize = 10 Mb + +; Turn on/off execution of remainder of sc_main upon quitting the current +; simulation session. If the cumulative length of sc_main() in terms of +; simulation time units is less than the length of the current simulation +; run upon quit or restart, sc_main() will be in the middle of execution. +; This switch gives the option to execute the remainder of sc_main upon +; quitting simulation. The drawback of not running sc_main till the end +; is memory leaks for objects created by sc_main. If on, the remainder of +; sc_main will be executed ignoring all delays. This may cause the simulator +; to crash if the code in sc_main is dependent on some simulation state. +; Default is on. +ScMainFinishOnQuit = 1 + +; Set the SCV relationship name that will be used to identify phase +; relations. If the name given to a transactor relation matches this +; name, the transactions involved will be treated as phase transactions +ScvPhaseRelationName = mti_phase + +; Customize the vsim kernel shutdown behavior at the end of the simulation. +; Some common causes of the end of simulation are $finish (implicit or explicit), +; sc_stop(), tf_dofinish(), and assertion failures. +; This should be set to "ask", "exit", or "stop". The default is "ask". +; "ask" -- In batch mode, the vsim kernel will abruptly exit. +; In GUI mode, a dialog box will pop up and ask for user confirmation +; whether or not to quit the simulation. +; "stop" -- Cause the simulation to stay loaded in memory. This can make some +; post-simulation tasks easier. +; "exit" -- The simulation will abruptly exit without asking for any confirmation. +; "final" -- Run SystemVerilog final blocks then behave as "stop". +; Note: This variable can be overridden with the vsim "-onfinish" command line switch. +OnFinish = ask + +; Print pending deferred assertion messages. +; Deferred assertion messages may be scheduled after the $finish in the same +; time step. Deferred assertions scheduled to print after the $finish are +; printed before exiting with severity level NOTE since it's not known whether +; the assertion is still valid due to being printed in the active region +; instead of the reactive region where they are normally printed. +; OnFinishPendingAssert = 1; + +; Print "simstats" result +; 0 == do not print simstats +; 1 == print at end of simulation +; 2 == print at end of run +; 3 == print at end of run and end of simulation +; default == 0 +; PrintSimStats = 1 + + +; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages +; AssertFile = assert.log + +; Enable assertion counts. Default is off. +; AssertionCover = 1 + +; Run simulator in assertion debug mode. Default is off. +; AssertionDebug = 1 + +; Turn on/off PSL/SVA/VHDL assertion enable. Default is on. +; AssertionEnable = 0 + +; Set PSL/SVA/VHDL concurrent assertion fail limit. Default is -1. +; Any positive integer, -1 for infinity. +; AssertionLimit = 1 + +; Turn on/off concurrent assertion pass log. Default is off. +; Assertion pass logging is only enabled when assertion is browseable +; and assertion debug is enabled. +; AssertionPassLog = 1 + +; Turn on/off PSL concurrent assertion fail log. Default is on. +; The flag does not affect SVA +; AssertionFailLog = 0 + +; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on. +; AssertionFailLocalVarLog = 0 + +; Set action type for PSL/SVA concurrent assertion fail action. Default is continue. +; 0 = Continue 1 = Break 2 = Exit +; AssertionFailAction = 1 + +; Enable the active thread monitor in the waveform display when assertion debug is enabled. +; AssertionActiveThreadMonitor = 1 + +; Control how many waveform rows will be used for displaying the active threads. Default is 5. +; AssertionActiveThreadMonitorLimit = 5 + +; Assertion thread limit after which assertion would be killed/switched off. +; The default is -1 (unlimited). If the number of threads for an assertion go +; beyond this limit, the assertion would be either switched off or killed. This +; limit applies to only assert directives. +;AssertionThreadLimit = -1 + +; Action to be taken once the assertion thread limit is reached. Default +; is kill. It can have a value of off or kill. In case of kill, all the existing +; threads are terminated and no new attempts are started. In case of off, the +; existing attempts keep on evaluating but no new attempts are started. This +; variable applies to only assert directives. +;AssertionThreadLimitAction = kill + +; Cover thread limit after which cover would be killed/switched off. +; The default is -1 (unlimited). If the number of threads for a cover go +; beyond this limit, the cover would be either switched off or killed. This +; limit applies to only cover directives. +;CoverThreadLimit = -1 + +; Action to be taken once the cover thread limit is reached. Default +; is kill. It can have a value of off or kill. In case of kill, all the existing +; threads are terminated and no new attempts are started. In case of off, the +; existing attempts keep on evaluating but no new attempts are started. This +; variable applies to only cover directives. +;CoverThreadLimitAction = kill + + +; By default immediate assertions do not participate in Assertion Coverage calculations +; unless they are executed. This switch causes all immediate assertions in the design +; to participate in Assertion Coverage calculations, whether attempted or not. +; UnattemptedImmediateAssertions = 0 + +; By default immediate covers participate in Coverage calculations +; whether they are attempted or not. This switch causes all unattempted +; immediate covers in the design to stop participating in Coverage +; calculations. +; UnattemptedImmediateCovers = 0 + +; By default pass action block is not executed for assertions on vacuous +; success. The following variable is provided to enable execution of +; pass action block on vacuous success. The following variable is only effective +; if the user does not disable pass action block execution by using either +; system tasks or CLI. Also there is a performance penalty for enabling +; the following variable. +;AssertionEnableVacuousPassActionBlock = 1 + +; As per strict 1850-2005 PSL LRM, an always property can either pass +; or fail. However, by default, Questa reports multiple passes and +; multiple fails on top always/never property (always/never operator +; is the top operator under Verification Directive). The reason +; being that Questa reports passes and fails on per attempt of the +; top always/never property. Use the following flag to instruct +; Questa to strictly follow LRM. With this flag, all assert/never +; directives will start an attempt once at start of simulation. +; The attempt can either fail, match or match vacuously. +; For e.g. if always is the top operator under assert, the always will +; keep on checking the property at every clock. If the property under +; always fails, the directive will be considered failed and no more +; checking will be done for that directive. A top always property, +; if it does not fail, will show a pass at end of simulation. +; The default value is '0' (i.e. zero is off). For example: +; PslOneAttempt = 1 + +; Specify the number of clock ticks to represent infinite clock ticks. +; This affects eventually!, until! and until_!. If at End of Simulation +; (EOS) an active strong-property has not clocked this number of +; clock ticks then neither pass or fail (vacuous match) is returned +; else respective fail/pass is returned. The default value is '0' (zero) +; which effectively does not check for clock tick condition. For example: +; PslInfinityThreshold = 5000 + +; Control how many thread start times will be preserved for ATV viewing for a given assertion +; instance. Default is -1 (ALL). +; ATVStartTimeKeepCount = -1 + +; Turn on/off code coverage +; CodeCoverage = 0 + +; Count all code coverage condition and expression truth table rows that match. +; CoverCountAll = 1 + +; Turn off automatic inclusion of VHDL integers in toggle coverage. Default +; is to include them. +; ToggleNoIntegers = 1 + +; Set the maximum number of values that are collected for toggle coverage of +; VHDL integers. Default is 100; +; ToggleMaxIntValues = 100 + +; Set the maximum number of values that are collected for toggle coverage of +; Verilog real. Default is 100; +; ToggleMaxRealValues = 100 + +; Turn on automatic inclusion of Verilog integers in toggle coverage, except +; for enumeration types. Default is to include them. +; ToggleVlogIntegers = 0 + +; Turn on automatic inclusion of Verilog real type in toggle coverage, except +; for shortreal types. Default is to not include them. +; ToggleVlogReal = 1 + +; Turn on automatic inclusion of Verilog fixed-size unpacked arrays, VHDL multi-d arrays +; and VHDL arrays-of-arrays in toggle coverage. +; Default is to not include them. +; ToggleFixedSizeArray = 1 + +; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays, +; VHDL multi-d arrays and VHDL arrays-of-arrays that are included for toggle coverage. +; This leads to a longer simulation time with bigger arrays covered with toggle coverage. +; Default is 1024. +; ToggleMaxFixedSizeArray = 1024 + +; Treat Verilog multi-dimensional packed vectors and packed structures as equivalently sized +; one-dimensional packed vectors for toggle coverage. Default is 0. +; TogglePackedAsVec = 0 + +; Treat Verilog enumerated types as equivalently sized one-dimensional packed vectors for +; toggle coverage. Default is 0. +; ToggleVlogEnumBits = 0 + +; Turn off automatic inclusion of VHDL records in toggle coverage. +; Default is to include them. +; ToggleVHDLRecords = 0 + +; Limit the widths of registers automatically tracked for toggle coverage. Default is 128. +; For unlimited width, set to 0. +; ToggleWidthLimit = 128 + +; Limit the counts that are tracked for toggle coverage. When all edges for a bit have +; reached this count, further activity on the bit is ignored. Default is 1. +; For unlimited counts, set to 0. +; ToggleCountLimit = 1 + +; Change the mode of extended toggle coverage. Default is 3. Valid modes are 1, 2 and 3. +; Following is the toggle coverage calculation criteria based on extended toggle mode: +; Mode 1: 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z'). +; Mode 2: 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z'. +; Mode 3: 0L->1H & 1H->0L & all 'Z' transitions. +; ExtendedToggleMode = 3 + +; Enable toggle statistics collection only for ports. Default is 0. +; TogglePortsOnly = 1 + +; Turn on/off all PSL/SVA cover directive enables. Default is on. +; CoverEnable = 0 + +; Turn on/off PSL/SVA cover log. Default is off "0". +; CoverLog = 1 + +; Set "at_least" value for all PSL/SVA cover directives. Default is 1. +; CoverAtLeast = 2 + +; Set "limit" value for all PSL/SVA cover directives. Default is -1. +; Any positive integer, -1 for infinity. +; CoverLimit = 1 + +; Specify the coverage database filename. +; Default is "" (i.e. database is NOT automatically saved on close). +; UCDBFilename = vsim.ucdb + +; Specify the maximum limit for the number of Cross (bin) products reported +; in XML and UCDB report against a Cross. A warning is issued if the limit +; is crossed. Default is zero. vsim switch -cvgmaxrptrhscross can override this +; setting. +; MaxReportRhsSVCrossProducts = 1000 + +; Specify the override for the "auto_bin_max" option for the Covergroups. +; If not specified then value from Covergroup "option" is used. +; SVCoverpointAutoBinMax = 64 + +; Specify the override for the value of "cross_num_print_missing" +; option for the Cross in Covergroups. If not specified then value +; specified in the "option.cross_num_print_missing" is used. This +; is a runtime option. NOTE: This overrides any "cross_num_print_missing" +; value specified by user in source file and any SVCrossNumPrintMissingDefault +; specified in modelsim.ini. +; SVCrossNumPrintMissing = 0 + +; Specify whether to use the value of "cross_num_print_missing" +; option in report and GUI for the Cross in Covergroups. If not specified then +; cross_num_print_missing is ignored for creating reports and displaying +; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing". +; UseSVCrossNumPrintMissing = 0 + +; Specify the threshold of Coverpoint wildcard bin value range size, above which +; a warning will be triggered. The default is 4K -- 12 wildcard bits. +; SVCoverpointWildCardBinValueSizeWarn = 4096 + +; Specify the override for the value of "strobe" option for the +; Covergroup Type. If not specified then value in "type_option.strobe" +; will be used. This is runtime option which forces "strobe" to +; user specified value and supersedes user specified values in the +; SystemVerilog Code. NOTE: This also overrides the compile time +; default value override specified using "SVCovergroupStrobeDefault" +; SVCovergroupStrobe = 0 + +; Override for explicit assignments in source code to "option.goal" of +; SystemVerilog covergroup, coverpoint, and cross. It also overrides the +; default value of "option.goal" (defined to be 100 in the SystemVerilog +; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault". +; SVCovergroupGoal = 100 + +; Override for explicit assignments in source code to "type_option.goal" of +; SystemVerilog covergroup, coverpoint, and cross. It also overrides the +; default value of "type_option.goal" (defined to be 100 in the SystemVerilog +; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault". +; SVCovergroupTypeGoal = 100 + +; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage() +; builtin functions, and report. This setting changes the default values of +; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3 +; behavior if explicit assignments are not made on option.get_inst_coverage and +; type_option.merge_instances by the user. There are two vsim command line +; options, -cvg63 and -nocvg63 to override this setting from vsim command line. +; The default value of this variable from release 6.6 onwards is 0. This default +; drives compliance with the clarified behavior in the IEEE 1800-2009 standard. +; SVCovergroup63Compatibility = 0 + +; Enforce the 6.5 default behavior of covergroup get_coverage() builtin +; functions, GUI, and report. This setting changes the default values of +; type_option.merge_instances to ensure the 6.5 default behavior if explicit +; assignments are not made on type_option.merge_instances by the user. +; There are two vsim command line options, -cvgmergeinstances and +; -nocvgmergeinstances to override this setting from vsim command line. +; The default value of this variable from release 6.6 onwards is 0. This default +; drives compliance with the clarified behavior in the IEEE 1800-2009 standard. +; SvCovergroupMergeInstancesDefault = 1 + +; Enable or disable generation of more detailed information about the sampling +; of covergroup, cross, and coverpoints. It provides the details of the number +; of times the covergroup instance and type were sampled, as well as details +; about why covergroup, cross and coverpoint were not covered. A non-zero value +; is to enable this feature. 0 is to disable this feature. Default is 0 +; SVCovergroupSampleInfo = 0 + +; Specify the maximum number of Coverpoint bins in whole design for +; all Covergroups. +; MaxSVCoverpointBinsDesign = 2147483648 + +; Specify maximum number of Coverpoint bins in any instance of a Covergroup +; MaxSVCoverpointBinsInst = 2147483648 + +; Specify the maximum number of Cross bins in whole design for +; all Covergroups. +; MaxSVCrossBinsDesign = 2147483648 + +; Specify maximum number of Cross bins in any instance of a Covergroup +; MaxSVCrossBinsInst = 2147483648 + +; Specify whether vsim will collect the coverage data of zero-weight coverage items or not. +; By default, this variable is set 0, in which case option.no_collect setting will take effect. +; If this variable is set to 1, all zero-weight coverage items will not be saved. +; Note that the usage of vsim switch -cvgzwnocollect, if present, will override the setting +; of this variable. +; CvgZWNoCollect = 1 + +; Specify a space delimited list of double quoted TCL style +; regular expressions which will be matched against the text of all messages. +; If any regular expression is found to be contained within any message, the +; status for that message will not be propagated to the UCDB TESTSTATUS. +; If no match is detected, then the status will be propagated to the +; UCDB TESTSTATUS. More than one such regular expression text is allowed, +; and each message text is compared for each regular expression in the list. +; UCDBTestStatusMessageFilter = "Done with Test Bench" "Ignore .* message" + +; Set weight for all PSL/SVA cover directives. Default is 1. +; CoverWeight = 2 + +; Check vsim plusargs. Default is 0 (off). +; 0 = Don't check plusargs +; 1 = Warning on unrecognized plusarg +; 2 = Error and exit on unrecognized plusarg +; CheckPlusargs = 1 + +; Load the specified shared objects with the RTLD_GLOBAL flag. +; This gives global visibility to all symbols in the shared objects, +; meaning that subsequently loaded shared objects can bind to symbols +; in the global shared objects. The list of shared objects should +; be whitespace delimited. This option is not supported on the +; Windows or AIX platforms. +; GlobalSharedObjectList = example1.so example2.so example3.so + +; Run the 0in tools from within the simulator. +; Default is off. +; ZeroIn = 1 + +; Set the options to be passed to the 0in runtime tool. +; Default value set to "". +; ZeroInOptions = "" + +; Initial seed for the random number generator of the root thread (SystemVerilog). +; NOTE: This variable can be overridden with the vsim "-sv_seed" command line switch. +; The default value is 0. +; Sv_Seed = 0 + +; Specify the solver "engine" that vsim will select for constrained random +; generation. +; Valid values are: +; "auto" - automatically select the best engine for the current +; constraint scenario +; "bdd" - evaluate all constraint scenarios using the BDD solver engine +; "act" - evaluate all constraint scenarios using the ACT solver engine +; While the BDD solver engine is generally efficient with constraint scenarios +; involving bitwise logical relationships, the ACT solver engine can exhibit +; superior performance with constraint scenarios involving large numbers of +; random variables related via arithmetic operators (+, *, etc). +; NOTE: This variable can be overridden with the vsim "-solveengine" command +; line switch. +; The default value is "auto". +; SolveEngine = auto + +; Specify if the solver should attempt to ignore overflow/underflow semantics +; for arithmetic constraints (multiply, addition, subtraction) in order to +; improve performance. The "solveignoreoverflow" attribute can be specified on +; a per-call basis to randomize() to override this setting. +; The default value is 0 (overflow/underflow is not ignored). Set to 1 to +; ignore overflow/underflow. +; SolveIgnoreOverflow = 0 + +; Specifies the maximum size that a dynamic array may be resized to by the +; solver. If the solver attempts to resize a dynamic array to a size greater +; than the specified limit, the solver will abort with an error. +; The default value is 2000. A value of 0 indicates no limit. +; SolveArrayResizeMax = 2000 + +; Error message severity when randomize() failure is detected (SystemVerilog). +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; The default is 0 (no error). +; SolveFailSeverity = 0 + +; Enable/disable debug information for randomize() failures. +; NOTE: This variable can be overridden with the vsim "-solvefaildbug" command +; line switch. +; The default is 0 (disabled). Set to 1 to enable. +; SolveFailDebug = 0 + +; Specify the maximum size of the solution graph generated by the BDD solver. +; This value can be used to force the BDD solver to abort the evaluation of a +; complex constraint scenario that cannot be evaluated with finite memory. +; This value is specified in 1000s of nodes. +; The default value is 10000. A value of 0 indicates no limit. +; SolveGraphMaxSize = 10000 + +; Specify the maximum number of evaluations that may be performed on the +; solution graph by the BDD solver. This value can be used to force the BDD +; solver to abort the evaluation of a complex constraint scenario that cannot +; be evaluated in finite time. This value is specified in 10000s of evaluations. +; The default value is 10000. A value of 0 indicates no limit. +; SolveGraphMaxEval = 10000 + +; Specify the maximum number of tests that the ACT solver may evaluate before +; abandoning an attempt to solve a particular constraint scenario. +; The default value is 2000000. A value of 0 indicates no limit. +; SolveACTMaxTests = 2000000 + +; Specify the maximum number of operations that the ACT solver may perform +; before abandoning an attempt to solve a particular constraint scenario. The +; value is specified in 1000000s of operations. +; The default value is 10000. A value of 0 indicates no limit. +; SolveACTMaxOps = 10000 + +; Specify the number of times the ACT solver will retry to evaluate a constraint +; scenario that fails due to the SolveACTMaxTests threshold. +; The default value is 0 (no retry). +; SolveACTRetryCount = 0 + +; SolveSpeculateLevel controls whether or not the solver performs speculation +; during the evaluation of a constraint scenario. +; Speculation is an attempt to partition complex constraint scenarios by +; choosing a 'speculation' subset of the variables and constraints. This +; 'speculation' set is solved independently of the remaining constraints. +; The solver then attempts to solve the remaining variables and constraints +; (the 'dependent' set). If this attempt fails, the solver backs up and +; re-solves the 'speculation' set, then retries the 'dependent' set. +; Valid values are: +; 0 - no speculation +; 1 - enable speculation that maintains LRM specified distribution +; 2 - enable other speculation - may yield non-LRM distribution +; Currently, distribution constraints and solve-before constraints are +; used in selecting the 'speculation' sets for speculation level 1. Non-LRM +; compliant speculation includes random variables in condition expressions. +; The default value is 0. +; SolveSpeculateLevel = 0 + +; By default, when speculation is enabled, the solver first tries to solve a +; constraint scenario *without* speculation. If the solver fails to evaluate +; the constraint scenario (due to time/memory limits) then the solver will +; re-evaluate the constraint scenario with speculation. If SolveSpeculateFirst +; is set to 1, the solver will skip the initial non-speculative attempt to +; evaluate the constraint scenario. (Only applies when SolveSpeculateLevel is +; non-zero) +; The default value is 0. +; SolveSpeculateFirst = 0 + +; Specify the maximum bit width of a variable in a conditional expression that +; may be considered as the basis for "conditional" speculation. (Only applies +; when SolveSpeculateLevel=2) +; The default value is 6. +; SolveSpeculateMaxCondWidth = 6 + +; Specify the maximum number of attempts to solve a speculative set of random +; variables and constraints. Exceeding this limit will cause the solver to +; abandon the current speculative set. (Only applies when SolveSpeculateLevel +; is non-zero) +; The default value is 100. +; SolveSpeculateMaxIterations = 100 + +; Specifies whether to attempt speculation on solve-before constraints or +; distribution constraints first. A value of 0 specifies that solve-before +; constraints are attempted first as the basis for speculative randomization. +; A value of 1 specifies that distribution constraints are attempted first +; as the basis for speculative randomization. +; The default value is 0. +; SolveSpeculateDistFirst = 0 + +; If the non-speculative BDD solver fails to evaluate a constraint scenario +; (due to time/memory limits) then the solver can be instructed to automatically +; re-evaluate the constraint scenario with the ACT solver engine. Set +; SolveACTbeforeSpeculate to 1 to enable this feature. +; The default value is 0 (do not re-evaluate with the ACT solver). +; SolveACTbeforeSpeculate = 0 + +; Use SolveFlags to specify options that will guide the behavior of the +; constraint solver. These options may improve the performance of the +; constraint solver for some testcases, and decrease the performance of the +; constraint solver for others. +; Valid flags are: +; i = disable bit interleaving for >, >=, <, <= constraints (BDD engine) +; n = disable bit interleaving for all constraints (BDD engine) +; r = reverse bit interleaving (BDD engine) +; The default value is "" (no options). +; SolveFlags = + +; Specify random sequence compatiblity with a prior letter release. This +; option is used to get the same random sequences during simulation as +; as a prior letter release. Only prior letter releases (of the current +; number release) are allowed. +; NOTE: Only those random sequence changes due to solver optimizations are +; reverted by this variable. Random sequence changes due to solver bugfixes +; cannot be un-done. +; NOTE: This variable can be overridden with the vsim "-solverev" command +; line switch. +; Default value set to "" (no compatibility). +; SolveRev = + +; Environment variable expansion of command line arguments has been depricated +; in favor shell level expansion. Universal environment variable expansion +; inside -f files is support and continued support for MGC Location Maps provide +; alternative methods for handling flexible pathnames. +; The following line may be uncommented and the value set to 1 to re-enable this +; deprecated behavior. The default value is 0. +; DeprecatedEnvironmentVariableExpansion = 0 + +; Turn on/off collapsing of bus ports in VCD dumpports output +DumpportsCollapse = 1 + +; Location of Multi-Level Verification Component (MVC) installation. +; The default location is the product installation directory. +MvcHome = $MODEL_TECH/.. + +; Initialize SystemVerilog enums using the base type's default value +; instead of the leftmost value. +; EnumBaseInit = 1 + +; Suppress file type registration. +; SuppressFileTypeReg = 1 + +; Controls SystemVerilog Language Extensions. These options enable +; some non-LRM compliant behavior. Valid extensions are "feci", +; "pae", "uslt" and "spsl". +; SVExtensions = uslt,spsl + +[lmc] +; The simulator's interface to Logic Modeling's SmartModel SWIFT software +libsm = $MODEL_TECH/libsm.sl +; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT) +; libsm = $MODEL_TECH/libsm.dll +; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700) +; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl +; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000) +; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o +; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris) +; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so +; Logic Modeling's SmartModel SWIFT software (Windows NT) +; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll +; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux) +; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so +; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux) +; libswift = $LMC_HOME/lib/linux.lib/libswift.so + +; The simulator's interface to Logic Modeling's hardware modeler SFI software +libhm = $MODEL_TECH/libhm.sl +; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT) +; libhm = $MODEL_TECH/libhm.dll +; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700) +; libsfi = /lib/hp700/libsfi.sl +; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000) +; libsfi = /lib/rs6000/libsfi.a +; Logic Modeling's hardware modeler SFI software (Sun4 Solaris) +; libsfi = /lib/sun4.solaris/libsfi.so +; Logic Modeling's hardware modeler SFI software (Windows NT) +; libsfi = /lib/pcnt/lm_sfi.dll +; Logic Modeling's hardware modeler SFI software (Linux) +; libsfi = /lib/linux/libsfi.so + +[msg_system] +; Change a message severity or suppress a message. +; The format is: = [,...] +; suppress can be used to achieve +nowarn functionality +; The format is: suppress = ,,[,,...] +; Examples: +suppress = 8780 ;an explanation can be had by running: verror 8780 +; note = 3009 +; warning = 3033 +; error = 3010,3016 +; fatal = 3016,3033 +; suppress = 3009,3016,3043 +; suppress = 3009,CNNODP,3043,TFMPC +; suppress = 8683,8684 +; The command verror can be used to get the complete +; description of a message. + +; Control transcripting of Verilog display system task messages and +; PLI/FLI print function call messages. The system tasks include +; $display[bho], $strobe[bho], $monitor[bho], and $write[bho]. They +; also include the analogous file I/O tasks that write to STDOUT +; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf, +; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default +; is to have messages appear only in the transcript. The other +; settings are to send messages to the wlf file only (messages that +; are recorded in the wlf file can be viewed in the MsgViewer) or +; to both the transcript and the wlf file. The valid values are +; tran {transcript only (default)} +; wlf {wlf file only} +; both {transcript and wlf file} +; displaymsgmode = tran + +; Control transcripting of elaboration/runtime messages not +; addressed by the displaymsgmode setting. The default is to +; have messages appear only in the transcript. The other settings +; are to send messages to the wlf file only (messages that are +; recorded in the wlf file can be viewed in the MsgViewer) or to both +; the transcript and the wlf file. The valid values are +; tran {transcript only (default)} +; wlf {wlf file only} +; both {transcript and wlf file} +; msgmode = tran +[Project] +; Warning -- Do not edit the project properties directly. +; Property names are dynamic in nature and property +; values have special syntax. Changing property data directly +; can result in a corrupt MPF file. All project properties +; can be modified through project window dialogs. +Project_Version = 6 +Project_DefaultLib = work +Project_SortMethod = unused +Project_Files_Count = 8 +Project_File_0 = /d/jspc22/trb/git/trb3sc/triggerbox/code/input_processor.vhd +Project_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1603455155 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 1 cover_noshort 0 compile_to work compile_order 5 cover_nosub 0 dont_compile 0 vhdl_use93 2008 +Project_File_1 = /d/jspc22/trb/git/trbnet/trb_net_std.vhd +Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1598871123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 2008 +Project_File_2 = /d/jspc22/trb/git/trb3sc/triggerbox/config.vhd +Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1603375388 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 1 cover_nosub 0 dont_compile 0 vhdl_use93 2008 +Project_File_3 = /d/jspc22/trb/git/trb3sc/triggerbox/code/triggerbox.vhd +Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1603455115 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 6 dont_compile 0 cover_nosub 0 vhdl_use93 2008 +Project_File_4 = /d/jspc22/trb/git/trb3sc/triggerbox/code/multiplicity.vhd +Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1603368422 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 2 dont_compile 0 cover_nosub 0 vhdl_use93 2008 +Project_File_5 = /d/jspc22/trb/git/trb3sc/triggerbox/code/tb_triggerbox.vhd +Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1603461258 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 1 cover_noshort 0 compile_to work compile_order 7 cover_nosub 0 dont_compile 0 vhdl_use93 2008 +Project_File_6 = /d/jspc22/trb/git/trb3sc/triggerbox/cores/delay_shift_reg.vhd +Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1602861382 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 4 dont_compile 0 cover_nosub 0 vhdl_use93 2008 +Project_File_7 = /d/jspc22/trb/git/trb3sc/triggerbox/code/triggerbox_pkg.vhd +Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1603368419 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 3 dont_compile 0 cover_nosub 0 vhdl_use93 2008 +Project_Sim_Count = 0 +Project_Folder_Count = 0 +Echo_Compile_Output = 1 +Save_Compile_Report = 1 +Project_Opt_Count = 0 +ForceSoftPaths = 0 +ProjectStatusDelay = 5000 +VERILOG_DoubleClick = Edit +VERILOG_CustomDoubleClick = +SYSTEMVERILOG_DoubleClick = Edit +SYSTEMVERILOG_CustomDoubleClick = +VHDL_DoubleClick = Edit +VHDL_CustomDoubleClick = +PSL_DoubleClick = Edit +PSL_CustomDoubleClick = +TEXT_DoubleClick = Edit +TEXT_CustomDoubleClick = +SYSTEMC_DoubleClick = Edit +SYSTEMC_CustomDoubleClick = +TCL_DoubleClick = Edit +TCL_CustomDoubleClick = +MACRO_DoubleClick = Edit +MACRO_CustomDoubleClick = +VCD_DoubleClick = Edit +VCD_CustomDoubleClick = +SDF_DoubleClick = Edit +SDF_CustomDoubleClick = +XML_DoubleClick = Edit +XML_CustomDoubleClick = +LOGFILE_DoubleClick = Edit +LOGFILE_CustomDoubleClick = +UCDB_DoubleClick = Edit +UCDB_CustomDoubleClick = +UPF_DoubleClick = Edit +UPF_CustomDoubleClick = +PCF_DoubleClick = Edit +PCF_CustomDoubleClick = +PROJECT_DoubleClick = Edit +PROJECT_CustomDoubleClick = +VRM_DoubleClick = Edit +VRM_CustomDoubleClick = +DEBUGDATABASE_DoubleClick = Edit +DEBUGDATABASE_CustomDoubleClick = +DEBUGARCHIVE_DoubleClick = Edit +DEBUGARCHIVE_CustomDoubleClick = +Project_Major_Version = 10 +Project_Minor_Version = 1 diff --git a/triggerbox/trb3sc_triggerbox.lpf b/triggerbox/trb3sc_triggerbox.lpf new file mode 100644 index 0000000..2f2fffc --- /dev/null +++ b/triggerbox/trb3sc_triggerbox.lpf @@ -0,0 +1,181 @@ + +MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" CLKNET clk_sys TO CLKNET clk_sys 5x; + +BLOCK PATH FROM PORT "INP*"; +BLOCK PATH TO PORT "TEST_LIN*"; +BLOCK PATH TO PORT "X*"; +BLOCK PATH FROM CELL "THE_BOX/proc_REGS.CONF_*"; +BLOCK PATH TO CELL "THE_BOX/gen_input_processor.*.THE_INP_PROC/PROC_REG.reg_in*"; +BLOCK PATH TO CELL "THE_BOX/out*"; +MULTICYCLE FROM CELL "THE_BOX/proc_REGS.reset_processor" 15 ns; +MULTICYCLE FROM CELL "THE_BOX/TIMER_PROC.tick_ms" 15 ns; +MULTICYCLE FROM CELL "THE_BOX/TIMER_PROC.tick_us" 15 ns; +# MULTICYCLE TO CELL "THE_BOX/reg_processed_in*" 10 ns; + +# BLOCK PATH TO CELL "THE_BOX/MONITOR_*"; +# BLOCK PATH TO CELL "THE_BOX_MONITOR_OUT*"; +MULTICYCLE TO CELL "THE_BOX/list_of_monitor*" 10 ns; + +# MULTICYCLE TO CELL "X_c*" 20 ns; +BLOCK PATH TO CELL "THE_BOX/THE_SCALER/reg_in*"; +MULTICYCLE FROM CELL "THE_BOX/THE_SCALER/gen_scalers.*.cnt*" TO CELL "THE_BOX/THE_SCALER/muxre*" 20 ns; +BLOCK PATH TO CELL "THE_BOX/list_of_scale*"; + +# MULTICYCLE TO CELL "THE_BOX/gen_coincs.*.THE_COINC/reg_in*" 2x ; + +REGION "COINMULT_region" "R35C70" 34 65; +LOCATE UGROUP "THE_BOX/gen_coincs.0.THE_COINC/coinc_proc" REGION "COINMULT_region"; +LOCATE UGROUP "THE_BOX/gen_coincs.1.THE_COINC/coinc_proc" REGION "COINMULT_region"; +LOCATE UGROUP "THE_BOX/gen_coincs.2.THE_COINC/coinc_proc" REGION "COINMULT_region"; +LOCATE UGROUP "THE_BOX/gen_coincs.3.THE_COINC/coinc_proc" REGION "COINMULT_region"; +LOCATE UGROUP "THE_BOX/gen_coincs.4.THE_COINC/coinc_proc" REGION "COINMULT_region"; +LOCATE UGROUP "THE_BOX/gen_coincs.5.THE_COINC/coinc_proc" REGION "COINMULT_region"; +LOCATE UGROUP "THE_BOX/gen_coincs.6.THE_COINC/coinc_proc" REGION "COINMULT_region"; +LOCATE UGROUP "THE_BOX/gen_coincs.7.THE_COINC/coinc_proc" REGION "COINMULT_region"; +LOCATE UGROUP "THE_BOX/gen_coincs.8.THE_COINC/coinc_proc" REGION "COINMULT_region"; +LOCATE UGROUP "THE_BOX/gen_coincs.9.THE_COINC/coinc_proc" REGION "COINMULT_region"; +LOCATE UGROUP "THE_BOX/gen_coincs.10.THE_COINC/coinc_proc" REGION "COINMULT_region"; +LOCATE UGROUP "THE_BOX/gen_coincs.11.THE_COINC/coinc_proc" REGION "COINMULT_region"; +LOCATE UGROUP "THE_BOX/gen_coincs.12.THE_COINC/coinc_proc" REGION "COINMULT_region"; +LOCATE UGROUP "THE_BOX/gen_coincs.13.THE_COINC/coinc_proc" REGION "COINMULT_region"; +LOCATE UGROUP "THE_BOX/gen_coincs.14.THE_COINC/coinc_proc" REGION "COINMULT_region"; +LOCATE UGROUP "THE_BOX/gen_coincs.15.THE_COINC/coinc_proc" REGION "COINMULT_region"; + +UGROUP "multis" +BLKNAME "THE_BOX/gen_multis.0.THE_MULTIPLICITY" +BLKNAME "THE_BOX/gen_multis.1.THE_MULTIPLICITY" +BLKNAME "THE_BOX/gen_multis.2.THE_MULTIPLICITY" +BLKNAME "THE_BOX/gen_multis.3.THE_MULTIPLICITY" +BLKNAME "THE_BOX/gen_multis.4.THE_MULTIPLICITY" +BLKNAME "THE_BOX/gen_multis.5.THE_MULTIPLICITY" +BLKNAME "THE_BOX/gen_multis.6.THE_MULTIPLICITY" +BLKNAME "THE_BOX/gen_multis.7.THE_MULTIPLICITY"; +LOCATE UGROUP "multis" REGION "COINMULT_region"; + +#LOCATE UGROUP "THE_BOX/gen_multis.0.THE_MULTIPLICITY/mult_proc" REGION "COINMULT_region"; +#LOCATE UGROUP "THE_BOX/gen_multis.1.THE_MULTIPLICITY/mult_proc" REGION "COINMULT_region"; +#LOCATE UGROUP "THE_BOX/gen_multis.2.THE_MULTIPLICITY/mult_proc" REGION "COINMULT_region"; +#LOCATE UGROUP "THE_BOX/gen_multis.3.THE_MULTIPLICITY/mult_proc" REGION "COINMULT_region"; +#LOCATE UGROUP "THE_BOX/gen_multis.4.THE_MULTIPLICITY/mult_proc" REGION "COINMULT_region"; +#LOCATE UGROUP "THE_BOX/gen_multis.5.THE_MULTIPLICITY/mult_proc" REGION "COINMULT_region"; +#LOCATE UGROUP "THE_BOX/gen_multis.6.THE_MULTIPLICITY/mult_proc" REGION "COINMULT_region"; +#LOCATE UGROUP "THE_BOX/gen_multis.7.THE_MULTIPLICITY/mult_proc" REGION "COINMULT_region"; + +LOCATE UGROUP "THE_BOX/gen_groups.0.THE_GROUPS/groups" REGION "COINMULT_region"; +LOCATE UGROUP "THE_BOX/gen_groups.1.THE_GROUPS/groups" REGION "COINMULT_region"; +LOCATE UGROUP "THE_BOX/gen_groups.2.THE_GROUPS/groups" REGION "COINMULT_region"; +LOCATE UGROUP "THE_BOX/gen_groups.3.THE_GROUPS/groups" REGION "COINMULT_region"; +LOCATE UGROUP "THE_BOX/gen_groups.4.THE_GROUPS/groups" REGION "COINMULT_region"; +LOCATE UGROUP "THE_BOX/gen_groups.5.THE_GROUPS/groups" REGION "COINMULT_region"; +LOCATE UGROUP "THE_BOX/gen_groups.6.THE_GROUPS/groups" REGION "COINMULT_region"; +LOCATE UGROUP "THE_BOX/gen_groups.7.THE_GROUPS/groups" REGION "COINMULT_region"; +LOCATE UGROUP "THE_BOX/gen_groups.8.THE_GROUPS/groups" REGION "COINMULT_region"; +LOCATE UGROUP "THE_BOX/gen_groups.9.THE_GROUPS/groups" REGION "COINMULT_region"; +LOCATE UGROUP "THE_BOX/gen_groups.10.THE_GROUPS/groups" REGION "COINMULT_region"; +LOCATE UGROUP "THE_BOX/gen_groups.11.THE_GROUPS/groups" REGION "COINMULT_region"; +LOCATE UGROUP "THE_BOX/gen_groups.12.THE_GROUPS/groups" REGION "COINMULT_region"; +LOCATE UGROUP "THE_BOX/gen_groups.13.THE_GROUPS/groups" REGION "COINMULT_region"; +LOCATE UGROUP "THE_BOX/gen_groups.14.THE_GROUPS/groups" REGION "COINMULT_region"; +LOCATE UGROUP "THE_BOX/gen_groups.15.THE_GROUPS/groups" REGION "COINMULT_region"; + +REGION "MONITOR_region" "R2C60" 13 120; +LOCATE UGROUP "THE_BOX/gen_monitors.0.THE_MONITOR/monitor_output" REGION "MONITOR_region"; +LOCATE UGROUP "THE_BOX/gen_monitors.1.THE_MONITOR/monitor_output" REGION "MONITOR_region"; +LOCATE UGROUP "THE_BOX/gen_monitors.2.THE_MONITOR/monitor_output" REGION "MONITOR_region"; +LOCATE UGROUP "THE_BOX/gen_monitors.3.THE_MONITOR/monitor_output" REGION "MONITOR_region"; +LOCATE UGROUP "THE_BOX/gen_monitors.4.THE_MONITOR/monitor_output" REGION "MONITOR_region"; +LOCATE UGROUP "THE_BOX/gen_monitors.5.THE_MONITOR/monitor_output" REGION "MONITOR_region"; +LOCATE UGROUP "THE_BOX/gen_monitors.6.THE_MONITOR/monitor_output" REGION "MONITOR_region"; +LOCATE UGROUP "THE_BOX/gen_monitors.7.THE_MONITOR/monitor_output" REGION "MONITOR_region"; +LOCATE UGROUP "THE_BOX/gen_monitors.8.THE_MONITOR/monitor_output" REGION "MONITOR_region"; +LOCATE UGROUP "THE_BOX/gen_monitors.9.THE_MONITOR/monitor_output" REGION "MONITOR_region"; +LOCATE UGROUP "THE_BOX/gen_monitors.10.THE_MONITOR/monitor_output" REGION "MONITOR_region"; +LOCATE UGROUP "THE_BOX/gen_monitors.11.THE_MONITOR/monitor_output" REGION "MONITOR_region"; +LOCATE UGROUP "THE_BOX/gen_monitors.12.THE_MONITOR/monitor_output" REGION "MONITOR_region"; +LOCATE UGROUP "THE_BOX/gen_monitors.13.THE_MONITOR/monitor_output" REGION "MONITOR_region"; +LOCATE UGROUP "THE_BOX/gen_monitors.14.THE_MONITOR/monitor_output" REGION "MONITOR_region"; +LOCATE UGROUP "THE_BOX/gen_monitors.15.THE_MONITOR/monitor_output" REGION "MONITOR_region"; + + +LOCATE UGROUP "THE_BOX/gen_input_processor.0.THE_INP_PROC/input_proc" SITE R71C134D; +LOCATE UGROUP "THE_BOX/gen_input_processor.1.THE_INP_PROC/input_proc" SITE R71C150D; +LOCATE UGROUP "THE_BOX/gen_input_processor.2.THE_INP_PROC/input_proc" SITE R71C70D; +LOCATE UGROUP "THE_BOX/gen_input_processor.3.THE_INP_PROC/input_proc" SITE R71C86D; +LOCATE UGROUP "THE_BOX/gen_input_processor.4.THE_INP_PROC/input_proc" SITE R71C102D; +LOCATE UGROUP "THE_BOX/gen_input_processor.5.THE_INP_PROC/input_proc" SITE R71C118D; +LOCATE UGROUP "THE_BOX/gen_input_processor.6.THE_INP_PROC/input_proc" SITE R75C134D; +LOCATE UGROUP "THE_BOX/gen_input_processor.7.THE_INP_PROC/input_proc" SITE R75C150D; +LOCATE UGROUP "THE_BOX/gen_input_processor.8.THE_INP_PROC/input_proc" SITE R75C70D; +LOCATE UGROUP "THE_BOX/gen_input_processor.9.THE_INP_PROC/input_proc" SITE R75C86D; +LOCATE UGROUP "THE_BOX/gen_input_processor.10.THE_INP_PROC/input_proc" SITE R75C102D; +LOCATE UGROUP "THE_BOX/gen_input_processor.11.THE_INP_PROC/input_proc" SITE R75C118D; +LOCATE UGROUP "THE_BOX/gen_input_processor.12.THE_INP_PROC/input_proc" SITE R17C134D; +LOCATE UGROUP "THE_BOX/gen_input_processor.13.THE_INP_PROC/input_proc" SITE R62C70D; +LOCATE UGROUP "THE_BOX/gen_input_processor.14.THE_INP_PROC/input_proc" SITE R35C150D; +LOCATE UGROUP "THE_BOX/gen_input_processor.15.THE_INP_PROC/input_proc" SITE R44C38D; +LOCATE UGROUP "THE_BOX/gen_input_processor.16.THE_INP_PROC/input_proc" SITE R17C54D; +LOCATE UGROUP "THE_BOX/gen_input_processor.17.THE_INP_PROC/input_proc" SITE R17C70D; +LOCATE UGROUP "THE_BOX/gen_input_processor.18.THE_INP_PROC/input_proc" SITE R17C86D; +LOCATE UGROUP "THE_BOX/gen_input_processor.19.THE_INP_PROC/input_proc" SITE R17C102D; +LOCATE UGROUP "THE_BOX/gen_input_processor.20.THE_INP_PROC/input_proc" SITE R17C118D; +LOCATE UGROUP "THE_BOX/gen_input_processor.21.THE_INP_PROC/input_proc" SITE R21C134D; +LOCATE UGROUP "THE_BOX/gen_input_processor.22.THE_INP_PROC/input_proc" SITE R66C70D; +LOCATE UGROUP "THE_BOX/gen_input_processor.23.THE_INP_PROC/input_proc" SITE R39C150D; +LOCATE UGROUP "THE_BOX/gen_input_processor.24.THE_INP_PROC/input_proc" SITE R48C38D; +LOCATE UGROUP "THE_BOX/gen_input_processor.25.THE_INP_PROC/input_proc" SITE R21C54D; +LOCATE UGROUP "THE_BOX/gen_input_processor.26.THE_INP_PROC/input_proc" SITE R21C70D; +LOCATE UGROUP "THE_BOX/gen_input_processor.27.THE_INP_PROC/input_proc" SITE R21C86D; +LOCATE UGROUP "THE_BOX/gen_input_processor.28.THE_INP_PROC/input_proc" SITE R21C102D; +LOCATE UGROUP "THE_BOX/gen_input_processor.29.THE_INP_PROC/input_proc" SITE R21C118D; +LOCATE UGROUP "THE_BOX/gen_input_processor.30.THE_INP_PROC/input_proc" SITE R26C134D; +LOCATE UGROUP "THE_BOX/gen_input_processor.31.THE_INP_PROC/input_proc" SITE R26C150D; +LOCATE UGROUP "THE_BOX/gen_input_processor.32.THE_INP_PROC/input_proc" SITE R44C150D; +LOCATE UGROUP "THE_BOX/gen_input_processor.33.THE_INP_PROC/input_proc" SITE R26C38D; +LOCATE UGROUP "THE_BOX/gen_input_processor.34.THE_INP_PROC/input_proc" SITE R44C134D; +LOCATE UGROUP "THE_BOX/gen_input_processor.35.THE_INP_PROC/input_proc" SITE R26C54D; +LOCATE UGROUP "THE_BOX/gen_input_processor.36.THE_INP_PROC/input_proc" SITE R26C70D; +LOCATE UGROUP "THE_BOX/gen_input_processor.37.THE_INP_PROC/input_proc" SITE R26C86D; +LOCATE UGROUP "THE_BOX/gen_input_processor.38.THE_INP_PROC/input_proc" SITE R26C102D; +LOCATE UGROUP "THE_BOX/gen_input_processor.39.THE_INP_PROC/input_proc" SITE R26C118D; +LOCATE UGROUP "THE_BOX/gen_input_processor.40.THE_INP_PROC/input_proc" SITE R30C134D; +LOCATE UGROUP "THE_BOX/gen_input_processor.41.THE_INP_PROC/input_proc" SITE R30C150D; +LOCATE UGROUP "THE_BOX/gen_input_processor.42.THE_INP_PROC/input_proc" SITE R48C150D; +LOCATE UGROUP "THE_BOX/gen_input_processor.43.THE_INP_PROC/input_proc" SITE R30C38D; +LOCATE UGROUP "THE_BOX/gen_input_processor.44.THE_INP_PROC/input_proc" SITE R48C134D; +LOCATE UGROUP "THE_BOX/gen_input_processor.45.THE_INP_PROC/input_proc" SITE R30C54D; +LOCATE UGROUP "THE_BOX/gen_input_processor.46.THE_INP_PROC/input_proc" SITE R30C70D; +LOCATE UGROUP "THE_BOX/gen_input_processor.47.THE_INP_PROC/input_proc" SITE R30C86D; +LOCATE UGROUP "THE_BOX/gen_input_processor.48.THE_INP_PROC/input_proc" SITE R30C102D; +LOCATE UGROUP "THE_BOX/gen_input_processor.49.THE_INP_PROC/input_proc" SITE R30C118D; +LOCATE UGROUP "THE_BOX/gen_input_processor.50.THE_INP_PROC/input_proc" SITE R35C134D; +LOCATE UGROUP "THE_BOX/gen_input_processor.51.THE_INP_PROC/input_proc" SITE R35C38D; +LOCATE UGROUP "THE_BOX/gen_input_processor.52.THE_INP_PROC/input_proc" SITE R53C134D; +LOCATE UGROUP "THE_BOX/gen_input_processor.53.THE_INP_PROC/input_proc" SITE R35C54D; +LOCATE UGROUP "THE_BOX/gen_input_processor.54.THE_INP_PROC/input_proc" SITE R39C134D; +LOCATE UGROUP "THE_BOX/gen_input_processor.55.THE_INP_PROC/input_proc" SITE R39C38D; +LOCATE UGROUP "THE_BOX/gen_input_processor.56.THE_INP_PROC/input_proc" SITE R57C134D; +LOCATE UGROUP "THE_BOX/gen_input_processor.57.THE_INP_PROC/input_proc" SITE R39C54D; +LOCATE UGROUP "THE_BOX/gen_input_processor.58.THE_INP_PROC/input_proc" SITE R44C54D; +LOCATE UGROUP "THE_BOX/gen_input_processor.59.THE_INP_PROC/input_proc" SITE R48C54D; +LOCATE UGROUP "THE_BOX/gen_input_processor.60.THE_INP_PROC/input_proc" SITE R53C54D; +LOCATE UGROUP "THE_BOX/gen_input_processor.61.THE_INP_PROC/input_proc" SITE R57C54D; +LOCATE UGROUP "THE_BOX/gen_input_processor.62.THE_INP_PROC/input_proc" SITE R80C134D; +LOCATE UGROUP "THE_BOX/gen_input_processor.63.THE_INP_PROC/input_proc" SITE R62C134D; +LOCATE UGROUP "THE_BOX/gen_input_processor.64.THE_INP_PROC/input_proc" SITE R62C150D; +LOCATE UGROUP "THE_BOX/gen_input_processor.65.THE_INP_PROC/input_proc" SITE R53C38D; +LOCATE UGROUP "THE_BOX/gen_input_processor.66.THE_INP_PROC/input_proc" SITE R80C54D; +LOCATE UGROUP "THE_BOX/gen_input_processor.67.THE_INP_PROC/input_proc" SITE R80C70D; +LOCATE UGROUP "THE_BOX/gen_input_processor.68.THE_INP_PROC/input_proc" SITE R80C86D; +LOCATE UGROUP "THE_BOX/gen_input_processor.69.THE_INP_PROC/input_proc" SITE R80C102D; +LOCATE UGROUP "THE_BOX/gen_input_processor.70.THE_INP_PROC/input_proc" SITE R80C118D; +LOCATE UGROUP "THE_BOX/gen_input_processor.71.THE_INP_PROC/input_proc" SITE R84C134D; +LOCATE UGROUP "THE_BOX/gen_input_processor.72.THE_INP_PROC/input_proc" SITE R66C134D; +LOCATE UGROUP "THE_BOX/gen_input_processor.73.THE_INP_PROC/input_proc" SITE R66C150D; +LOCATE UGROUP "THE_BOX/gen_input_processor.74.THE_INP_PROC/input_proc" SITE R57C38D; +LOCATE UGROUP "THE_BOX/gen_input_processor.75.THE_INP_PROC/input_proc" SITE R84C54D; +LOCATE UGROUP "THE_BOX/gen_input_processor.76.THE_INP_PROC/input_proc" SITE R84C70D; +LOCATE UGROUP "THE_BOX/gen_input_processor.77.THE_INP_PROC/input_proc" SITE R84C86D; +LOCATE UGROUP "THE_BOX/gen_input_processor.78.THE_INP_PROC/input_proc" SITE R84C102D; +LOCATE UGROUP "THE_BOX/gen_input_processor.79.THE_INP_PROC/input_proc" SITE R84C118D; + + diff --git a/triggerbox/trb3sc_triggerbox.prj b/triggerbox/trb3sc_triggerbox.prj new file mode 100644 index 0000000..5b07f80 --- /dev/null +++ b/triggerbox/trb3sc_triggerbox.prj @@ -0,0 +1,256 @@ + +# implementation: "workdir" +impl -add workdir -type fpga + +# device options +set_option -technology LATTICE-ECP3 +set_option -part LFE3_150EA +set_option -package FN1156C +set_option -speed_grade -8 +set_option -part_companion "" + +# compilation/mapping options +set_option -default_enum_encoding sequential +set_option -symbolic_fsm_compiler 1 +set_option -top_module "trb3sc_triggerbox" +set_option -resource_sharing false +set_option -vhdl2008 1 + +# map options +set_option -frequency 200 +set_option -fanout_limit 100 +set_option -disable_io_insertion 0 +set_option -retiming 1 +set_option -pipe 1 +set_option -force_gsr false +set_option -fixgatedclocks 3 +set_option -fixgeneratedclocks 3 +set_option -compiler_compatible true + +set_option -max_parallel_jobs 3 +#set_option -automatic_compile_point 1 +#set_option -continue_on_error 1 +set_option -resolve_multiple_driver 1 + +# simulation options +set_option -write_verilog 0 +set_option -write_vhdl 1 + +# automatic place and route (vendor) options +set_option -write_apr_constraint 0 + +# set result format/file last +project -result_format "edif" +project -result_file "workdir/trb3sc_triggerbox.edf" + +#implementation attributes + +set_option -vlog_std v2001 +set_option -project_relative_includes 1 +impl -active "workdir" + +#################### + + + +#Packages +add_file -vhdl -lib work "workdir/version.vhd" +add_file -vhdl -lib work "config.vhd" +add_file -vhdl -lib work "../../trb3/base/trb3_components.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_func.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_protocols.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_components.vhd" + + +#Basic Infrastructure +add_file -vhdl -lib work "../../trb3sc/cores/pll_in200_out100.vhd" +add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out200.vhd" +add_file -vhdl -lib work "../../trb3sc/cores/pll_in200_out200.vhd" +add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out240.vhd" +add_file -vhdl -lib work "../../trb3/base/cores/pll_200_4.vhd" +add_file -vhdl -lib work "../../trb3sc/code/clock_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd" +add_file -vhdl -lib work "../../trb3/base/code/sedcheck.vhd" + + +#Fifos +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x8k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_9x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" + + +#Flash & Reload, Tools +add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" +add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" +add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd" +add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd" +add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" +add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" +add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd" + +#SlowControl files +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" + +#Media interface +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_0.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_3.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync.vhd" + +#TrbNet Endpoint +add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_gbe.vhd" +add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd" + +add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd" + + +# #GbE +# add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_wrapper.vhd" +# add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_logic_wrapper.vhd" +# add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_med_interface.vhd" +# add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_multiplexer.vhd" +# add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_dummy.vhd" +# add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_receiver.vhd" +# add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_receive_control.vhd" +# add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_main_control.vhd" +# add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_mac_control.vhd" +# add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_prioritizer.vhd" +# add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_selector.vhd" +# add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_type_validator.vhd" +# add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_trans.vhd" +# add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_constr.vhd" +# add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_transmit_control2.vhd" +# add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_ipu_interface.vhd" +# add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_event_constr.vhd" +# add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_setup.vhd" +# add_file -vhdl -lib work "../../trbnet/gbe_trb/base/ip_configurator.vhd" +# add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_ARP.vhd" +# add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Ping.vhd" +# add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_DHCP.vhd" +# add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd" +# add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_TrbNetData.vhd" +# add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_KillPing.vhd" +# add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Forward.vhd" +# add_file -vhdl -lib work "../../trbnet/gbe_trb/media/serdes_gbe_4ch.vhd" +# add_file -verilog -lib work "../../trbnet/gbe_trb/media/sgmii_channel_smi.v" +# add_file -verilog -lib work "../../trbnet/gbe_trb/media/reset_controller_pcs.v" +# add_file -verilog -lib work "../../trbnet/gbe_trb/media/reset_controller_cdr.v" +# add_file -verilog -lib work "../../trbnet/gbe_trb/media/register_interface_hb.v" +# add_file -verilog -lib work "../../trbnet/gbe_trb/media/rate_resolution.v" +# +# add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_8kx9.vhd" +# add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_4096x9.vhd" +# add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_512x32.vhd" +# add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_512x32x8.vhd" +# add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_512x72.vhd" +# add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_64kx9.vhd" +# add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_64kx9_af.vhd" +# add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_32kx16x8_mb2.vhd" +# add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_2048x8x16.vhd" +# add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_65536x18x9.vhd" +# add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/slv_mac_memory.vhd" +# add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/ip_mem.vhd" +# add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_64kx18x9_wcnt.vhd" +# add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_32kx18x9_wcnt.vhd" +# add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_64kx9_af_cnt.vhd" +# add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_8kx9_af_cnt.vhd" +# add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_2kx9x18_wcnt.vhd" +# add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_4kx18x9_wcnt.vhd" + +add_file -vhdl -lib work "code/input_processor.vhd" +add_file -vhdl -lib work "code/multiplicity.vhd" +add_file -vhdl -lib work "code/coincidence.vhd" +add_file -vhdl -lib work "code/triggerbox.vhd" +add_file -vhdl -lib work "code/triggerbox_pkg.vhd" +add_file -vhdl -lib work "code/scalers.vhd" +add_file -vhdl -lib work "code/groups.vhd" +add_file -vhdl -lib work "code/monitor_output.vhd" +add_file -vhdl -lib work "cores/delay_shift_reg.vhd" + +add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming.vhd" + +add_file -vhdl -lib work "./trb3sc_triggerbox.vhd" +add_file -constraint "./trb3sc_triggerbox.sdc" + + + diff --git a/triggerbox/trb3sc_triggerbox.sdc b/triggerbox/trb3sc_triggerbox.sdc new file mode 100644 index 0000000..ebffda4 --- /dev/null +++ b/triggerbox/trb3sc_triggerbox.sdc @@ -0,0 +1,5 @@ +define_clock {CLK_CORE_PCLK} -name {CLK_CORE_PCLK} -freq 200 +define_clock {clock_reset_handler|REF_CLK_OUT_inferred_clock} -name {ref_clk} -freq 200 +define_clock {clock_reset_handler|SYS_CLK_OUT_inferred_clock} -name {sys_clk} -freq 100 +define_clock {serdes_sync_0|rx_full_clk_ch0_inferred_clock} -name {full_rx} -freq 200 +define_clock {System} -name{system} -freq 100 diff --git a/triggerbox/trb3sc_triggerbox.vhd b/triggerbox/trb3sc_triggerbox.vhd new file mode 100644 index 0000000..c11071f --- /dev/null +++ b/triggerbox/trb3sc_triggerbox.vhd @@ -0,0 +1,450 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.version.all; +use work.config.all; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.trb_net16_hub_func.all; +use work.version.all; +use work.trb_net_gbe_components.all; +use work.med_sync_define.all; + +entity trb3sc_triggerbox is + port( + CLK_SUPPL_PCLK : in std_logic; --125 MHz for GbE + CLK_CORE_PCLK : in std_logic; --Main Oscillator + CLK_EXT_PLL_LEFT : in std_logic; --External Clock + --CLK_SUPPL_PLL_LEFT : in std_logic; --not used + --CLK_SUPPL_PLL_RIGHT : in std_logic; --not used + --CLK_CORE_PLL_LEFT : in std_logic; --not used + --CLK_CORE_PLL_RIGHT : in std_logic; --not used + --CLK_EXT_PCLK : in std_logic; --not used + --CLK_EXT_PLL_RIGHT : in std_logic; --not used + + TRIG_LEFT : in std_logic; --Trigger Input + + --Backplane, all lines + BACK_LVDS : inout std_logic_vector( 1 downto 0); + BACK_3V3 : inout std_logic_vector( 3 downto 0); + --Backplane for slaves on trbv3scbp1 + BACK_GPIO : inout std_logic_vector(3 downto 0); + + --AddOn Connector + INP : in std_logic_vector(95 downto 0); + X : out std_logic_vector(8 downto 1); + + --Additional IO + HDR_IO : inout std_logic_vector(10 downto 1); + RJ_IO : inout std_logic_vector( 3 downto 0); + SPARE_IN : in std_logic_vector( 1 downto 0); + + --LED + LED_GREEN : out std_logic; + LED_YELLOW : out std_logic; + LED_ORANGE : out std_logic; + LED_RED : out std_logic; + LED_RJ_GREEN : out std_logic_vector( 1 downto 0); + LED_RJ_RED : out std_logic_vector( 1 downto 0); + LED_WHITE : out std_logic_vector( 1 downto 0); + LED_SFP_GREEN : out std_logic_vector( 1 downto 0); + LED_SFP_RED : out std_logic_vector( 1 downto 0); + + --SFP + SFP_LOS : in std_logic_vector( 1 downto 0); + SFP_MOD0 : in std_logic_vector( 1 downto 0); + SFP_MOD1 : inout std_logic_vector( 1 downto 0) := (others => 'Z'); + SFP_MOD2 : inout std_logic_vector( 1 downto 0) := (others => 'Z'); + SFP_TX_DIS : out std_logic_vector( 1 downto 0) := (others => '0'); + + --Serdes switch + PCSSW_ENSMB : out std_logic; + PCSSW_EQ : out std_logic_vector( 3 downto 0); + PCSSW_PE : out std_logic_vector( 3 downto 0); + PCSSW : out std_logic_vector( 7 downto 0); + + --ADC + ADC_CLK : out std_logic; + ADC_CS : out std_logic; + ADC_DIN : out std_logic; + ADC_DOUT : in std_logic; + + --Flash, 1-wire, Reload + FLASH_CLK : out std_logic; + FLASH_CS : out std_logic; + FLASH_IN : out std_logic; + FLASH_OUT : in std_logic; + PROGRAMN : out std_logic; + ENPIRION_CLOCK : out std_logic; + TEMPSENS : inout std_logic; + + --Test Connectors + TEST_LINE : out std_logic_vector(15 downto 0) + ); + + + attribute syn_useioff : boolean; + attribute syn_useioff of FLASH_CLK : signal is true; + attribute syn_useioff of FLASH_CS : signal is true; + attribute syn_useioff of FLASH_IN : signal is true; + attribute syn_useioff of FLASH_OUT : signal is true; + attribute syn_useioff of INP : signal is false; + + + --Serdes: Backplane + --Backplane A2,A3,A0,A1 Slave 3,4,1,2, A0: TrbNet from backplane + --AddOn C2,C3,C0,C1,B0,B1,B2,D1(B3) Slave --,--,5,9,8,7,6,-- + --SFP D0,B3(D1) D0: GbE, B3: TrbNet + + +end entity; + +architecture trb3sc_arch of trb3sc_triggerbox is + attribute syn_keep : boolean; + attribute syn_preserve : boolean; + + signal clk_sys, clk_full, clk_full_osc : std_logic; + signal GSR_N : std_logic; + signal reset_i : std_logic; + signal clear_i : std_logic; + + signal time_counter : unsigned(31 downto 0) := (others => '0'); + signal led : std_logic_vector(1 downto 0); + signal debug_clock_reset : std_logic_vector(31 downto 0); + signal debug_tools : std_logic_vector(31 downto 0); + + --Media Interface + signal med2int : med2int_array_t(0 to 0); + signal int2med : int2med_array_t(0 to 0); + signal med_stat_debug : std_logic_vector (1*64-1 downto 0); + + --READOUT + signal readout_rx : READOUT_RX; + signal readout_tx : readout_tx_array_t(0 to 0); + + signal ctrlbus_rx, bussci_rx, bustools_rx, bustc_rx, busrdo_rx, busscaler_rx, bus_master_out : CTRLBUS_RX; + signal ctrlbus_tx, bussci_tx, bustools_tx, bustc_tx, busrdo_tx, busscaler_tx, bus_master_in : CTRLBUS_TX; + + signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); + signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); + + signal sed_error_i : std_logic; + signal clock_select : std_logic; + signal bus_master_active : std_logic; + + signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0); + + signal timer : TIMERS; + + signal sfp_los_i, sfp_txdis_i, sfp_prsnt_i : std_logic; + + signal sorted_INP : std_logic_vector(INP'range); + + attribute syn_keep of GSR_N : signal is true; + attribute syn_preserve of GSR_N : signal is true; + attribute syn_keep of bussci_rx : signal is true; + attribute syn_preserve of bussci_rx : signal is true; + attribute syn_keep of bustools_rx : signal is true; + attribute syn_preserve of bustools_rx : signal is true; + attribute syn_keep of bustc_rx : signal is true; + attribute syn_preserve of bustc_rx : signal is true; + + +begin + +--------------------------------------------------------------------------- +-- Clock & Reset Handling +--------------------------------------------------------------------------- +THE_CLOCK_RESET : entity work.clock_reset_handler + port map( + INT_CLK_IN => CLK_CORE_PCLK, + EXT_CLK_IN => CLK_EXT_PLL_LEFT, + NET_CLK_FULL_IN => med2int(0).clk_full, + NET_CLK_HALF_IN => med2int(0).clk_half, + RESET_FROM_NET => med2int(0).stat_op(13), + SEND_RESET_IN => med2int(0).stat_op(15), --? + + BUS_RX => bustc_rx, + BUS_TX => bustc_tx, + + RESET_OUT => reset_i, + CLEAR_OUT => clear_i, + GSR_OUT => GSR_N, + + FULL_CLK_OUT => clk_full, + SYS_CLK_OUT => clk_sys, + REF_CLK_OUT => clk_full_osc, + + ENPIRION_CLOCK => ENPIRION_CLOCK, + LED_RED_OUT => LED_RJ_RED, + LED_GREEN_OUT => LED_RJ_GREEN, + DEBUG_OUT => debug_clock_reset + ); + + +--------------------------------------------------------------------------- +-- TrbNet Uplink +--------------------------------------------------------------------------- + + THE_MEDIA_INTERFACE : entity work.med_ecp3_sfp_sync + generic map( + SERDES_NUM => SERDES_NUM, + IS_SYNC_SLAVE => c_YES + ) + port map( + CLK_REF_FULL => clk_full_osc, --med2int(0).clk_full, + CLK_INTERNAL_FULL => clk_full_osc, + SYSCLK => clk_sys, + RESET => reset_i, + CLEAR => clear_i, + --Internal Connection + MEDIA_MED2INT => med2int(0), + MEDIA_INT2MED => int2med(0), + + --Sync operation + RX_DLM => open, + RX_DLM_WORD => open, + TX_DLM => open, + TX_DLM_WORD => open, + + --SFP Connection + SD_PRSNT_N_IN => sfp_prsnt_i, + SD_LOS_IN => sfp_los_i, + SD_TXDIS_OUT => sfp_txdis_i, + --Control Interface + BUS_RX => bussci_rx, + BUS_TX => bussci_tx, + -- Status and control port + STAT_DEBUG => med_stat_debug(63 downto 0), + CTRL_DEBUG => open + ); + + SFP_TX_DIS(0) <= '0'; + gen_sfp_con : if SERDES_NUM = 3 generate + sfp_los_i <= SFP_LOS(1); + sfp_prsnt_i <= SFP_MOD0(1); + SFP_TX_DIS(1) <= sfp_txdis_i; + end generate; + gen_bpl_con : if SERDES_NUM = 0 generate + sfp_los_i <= BACK_GPIO(1); + sfp_prsnt_i <= BACK_GPIO(1); + BACK_GPIO(0) <= sfp_txdis_i; + end generate; + +--------------------------------------------------------------------------- +-- Endpoint +--------------------------------------------------------------------------- +THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record + generic map ( + ADDRESS_MASK => x"FFFF", + BROADCAST_BITMASK => BROADCAST_BITMASK, + REGIO_INIT_ENDPOINT_ID => x"0001", + TIMING_TRIGGER_RAW => c_YES, + --Configure data handler + DATA_INTERFACE_NUMBER => 1, + DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE, + DATA_BUFFER_WIDTH => 32, + DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE, + TRG_RELEASE_AFTER_DATA => c_YES, + HEADER_BUFFER_DEPTH => 9, + HEADER_BUFFER_FULL_THRESH => 2**8, + USE_GBE => USE_GBE + ) + + port map( + -- Misc + CLK => clk_sys, + RESET => reset_i, + CLK_EN => '1', + CLK_125 => CLK_SUPPL_PCLK, + CLEAR_N => GSR_N, + + -- Media direction port + MEDIA_MED2INT => med2int(0), + MEDIA_INT2MED => int2med(0), + + --Timing trigger in + TRG_TIMING_TRG_RECEIVED_IN => TRIG_LEFT, + + READOUT_RX => readout_rx, + READOUT_TX => readout_tx, + + --Slow Control Port + REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00 + REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 + BUS_RX => ctrlbus_rx, + BUS_TX => ctrlbus_tx, + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + + ONEWIRE_INOUT => TEMPSENS, + --Timing registers + TIMERS_OUT => timer + ); + +--------------------------------------------------------------------------- +-- Bus Handler +--------------------------------------------------------------------------- + + + THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record + generic map( + PORT_NUMBER => 5, + PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"a000", 4 => x"9000", others => x"0000"), + PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 12, 4 => 10, others => 0), + PORT_MASK_ENABLE => 1 + ) + port map( + CLK => clk_sys, + RESET => reset_i, + + REGIO_RX => ctrlbus_rx, + REGIO_TX => ctrlbus_tx, + + BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED + BUS_RX(1) => bussci_rx, --SCI Serdes + BUS_RX(2) => bustc_rx, --Clock switch + BUS_RX(3) => busrdo_rx, --Triggerbox config + BUS_RX(4) => busscaler_rx,--Sclaer + BUS_TX(0) => bustools_tx, + BUS_TX(1) => bussci_tx, + BUS_TX(2) => bustc_tx, + BUS_TX(3) => busrdo_tx, + BUS_TX(4) => busscaler_tx, + + STAT_DEBUG => open + ); + +--------------------------------------------------------------------------- +-- Control Tools +--------------------------------------------------------------------------- + THE_TOOLS: entity work.trb3sc_tools + port map( + CLK => clk_sys, + RESET => reset_i, + + --Flash & Reload + FLASH_CS => FLASH_CS, + FLASH_CLK => FLASH_CLK, + FLASH_IN => FLASH_OUT, + FLASH_OUT => FLASH_IN, + PROGRAMN => PROGRAMN, + REBOOT_IN => common_ctrl_reg(15), + --SPI + SPI_CS_OUT => spi_cs, + SPI_MOSI_OUT=> spi_mosi, + SPI_MISO_IN => spi_miso, + SPI_CLK_OUT => spi_clk, + --Header + HEADER_IO => HDR_IO, + --LCD + LCD_DATA_IN => open, + --ADC + ADC_CS => ADC_CS, + ADC_MOSI => ADC_DIN, + ADC_MISO => ADC_DOUT, + ADC_CLK => ADC_CLK, + --Trigger & Monitor + MONITOR_INPUTS => open,--KEL(32 downto 1),--(others => '0'), + TRIG_GEN_INPUTS => open,--KEL(32 downto 1),--(others => '0'), + TRIG_GEN_OUTPUTS => open, --X(4 downto 1),--open, + --SED + SED_ERROR_OUT => sed_error_i, + --Slowcontrol + BUS_RX => bustools_rx, + BUS_TX => bustools_tx, + --Control master for default settings + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + DEBUG_OUT => debug_tools + ); + +--------------------------------------------------------------------------- +-- Switches +--------------------------------------------------------------------------- +--Serdes Select + PCSSW_ENSMB <= '0'; + PCSSW_EQ <= x"0"; + PCSSW_PE <= x"F"; + PCSSW <= "01001110"; --SFP2 on B3, AddOn on D1 + +--------------------------------------------------------------------------- +-- I/O +--------------------------------------------------------------------------- + +-- RJ_IO <= "0000"; +-- BACK_GPIO <= (others => 'Z'); + BACK_LVDS <= (others => '0'); + BACK_3V3 <= (others => 'Z'); + + + +--------------------------------------------------------------------------- +-- LED +--------------------------------------------------------------------------- + --LED are green, orange, red, yellow, white(2), rj_green(2), rj_red(2), sfp_green(2), sfp_red(2) + LED_GREEN <= debug_clock_reset(0); + LED_ORANGE <= debug_clock_reset(1); + LED_RED <= not sed_error_i; + LED_YELLOW <= debug_clock_reset(2); + LED_WHITE(0) <= time_counter(26) and time_counter(19); + LED_WHITE(1) <= time_counter(20); + LED_SFP_GREEN <= not med2int(0).stat_op(9) & '1'; --SFP Link Status + LED_SFP_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)) & '1'; --SFP RX/TX + +--------------------------------------------------------------------------- +-- Test Circuits +--------------------------------------------------------------------------- + process begin + wait until rising_edge(clk_sys); + time_counter <= time_counter + 1; + if reset_i = '1' then + time_counter <= (others => '0'); + end if; + end process; + + + +--------------------------------------------------------------------------- +-- TriggerBox +--------------------------------------------------------------------------- +sorted_INP <= INP(95 downto 80) & INP(63 downto 32) & INP(79 downto 64) & INP(31 downto 0); +--order from 0: ADA1 - KEL1 - ADA2 - KEL2 + + THE_BOX : entity work.triggerbox + generic map( + NUM_PHYS_INPUTS => 96, + NUM_INPUTS => 48, + NUM_VIRTUALIN => 32, + NUM_GROUPS => 16, + NUM_COINC => 16, + NUM_MULT => 8, + NUM_OUTPUTS => 8 + ) + port map( + CLK_SYS => clk_sys, + CLK_FULL => clk_full, + RESET => reset_i, + + INP => sorted_INP, + OUTP => X, + MONITOR_OUT => TEST_LINE(15 downto 0), + + BUS_RX => busrdo_rx, + BUS_TX => busrdo_tx, + BUSSCALER_RX => busscaler_rx, + BUSSCALER_TX => busscaler_tx, + + BUSRDO_RX => readout_rx, + BUSRDO_TX => readout_tx(0) + ); + +end architecture; + + + -- 2.43.0