From d1ce1a4ac82be71254b5c795afda12a51cb0b8a8 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Thu, 28 Apr 2011 16:22:13 +0000 Subject: [PATCH] Xilinx FIFO 19x16 obuf by Boris --- xilinx/virtex4/fifo_19x16_obuf.vhd | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/xilinx/virtex4/fifo_19x16_obuf.vhd b/xilinx/virtex4/fifo_19x16_obuf.vhd index 254e1ef..1230adf 100644 --- a/xilinx/virtex4/fifo_19x16_obuf.vhd +++ b/xilinx/virtex4/fifo_19x16_obuf.vhd @@ -34,7 +34,7 @@ port ( rd_en: IN std_logic; rst: IN std_logic; wr_en: IN std_logic; - data_count: OUT std_logic_VECTOR(4 downto 0); + data_count: OUT std_logic_VECTOR(3 downto 0); dout: OUT std_logic_VECTOR(18 downto 0); empty: OUT std_logic; full: OUT std_logic; @@ -46,6 +46,7 @@ end component; begin +WCNT(4) <= '0'; the_xilinx_fifo_19x16_obuf: xilinx_fifo_19x16_obuf port map( @@ -55,7 +56,7 @@ port map( rd_en => RdEn, rst => Reset, wr_en => WrEn, - data_count => WCNT, + data_count => WCNT(3 downto 0), dout => Q, empty => Empty, full => Full, -- 2.43.0