From d1d606c158583631ca619d590b12287e62de111e Mon Sep 17 00:00:00 2001 From: Tobias Weber Date: Fri, 10 Nov 2017 11:45:57 +0100 Subject: [PATCH] Integrate slow control changes into Mupix8 board top-level. --- mupix/Mupix8/sources/MupixBoard.vhd | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/mupix/Mupix8/sources/MupixBoard.vhd b/mupix/Mupix8/sources/MupixBoard.vhd index 0528d97..3a62433 100644 --- a/mupix/Mupix8/sources/MupixBoard.vhd +++ b/mupix/Mupix8/sources/MupixBoard.vhd @@ -161,11 +161,8 @@ architecture Behavioral of MupixBoard is clk : in std_logic; --clock reset : in std_logic; --reset --mupix control - ctrl_din : out std_logic; --serial data to mupix - ctrl_clk1 : out std_logic; --slow control clock 1 - ctrl_clk2 : out std_logic; --slow control clock 2 - ctrl_load : out std_logic; --slow control load - ctrl_dout : in std_logic; --serial data from mupix + mupixslctrl : out MupixSlowControl; + ctrl_dout : in std_logic; --serial data from mupix --TRB slow control SLV_READ_IN : in std_logic; SLV_WRITE_IN : in std_logic; @@ -179,6 +176,7 @@ architecture Behavioral of MupixBoard is constant fpga_clk_speed : integer := 1e8; --100 MHz constant mupix_spi_clk_speed : integer := 5e4;--50 kHz + signal mupixslctrl_i : MupixSlowControl; component MupixBoardDAC is port( @@ -323,10 +321,7 @@ begin -- Behavioral port map( clk => clk, reset => reset, - ctrl_din => ctrl_din, - ctrl_clk1 => ctrl_clk1, - ctrl_clk2 => ctrl_clk2, - ctrl_load => ctrl_ld, + mupixslctrl => mupixslctrl_i, ctrl_dout => ctrl_dout_sync, SLV_READ_IN => slv_read(1), SLV_WRITE_IN => slv_write(1), @@ -338,6 +333,12 @@ begin -- Behavioral SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(1) ); + ctrl_din <= mupixslctrl_i.sin; + ctrl_clk1 <= mupixslctrl_i.clk1; + ctrl_clk2 <= mupixslctrl_i.clk2; + ctrl_ld <= mupixslctrl_i.load; + + boardcontrol_1 : component MupixBoardDAC port map( clk => clk, @@ -349,7 +350,7 @@ begin -- Behavioral spi_din => spi_din, spi_ld_tmp_dac => spi_ld_tmp_dac, spi_ld_thres => spi_ld_thres, - spi_ld_adc => spi_ld_adc, + spi_cs_adc => spi_cs_adc, injection_pulse => testpulse, SLV_READ_IN => slv_read(2), SLV_WRITE_IN => slv_write(2), -- 2.43.0