From d313a5b11238dcfbe5fa98347da4709795cedf7b Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Tue, 3 Aug 2010 13:39:02 +0000 Subject: [PATCH] *** empty log message *** --- gbe_ecp2m/trb_net16_med_ecp_sfp_gbe_8b.vhd | 154 ++++++++++----------- 1 file changed, 76 insertions(+), 78 deletions(-) diff --git a/gbe_ecp2m/trb_net16_med_ecp_sfp_gbe_8b.vhd b/gbe_ecp2m/trb_net16_med_ecp_sfp_gbe_8b.vhd index 877620f..fe9069c 100755 --- a/gbe_ecp2m/trb_net16_med_ecp_sfp_gbe_8b.vhd +++ b/gbe_ecp2m/trb_net16_med_ecp_sfp_gbe_8b.vhd @@ -16,10 +16,7 @@ port( RESET : in std_logic; GSR_N : in std_logic; CLK_125_OUT : out std_logic; - CLK_RX_OUT : out std_logic; - CLK_TX_OUT : out std_logic; - CLK_125_TX_IN : in std_logic; -- gk 28.04.10 used when intclk - CLK_125_RX_IN : in std_logic; -- gk 28.04.10 used when intclk + CLK_125_IN : in std_logic; -- gk 28.04.10 used when intclk --SGMII connection to frame transmitter (tsmac) FT_TX_CLK_EN_OUT : out std_logic; FT_RX_CLK_EN_OUT : out std_logic; @@ -135,7 +132,6 @@ component serdes_gbe_0_intclock_8b is ffc_trst : in std_logic; ff_txfullclk : out std_logic; ff_txhalfclk : out std_logic; - refck2core : out std_logic; ffs_plol : out std_logic); end component; @@ -250,45 +246,49 @@ begin -- Reset state machine for SerDes THE_RESET_STATEMACHINE: trb_net16_lsm_sfp_gbe -port map( SYSCLK => refclkcore, - RESET => '0', -- really? - CLEAR => RESET, -- from 100MHz PLL, includes async part - -- status signals - SFP_MISSING_IN => SD_PRSNT_N_IN, - SFP_LOS_IN => SD_LOS_IN, - SD_LINK_OK_IN => '1', -- not used - SD_LOS_IN => '0', -- not used - SD_TXCLK_BAD_IN => sd_link_error(2), -- plol - SD_RXCLK_BAD_IN => sd_link_error(1), -- rlol - -- control signals - FULL_RESET_OUT => quad_rst, - LANE_RESET_OUT => lane_rst, - USER_RESET_OUT => user_rst, - -- debug signals - TIMING_CTR_OUT => open, - BSM_OUT => reset_bsm, - DEBUG_OUT => reset_debug - ); +port map( + SYSCLK => refclkcore, + RESET => '0', -- really? + CLEAR => RESET, -- from 100MHz PLL, includes async part + -- status signals + SFP_MISSING_IN => SD_PRSNT_N_IN, + SFP_LOS_IN => SD_LOS_IN, + SD_LINK_OK_IN => '1', -- not used + SD_LOS_IN => '0', -- not used + SD_TXCLK_BAD_IN => sd_link_error(2), -- plol + SD_RXCLK_BAD_IN => sd_link_error(1), -- rlol + -- control signals + FULL_RESET_OUT => quad_rst, + LANE_RESET_OUT => lane_rst, + USER_RESET_OUT => user_rst, + -- debug signals + TIMING_CTR_OUT => open, + BSM_OUT => reset_bsm, + DEBUG_OUT => reset_debug +); -- gk 28.04.10 -- SerDes for GbE -clk_int : if (USE_125MHZ_EXTCLK = 0) generate +clk_int : if (USE_125MHZ_EXTCLK = 0) generate + + refclkcore <= CLK_125_IN; + SERDES_GBE : serdes_gbe_0_intclock_8b port map( - core_txrefclk => CLK_125_TX_IN, - core_rxrefclk => CLK_125_RX_IN, + core_txrefclk => CLK_125_IN, + core_rxrefclk => CLK_125_IN, hdinp0 => SD_RXD_P_IN, hdinn0 => SD_RXD_N_IN, hdoutp0 => SD_TXD_P_OUT, hdoutn0 => SD_TXD_N_OUT, - ff_rxiclk_ch0 => sd_rx_clk, - ff_txiclk_ch0 => sd_tx_clk, - ff_ebrd_clk_0 => sd_rx_clk, + ff_rxiclk_ch0 => sd_rx_clk, + ff_txiclk_ch0 => sd_tx_clk, + ff_ebrd_clk_0 => sd_rx_clk, ff_txdata_ch0 => sd_tx_data, ff_rxdata_ch0 => sd_rx_data, ff_tx_k_cntrl_ch0 => sd_tx_kcntl, ff_rx_k_cntrl_ch0 => sd_rx_kcntl, - ff_rxfullclk_ch0 => sd_rx_clk, + ff_rxfullclk_ch0 => sd_rx_clk, ff_xmit_ch0 => '0', ff_correct_disp_ch0 => sd_tx_correct_disp, ff_disp_err_ch0 => sd_rx_disp_error, @@ -306,9 +306,8 @@ clk_int : if (USE_125MHZ_EXTCLK = 0) generate ffc_macro_rst => '0', ffc_quad_rst => quad_rst, ffc_trst => '0', - ff_txfullclk => sd_tx_clk, - ff_txhalfclk => open, - refck2core => refclkcore, + ff_txfullclk => sd_tx_clk, + ff_txhalfclk => open, ffs_plol => sd_link_error(2) ); end generate clk_int; @@ -394,48 +393,49 @@ buf_stat_debug(11 downto 0) <= sd_rx_debug(11 downto 0); SGMII_GBE_PCS : sgmii_gbe_pcs32 -port map( rst_n => GSR_N, - signal_detect => sd_link_ok, - gbe_mode => '1', - sgmii_mode => MR_MODE_IN, - operational_rate => "10", - debug_link_timer_short => '0', - rx_compensation_err => pcs_rx_comp_err, - -- MAC interface - tx_clk_125 => refclkcore, -- original clock from SerDes - tx_clock_enable_source => pcs_tx_clk_en, - tx_clock_enable_sink => pcs_tx_clk_en, - tx_d => FT_TXD_IN, -- TX data from MAC - tx_en => FT_TX_EN_IN, -- TX data enable from MAC - tx_er => FT_TX_ER_IN, -- TX error from MAC - rx_clk_125 => refclkcore, -- original clock from SerDes - rx_clock_enable_source => pcs_rx_clk_en, - rx_clock_enable_sink => pcs_rx_clk_en, - rx_d => pcs_rx_d, -- RX data to MAC - rx_dv => pcs_rx_dv, -- RX data enable to MAC - rx_er => pcs_rx_er, -- RX error to MAC - col => FT_COL_OUT, - crs => FT_CRS_OUT, - -- SerDes interface - tx_data => sd_tx_data, -- TX data to SerDes - tx_kcntl => sd_tx_kcntl, -- TX komma control to SerDes - tx_disparity_cntl => sd_tx_correct_disp, -- idle parity state control in IPG (to SerDes) - serdes_recovered_clk => sd_rx_clk, -- 125MHz recovered from receive bit stream - rx_data => sd_rx_data, -- RX data from SerDes - rx_kcntl => sd_rx_kcntl, -- RX komma control from SerDes - rx_err_decode_mode => '0', -- receive error control mode fixed to normal - rx_even => '0', -- unused (receive error control mode = normal, tie to GND) - rx_disp_err => sd_rx_disp_error, -- RX disparity error from SerDes - rx_cv_err => sd_rx_cv_error, -- RX code violation error from SerDes - -- Autonegotiation stuff - mr_an_complete => pcs_mr_an_complete, - mr_page_rx => pcs_mr_page_rx, - mr_lp_adv_ability => pcs_mr_ability, - mr_main_reset => pcs_mr_reset, - mr_an_enable => MR_AN_ENABLE_IN, - mr_restart_an => MR_RESTART_AN_IN, - mr_adv_ability => MR_ADV_ABILITY_IN - ); +port map( + rst_n => GSR_N, + signal_detect => sd_link_ok, + gbe_mode => '1', + sgmii_mode => MR_MODE_IN, + operational_rate => "10", + debug_link_timer_short => '0', + rx_compensation_err => pcs_rx_comp_err, + -- MAC interface + tx_clk_125 => refclkcore, -- original clock from SerDes + tx_clock_enable_source => pcs_tx_clk_en, + tx_clock_enable_sink => pcs_tx_clk_en, + tx_d => FT_TXD_IN, -- TX data from MAC + tx_en => FT_TX_EN_IN, -- TX data enable from MAC + tx_er => FT_TX_ER_IN, -- TX error from MAC + rx_clk_125 => refclkcore, -- original clock from SerDes + rx_clock_enable_source => pcs_rx_clk_en, + rx_clock_enable_sink => pcs_rx_clk_en, + rx_d => pcs_rx_d, -- RX data to MAC + rx_dv => pcs_rx_dv, -- RX data enable to MAC + rx_er => pcs_rx_er, -- RX error to MAC + col => FT_COL_OUT, + crs => FT_CRS_OUT, + -- SerDes interface + tx_data => sd_tx_data, -- TX data to SerDes + tx_kcntl => sd_tx_kcntl, -- TX komma control to SerDes + tx_disparity_cntl => sd_tx_correct_disp, -- idle parity state control in IPG (to SerDes) + serdes_recovered_clk => sd_rx_clk, -- 125MHz recovered from receive bit stream + rx_data => sd_rx_data, -- RX data from SerDes + rx_kcntl => sd_rx_kcntl, -- RX komma control from SerDes + rx_err_decode_mode => '0', -- receive error control mode fixed to normal + rx_even => '0', -- unused (receive error control mode = normal, tie to GND) + rx_disp_err => sd_rx_disp_error, -- RX disparity error from SerDes + rx_cv_err => sd_rx_cv_error, -- RX code violation error from SerDes + -- Autonegotiation stuff + mr_an_complete => pcs_mr_an_complete, + mr_page_rx => pcs_mr_page_rx, + mr_lp_adv_ability => pcs_mr_ability, + mr_main_reset => pcs_mr_reset, + mr_an_enable => MR_AN_ENABLE_IN, + mr_restart_an => MR_RESTART_AN_IN, + mr_adv_ability => MR_ADV_ABILITY_IN +); pcs_mr_reset <= MR_RESET_IN or RESET or user_rst; @@ -448,8 +448,6 @@ MR_AN_PAGE_RX_OUT <= pcs_mr_page_rx; -- Clock games CLK_125_OUT <= refclkcore; -CLK_RX_OUT <= sd_rx_clk; -CLK_TX_OUT <= sd_tx_clk; -- Fakes STAT_OP <= (others => '0'); -- 2.43.0