From d32122d0606d02702d4e94870aa217ead9fc9e4d Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Fri, 5 Sep 2014 16:29:06 +0200 Subject: [PATCH] updated bus_handler_record --- lattice/ecp2m/fifo/fifo_var_oreg.vhd | 18 +-------- trb_net16_regio_bus_handler_record.vhd | 53 +++++++++++++++----------- 2 files changed, 31 insertions(+), 40 deletions(-) diff --git a/lattice/ecp2m/fifo/fifo_var_oreg.vhd b/lattice/ecp2m/fifo/fifo_var_oreg.vhd index 729946c..6f5a256 100644 --- a/lattice/ecp2m/fifo/fifo_var_oreg.vhd +++ b/lattice/ecp2m/fifo/fifo_var_oreg.vhd @@ -31,26 +31,10 @@ architecture fifo_var_oreg_arch of fifo_var_oreg is begin - assert (FIFO_DEPTH >= 8 and FIFO_DEPTH <= 15 and FIFO_WIDTH = 36) + assert (FIFO_DEPTH >= 9 and FIFO_DEPTH <= 15 and FIFO_WIDTH = 36) or (FIFO_DEPTH >= 8 and FIFO_DEPTH <= 11 and FIFO_WIDTH = 18) report "Selected data buffer size not implemented: depth - "&integer'image(FIFO_DEPTH)& ", width + 4 : " &integer'image(FIFO_WIDTH) severity error; - gen_36_256 : if FIFO_WIDTH = 36 and FIFO_DEPTH = 8 generate - THE_FIFO : fifo_36x256_oreg - port map( - Data => Data, - Clock => Clock, - WrEn => WrEn, - RdEn => RdEn, - Reset => Reset, - AmFullThresh => AmFullThresh, - Q => Q, - WCNT => WCNT, - Empty => Empty, - Full => Full, - AlmostFull => AlmostFull - ); - end generate; gen_36_512 : if FIFO_WIDTH = 36 and FIFO_DEPTH = 9 generate THE_FIFO : fifo_36x512_oreg diff --git a/trb_net16_regio_bus_handler_record.vhd b/trb_net16_regio_bus_handler_record.vhd index 7963344..1fe2f04 100644 --- a/trb_net16_regio_bus_handler_record.vhd +++ b/trb_net16_regio_bus_handler_record.vhd @@ -15,16 +15,9 @@ entity trb_net16_regio_bus_handler_record is port( CLK : in std_logic; RESET : in std_logic; - DAT_ADDR_IN : in std_logic_vector(15 downto 0); -- address bus - DAT_DATA_IN : in std_logic_vector(31 downto 0); -- data from TRB endpoint - DAT_DATA_OUT : out std_logic_vector(31 downto 0); -- data to TRB endpoint - DAT_READ_ENABLE_IN : in std_logic; -- read pulse - DAT_WRITE_ENABLE_IN : in std_logic; -- write pulse - DAT_TIMEOUT_IN : in std_logic; -- access timed out - DAT_DATAREADY_OUT : out std_logic; -- your data, master, as requested - DAT_WRITE_ACK_OUT : out std_logic; -- data accepted - DAT_NO_MORE_DATA_OUT : out std_logic; -- don't disturb me now - DAT_UNKNOWN_ADDR_OUT : out std_logic; -- noone here to answer your request + + REGIO_RX : in CTRLBUS_RX; + REGIO_TX : out CTRLBUS_TX; BUS_RX : out ctrlbus_rx_array_t(0 to PORT_NUMBER-1); BUS_TX : in ctrlbus_tx_array_t(0 to PORT_NUMBER-1); @@ -34,6 +27,21 @@ entity trb_net16_regio_bus_handler_record is end entity; +-- type CTRLBUS_TX is record +-- data : std_logic_vector(31 downto 0); +-- ack : std_logic; +-- wack,rack : std_logic; --for the old-fashioned guys +-- unknown : std_logic; +-- nack : std_logic; +-- end record; +-- +-- type CTRLBUS_RX is record +-- data : std_logic_vector(31 downto 0); +-- addr : std_logic_vector(15 downto 0); +-- write : std_logic; +-- read : std_logic; +-- timeout : std_logic; +-- end record; architecture regio_bus_handler_arch of trb_net16_regio_bus_handler_record is @@ -64,12 +72,12 @@ begin --Decode Addresses --------------------------------------------------------------------- - proc_port_select : process(DAT_ADDR_IN) + proc_port_select : process(REGIO_RX.addr) begin next_port_select_int <= PORT_NUMBER; gen_port_select : for i in 0 to PORT_NUMBER-1 loop if (PORT_ADDR_MASK(i) = 16 or - (DAT_ADDR_IN(15 downto PORT_ADDR_MASK(i)) = PORT_ADDRESSES(i)(15 downto PORT_ADDR_MASK(i)))) then + (REGIO_RX.addr(15 downto PORT_ADDR_MASK(i)) = PORT_ADDRESSES(i)(15 downto PORT_ADDR_MASK(i)))) then next_port_select_int <= i; end if; end loop; @@ -89,15 +97,15 @@ begin else buf_BUS_READ_OUT <= (others => '0'); buf_BUS_WRITE_OUT <= (others => '0'); - if DAT_WRITE_ENABLE_IN = '1' or DAT_READ_ENABLE_IN = '1' then - buf_BUS_DATA_OUT <= DAT_DATA_IN; - buf_BUS_ADDR_OUT <= DAT_ADDR_IN; + if REGIO_RX.write = '1' or REGIO_RX.read = '1' then + buf_BUS_DATA_OUT <= REGIO_RX.data; + buf_BUS_ADDR_OUT <= REGIO_RX.addr; port_select_int <= next_port_select_int; end if; - if DAT_READ_ENABLE_IN = '1' then + if REGIO_RX.read = '1' then buf_BUS_READ_OUT(next_port_select_int) <= '1'; end if; - if DAT_WRITE_ENABLE_IN = '1' then + if REGIO_RX.write = '1' then buf_BUS_WRITE_OUT(next_port_select_int) <= '1'; end if; end if; @@ -112,7 +120,7 @@ begin BUS_RX(i).read <= buf_BUS_READ_OUT(i); BUS_RX(i).write <= buf_BUS_WRITE_OUT(i); BUS_RX(i).data <= buf_BUS_DATA_OUT; - BUS_RX(i).timeout <= DAT_TIMEOUT_IN; + BUS_RX(i).timeout <= REGIO_RX.timeout; port_mask_disabled : if PORT_MASK_ENABLE = 0 generate BUS_RX(i).addr <= buf_BUS_ADDR_OUT; end generate; @@ -148,11 +156,10 @@ begin proc_reg_output_signals : process(CLK) begin if rising_edge(CLK) then - DAT_DATA_OUT <= buf_BUS_DATA_IN(port_select_int*32+31 downto port_select_int*32); - DAT_DATAREADY_OUT <= buf_BUS_DATAREADY_IN(port_select_int); - DAT_WRITE_ACK_OUT <= buf_BUS_WRITE_ACK_IN(port_select_int); - DAT_NO_MORE_DATA_OUT <= buf_BUS_NO_MORE_DATA_IN(port_select_int); - DAT_UNKNOWN_ADDR_OUT <= buf_BUS_UNKNOWN_ADDR_IN(port_select_int); + REGIO_TX.data <= buf_BUS_DATA_IN(port_select_int*32+31 downto port_select_int*32); + REGIO_TX.ack <= buf_BUS_DATAREADY_IN(port_select_int) or buf_BUS_WRITE_ACK_IN(port_select_int); + REGIO_TX.nack <= buf_BUS_NO_MORE_DATA_IN(port_select_int); + REGIO_TX.unknown <= buf_BUS_UNKNOWN_ADDR_IN(port_select_int); end if; end process; -- 2.43.0