From d444bf7f96300937a2da5f8828e07e5f0238e504 Mon Sep 17 00:00:00 2001 From: Cahit Date: Tue, 3 Nov 2015 10:17:41 +0100 Subject: [PATCH] made project compatible with tdc_v2.2 --- tdc_release | 2 +- tdctemplate/config.vhd | 2 +- tdctemplate/config_compile_gsi.pl | 4 ++-- tdctemplate/trb3sc_tdctemplate.lpf | 8 ++++++++ tdctemplate/trb3sc_tdctemplate.prj | 7 +++---- tdctemplate/trb3sc_tdctemplate.vhd | 23 ++++++++++++----------- template/config_compile_gsi.pl | 2 +- 7 files changed, 28 insertions(+), 20 deletions(-) diff --git a/tdc_release b/tdc_release index e8932f5..8d7edce 120000 --- a/tdc_release +++ b/tdc_release @@ -1 +1 @@ -../tdc/releases/tdc_v2.1.6 \ No newline at end of file +../tdc/releases/tdc_v2.2 \ No newline at end of file diff --git a/tdctemplate/config.vhd b/tdctemplate/config.vhd index 6679bdf..bfddb39 100644 --- a/tdctemplate/config.vhd +++ b/tdctemplate/config.vhd @@ -12,7 +12,7 @@ package config is --TDC settings constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement - constant NUM_TDC_CHANNELS : integer range 1 to 65 := 3; -- number of tdc channels per module + constant NUM_TDC_CHANNELS : integer range 1 to 65 := 41; -- number of tdc channels per module constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3 -- 0: single edge only, diff --git a/tdctemplate/config_compile_gsi.pl b/tdctemplate/config_compile_gsi.pl index 052a7c1..416f4ee 100644 --- a/tdctemplate/config_compile_gsi.pl +++ b/tdctemplate/config_compile_gsi.pl @@ -1,12 +1,12 @@ TOPNAME => "trb3sc_tdctemplate", lm_license_file_for_synplify => "27000\@lxcad01.gsi.de", lm_license_file_for_par => "1702\@hadeb05.gsi.de", -lattice_path => '/opt/lattice/diamond/3.4_x64/', +lattice_path => '/opt/lattice/diamond/3.5_x64/', synplify_path => '/opt/synplicity/J-2014.09-SP2', #synplify_command => "/opt/lattice/diamond/3.5_x64/bin/lin64/synpwrap -fg -options", synplify_command => "/opt/synplicity/J-2014.09-SP2/bin/synplify_premier_dp", -nodelist_file => 'nodelist_gsi_template.txt', +nodelist_file => 'nodes_gsi_template.txt', include_TDC => 1, diff --git a/tdctemplate/trb3sc_tdctemplate.lpf b/tdctemplate/trb3sc_tdctemplate.lpf index e69de29..b5995bb 100644 --- a/tdctemplate/trb3sc_tdctemplate.lpf +++ b/tdctemplate/trb3sc_tdctemplate.lpf @@ -0,0 +1,8 @@ +MULTICYCLE FROM CLKNET "clk_sys" TO CLKNET "clk_full" 1 X ; +MULTICYCLE FROM CLKNET "clk_full" TO CLKNET "clk_sys" 2 X ; + +MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET clk_full TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET clk_sys 2x; +MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET clk_full TO CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET clk_sys 2x; + +MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" CLKNET clk_sys TO CLKNET clk_sys 5x; +MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" TO CLKNET clk_full 2x; diff --git a/tdctemplate/trb3sc_tdctemplate.prj b/tdctemplate/trb3sc_tdctemplate.prj index ef3b94b..49d6a04 100644 --- a/tdctemplate/trb3sc_tdctemplate.prj +++ b/tdctemplate/trb3sc_tdctemplate.prj @@ -179,22 +179,21 @@ add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd" add_file -vhdl -lib work "../../trb3sc/tdc_release/tdc_version.vhd" add_file -vhdl -lib work "../../trb3sc/tdc_release/tdc_components.vhd" add_file -vhdl -lib work "../../trb3sc/tdc_release/bit_sync.vhd" -add_file -vhdl -lib work "../../trb3sc/tdc_release/BusHandler.vhd" add_file -vhdl -lib work "../../trb3sc/tdc_release/BusHandler_record.vhd" add_file -vhdl -lib work "../../trb3sc/tdc_release/Channel_200.vhd" add_file -vhdl -lib work "../../trb3sc/tdc_release/Channel.vhd" -add_file -vhdl -lib work "../../trb3sc/tdc_release/Encoder_304_Bit.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/Encoder_288_Bit.vhd" +#add_file -vhdl -lib work "../../trb3sc/tdc_release/Encoder_304_Bit.vhd" add_file -vhdl -lib work "../../trb3sc/tdc_release/fallingEdgeDetect.vhd" add_file -vhdl -lib work "../../trb3sc/tdc_release/hit_mux.vhd" add_file -vhdl -lib work "../../trb3sc/tdc_release/LogicAnalyser.vhd" -add_file -vhdl -lib work "../../trb3sc/tdc_release/Readout.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/Readout_record.vhd" add_file -vhdl -lib work "../../trb3sc/tdc_release/risingEdgeDetect.vhd" add_file -vhdl -lib work "../../trb3sc/tdc_release/ROM_encoder_ecp3.vhd" add_file -vhdl -lib work "../../trb3sc/tdc_release/ShiftRegisterSISO.vhd" add_file -vhdl -lib work "../../trb3sc/tdc_release/Stretcher_A.vhd" add_file -vhdl -lib work "../../trb3sc/tdc_release/Stretcher_B.vhd" add_file -vhdl -lib work "../../trb3sc/tdc_release/Stretcher.vhd" -add_file -vhdl -lib work "../../trb3sc/tdc_release/TDC.vhd" add_file -vhdl -lib work "../../trb3sc/tdc_release/TDC_record.vhd" add_file -vhdl -lib work "../../trb3sc/tdc_release/TriggerHandler.vhd" add_file -vhdl -lib work "../../trb3sc/tdc_release/up_counter.vhd" diff --git a/tdctemplate/trb3sc_tdctemplate.vhd b/tdctemplate/trb3sc_tdctemplate.vhd index d683dfe..3e8a66d 100644 --- a/tdctemplate/trb3sc_tdctemplate.vhd +++ b/tdctemplate/trb3sc_tdctemplate.vhd @@ -418,19 +418,20 @@ begin DEBUG => c_YES, SIMULATION => c_NO) port map ( - RESET => reset_i, - CLK_TDC => clk_full_osc, - CLK_READOUT => clk_sys, -- Clock for the readout - REFERENCE_TIME => TRIG_LEFT, -- Reference time input - HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals - HIT_CAL_IN => clk_cal, -- Hits for calibrating the TDC + RESET => reset_i, + CLK_TDC => clk_full_osc, + CLK_READOUT => clk_sys, -- Clock for the readout + REFERENCE_TIME => TRIG_LEFT, -- Reference time input + HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals + HIT_CAL_IN => clk_cal, -- Hits for calibrating the TDC -- Trigger signals from handler - READOUT_RX => readout_rx, - READOUT_TX => readout_tx(0), - -- - LOGIC_ANALYSER_OUT => logic_analyser_i, + BUSRDO_RX => readout_rx, + BUSRDO_TX => readout_tx(0), + -- Slow control bus BUS_RX => bustdc_rx, - BUS_TX => bustdc_tx + BUS_TX => bustdc_tx, + -- Dubug signals + LOGIC_ANALYSER_OUT => logic_analyser_i ); -- For single edge measurements diff --git a/template/config_compile_gsi.pl b/template/config_compile_gsi.pl index 2fa920e..8fb3469 100644 --- a/template/config_compile_gsi.pl +++ b/template/config_compile_gsi.pl @@ -6,7 +6,7 @@ synplify_path => '/opt/synplicity/J-2014.09-SP2', #synplify_command => "/opt/lattice/diamond/3.5_x64/bin/lin64/synpwrap -fg -options", synplify_command => "/opt/synplicity/J-2014.09-SP2/bin/synplify_premier_dp", -nodelist_file => 'nodelist_gsi_template.txt', +nodelist_file => 'nodes_gsi_template.txt', include_TDC => 1, -- 2.43.0