From d4650692cd28adc06cdd34d13310e00a63162924 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Tue, 23 Aug 2022 17:13:40 +0200 Subject: [PATCH] update project files with automatic ADC reader --- adcaddon/trb3sc_adc.prj | 2 ++ backplanemaster/config_compile_frankfurt.pl | 4 ++-- backplanemaster/trb3sc_master.prj | 2 ++ cts/trb3sc_cts.prj | 2 ++ halfmasterhub/trb3sc_master.prj | 2 ++ hub/config_compile_frankfurt.pl | 6 +++--- hub/trb3sc_hub.prj | 2 ++ padiwa/trb3sc_padiwa.prj | 2 ++ tdctemplate/trb3sc_tdctemplate.prj | 2 ++ template/trb3sc_basic.prj | 2 ++ triggerbox/trb3sc_triggerbox.prj | 2 ++ 11 files changed, 23 insertions(+), 5 deletions(-) diff --git a/adcaddon/trb3sc_adc.prj b/adcaddon/trb3sc_adc.prj index 7da9261..84e0f5d 100644 --- a/adcaddon/trb3sc_adc.prj +++ b/adcaddon/trb3sc_adc.prj @@ -116,6 +116,8 @@ add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd" add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_19x8_preset.vhd" +add_file -vhdl -lib work "../../trb3sc/code/adc_controller.vhd" #SlowControl files add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" diff --git a/backplanemaster/config_compile_frankfurt.pl b/backplanemaster/config_compile_frankfurt.pl index 0cf8f69..b40a05a 100644 --- a/backplanemaster/config_compile_frankfurt.pl +++ b/backplanemaster/config_compile_frankfurt.pl @@ -1,8 +1,8 @@ TOPNAME => "trb3sc_master", lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; lm_license_file_for_par => "1702\@hadeb05.gsi.de", -lattice_path => '/d/jspc29/lattice/diamond/3.10_x64/', -synplify_path => '/d/jspc29/lattice/synplify/O-2018.09-SP1', +lattice_path => '/d/jspc29/lattice/diamond/3.12/', +synplify_path => '/d/jspc29/lattice/synplify/S-2021.09-SP2', #lattice_path => '/d/jspc29/lattice/diamond/3.10_x64/', #synplify_path => '/d/jspc29/lattice/synplify/N-2017.09-1/', # synplify_command => "/d/jspc29/lattice/diamond/3.6_x64/bin/lin64/synpwrap -fg -options", diff --git a/backplanemaster/trb3sc_master.prj b/backplanemaster/trb3sc_master.prj index 81e1854..ad3212f 100644 --- a/backplanemaster/trb3sc_master.prj +++ b/backplanemaster/trb3sc_master.prj @@ -120,6 +120,8 @@ add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd" add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_19x8_preset.vhd" +add_file -vhdl -lib work "../../trb3sc/code/adc_controller.vhd" #SlowControl files add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" diff --git a/cts/trb3sc_cts.prj b/cts/trb3sc_cts.prj index 646d4a6..c440017 100644 --- a/cts/trb3sc_cts.prj +++ b/cts/trb3sc_cts.prj @@ -122,6 +122,8 @@ add_file -vhdl -lib work "../../trbnet/special/uart.vhd" add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd" add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd" add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_19x8_preset.vhd" +add_file -vhdl -lib work "../../trb3sc/code/adc_controller.vhd" #SlowControl files add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" diff --git a/halfmasterhub/trb3sc_master.prj b/halfmasterhub/trb3sc_master.prj index 81e1854..ad3212f 100644 --- a/halfmasterhub/trb3sc_master.prj +++ b/halfmasterhub/trb3sc_master.prj @@ -120,6 +120,8 @@ add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd" add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_19x8_preset.vhd" +add_file -vhdl -lib work "../../trb3sc/code/adc_controller.vhd" #SlowControl files add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" diff --git a/hub/config_compile_frankfurt.pl b/hub/config_compile_frankfurt.pl index 6aa6e41..6ed0532 100644 --- a/hub/config_compile_frankfurt.pl +++ b/hub/config_compile_frankfurt.pl @@ -1,8 +1,8 @@ TOPNAME => "trb3sc_hub", lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; -lm_license_file_for_par => "1702\@hadeb05.gsi.de", -lattice_path => '/d/jspc29/lattice/diamond/3.10_x64', -synplify_path => '/d/jspc29/lattice/synplify/O-2018.09-SP1', +lm_license_file_for_par => "1710\@jspc29", +lattice_path => '/d/jspc29/lattice/diamond/3.11_x64', +synplify_path => '/d/jspc29/lattice/synplify/R-2020.09-SP1', #synplify_path => '/d/jspc29/lattice/synplify/L-2016.09-1/', #synplify_command => "/d/jspc29/lattice/diamond/3.5_x64/bin/lin64/synpwrap -fg -options", #synplify_command => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp", diff --git a/hub/trb3sc_hub.prj b/hub/trb3sc_hub.prj index 9aa1b13..5862200 100644 --- a/hub/trb3sc_hub.prj +++ b/hub/trb3sc_hub.prj @@ -120,6 +120,8 @@ add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd" add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_19x8_preset.vhd" +add_file -vhdl -lib work "../../trb3sc/code/adc_controller.vhd" #SlowControl files add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" diff --git a/padiwa/trb3sc_padiwa.prj b/padiwa/trb3sc_padiwa.prj index 297e689..6497e53 100644 --- a/padiwa/trb3sc_padiwa.prj +++ b/padiwa/trb3sc_padiwa.prj @@ -117,6 +117,8 @@ add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic.vhd" add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_19x8_preset.vhd" +add_file -vhdl -lib work "../../trb3sc/code/adc_controller.vhd" #SlowControl files add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" diff --git a/tdctemplate/trb3sc_tdctemplate.prj b/tdctemplate/trb3sc_tdctemplate.prj index 5b88f31..a397525 100644 --- a/tdctemplate/trb3sc_tdctemplate.prj +++ b/tdctemplate/trb3sc_tdctemplate.prj @@ -172,6 +172,8 @@ add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd" add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd" add_file -vhdl -lib work "../../trb3sc/code/fee_signals.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_19x8_preset.vhd" +add_file -vhdl -lib work "../../trb3sc/code/adc_controller.vhd" #SlowControl files add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" diff --git a/template/trb3sc_basic.prj b/template/trb3sc_basic.prj index 75bfd56..ca2c3fa 100644 --- a/template/trb3sc_basic.prj +++ b/template/trb3sc_basic.prj @@ -120,6 +120,8 @@ add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd" add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_19x8_preset.vhd" +add_file -vhdl -lib work "../../trb3sc/code/adc_controller.vhd" #SlowControl files add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" diff --git a/triggerbox/trb3sc_triggerbox.prj b/triggerbox/trb3sc_triggerbox.prj index 5b07f80..9c5599e 100644 --- a/triggerbox/trb3sc_triggerbox.prj +++ b/triggerbox/trb3sc_triggerbox.prj @@ -121,6 +121,8 @@ add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd" add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_19x8_preset.vhd" +add_file -vhdl -lib work "../../trb3sc/code/adc_controller.vhd" #SlowControl files add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" -- 2.43.0