From d53d5605a861995c04afef8770a0bdf1a79b60af Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Mon, 17 Jan 2022 15:33:09 +0100 Subject: [PATCH] RST distribution to be included. Reset of Master Ports fixed. --- media_interfaces/med_ecp3_sfp_sync_all_RS.vhd | 8 ++++---- media_interfaces/sync/med_sync_control_RS.vhd | 10 +--------- media_interfaces/sync/rx_control_RS.vhd | 6 +++--- media_interfaces/sync/tx_control_RS.vhd | 2 +- 4 files changed, 9 insertions(+), 17 deletions(-) diff --git a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd index b1be58c..595da83 100644 --- a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd +++ b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd @@ -190,10 +190,10 @@ begin clk_rx_full(1) when ((quad_mode >= 8) and (IS_MODE(1) = c_IS_SLAVE)) else clk_rx_full(2) when ((quad_mode >= 8) and (IS_MODE(2) = c_IS_SLAVE)) else clk_rx_full(3) when ((quad_mode >= 8) and (IS_MODE(3) = c_IS_SLAVE)) else - clk_tx_full(0) when ((quad_mode = 1) and (IS_MODE(0) = c_IS_MASTER)) else - clk_tx_full(1) when ((quad_mode = 1) and (IS_MODE(1) = c_IS_MASTER)) else - clk_tx_full(2) when ((quad_mode = 1) and (IS_MODE(2) = c_IS_MASTER)) else - clk_tx_full(3) when ((quad_mode = 1) and (IS_MODE(3) = c_IS_MASTER)) else +-- clk_tx_full(0) when ((quad_mode = 1) and (IS_MODE(0) = c_IS_MASTER)) else +-- clk_tx_full(1) when ((quad_mode = 1) and (IS_MODE(1) = c_IS_MASTER)) else +-- clk_tx_full(2) when ((quad_mode = 1) and (IS_MODE(2) = c_IS_MASTER)) else +-- clk_tx_full(3) when ((quad_mode = 1) and (IS_MODE(3) = c_IS_MASTER)) else '0'; ------------------------------------------------- diff --git a/media_interfaces/sync/med_sync_control_RS.vhd b/media_interfaces/sync/med_sync_control_RS.vhd index 9dae191..e77929a 100644 --- a/media_interfaces/sync/med_sync_control_RS.vhd +++ b/media_interfaces/sync/med_sync_control_RS.vhd @@ -105,14 +105,6 @@ architecture med_sync_control_arch of med_sync_control_RS is -- attribute syn_preserve : boolean; -- attribute syn_keep of rx_lsm_state : signal is true; -- attribute syn_preserve of rx_lsm_state : signal is true; --- attribute syn_keep of link_half_done_i : signal is true; --- attribute syn_preserve of link_half_done_i : signal is true; --- attribute syn_keep of link_full_done_i : signal is true; --- attribute syn_preserve of link_full_done_i : signal is true; --- attribute syn_keep of word_sync_rx_i : signal is true; --- attribute syn_preserve of word_sync_rx_i : signal is true; --- attribute syn_keep of word_sync_tx_i : signal is true; --- attribute syn_preserve of word_sync_tx_i : signal is true; begin @@ -147,7 +139,7 @@ begin -- outputs RX_SERDES_RST_OUT => rx_serdes_rst_i, -- CLK_REF based RX_PCS_RST_OUT => rx_pcs_rst_i, -- CLK_REF based - LINK_RX_READY_OUT => link_rx_ready_i, -- CLK_REF based + LINK_RX_READY_OUT => link_rx_ready_i, --LINK_RX_READY_OUT, -- CLK_REF based STATE_OUT => rx_fsm_state ); diff --git a/media_interfaces/sync/rx_control_RS.vhd b/media_interfaces/sync/rx_control_RS.vhd index de556f8..3e192f5 100644 --- a/media_interfaces/sync/rx_control_RS.vhd +++ b/media_interfaces/sync/rx_control_RS.vhd @@ -210,7 +210,7 @@ begin when FIRST => rx_state_bits <= x"2"; - rx_data(7 downto 0) <= reg_rx_data_in; + rx_data(7 downto 0) <= reg_rx_data_in; sync_k_i <= '1'; if( reg_rx_k_in = '1' ) then case reg_rx_data_in is @@ -276,8 +276,8 @@ begin end case; -- BUG: master ports don't reset correctly --- if( (RESET = '1') or (link_rx_ready_qrx = '0') ) then - if( (RESET = '1') ) then + if( (RESET = '1') or (link_rx_ready_qrx = '0') ) then +-- if( (RESET = '1') ) then rx_state <= SLEEP; rx_dlm_word_i <= x"00"; rx_rst_word_i <= x"00"; diff --git a/media_interfaces/sync/tx_control_RS.vhd b/media_interfaces/sync/tx_control_RS.vhd index feaa457..632600b 100644 --- a/media_interfaces/sync/tx_control_RS.vhd +++ b/media_interfaces/sync/tx_control_RS.vhd @@ -131,7 +131,7 @@ begin link_active_qtx <= link_active_int when rising_edge(CLK_TXI); - -- if not set, send toggling idles + -- if set send IDLE1, else IDLE0 send_steady_idle_int <= link_tx_ready_qtx and link_rx_ready_qtx and link_half_done_qtx when (IS_MODE = c_IS_MASTER) else link_tx_ready_qtx and link_rx_ready_qtx and -- 2.43.0