From d5a1a037d011afc747c3fa2a9f71944003e608c5 Mon Sep 17 00:00:00 2001 From: Cahit Date: Wed, 17 Apr 2013 11:36:48 +0200 Subject: [PATCH] Work on release v1.4 has started - cu --- tdc_releases/ReleaseNotes.txt | 2 + tdc_releases/tdc_v1.4/Adder_304.ngo | Bin 0 -> 204115 bytes tdc_releases/tdc_v1.4/Adder_304.vhd | 1310 +++++++++++++++++ tdc_releases/tdc_v1.4/BusHandler.vhd | 89 ++ tdc_releases/tdc_v1.4/Channel.vhd | 236 +++ tdc_releases/tdc_v1.4/Channel_200.vhd | 278 ++++ tdc_releases/tdc_v1.4/Encoder_304_Bit.vhd | 428 ++++++ .../tdc_v1.4/FIFO_36x128_OutReg_Counter.vhd | 1094 ++++++++++++++ tdc_releases/tdc_v1.4/LogicAnalyser.vhd | 79 + tdc_releases/tdc_v1.4/ROM4_Encoder.vhd | 262 ++++ tdc_releases/tdc_v1.4/ROM_encoder_3.vhd | 262 ++++ tdc_releases/tdc_v1.4/Readout.vhd | 947 ++++++++++++ tdc_releases/tdc_v1.4/Reference_Channel.vhd | 129 ++ .../tdc_v1.4/Reference_Channel_200.vhd | 393 +++++ tdc_releases/tdc_v1.4/ShiftRegisterSISO.vhd | 54 + tdc_releases/tdc_v1.4/TDC.vhd | 429 ++++++ tdc_releases/tdc_v1.4/bit_sync.vhd | 60 + tdc_releases/tdc_v1.4/fallingEdgeDetect.vhd | 17 + tdc_releases/tdc_v1.4/risingEdgeDetect.vhd | 17 + tdc_releases/tdc_v1.4/tdc_constraints.lpf | 925 ++++++++++++ tdc_releases/tdc_v1.4/trb3_periph.vhd | 795 ++++++++++ tdc_releases/tdc_v1.4/trbnet_constraints.lpf | 46 + tdc_releases/tdc_v1.4/up_counter.vhd | 41 + 23 files changed, 7893 insertions(+) create mode 100644 tdc_releases/tdc_v1.4/Adder_304.ngo create mode 100644 tdc_releases/tdc_v1.4/Adder_304.vhd create mode 100644 tdc_releases/tdc_v1.4/BusHandler.vhd create mode 100644 tdc_releases/tdc_v1.4/Channel.vhd create mode 100644 tdc_releases/tdc_v1.4/Channel_200.vhd create mode 100644 tdc_releases/tdc_v1.4/Encoder_304_Bit.vhd create mode 100644 tdc_releases/tdc_v1.4/FIFO_36x128_OutReg_Counter.vhd create mode 100644 tdc_releases/tdc_v1.4/LogicAnalyser.vhd create mode 100644 tdc_releases/tdc_v1.4/ROM4_Encoder.vhd create mode 100644 tdc_releases/tdc_v1.4/ROM_encoder_3.vhd create mode 100644 tdc_releases/tdc_v1.4/Readout.vhd create mode 100644 tdc_releases/tdc_v1.4/Reference_Channel.vhd create mode 100644 tdc_releases/tdc_v1.4/Reference_Channel_200.vhd create mode 100644 tdc_releases/tdc_v1.4/ShiftRegisterSISO.vhd create mode 100644 tdc_releases/tdc_v1.4/TDC.vhd create mode 100644 tdc_releases/tdc_v1.4/bit_sync.vhd create mode 100644 tdc_releases/tdc_v1.4/fallingEdgeDetect.vhd create mode 100644 tdc_releases/tdc_v1.4/risingEdgeDetect.vhd create mode 100644 tdc_releases/tdc_v1.4/tdc_constraints.lpf create mode 100644 tdc_releases/tdc_v1.4/trb3_periph.vhd create mode 100644 tdc_releases/tdc_v1.4/trbnet_constraints.lpf create mode 100644 tdc_releases/tdc_v1.4/up_counter.vhd diff --git a/tdc_releases/ReleaseNotes.txt b/tdc_releases/ReleaseNotes.txt index 7156eaf..394ab7a 100644 --- a/tdc_releases/ReleaseNotes.txt +++ b/tdc_releases/ReleaseNotes.txt @@ -4,6 +4,8 @@ tdc_v2.0 15.11.2012 Double edge detection for longer than 20 ns is implemented. (Not stable-will be fixed in future releases.) +tdc_v1.4 Limiting data transfer functionality is added + tdc_v1.3 05.03.2013 Encoder efficiency is increased to 100%. Extra bits are encoded in the data (low resolution and no successfull binary conversion, see the diff --git a/tdc_releases/tdc_v1.4/Adder_304.ngo b/tdc_releases/tdc_v1.4/Adder_304.ngo new file mode 100644 index 0000000000000000000000000000000000000000..e7a70baac9b89eb158017cae82cb5f219a06d996 GIT binary patch literal 204115 zcmZ^M2bf#M^}Xps7hvyd*Iwyqy=w#{M7!&?Wgs9MY-Fl_m?El0XbM$y(Skw<2ogZF zppZZm5)u)b2u&dnL>FCj(FG(R0tC?&2=Kq>&c64qc=Px7z46XDb7t`4JJn+DSj#)ktnX8eN zRzL-b@r{O7LStxuB`DF-AM%Udn>KBY7u4`C8jv1$?D0n|ADbVYrb4x@158B5r>WVS zaOGTLKJpthodQu3%wEmSFPKO9mDy-6zX1G738(ym1(aVk<>u#8er=&g{cF@+o?Mx| zy3kKjel4M&puA6%r?}2uSCk*4{Q5Dcz9`!NP1eaH8>~9nDC7eokLLT_>Z5RPhFg6U z=KDqUFmIM94|isY@-R0b%EP=-x4rqOf7sQdKW2v_j(ziC?-f2L4|>F{Za&NjmmPXO z%->MRVcy1~Jj_|&oY$ zxd~T35BxkKhq*h7=F!}Cb*H*{i0;yan}<6)#N0g0Nx0=FVgAl;dy_D)M8&6uKg`)B z=42;f&S7pe=A!xKt~qm2-JWiK66Wmgx;KgF?IxOoJ4sPL%-u(nNBw(?@-Tlt%duxJ z%>8}V$)mc1gn4N0M{ad<;m-bUb#vj)fucI-)1o}gKSY#=d54PfFz0Buy$RHRq^qAm zIF9f+=1sudt2#~|=4IUKCScBqqB=BxT;3@@f%3R|2(LQm#}{?T^JM_}(sLO}Ko z54sJE&!rYZ|E@ZUaqJ$Ur<*RYfO;VGU{?U-Q|La~2uj?WaY{@?5S2d)vnhMB$fEoM zDX0864uGM@WScPJVYi8K9702Nw~6ru6sgdovJMJG=t(JoXHQ58g7cJ=keQ*^M6*#y zni4>>&xuNLXb(M`a82i9=c$yR+Fi!s$_t_q91TM+*WCh9`1X>l0+zojB{1}#!VEqG zy&>yB1Y5EWxbjxaZG{htrxjfQhQA}Kz)>~ywx|Nf$#j0Bc4i%x#1%P8! zs3U;+uL3@Ztc8N;iH zMsRK!URgAP!|U*BvJrH`no>f(4X+_3Wcl#gQUXJ#i)L}q8(vS;frIq0&*xgoN6|AV zZ;xWMx`C(@$I0P-;p<$u(kH8cWI#$_*WMks&M|~zJnI7EuxpM0aCjTGgylGV4iCv@ zQO7LVESwEeowntCg#DSQ6m`xPRp1akJS?ifL3emmRsmPOC#s;+u^Qe;)`3n4%R1of zCbACL^#dUphb!L~;lPn%_RnPm2>^EONqM{5#^B1f z!Y;Z&P{Vr(XUAaIu?Jis z2e#Y-xQ`eIC6zxs>Cj_1 zVGd{98pm*c96rjeaSZ3j;bWu(W}Ys>hs*ZilLUYh{qPC0QpEFkSt&fr%1Y5ErwR$q zkHe?LT}%1=c&-cv75Is$0_Vr!p9?c^5*|LICaOThe=6&QD`(0&U{_vB;L6!j0z=P@ zx|QU$_$c~^iVNT@GkloVHZxi z!v$#YdzDd>rS8kDYz^>Tm1@MTdlh2?Ji#quX`lzfEb~U5~t~@CvF!U)YfnBeQX8Gjyq6EmljDYpQhFkg~Y!17n61aRKYvsyRr({)fFWokbEovzP$QSSk9-^|K!|O`IP#RbOnZf zCM0}*{8Sjm=f`4R)Io|bL=}8~{6?6;C*iMz<$S{YQq~DqzLs@Rh-d#f>o!8!6=V$* z;Mvn;4P^K1%c;D5_(Fkl$H^mm9n%LKwR{X6Hv6U)Sjx^L?TDX!rW`*Ux`CCHTY!2W zY)qA0Kz7c4qh{xDBzn%t(eZKi%T5k0JR7%5QqRo(Thh+Kxtdca?Mt&OX`7>QFcPtC ziK6vSN>d!pq_f|t*(Isq;Tbyv|335E153X>J&uy{#~(U=)Afun}?2l zvSxGWt~)w*4&8Nc+Rnk0o3nNfraau5%1ywbb?mUrMV)Wit>eybWMOKmBu<1Q2juJ= zEPJ{!l|vkkXxkac4zY8%zZ}`#$)RK_V^@N%T-8{W8Me#$l2ke4yZbgSePbw#e@O|aCWfBxrGsjliIcxJv4HxljYsA;1tG1)yRd8k+|3yxy;SNs$V+|Vcd*Jo@e%Nl;CX?Yd`zeubR=e3FW;xEIxNu;Um>K6K+p zxxb{R>LauJMme*4d@21sNB_OU&cLb6v=w&Wdh6v>YEG8hq#U*JDAl||WLbj#Y~-m> zaT%F0z0u%55s6M6Qr)l1anCgB z`HKt&n%W>NMet$0nm}+-H99RP5L^U}u2vQZet{lcivY(7TyBl7(~t;MYo{dwx7H|1 z1SYR8qdXt`!Zk{kp(3lsB!F0~+>{8MSfMQtJb@TpNqUY)5F=l7WEphU*AOd z5i)t?%bG-B;Q!(hAty%uo0JIR{^ycJ2>3iN0qiB8$XMWM#mHxtD8miM865t#E~N+NLUJsDH{N;>ks49_IodbcE12+tcnf$$mk?S@1U)IasuL%>@t zSp+8kOU8>Y9p22!GKlhPmPBCA>t%_+t(OxLfq}17B?7lzY)b^;`F%?uDDr@;829KS z^`a~SuO1=58QpkxGNLa6r+R`<&d-Kr894ELS0d=qW=dQI1b$IbaRF(<&vOovAs@$C zW6lBL9w9pKp&mnF!yaW>2#3l!`=)y!n3a-29><}2&i=KYQsncT{Te+G_350wiaijF z--i%qNR8u+H)qdYv*7jav7S&n7TCC10kwQ@;wk)Kl;C}gmAAkXHE}Ve?)qDT*fc>S=)2t0$HvsJ366pYv+(*q&)^BNMu zfqM>(717)C&}j=wJrKD)a(}D`qCyibiQw__oXMWh<3urMJlj(WUT>1fRggNI zutvKj3E?(x^viG$ME;C^5$%DfGe$p%^+2fW6GGew;x2IX({v96OFOyJO?SUu| zqyH)QK-3$f@AX8G9~tN$BBoAwcsM`W?r|EAtVjQykX7Ny>*zbV9*8<)Jo||G%po9OzXZL z2u?qo?Sar45B3rzT3O6+5=JKNABn~f~vZ!D+}=r-`%Mm2wi<= zp$CH3H}x3LH_5lAdrG0Jt382;!uY?{dP>3T+ZsI(b@fQKw-gn+g~~W1a4d?U``4m` z_-63BW)Fk_-dOH|5cwNoJrMl4Hq!&atZRD0jO&)s%TlrwPL!j+>-0cW*U0Tj38BG1 z`+E?C=ITlhgsQHpNr>+Y|Jc)GxG^04eNXLt!+V9*BZTo+=6fIn;_^rjggxpv#U2PQ z7VA9_Of5tugo~TeOS?S~*)?)&Zy>19#j2+e0&z*E2g2aGu+#&gGxTc!Q%9~b-0zK^ z-{>g?7thW1K(O=|tsV$2p5yC*aL~Bfk`SsotgtsOm{3b{KF z&itb%HhLg9bW*YhLR}}MdmuP;Or!^bL&p|-AUJfCuLpudhcPqTb^v3su$j{cwO z5yHA<-5v;D?ULz%;QP*{9tcM46zzeq8(rBH5d54=d3S{IiG69S2SO)pAMb%M=yquI zKp1q}`g$NZ9nbba@NjXt2ZB3eJ)yyah0*b1Pbu`<^{F0+3jLrbei1lW>S>UE0{DH& zRoT6^V4QvfnDK|2ftd$J{yN}jqF}C08Z--7BSPe8=7YJaV$jS5^M|N`!HAl1RoK8x zfGH_26J-lZ1uwH80?qIJ24)P*@p%IS;>xazo~mQQ8xOwO#{Qhxgup?IMlyQ7#JP~@)&Ddpbdx_BpgruqoF=#*^>F(2bYn= z-kltVn<*9z4EOb~%Lax+{cFp>aM+4I1H+D9X6VuR9Gv5_1`Yc9S0;iZeQC!a;SgNX z@-p){Y?r1D3YeG5C4bz;FzHX6haG=VvX0hGTt3!@wXqeOBGTMA+4zMh%o^Y6b?~-4{w2n24sD zCJF)SvtlNSqnfLjD2Uced71I~+?3zY74*Ozs#zrZZvWA*2A~3#i9-DPf)Nvij_M0m zO%(59fwGB0$M+5SOceLXP|-wbB>a$$k-rfqBu_LXG|2kwO-pqaWK}*8>o5cJPyX{9RoGVyU7|^6UD(;J#C_R(5%)l zQS6pVnkWw8sx=eE9Iv1yhvfa@h4-=e;*BM>!M4aq47D6vydkQ*<#tUyB$t5w`F3n2F+8 zyk0j^9E;bgCW?dmiqAx`>91NQievF=*+g-0Un!a>?&Ft<@eKF~$KvI@iQ?d%k}^?< zQ#0vh#ul&@FQ!ctd;DU@L~#gT%98Edx7ELNP@UgOq;!*Q>#6)p)AG1sp_y0*o zzu@tsK9h(e_(7?~Irz4#u4(x8`zm|6Vq!cxY6!25N%ax}#{K*srY74D5G*%bP^(@f|)B#UcC~ zG2cB`k4OBs{UE{?T;nrQZ1-O*6U8z53u^q%^s})D$LN}(iQ=G_ z^CpVJcXi7|u}gpIm?#d!pR*>42h*R@CJK?AZoCRcm`*Up0+PEZtl#w)#!Y{;ig^DY zi4W^ikrj7YylnBVlslRNv{E6lbf@Kuc3ZY|n+kcUL z@}G-%`1KD)OO`Aj$GfwGuUAlxvUo#!);X-&cJWTj$H$j1+-4j48t1J=6aX~OhW_I~ z^QQ{ktn5MyrV91VA%t{0ZL^%-F_``=S-ryew##-Q(`Iv%^!M_mJ1rxZX1-l_)OLkm zaMf{O-z-# zI$=XmTR6ih6}3%#k-HhOS`e8MzLl|s3&y6Z?{;ly%Fo~|%0A}6qHfWc+vEr1P zvUJv&PESOq;y&wgx2`F#XPxghX!~<=(y438tXW67rEKH3h}xy*+g>M{4rH6Uw_D0K z_0+ag%8t#Fq667+{--0f{n;?<6tXQHYdVna&-yN88$aZCO4)%>Ze3IU%zWJ`HP5!; zld3J8XB%JgInb2xGv7@*kUc^laUpwjJ?qvr6|R|gcOBuBLo?qf+t7q<#FJSYvR%Bh zWFwPyn4gL{kR8*Pol^7cE_<5_P3^AsczdyFLv|-V*m4lt=?n7?WJmtbZYf*%*O*hv z?y@U#4rIsS8@~hD{d0EQf$aV{#%<9yK3KO)&9zG{4LgwC;=XPv+xoOy%8t#lyd$(D zI5+J;cAU3#>#}{^SUIKaF4H#_*stx_tmziAjX$X9=wTxL z3ER?#3wEjTDdEg&+=eEmVl(rxwgcIr*AH8`MSBR|n|Dgt*6SNol(NIDpQ*9V_NVRG zFk$!NGYz|{aXZYnxRBjHcSoF3_RjK3+JWrI|0UxFDPxBgDhHc8<t5nnQMCyXu0KV^EQgP*pz2Oo47%lmCCg455!;pn-1;JRe{J1%%h~oV5ZWn!2lWpb6iiHx9o#(w6>_-XUe}F%#I}7z z)N99aFz>cy`?HEDH|5XF>m6(g89b0j0otRNiwF0O*{#z%%7c4y)WOl~$%Cn~&Cxr@ zgNIQ@+et%U@DT29l%$uB2ainK9KB>bczR(fhj}%F*_xfh?Zxp)yCmHO%>1R(9#Q(G zf2uNy#?Q*xGMITr*UrI|bJ!`AMC0Yg6o(HS4F1Mv=g{0GmaRjm3spM@GcU8%<{>^rFJ`B6qHWLlh>UKex@>Ivpp@By&JBK(tRJ3z2^NGBjL*vbwor9Ur zCG8wcdBt{b9vZ*QjwV&o|Ac?4;5a(AZ$rxQfS{XyD%w|=%3=n`p#Jrj{F_7*AJ}oh zB$~mub5kWTb9V48yVgm#^lsbcVD_gmJBKVL>~ zbsSRx`|oQxENog*at&Y z7N5)QZ)Tjru<^~ZlZ8Y2_h&eSuNU;c?Rd|}obBA2=|POXq(IsEkbaS}Yr=7@zY}w^ zG(P%2pd1gK@%aerCyvSZo^1a&PCJ;s*Z*bRDNHu{S8&}Wqx|dFY!=5b|C${qOTqA~ zyq)Ev(TCqVQE6CkqdL zmv*wS@lQ!73!|wp$G>qHwV!JSk@|N&>=u~M=D(xuNMYkWRVRyP zpKdu>nEaT}$-?A%*~!8v{S=97hEXp&9^ezM{w9^x{Wk`qe&l9}e63-V5wc=nz;<8^ zm#qG;ZKL?BWXb-4by`lAEF73o zak6M=Zqd%-13(*1}x=dDaHe{N_KVuEKa-a5;;3#lepj=_SQks^Yh^IG+t%6L+!*#?>u5%jcvMDo&Qj>zo|UNdvbl zo5V?I;O3l@g;958oGh$((Qy}t`vLt14SEPy!~^%2ox%vlJuxQ>lj{*Di=E_T*8?J- zPTM3diwB;hobLJw*!Wz-$-<~lohaj!H1KxUVbN?W>|_zgS87fc9=ug>vM}m{ww=Xk zW#HdAJIkk))7&hPA0=#Z9K&D;UU60j!5NP8;RVkW0%F*dT^7XoyBD8!67FWIC&5DD~Cnl4N6WH9t>ujEZI0X zQg^cC&|oO#WMOhR;$>T+7blEHfCX+F3r!oSAU4M9$CKIh11Kl;<%F~D`uYKm`srw+&SlvaDE5BlZA=P9Op6JdFHjXDHfS>)GkWb&BYiEw#brg z#u5|wUDfh;LF(%z99gX}TdVPn-2ynnTd>kGgW_ThcU%CcD{CYv02msm3IMKKmH=Sr%(?(z*HA096{Si1@&+{(@To=QnG5$pvr{v-(5;aldD65EUg5Vtoam1Bk`X zEMHobfNyL01OP+V&I$m&tx*;LLb{^g1#s@MRucikIWTymG>i(Y+!hMhwQ52DaAl>O z01%CD!vcUA(?mFM+ZFs@Qj{ROf?wAJK&}M8><9o6{G*VJ;XE09Kv;$^7Y82~@xVba z_)6Wa1m}RDe*C3lO5O)Q%(w;ct;^tN5dol)F6Heph-X8=|E2|iIzKN80OR`Om;m7I zC&CQeW(GS=Q396#M+pG&c)uh7azFTnAkiU45gdwv1H(so<`u=K5t z0AT6AvI2mmZ{`I6OJ7R}0EWF@6#z{Ci?oCCPl!5k8VemK>KtDHOP@-+b>PM=_(E6! zu;az90ATvdDFL94W;nhz`~U15`N?qIzYsepS^|-ED05k$DxCjM9|s$HzWd^ z_Z2}N$L&jKzm_ZmoA)Y91Qzb&lL$QBGbRz(93sFD^Eh_r(ALs-9PdIq)j(s= zo6rtPiC};|T9ybESyB`Lo|}Z?1USLK9ZP6&L?Y;l1r>qd=oZ>i2?P(lLb0YqVDh4v zM9^JZWh6pD4L;IShKg)al11Rv<}y0COA1Y9MHw6@Ls57!bs;j22Wg>sEs4O12^lXe zX%QOF%Q7%|U8%w|sE}WpjD;hDb?GP?4;E!Lh(#bG5mYlXCJ@}Qgl3f`0=EWa#ke5~ z&B)0zFj-#;PYpuc>V(#>$TAqH)BO^GTkFa2;A@p3RTX7$7Zh42DG{ zFWljT*6N5N6L4z{OCpH-Ds_p#oYiD_@Zsaoid|U-2Ckfv2;5qsAQ1{`@IL7%iGug% zL=nLUECUPQsYwJe{AWiZu=#FL&lo<-82ocfl%W!@M?@ZLKUr@Q;Ow)wrLx|V5yTCd z)hfy|@chM$L}1M;F^Ry3SL+gi=PxxSf|x#Ek_dcgDv4k?-BXbW6?r)C0%Lp&)o4is zZapJJ{GmzfInfdP4AOc!E>&>rF%foN7}CSn%R^&_$|r0H7m;Sy~^Jj0^wWEJ4+IQ$^TFi zL2vy%DiP|@;6G{-p(53^1mM+eErIZT(RFQ!U|`%7lL&^vEk23B(Z7}@0=I6I5#;-+ z8xpb%IT5@oDG?G~o09Yy_$+i=rBQ_u48EVDFD(c>HKx5s?VIx&(!$&a-1U^IDh3 zBtkv}|K1S@B6?Xy05~~Y#im3MieD*-Ky_h7A~5G-8B(0Ut@B&53=Ay9B?7n3%Sr^{ zIVL6$+(uZZl_Y|W_-R)lxR0{Vu1W+Jo-2C-=XC2A(slfd#UVf$yh>B?2#U1&Lr}{EYyob5JoncL1E^t&EzL?~dv+adx%1beI@}s;&V9)k3f#7+iwV(8y&)3VPTVsgw z{v>iDh+hV*9b^QtprRF*p7NEz(yCO!=EXUQz``Xms8~bM+D1kLPd58@i8?BKeg%Kp z$C|7=#PTuR*;@MNnW-@0S1?OI+q4lFx-cwNaBopTB5-f3nnch^Tgc$z*EcIF!-TtN zYcmo#VZxg`7TxIxgdFbM&8^3FW&tMZ^zD&%iaG@5;spPcb%^EIb8b$FJUJb_+UEj@ z*B+FeGQ+6}6Mp)3cWZJ8%<1V{*6=DYH>YpcmY2YcqrTnJUIKGo`gTov3C!i`+ok3u zF#D!&S=>wTCm{RcWv_x`7`MCxPb)hr>LJ*u#aS=T z{w>LS3HEPWpO@g^Zd>#c*f0B*5dNLrj6WLMw@unhaF1`(@e&-7t&?7Y9pAd;B{;Z? z8eW3Ce9MA|m}Et);w3m%3u|72Jzo^}672axZ`64Ldf!$huYw(ng}ns#$5wtX!Liz+ z>mlZH<3G%K2>xzkpLoh+4=ep;i6af3qXRc@dup1?V_}Pom*9wOp7IiiVgKqin^r7aGr@g6N%(h0;snAz<4A8K+#L(* z9sy4V@7pZlC0G%ydI=t(3u0b^#~b}Z^j)KP_I=+xpNHVt+_YWQL{xKDW*{nfz-qXvd87;AVL?wz_JHu|fQ51Aw!oCj;( z%JfGnABr0o-aQ`(8yF7T0~G_q!MWdWU^oQ#mkbPt?Y@G6;Zaaac^Q3@9y3{u@o{g? zE1AzBxF_Rf^fw&u=^7XgL9K0IxOeVO7#Mcv?xum^u>B)uVA#=r)C~-W?XIeU;T?`1 zV|qp?HzS_f*k`kG{-$)_on?cB9gWny40q_?i(W!sE!=4t7#^U1_Zb+j?QdBF!+zdD z#CP|%Nsgy@Am_Tn5vXg$$UOs27Iw;H;dzfsV4OW4p32lQsYf#IuhKOzyd&I{ zGcX*3zbXU6F}Sg9V0i3`msXt4)|VGIrVJX6&h>Qz!=B!dFfiPw*T)PDVld+fL)>s+ z`BT!X(AR>0@p+kXw(MHV!0^bqE@EIfYS&c_3`gzSvVq|~_)F2ia6JFqF)-ZM*AVgD z9d4Xsb4}jB@R%xR4Gc&6&uK5CKh?fz$;)sve`yg z!y&l3VPLou{#Y|G+;N-w4Gc!XAHoKLBk+fcfni6lDj68=gWngtOoT&lmB9f1woBjd zG6oGBUCJ34cJy~$1H-|&qG@2*pDWu2hDX7bDFefvUXd^`?CJMSo+6-^COs1RQ4h?o zeO^X?>-;wn1H+E~HfCTrpuepf7~ZXZQ#CL=+Ag;Y42SyivVqZ77Yz)D?Xs+w(buPt zd}mi2)1Npm<_!#Y&-ayqLD+tk_7eL0=D+F~7!J;*Ed#>={a((%pqWeJ27>*(q+wt< zY8OWh4105N&A{-Gx~O7ccu1X}@iO`g`h|jlVRtSp85j=1MPUQOegJq%!prC@yr1N} zjQ+BC&TnA!*bN&P9v^z1UC&eXG5t;S(+dU-hv0N&U^r|Wrwj~2a9YMHqMS7+%Yg5wu4#*hIf&$!BMtsql7_%_7993 z2zK+phJoR5iq}xxV=FgvK+T}xaQ>)bV0d`!m+>-VtVtCN4Ewo%$-r=IeiSw^+y(pl z4Gc$mdCtJFrzvG%c;M{UH832vecJ|xqqA?yz;F!qs(P6Sx3hQMz_8W(Bn%A4U?0O^ z(^u1b#|#>d=$>T*!~X0QF)$pRJuL%+o*Qa9J-2W<{boJ%lHV@5a5?>A9dLiCr9AyS z-8Y=F3pl?caA3kQ4?f03(q|yR%s4#nWe5-KQL%AqlYS%*>=P9LSvBMEBJGM1-m#qz zSqAo$rjsv$-Qz+=KhX#NuOk5Z9X+rtD**agKd`eU0QyxtkZ^1yTjZZ>f_@ec zEQ-1SW@`qv?FsPoQVN zZiy0P`j9(KYvFP%bR7Jh=qH{+6THe28oc}y{DW)Y3(^9?o4vt8Lm~*q=OR3KGcNcGpD4nUDSs)0fg^J8 zoU$wfM}Hzs#<4GWMoyMNP=7A^k7wru&uYptaP((wiBM37K8r|%iu}|s0eE$KMIboN z27la;2;y~WO(KZ$VNr>|iL{It-s24(+>&Jw<^7}+m<==JPQhD9U$&tl2l}K4p8rV3 zYd%a~UKM3<1P<;WlL(yHJ0}r1v5$-nPgG16WEmK^mkbZjh}e zwu?ywo^P9x2;#nFOCUI=2Dd3mgzOpWbOnMU3o8P^aW}ZNUm|cT7MBQuv3W-#Fz1I^ ziNLJ|mPBCSW_gLgt@%}nP*8{dqXdGAzZaDNL}Oivz?`{tiNNG}35lR5CQ=fCqwec4 zG?ejO9Z}KO^LvZSviTo!lAZA5W|^%i6HQAikk6~Zs5bNTZBIp6I>zgBI7s# z4ZRl?2wGZ?@{SL9BRAMrlL+GO4@(4|4^$+A-rAre5qLf$DG_+SeqJK*e4U6yV9&Zm ziNN!<>JmY3t)>KmnK!}Jn-YPAYo;Uu3spuU@M~om47>;&T%{z-z>5{7r#NE=y21MLzjQ6_(t(Yi6uW6}3TUb1X`7%T8v?v4n{!@?u zMDLXZ!naEwge3yizoQaC<8KpS2Zukn6L?29h3lKZTQWL)tM*Un1E$vo-YCm@DC~h3 z{Q|+adjhXDB|`QLz1IEdDzYuU;kvFSRdDNuutX4yYoiiDn19uh2)d%2mI!$<^hQh~ zROEuH0Qk1+qP#@VTNigE0w*rCBmzf&S(gaRIX@v0IPr^=L~wL^O_o6fe=04;cYOjs zFA32&H9quukI7UdUl2tm;P}~Lf#3ulI8%lTr~SYg4Os?0oaU1V%*hep>|2<46ZlD1 zBJlH+vP3XcPL4?g_8jXM2%poBZ%YLBoG4>4hA3y7vJAX9E+-M#oROa5G#@y+BFn($ zBa#wEd>s&%Q6@Ysf_Qd>Y@kB+DTB%aug18@!y82))8Bo})O<;(2ku zxFB)}4#T5ew+d>c-(Pa_PC-0Z?jHzy2|QNr_xrsBo*no1<-7zQ9rwFa>YW$Oc@f9{ z8E#yh#_@=}e}-$NL*R*W|Ma%E4So>(V$?&hwZ5_!=bF~9dkJ=9gQl0@s-~yB1Y+91 zLBdOL4A-lA2|P0IUq9w0xZl=`cnOZ7&+-x+Dsh2ohl|ZnKQSgfb{cC5v1be-xL|d%h0gQ#**=I4{E3zgF5yu;*)ayaao`X3I;k=WE2h1iHL`jfR)tA6S|d zFF}I7H)9@LzYFlMu7}{onEPHRc?dRkrM4I6NUi1-%wvV}+BA>H$m&r~Rs4Q#zY2Q^ z?xt08UV?|hss%5>AzaPxCAc?MRbGOBb88wJN6c6DMv7kx=wCVGsY$;{@NvXT=oqHF z1plJ-an(z}@xD&cOR%*cmAwT2H1(0?B@mImj?YW**!eK;CHMgIf;WcT#QQCeK)@x&N+t33mLwxR>DIirXQ3 zAJ=nY+TMuhR~p_8d#chu^uJs25;%_ZwM$-tWA%>m670u21uubN)%SMJOK?cuN_YtV zg}wg*ZxF{9@D6n`DZbMo^c8co^1PvW!uu~RdlVCT7R|phUWOa_Rm4j~c(=WzXkhrz zcd2DyxEuf3HZZX4;=G5@^IrNd@fjFCykFQcFue0#D~JSDil&@yP)oeR?j2A$bo z@Q&7Te(ACQq^4J+PjBai4GixT|4exqcISe)f#7(aAN4XkDXIVbnt|ck&Z`(0437R& zx(0?FJvC=wIG`uD4GdqXoRTpx9MF?f28PGfi4iZuYftx|lrS*7558pzHQdR@3=(!U zTQ@L#9z3yXVEF8Hf@NUXofFCihQoHe&%m&w#}^F@hwZq$f#DiM+Yu!L!&V;|HZUB6BP#}m_nyNG28R7{ry@9a3*(a<>%)~n!_hf3V_?|R zL%Rls2gr}x28IX7tKL2xg8_Zd8w>#6DtoKqHkKRuhTjqEKhWou@H=n)2N^2k7Xtea zse3j2a$kSCX<)bqew;Ee+ym)^f#Lof|A9q=hR51L zmVrU9^}S)T0LP;JJ6;Jd?%aO>5#Qb2_*KFF1M&ujgY%=Tf#IQ+Y8e>b4fanP7!FP< zX<&F5>{IeGeCN@>U(~?Bw!SwaUWN@=9ybsi&;4p%hTl8v-?w65xUcsO8yF73-pase zcl-v1L$G(jz_8VO4DW|6%geB2kA#8XVVF!A7gX+Q6_siH?Ecxb2)YFzo5hEd#@ciPug3;4rbZH*8}( z@wb0z&QsYK&qwLs-tT4fMd*%E1H%E`DQ;jmpgT1T3fih*H&wul-Sj=^Rn1H+zf9yTx>(arn@1~KS++29Wk zsaFhPeO%Wnj1u=El4XKf&r3FW5MJ&0oOjpGJJwT3|qaC-@tGTHYyny-bXgf85s5_tPBjtdQR8CaCAmf28KNyZ5tTw(~+iu;TQyo z`0jAynH>FA(aZ3xnf~Fbfnlp>*9{CuXCz@@I6AXq28LrDDjOJ%!EnUDa706vf#DGn z%o`Yvf#owWh-lwS4FiMY#9+-!@U+nWSuF#@rVVur3_BXg8W;}SP};z7sAn2X)6aHi zB@G%5+swFu;WNy0-gfx-@sdfw0f-u^V##v`XGk&qu`Ug?2rWd@_gtR;+W)xy7do?G z`i5In;fh-ye%Rt8sqoVk$`u#UFVoZORs6a2QlKQHKX=}3SIRtYp_Z+;rwV5)!dKjS z2l{*Z<76?x)XwymiUhB;XosD*-hTO_-IgugY01unJ`+YI3+Wf?=}$ND=OX<14E;qY zH8^l18eDPVfd?LR%<>8ReD8a#K*$R8_h!^|Vz*s4+vT8Rk3al4$M_kCwe12+cLLu# z!>8|ANAJ?E>(gI?Mf7i#eW{fv^xxA~cuWJ7<%NS*TuJqfB(PG@N^1JEWi0RW_`eU{ zhv*g6^oKj-?NlvP$Fx;+xYg`y5>wR?sHQ)fp~^z1WhI6%s-ZX{!T(SWF;qk6mL>Km zMMaJLj%v{VRz#5{$!RNSyJp_ls;zU&fy9w{PegjnQ99}>cvWsn&E_EHG*O@}F?0#7 z$kEd@27?Nn>XYR#D%8kt3lhWdP$O4{ZEQtyrO|-)o@5V(a-mw(#W02{wks6f_14($ zePUOpNc(zSSpmT(`J9u4IV2yYu{#VvTu$npOgOj zwUsQAud1fMkoo_}Pb3@kKgcm;SEjhXRK!@-f6$oJf6(aDhEb_E2VW?XY&EymRrb}p z4~Bpm+Lq?19oD59sq<+|t0BD9p@trB(?$s1bfL6MTU8BFXerl7(PrrhLX_5N%j@Yu zYUr5+Z9Y8*hf>l!o7HoT)X?*!d9I~rcTq~37vg$eAEh1IDtcBQrKEW&s^3welr%4w z^c!kw=vC6Zs`PtPl#=GPjD8_X4YmCAS5v>@MJZ|CNa>e})zDj{d9$uxFr<_;|BUE& zLn$TAzl!?pNHz3MjJ9d|6;Mh^)6VOcTGi0MN%L+;ziUh>Y2Hifxl?NB1Jb--({GJa znx-wRU-+k#G#^&v^bKjgnWkqOQA(O`(|X>J z3asFxzZ!bt5v5t$qI%X5r7hY@ddd-{q**1bCoxesop;7Nw-|<@K~P6<9w)e|7X!E=ozW zK~~T7Qh^zyncmWK$tWdFUtCWUqm(rL6+Nv?1qPC|`SqMKN=Y+V((~90d+DLqAv zQql}%^prN5$3~h!Q_p8p0V_&>b@ittD6P?!(=+f?V0M`PYU}BDlon`9=vji4l4i83 zC+|_3qRrBi{U{|(xU6UTsldjh+1RHi6H-c=O|p8PpbC7SG~a9Kd4-hbX^ZPgg(?ss z%?}!Snj)p78H?&^jg*pRyrkzes=!>*%vE}(C8ZVGGI~a&3d|?Xysn->NhxWfDLs8s z1vVqig1VlNNhxVIkLcN$ls0KA>ZzENl4eUwPxhpgG+X8MTu>EQNSatj&rqe5G>ejY z;;0JHc|EXoO;0qXlr)RudX_1rq*+qY6IoRtPMWx1&rzk6G)r@OPOA!RAEv+BdO|Cu zq}d^(r^u?nPNdnfsi)LZN}8QxdOj_sq)C+Zgj^NaB|)1{&&H*cG|P&5=CKOwMw;EG z>AAd=l4kd`o*}FPNz&}mP(1Nh1@@-go>4tnm{O`?pQH-xTcTrYU_aXSt?BpmD5V;f zhxI#ulu`|;f_~pm1%5;|?BCVz9#Tr019JL(K@~WNGzYfzTZojB=HP^WyO2`S98%Tq zBT|~8&C>58Qc9Xb%lb`76*!zUhx_!qla!L?h^&5ZQU#78&5`WG&xJZR7)voewx?sy{f>^NOML zY0gaQmu*$xtZDRDO}|A;DQV7*>$hwvB~8AfUyxRTb4hcqU%%N)DQSL@)9(VSz$i?o;F1JwKK=SNrKGvE zs9$wffy+p987c6ZGo^Lf^7^%G75Gbp{_5!0q$wrMwMiAgi`6P{y+wbu6u(qWDQRwq z>zB7FCC!Z$6~If`DsU5NZu0BbxGAmCmea3rtH3R!xkc%>$tfkxtr`9PxeDA)n%kQC z-E&GwQ;q32<0);^R#yD(I;EufdqltOPAO^bEb2GiRp1|_`NuT<{ye3mxjU`jomYW- zeDqgCzc)`QY3@zxxA9fre$w1mQvtlKPbq002tdD^EZ zL{LhaXR>-SgbF-InrB;jLItIH+TtpJ$rLKkB+UyAJ+FgO(!3belQAeI%}XUceM1Fa zAUzEjrKEW)q5_y}LTQt> zqMolpDQVue6wg(mlr-<;^|Tokc$YNoj-Km6DQW(l)U#t$;C-s;y_yPq5JsIJkmiH9 zo=Zb1Y5r5ubGuZaLz<3X&)=bxG#};kj2{*FBusy`^=uzXN%Lt&&lpmH&q?!HQ_mKn zlr&$&^h72~Nz*Os`9~`773IG4DV}>oDb?_GL{Dg(x1^Y?U*V2>UD9zIr*Aw4VaF8?u4LvE3Qqs(f>S=tGl4e#(PvKL+ z0BHhBPcWpkLR&^p0aU>dX{@da4#yC|VbTnz^n^hb93jo@x(bf^z>Sh-G@^o-f=FqT zwxXVXNGWN;mY&o|DQPy!>q(C)xCv=C?&v9*l#=FqNj*hU1vjOdzF*UmDk&w+58`@4 zC8eZ^RP@A66&xqcxL;4mq?9xhIX#6_1t-JwS6fftq?9!CGJ2M%3PwpYzp3YyQc9Wy zF+Hc0QqpWz*7H(TaEkm zfTc7`TU1Y?Rl&ui*`}s=?l7gKSrS$}371mRY+KONc2#gGY2sZK+>ZNUyAu7C($jub za0k+C-&Q>3mr~N~n9#G2DJ9KLRTZQI3bmCWO~TTXj47?tme&)ERd5+;miZJ}+)+A4}CO;bvmy`p;JHKnB4yQC*wtKhz* z*;gr^|4k`r_RHvL+$xyz(_c+Jg_}~+?4Qz;zE$u5()_5dCxuf=ngb*H`vR1b=AfdU zWv+sU#AutQXQ5L{nsi>zWLLpMN%P~5p0iFVX%0*3IqfQVnni!L^b~wbN%NDq;yLju znDfzJ4LxU`(kyLJJvE!m%JbSvPpjx6@Qt4Qqr7nDgG(}rKGtaulS1uDtIAj z3LO=^D2iUWh%^@^6@TME1ur4w;+o>GB2Y@2OXG^ah(IZ6epONYe)$qHF;!j1W;P0u1Qd9BAB`BpDu8Qdo zOW>&yZDqxay--S;t0Q`C7)nX=r=kk}xdk7}q$$(?*YMH%8q!>o)(hCG;I%&btD$(w zU`k1IT~YJVbMW87qO{JiCb!!#;Yn1-#s^HBj=x!#>%{jgJ zmkQoWnp@h67gVB@G`A)6N=cNG=Ju-MwVxh;De-j zQ0a9eDXq|!(aUA3;KQV;cUAC_82o#LG>@e8@}w&G7-=4@>t&fKCC%dz#mfOx+N7w;PcbyubSfJf+;1<3vtCO z0aHpEdQQYE2dm&qq61zV(fy{VU9 zrj#^q#1yZJOetyJEbCR2Rq&q)+I)HmWlBl&ucG2rnpN-}(!4WG@dC`0lBS(jykN5m z{+l%KHuP%ElxAs*>h+&h@B`A&b0S_Ino`pIC#-nUYD!7-VL`7Yt%4tsrqk7HPg7c= zEv0zjX%+mGG@rEf+SZhk=Cg$2WveMA&F59U%r&K?=~{}{xTdsDTVC-}+$u=ViGuW; zh?nlBlr;35h}Z2_!EZ?ObxSY&O(|) z^jmd2Ezp+GE7mKEo)cMtre3a| zQqov4WrgynGenwDSy{s!sC)F{)v# zpsevGauZa;cvo5Y1)kCpZ7IcTjVWs$X(roxT`x*WGe4nM0;7~P(W+hrj8f8UX6Y5l zD6P|$*QxZQIp--<(Mk#5w%<47Alocb*RxQ0s8KtCI7}qP5QQD!cqL)aclr-B! z^`dH&l4fy9FQ}%hZAr7O(u=ZDN}6~^Sxc+%Xgfds)znMDQA(QaQ+h!+W$j3s9qM{f zI7$n&C6u+i2;K57ZB@M(9Hpe$-_lFWQQD@hte2ou)`6rs(5IKNqm(oUW%Yt}$~uHJ z2erAMbEMMC>rq;vEu)v; zQ`XU>$#nI~iIkG&n3P`fPg%#2=GeMkB#=_l93RmO1X9|ht*93wq?9ySOD`};DQQm1 z>m>=5bqZ-t?&#$RDJ9LRNxd$kvVJm+{;KIU5Gf_i>2baOA*H0rRrGp|$~uEIXZZE{ ziIkG&XF0v%qOyJ-roY;HwM9xvb5=&L>Zq(dY0hry)fy=!%{ei>z9XfiIk&9Wc2w3c z6SVpCs*;qF=Dea_hf-M=kmiDEdJRfSNmEGcbu5*25os=L=rt@U&C(Xt%V{d>Qqo*f z(`#T-N}6AV^{SbalIF64UNKWyza~wws~6p*v_xAxKk!H<0Frj9ztBSrtG1 z)zmAuQc9YeQhJS6W!+4gzt;5{u9TAImWW=2mQvE(TGXq;D(m(bZB%zPjTWk;spggS zw+3=|kmhe4z342Zr1^VNS$FdB>@MQ(tm!3cDNWNB)=L{xN}9VXdKp}0-9wst{CeSB zN=b8XPA{6PtouoGUt6!uOKE|&gkG0dSr3us!KPl5mr~NyV|rC#N=fr@S@9~r%6gPE zkNWhwz{+}pa*t&duL(>k)$n9dS&bGvdWvdzivE9^kL6EO4Ns@_D#XfqmTGvWp?C#i zN~wnDqI&6LWxYU}=WBY|V@gTW4D02UDJ9K|1-)#tvR)?5OI^LtGNmQjQhJePWxYn4 zSKE4dXG%%)dO|PTOetwvRlU$NrKEY&(u+J(TBj|qmy%Z2zew{hpI&^LQqsJg)eBE6 zt4*4BT6$S*N=fr>TrXTrX@|CoUh0}s(!3wl%Un}Rnh#2P@oZ&%NSY6oUO1al(sVL< z(QIXX?5Dq)dMR#7N%KicFV(HA&q(uWT`wd~DQP~B=!Ly0CCwK_y%e~z{u`rhnqCH+ zQqp{x*UOD7>wl#As-u??r<62bC-uVP%KDZx-_-P?(%E~Xamx$-_R@1Q%aiYQN4OS zr7hY@idU|ulr;Te74qXMA>=2Gzo1vXSD``D40Kg!Caw}fGf6Wur9!jH$PFp_tFA(U z2yy|^1QIF~#91^HBu%iYLZNBMg;KOxDm0!)ZoExfS%oG#$jv3qT%QU}W|5n0(pFTV zdF2+M+77MG3hd(zZoSg|<}4ZAqFf z!z#2D`?nQowkoJltO;%*X<}U!S`LU^THg?1v%jx811 zIgH%Sq}e&HLWu%$i4JWQ721XU+l4f{L{(^64%{-*EGwzdu5ILYBh79~g?3LMw>xQe zHIRpgR>`m3ozd$NCfl4j483hh+}w>N3_s;kgGKIHZx%{~zo+Bb{bzNFc=s6zX- zkXs(3js8!ue<{+W@+!1{1Kf{Dvwug04u~Rm0BH_Ls?dQYbToT=4ApRSQ-zMTz#W^TEv7=4*GDPUa9ml1j_)9M0@ZMWPlZloZ%-u6iA5F4 zvbQIZ<|Ha}avUX3Ce6ud6*{GY+^M8Fr9qz^=8~sn>9w1v3jL!Eu10^|-KGE8BRU_2 z?(wV8y%})#HfSrT(0yF;{FAsks7F9p)2w@jbWfA+ z*#v5NwnAG*g`Q*G^Q3#8bT6>(1=77hx+d#hBwdqqFR|_=(!E5wm+PqIl`#F)R-so} z_bTaLB^|y~r9!Wh?lsc2Sl1$5i*#?W?oHCYLAtkMDEU^2wv-C}lXd?h-9Jh9HtXId z-P@#lhjnezy+gWpS@$mK-X-0?tElBYKmFBIq4!z$KIz^k-3P4u59vN2-G{9EkaQoC zuEV;INY^19zD7W4fwqJS;aij{^eO2+A>C)J`;2s-k?wQWeL=dR%6|2q+5-2s)&-ROIuY9ufe)CNVf**)@0pU zq+648YqM@`(ydLpby&9!>F6vp?DL@(Uxv1b8eWfe>yvIh(rv)H4M?{E>87)8I_aj9 zu8(znr0XMHe;&2;w`nV@;s3|leTOS?y#K>L_OTPoIoRPd zTY%*XK&}Af3bI^5$Q6WKVU{Zlxx$bu!g56*R|InOuU+AP3rs4KO8>$Y{)e0ja;Yqr z3b|CsrLkNZ%>TET_bJP^}=K&sr3T1^_2>iA|$oGp0*l-tZyc%jo2C*!5SLD z8rrj-!E;J#d(a)&8alulIzZ1lvYvG^kT&Izz5AKbGqc zx&DwFV5U_D_+he>)PXEF2y%lUH<;xHLvAqSY%Dhfazh|7l;ws(ZYbo2g=m%GI#`O4 z)DbK<0&*iDHL2eWnJImQ2XNTNqmKy`P(U2Q!q*caxVX~6caV+;Oc256PMkedoQ zC(BKPoD*`>^|Z=#H%w-dI)mkALT(1+X0hBX$jyS>Y?hk?x!I6&v78HXF38RG(JJuj zI(2S{q|Rr#`H-6rxdkk@5OND3w}|ByL2eP`7PFiia_|Z}b%~Z%S>lArNK%)w+%m{5 zh1_zMTMoJ9kXylWDR~8kkmCSw+3=+Ah(v~){5HZadt*4RSkJZU^LcKyD|??S$M;$n7Sy%5E!6T9WE# zxjpa`KjikZ++N7-h1@=t+XuOQkUPL~2OxI%E1Us9+Dbhxd7zg947S_miq;A zzd-H?%N>E-5y%~7xucLf3b|u(TIIMICM8Kd!Ez@ccLH)JS?(m{PD1V!%bkMUDaf(E zK21FXxigSEYok@phG24$)blKN9&+a)7h<^(&mX7Aq((7RIc%gl0_1F+;EX<1l~KrRd9va(!O$Yq6Gwjj-A*TPbiq~&0_9FWTaxtuJQ3vxLj zmz(8sLoPSu6fE}zuUk)YXR#sv0O{YnIPAShFn{gYYVxykZZ^K`3-@kAW1W` zoEdUv$hBv=4v=dPxsEK?5po?N*NNpiL#`9#y0Go*;(#RsN$bjT7RYslTsM~M2DxsK z>&|jLAlDsoJz1_NTuQ*J8lGcai`arG^=}-ZV1Z_f!q+t4P&`skQ)X$_PRK2coder zByA+ijfC7t$cSZ*5Rra^9cjNUfG1e1cK&1AWmkedm)*(^63a6Z4Nn6Z%w%7(sI+EsQYjDFF+^~kFYz<2xw-nZ}jICiAtYI0f zVFk;rfZPhmtz@~CkXs2k56gKV=Yia6mRk+E)sS1mdbZX?($*?S+B%k72f1~SThDUq zA-5iK8(3}wIX~q5klSOXRrdH{ zvXivEEVmDG`yjWU<@Q5vKjaRu+(F14gv241I|R8ykPC!pm0xtQ6eDSeS?)084nyt; z%N>Q>Q833??il2bLGC!qoq*hN$OVnGO3(|Fm86|yxl@ok1wTE_a;G788gge??kwca zK<*sNorByt$ej<+Dj^jtMM&BOmb(DC3y{0Wa+e@?5ptJV?lR;qL+)3Wy8^jiA@`e} zR{6~hlbNK2S?((2!jPjM*Mt8dcMWpaS?&hpu0!r7%iVhEcYC8&ms4Mhv_HP9KBGN7NY!ZDq8=q$TQ1ESDL6k|{vc zSy(O$b*xN~#eiLeyz2mj<~s z$f;RQf}8|74a;dDr-57vmeWE`3%QaOTBS6|k`AIS!?vhQ43>OEU5@pvoE4U|L|vY( zp**aiJgh;-)=&X*6<`e&*%~Us8Y;pXDzjW=$W?}16_%?4xhjyW%5v2pR}FG{meWH{ z54kT{&#D`Vx;i218Z1`>ay1}VljUkbt`_8Kvs`V+)rMRhmNP)k0J*wsi|Pho$wAch zSneyxeFeGtELR_L^&!`QkGNQkn6{C{UO&Masyay0OSThZXnAIg4`g;4QBlu z9DpSUQQKH<2;_!9ZYawQh1^ic4P&|CkQ)xU5iBS#CPyrbBK9%guz`49Lwg z&?>V$Fj3KI2p6>V*Y%ytt|?{L!A4#@2A6ZOs*ZSAtaq$29wX4={fncYsJ z_6KNdj}De%M7@`7-(JY1{_KbA%A}Q3Guqh0IYKQ6KZt)^W%j3lsGT1#O*hz+@om zAltr^kO>Bf`cx9V?G$8A>4^HYm9|bp=Cqrr+1ZTxEM(5YPtWP;Z6RpE*^HW&cixe+DmTPoVR<$}pX)VJBzMj&%LOw@PS*4}~4 z9RpF{wNrT)GIza1{dKRood zKOyr+h^QYC+Ij?;M|z@uY@@Bm5tuwg{e*4bQ^-8k67^pedfQ)+`O8Jru^??dgG?+= z)a*A#>gSMoZXxOyZhG5G0!u-n{+n&z-;nv+MAWaG^tM-!dF3bS*D>0PLnf{w>NjTE zdIOm^PNIGrpsjy&uoNTecWnFKLFS#EsQ>lR+ulRw-w08EP}0^1$b2voDaipXDJce% zk4WjFw3Xfrlafdo==Mn&A~1P~lrcVU~Wq-=Eir0kH%79>)RB-+XWnH)MI<+RdPPRQhR6De1SwsIR_g1JIZTM92sRw8{t zw@=CgnJ;2Q%B!WVypYLjCK5Zhk@CY&@&$;LKTdB;h76qBNGTTDN(sT_B9fAAADr7r zaBd?NG|}4%LZ+aDNQL~g1?M$Vp(v4xsA#JQWQv%GRMbgZMdL8}iKJrNr-F>iK&0Y! zdRuYG6!#J-H9}iykV#VzNo}MpHDuIwB1t~l(x_l5LZlLG`$|Bjgq28I5527OORoMoUjz|r>wAD}vOJO24V%rC27E&Vvk&JBnj8Rzf5~(rU zz9uFjHBk`hYqot~`(epWq^2QSr5R+J!Mr)!zUGi=ZY5F+wtXhZvI9iiej;^_(N-78bWsthtC_aCLZ+*eNR|L?b<@F8j7Z(t z_H~C$cRP`K_~>mtAp>VZQZFTK^@2<z(89AATz*5q=8=A8U&evVImDy(AE%W4K@&IsE)RVdSJ2;X&BpD zIOmau1&K5wiQYB>DvZz(X{435MnZ*=ZX%5e(U#o+6U;}mtsM=S(M}?bVOu*EGGk&y z8mFal9Aw6siS(_Dw#LKsZ2;zR+WO84la@#hwzUq(IDAB!z_xZGWF{(!^u3A7?;-QO zgGiJ7v^5zrlcGeLqN1%SE|^S2n##7;37M&3B281!+onNgnt@2u?X)!=GSj_8nh~L` znUI;OAQJmclQhc@OLij7X4^LhGIPMV^i;YaNUP1XwHh+3okUs_pslq!Sc(y8osqWI zL1vwuNI&>!YrP7VB1GDtq^%8**v;wB>`$&tW2MRnXQ}2TTScZDZTF9WvX3MB0%=Z`%Qx z9XcZIw9?j2$n10zX;+B0c0*=2%>8=W@_S*j5@`?HzP*sy6C=_-Exm0YWcHbfwBJQr z2VmMCfO(v@4npRjmPm&zv~?&1lZ!|Jwtc@q<`*TA4x8w0haq#=L8K#o+ByoEBT*t9 zQ_9~`&j>lp06Di2HF9?~Sfk-Fq^tO|bIq4kMSh z*ok!3M_cDquoNNEdA5D$A#>hJq>zW+b^$V>5Ront+PVmti+UnmveDKh$XxOe>2jF1 zel@~Gh;)T*-xbJQaS`daAiXUNncw0>x~ikCtB|>BA<{KBZC!`VwIGphB+=Fl8%#PP z-DKN$6EZjbM7kBDx7~)!Z55FsX4;BCCgLO#dxuB53z<7HBK@wVxBc#h$xI~n4v%yn zGWQ}xdZ47YJ%G#uBat3DXzL+l9{PwBjndX1koiMNq(4ox^=AMk2az7J?RyNF$Am~v z4D_}qka=Pw(o-*O{RNq)VIsv8v=xI)%s`}PcG`Ltg~>~#7i{}pK<0&xNH4AQwwI83 z=_bt*5Qmka=w-QrtsZZxpZ;BGOy7eQzQ2)=Z>-T=cegF#QvNd7QTX zh0MQNqRB^Vf(5=-JflLt{(G<1P zR#C_lbrVf7y0scO&(Nq~UffJu#UWGNNi?Ye+Dd~=YK&;qTG~=WMr|eP((UkGiR$0iDi4sjY6>Y(J zhNhf}Xv(wg(?OajI>q750jl} zsPhcrXG!5AHHGoV56VWtu z(%TwBrlFr`8pUYK2pOY_Xd0Vot1)C6JBg-AfVRHY!BUK9nzHR{3Yn&MqG{%%w>5`M zvk1|&P|{Wl$h0sLjmbeI|9A zZldWDqOGow=?Zg;p0+Grn5;z8jcs3d$aISlO%E--tp{X!n2DyRi?({f)H49{IBoTY zOm8jG^s&%ZpAbwgqOr2=>kFB_N}}m!qPO*fOg{(F^!L-&0Lb)@63svrZ4HFXKoijn za?;kII81(`v9ay5LB?hvnjv<2+YrbM@e<9@2yG36%rFJf3^&r&aL5d|6U_)8ZH-jH zQiNzmvF#fLnNe1vv9sGoL&hFTf`92U%ujr`95hJcJJQl6z9NePlK74^_*u##T~hiC zB>xcjGOu5q>0rSN1$A+qewd(A9V&=1Jc zIh70Ch%7T+(Y`8|t69)_cB2r_i-`3CNLKrxFi(C;z zN`srKT64L8&e;BRnGvbZR@l*w%Xw}g=Y$ZM_MM^7*Idrk$sb{pXNHBGnq+Ih%8)T)3Fm=PSwlOhR8y<3rVnoQ%VMHoVD5tLBa)Mo!CPb#3eNdtcmkx!H_8=mYZ+56vk<0N;SsDT9zW_h(mn;3QG zn5bzpA~N%w1+^13zmdo1-~b{s<@PqCXRh#k)J`R84%Q~Ew9fs^;eD0$6#3Q@C95RtE{*FXL(mjFc^|`DSmZc7nFPv|4Bt~6Ld3^TrBJ#N@*k9r`t4Br6UMfUBYc=s~8!o?e2-(w( z$XKA@8v6J2@QBm1y+ubdT=nVW5%O2dEQNxdPL1mN<>EXlq!Fa%i?+=JGu~gd;82%ySXgplO;jqt=i4EKI5{e zQOFJsMBY3ZJ3E5Q!Vw|c#}Rqs;JZ~hxGZFsr45nSJw3Z7&KU|SgfvGHd2Mv3bT4^L zrBjv`L|(mjqs1I9Q&d8J6GmjXp!xQCF7x|kX+q?0mdtNzaGB2}B>b}E<45t8T6E1VPglywQP zQ+)ZB*UVy-WfCIKPQCIfCzqM&j2)L++7Wr?YG!S9E;G7?G{q2kx^2}~-MP#lk57{o zk*7+PtDd;u(|JYB77;|ATpg?L?hSV~x0crIe)> zk%!N^60e})iztQs+Jnensw{2HUq!+fSjtj~$Us;14?pm=KMM%i#D&O188a^8uO{FN zGi6B-dGPki8P|Btr!gTLI}mwbW<5VY+Q1id3TccZa{rEecSiG?kLiq!WTOp{`?8Z; z{LBiz5LC!UQAF-7G;$FFTb-a)TfuceOCTXZsPpB-JKrHZUM^=W_LSJFj_{2wC5c$Q_O{>lSkv z@yJq#$n9$nHao!OZM~3Rc@ep7{PL?ExV-6;r3#T-7h7%yxV*vkD?Jma=SHM&{QG76 zdNizXp!M-cgA#VO<2 zeFI<vh)4cwxWW5A-0fJqljF( zt3x_|o(x~4ElUd`mlU7=BJt?hBahE2VMMxBMUw)w7X9LGI;Zz$6%!&Cf9I~1cpU9k z3RyXb$VKA{9_mO1d`Y-ZmIg#Fyf%G#;y&786ta>Zkqg$`IJSV-+!m0f4w3V#FYUUQ z%dKW1D|!(*uhF|*Z12FApvPpXLgd_K3woXAHMcm0tl&nZYeT83xw+h|lBEKXb2eUC zoOmw&Ngkg%Cn9G*Ja@V(uenhtYQncO*IZx{vTOvA)0$uIm>8e)*gZf;U0E|CofAf$8^~+U zb%>f}LWrE|p84-QE?x5YEMr9Elv%-H$z0C%iJGMYh@8A+r7m%{HcKl@Jt8ORH(vgd z*PIa$vXl>z-@Cdvyj)I~$7d-mA}7vJmHwMcXH3*A=|SX#2SY11<#H;!uju|PsYIls zd&ar^)frs)K-AQ_5c%E7=Z*Qh2XMgzSrSB!@8qa-jIaHB7?%7PQo@1AZ!>L5w}s0I zK_NA9M2;Jnz9$=P^ui9Zv>|eA=c-<|R=5}hOVDkXqKF)GfA%K+&Iw#dLe!Kjh#Z|^ ze4orz&yHiNGH1zvNoO4L*-5IK0YVmaG8aIq4KTYrR(ck8s%|AY`EsBKwqT*K#PA-P!1)kE23HME2hM zwnyT*!x9oT3kDF`Ye~&n19;7@R$1y1*|W^VZi#!d3x(`Fq<{~RJ^p-Od_NWRf;zI) zBC@+;(U_ZDc2o$d^dPdE{jKRZm*)SZ5|Nh6TM8zQA?>`PW{L}uU7w8Xo_NHyHOP`6 zvP&R1<5#}+)?p!&9f<7Q>DHOfT(&X^nLm!mPE-4R_>oIfRF*bGc0AxHpOwoN4k7bJ z5!vB~SpH31Hdo5hg2?tQRnf#*I=lx1|L9oC8%Cu0;-Im1Uh`{tBtlhvDqd6Xk);)pO;k;j?{Ha7FJ$%zA{(#i{ycFEsUnZh>}Et7=XJQDL^g70h9u7XD@J5#L}bICvn}PnKY|Oj37Iv3$OhvY{{Ax+^a5|P)FZOK=kkw< zQCChLpTvjAue8zPOwbF;iJC-<$a*cb2mhb~E<)!QGK&Y1bw@^Xr*c`!BugbC4fQPL zTwH3SLS}X$vd)})EfeR8B`mTeh^+lp^34pqrW6-4lLL{pqCLM!9Fx_o7xWRAF^04OWX@cv8qGF+`SMIWCYmek$0#3S%kxi4~FM_Nb@alCojLc$lFef&;T;kkeA*uZQ4EsxLNO^7UX?DAm#8(X*_uBdr8 zh{%HGTq*37iok_*WobZUfg4pvHsfo5W)|{}ACbxmYA1i+1}@wyOC2IpHg=iA&l%u? zzd}a5h)iyGWg$O;!G(flsX}D_8})5(sUUEHVIgn35t+}Nxfg#fh6@wRQh~_43#a$v z=OJ)GVecWG&>?03x$Kj7*(L1-$^aEcJ*a%5w7zT!v#phJA?4 zl42a3iOb)dveY6nbBPWwW^s8%CFE}&L}rR4eb=4K%YIoZ5t*_5$PqKRykrvciVKk$ z{usKjE|(YN@p*+HGX1!bzgOWhWDzxg#YSDa?{mzr!{xcSEU~eaRCd7icU+#03VB&x zd;S4#`STry;}JeW;0wQnyyOu5{C{LQLwIj~Rx@#Nd-}|EF^cbt_+Z&|#XoIME z(T2z}Z}i~_yymE|kQbteEPeWU3qI!I3(aL|L1ZcG$nBST&EfL4hr);~`CBQ+IxdGf zM9q*1k=lm&o(|)3s8Y!DK}44LYvVv0mo}d)4T#j-O*+4k%fVV9&-oE4J-%4O&gFpr zqz;kl29>Yy=MMN{c~SGM7m;Zp|1X<(&Aw(?st}pF$KLuFmwjSFo^d0xc$>!$9&*{+ zDoX_-RpkQ<`I!KGalVkJoro-UBAaa~ui3*b%Ope=Z4rEQhRg0cAy3&6S>#l_F$M57 z<(8n3Cu4{#e6;zZ$6R(b$kK|)LhhAij&j*KEMzc($bwA*gZZ-zT!=uHW<(a)Y<2Nh zJ#Ya7Ay0%5sq9jFMP9!4_8wUp5t;J7zJVV@;DQN49uFWgdBFZhOc1!xf-Loj%s+P5 z*5_0ZxIlxD$9#y)_e-ayY?}#O*g=+BMCKi~atwbbs(35AkVid;%;TvXAaDT+A&A;j*zjK7X+xGRK;cbAI5`Xc0Bx!{v!H)&J+{ojud~Csny@7?-65k=Z`j zw(~Qq;tgCv9ttBe>-ZdHgbX*44|>fXK{! ztOeF{Stlgq0Y4%$4GL-b`8-@8MV2~5X6&7O*T!qsqBHtlW%7P6A~URAp1CQP{MgK- z3X$nIzRlF0%jybIbDtZL>8{kv%Foh^>%Fp6ATp_(D)|zxSBH{Y^%6%~ z_{#|RNBg-q36bwpJ8fw|1%V6I2)W0O$bSnhIGR{{#i)?}7$V=*`m=ZqUbDDGmR3am zvn^Y#j$9U#$LH<{BHvzaqT{d1;X*v3=58}0-z>|f9>8lBAwup7Au_(HxBd;6g*>t} zBJ%Z}CV4M#Sx_FII|GP()oP`wFqg`ZsJT;*$iHhY^6%s_MIN6!e29Emab~0vm-!>2 z<_;|)UmQxh>Etq>UC8YoL_WVib7A6~A+JJ~N<=<;a5(QKUh@mDklS2{jBQF@nT|_^ zL6!uOf3@p!ZUmRP{6cPZAo6L`hC^O*nbRbsFOJA3^NrIha+y6UOB*5|&o9@Y6_?o@ zLjD{@&4Fi z;lg4<{^UjE?`OMLd(CRX1<7QoLgd|lO6^c{`HpQFJ%Vj?Bl6DIYc|y5@@-Jm+^9fg zq?Kk(dM@7>g#6Ko$lD`!tsKbZ>#!`75P2)_tE?2j1=U{Jg!I}Gc~iS`gNDn$iI5v& zh`iCfRjdq`FFdleBJz4J&yjsxK3594K7z<=t&T38%q9J5TK3C5U5hLUBF}4H73j`oBrc@Kfyi^&Mz&bQN>R3Y+krsdW7nH5~f zQ^+N5ME+7{X!fkU=IQ^W0+E3l7h5OB{7KdedQ5gZ5qU`6uVG_eGw2X&cPAn8;F|aM z`13nls8qMb2<}I3VQ02qO0$ zSpQ1m@)xr#&4}DHM|bTmmxp3PE(jsg-+Ib1*eP_>9kj~Qh{)ZOCsuC5rlY!AiRaDDMj>ZK5&6@~d=uE- zA*!Duva}#_Vi^@mu2_*g4Y44OoO)ncM^ie$1gh=o68+U8cS_Ce< zENadOB67pNGHVm}=6aPZ4TxO-yv&}&k#?P5$mxDW{&2Y9I)0W87l@Xn4w376Z<*AC z3ZhyqkI!jdM6T_WuXzD3Jr+8r+dfT&$ThTD$c67;R#9>Zj~@6( zN5}*pA{V@U+cEJBJ3T5(Eh6WCuN#!8In5!Y!-L3qqoXeqXI4&@plf$15ji)_%u2yX zp5hZVzjGndb-w2T_VhwjljZUG9YN%rR`s^=*M@Mxdr@<|1Cg^;8P}bof~Y2%h5R;- z$XOj6hwNNBVzRU$a^}K8lPG|i-#LXG7e(ZZd9}B<<#IfovHNJ81(DOU=^rH?o8#O< zjtwJn+EL|D{{E+GtWK6DL^_k!+Y{&Bqk}?@2_kap*;eNjR1lTjB1;1zr~Fm!OycoA zGA!h1KO!e*)c#qL3Zfcelcf%klS-JTcHnY25z^{Jgrq$^~f>_krT(>9lMOn zA$lSE*bzCQc=fLvayi&1WbYUv9bcMpotGv89@mjkdyRWG18A9Z^8=jx?@|v(0;UAMmM2_vIc#wD;^-&4g zBY?;;i=Ik}d$X5cmU={vZa;l7I~WsHPm_?{eTcNLIH*aC`R-9!Y7sfA_xhPns359t z79qQN5IORNx?kc|dDplsm53ZMD!JeYDu}9!OGt|gk;9*B&ws;ZGkJVk2qK5=+cGFS zmtT8C&8`ka4sG)M#-Cg^Q3}~5j>sW5!vTNyGDt%SGUMgg~;BkowWz>n)v8YQp+QR24!(wv8du zGSsm*aR#Wf%F>F+uG{NRoKFQ&m8UZ{KHEeP*=1|$$;3!5YnP=Nk(~!OY?aubrDWMU zgvd^HtJb?rYY|mRg{axuh{%pJbT=bhmhcMMDuBoigCBRS&!xs7OFbgnD~(6)aH;kS z+0utd^W1m06R%~`OtRD>@|$e&N>g~v;!z<@9z?b)nr%ShyiVnir4o^CPv}c0jsv>Np(4$QYg2>jBCVl^i%fj+VZtg&2t4SHVP3E#-fX->nW^qKe zJU8Z5LKZN~(uPP=;W86gEu#AG@2Hzb5!qt2@+{lqM3pR$-^l6mCB zD_rI_&^g_ojs1vh+%?HPg3Fv?S?UmJ>^`#ZTP}0hgfw~)+356JN8%abzrUk4su0=m zier9a+p~H^%|>oSHrQmcG~jC|^7w3|KxF++THUW)X7-7i4V{Sm>YgrAmdi{=StcQ} z-n#8Jh^%{M+ZHFUncgmB{TLz*l?Sv)yxvTT$OW!JfUuM#!CG9$89j@dmra{10LWW5j~Yc|R?sxX)T{T+2ZBO+_OAJdE< zmx{d!ikfu;h^+qRdFQdbX51o6JtDun|F)Br%U5wB4L(HbPYmDsip#%UveY87+KoR~ zB;-r2kaawWtlB_3tvavy+#^dRBCEWwzM8+kRP32v$l5MMR^F?)%g-5#{S}fWL1d)~ zXoGhk>&ENZ=2Zj4-G%I6_vG@dO_oMP78>Q=)Q8J6L`Yo#kpED@kzaq<$Z`$F6*S^&&9<~$m6rT7Lh5vQ`JxT+K(GW&2k<@CKoczILqbH zh%A+e%x`riUFGtKUC6R7MCPmbD!!b{!wOjvMCKhkrlN_KS=tb(XjZ0M;<34(^@7$c6-8w3C1Ksqv=%A0H!5nDvLG^7 znS3N2mwPNimJA~@=bd_ACPv8axGYVG%u%GL`3A4K%O#{Xh{){s2L#e{xl=1k10u7% zxEnvj<@P{A=C@%ZB*yI*nn zqgR&Lqa(ewD*vrNDdsf@IlzgmJzddGI}=Bn_2Gm}PPHI1snSt@RVqlaA8fLW&?Wd; z@o(*PPRDHV|Hju4v;3Kl2YI?)V-hYSLg(qJ{BL~yC(8w@o@mGAaKDhM|HjvUvaCCD za|M^fOtLh{eg99EQB@q@oXa6mA&dDDS$f6FeEGSwIb^9rWT{cP>hSY2xV(yxMZJhD zxwegyKMLWpEV5J~QroE0H{Vl1FXtj;5jP@B?5Kae0GIs&vQ!{aGu&{e8<%~}LKgmS zEc~~Zq}6ApE#tCJNS1I{@vD^N|4*u?#h3C||8Th)Aq&|NnU*^5xsKQDMQ7}OFBn5) z>cEkPzqst-mZcSu#WyTiU6af1tTr7>1tN%4z0u6tz@>#fVwf}|vRJz0J)ODiYM^r} z;csX^-u9wx-Y;SIH@*CiERBdPvgqvyewGcF4H7aXfXKqihLx94K{OqSEcJ*iG_B#B zHe9xM2$}3dWWnJX%Ovhivr?8?L>5SCvoA41+WCac??I$;Qqj{(si2orlBE)nDT~I$ zyK>n&B4j=nB9k}0)i>m_m06Yqk@+XQt@@HnQ%uOb4n*d=lyBWEF8QY}=)IXIj>xHS^dIndknv&>mj1sb9!1qKN$BPVm+mF2B~v(t=1u7t7rUm;6%~w4aJF zB6GWwwkP(d(IRRpOo+@iE?n*{uh}pzWbPm$b81}+i*nh(B})S$bM#oS^$M5uSMLS}a&GSj10l`rs`)fKW#LS)7X_I#tb z)O&@@W=CX(5nXyG#(Xt{kXd7hOn+bZO$lDJiab8ES`nG9!J@C`amhb*K}Q{lATp_X z=9~Q71TIG>)=tbH%cKvlV!LkhniU*EW(gtkeGXT#30&%wvNR&{->=`k;`+qk})65~EH-A$vZ`;6mi9CY4(^rGj3*P?iLde=psCdNY@4 zIw8|L5c#stVMQS>iwA{F7f0laik_y4@u@P%(uT|UkgGs%L;Sle?`6OW_9BvCW}hcF`lGHbghp5qF7WNAX=)AjLniBVTTDdhVgBA;BG zVmDDiFIy=~10o;iTU4+Cm&ryU|MesCkyaT~| zZ=Hy|e_-WezD3eow=5y>f6qUY?qz)*t4jsFT&a+6?1=pRo^?oNE?;|vjK>gp*J>Zm z-=%=dqsr2X$UAw)9pvK^E~_f!>j)wv?|S$9feN@3t4)?>MBY|yT+5%2;4-d4z6v4o zR<2Vobi8KFAxk47Zx-5;#>YHdHde^L1BkqlbL3Y+Uh|1hmU={9zo$#jpJAoPMj>DN z5P5BUbu&L#gv;B?Qj5r||E!bVP(d$?E946gBEyy6cR0l5!gA@X8d``sG6=533Rw}Xhh@OXC1TU_3Z%hG_zP}4|GJ(o9ZLf-Nt^8DX5 zJO0Gwbs|e0BF`mR75teCF25|~O)nzPewQOBKWBi;Hp^0l$TMxW_294gq$?pIZ@3Y8 zTG1wPO(eKXv@8{fJhksi_Qa^W6cO^e6Okw5(b%t4(92TGG6|8v-hRa;E-xsAyk=&ua!9vNR&{m#b5hJ}!^Pg}f3#WZ-hub4R&6=8~lz zk%xwNy6oZds8+~deTY1Gd&>(emxlwg)FSf0-SL%saLGS)K_A7imXDv0_P1O2JaNAt z3W=JRm5AJzrB$AByyijH3tID%3z2)@pGm6DGz777i@^!wQ)@Kja=?F2pNhZa_8DbHxkDX{;3PP z_K*dUJJhwuXXZ6`*hJ0qVMK24*(R2o%k4y#CPZ#)kg?WvF1I>_JQqadRuU+XINJD> zvNRylmt*C(g?UZ>sSCPAXZ?u$`N@sPiN`zt)CH3|L~gN73U%Z)e~O5;pYbAcv&wg( zB$pe_vQ!~*(~)x83|x9+LY{Ub@~5loe))$>{;3Pv&(jJ-Zq(Mi@tVu^DpB*46Olib z82{zhT(0xWG6|91Drb!Rx8l-ToscK(h}@vt6*2Of{8JaSpTQU+*H3(Rxfz!pi>Mj2 zBJzj*&o?CQ_my!WPec&8u2q}jji?~f3YRR+h+Mn4>EiZWE|)-?s2?QMlSiMF6gKW#1Xl;_>>2UXRhf{vG#xs zk&Cjlx;2K^oaPYnP!y31XD78!oC!FUva}#_!H2_AV$4sG$LGN?BIn26ce%&cK3OYj z9yB3x-ZAs)1zdg~5b{6}k#kS2zdM1;iDp?E5a}{xOx?w$BPQg2KO*PY%5359tx4a> z<8!|bk+YYLOnll~8c$2I=goayM9zwws+oAak8{gXg~*vN#$Qg1`LQ}7_qq`|BUA17 z&!`~M=%6eWh@2j)nq?-Jc7u?6oQRxe(6#=T%aLJO!iIhHy4YFW)onMIBWyzY?TDOO z{czpix#XX^pd)#A43Sd|6@y2(9O@A@cUuuTd6~1$OD>1V<8xO8k&~V(W;(g#pE#mx z-(^PR_bbEO`*JzJC)U0*gvg2I3ioAqIFb4rWobm@goS?&D$Z;6jR?6TfJn#8%9&HR zw8|rShaQpN6@FeKas2EpkL2w>M2zu0`axJ)#Gf^0oI=iGFVL zAadNr@qPJwzfyO?)7stpt&ylehhpcn#ad zBG&G6AkyA-Xv^WeW~aE2KgSU{>WOyM4_tP1$|*&+^!zEs` zRYaBsMB2Xbony6#)Y2~GPkuxWUKUC{!)uxpveY4R&>8iIJzO^T3c1mX$bolyuUyAv zGlMKuh#X*ztW3OH__aJfe{>_Ve>d~hg}i1Hlc@Ql0+IceZ?R|N(ij!e>qKPVN!Q*b z9`B7DvP?px_2l@WiL;A_N+CDc5!q+i@!xk+L8QtyA=k$c+57Fbu@){X5m{Oh+3V4} z+>g1e;1TkN2qJsFxws*5w9)BhX+~s^)`mNYqjx!Ze69;2viqBc857SPWsRcdIwK;x zwT+tMR1m3jM98%PL|QHteU=zYrR=iQBeLtTqpRvuL8OxM_*~;dWS3_{+m`0Cggidi zXc5`DRdR&O?kkZ6|m`nbt z3%Yg>L1g=xk0YnJR5|FJ%2f_TnoAwkZs)Qny9cO**D4>M34C*Oyfli-A}&#Lr45no z*5&h!AnK&{OFblanjL6pCd0P(VHB;pAx!i=v zR}dRr1_)cGl7`*WEAk){((k`rTzf9itn&!v7uw)k++pLo{J zqZ2ik>JZtyf4f>6s34L;9-m9Rh-{Wu(RCP?xeatq*S}|GKWo;3Pd*fu=m@z+561w}*`KR%RTT8y>k|^n% z%0+fWHfr&zapD;vvrou{F+?_O9G{$cKZJkkg4SGUMP!4A;Wepz?HMAXCcH-dxS#cN zzV9=U%k=X2Twq4zS1(-45^Lw5x}a;HA3|ikTKN{nSxxl^r&#-ZBO>emb2(!dF5jz! zoEJc(VN+`2T3G6Lep%`fS?55(6h7wF|H$KWt`Cv5zpNQ5!`J>MC~D5tBC^)V$H{6g z;}#)Z9z@nmQTIvIe8u(w-AgVdB5PzbCr5bAzg?o{92X+1-)ncf9hWbOED0jNtZSKG zh0Et2A!j=fskdLA%kFQYex?_4RveMlE^7~;$2-r{nUeRmho9L{{nf zRK1PM#}Qdt5Lr2GqS?XaBfF3@!icOC$YEK`CI8d~-Saa{h^+Y3zK_4+Q%Aj`=JX&U zEA)J|bUCm2&>%|#B6Yh*rhdWYeZP>?{D>^SEjh-Yxzzkq7qp+#bcihXyk^M^yyo4g zsOj_~vTWvX*6v*1amZ4I$TF^SU$937QAdf{eaL7`L$U?2gb((dB7=ZjfuD9oMuV0oXMCOTEcJkkEs`tnv8Q$aj`0V0~TB+0f@S3~jkv!UfNX50loRwVe zvWT_Y{fNw+yh%Hi%N=o9>JXVL`g~Jjd~SCMIm(O3oSDb9w)2|XGO!1Bi)G1zGc$rGhF_xm!$%c*)~=j`iRTTAt6UN5t(&TyK^nL++>wy5+X^DG49!1 zZj1;y+>XdB6HJNkU{n9d_5po#42vN$^L5RGy}YJZA!-h@A~KVydyaBkuJ;N#G=j*C zUDfjw&xSu3WNAiZhKEyHOyV`y`h^@4LS*{JKJ|}Wt}!KKKJ>T$>8?Ij59QJm74iVK z_M{!gn48O0HZI{$@k+2=pR6{K6t^J*$#>aHlBGz~_=*}p2;6QW`L1axr~lF=Wg_{` z#Nn3W0X_c_`TQ3M}<4>ho2=rNkV^?9-1le zYcqH-{@;Erf83hB5Y7s>2R_j+{@Z=I_W$pG4Ts+Gf2?0C3D&RJwh#2>S2mKeQu~R1 z9S(^)@VT1Lu)l_xL_OB8)h?`Gn{2D90n1KOR{K8DucL5}@PD7DU;HyUv?A-*x;WM^ z`>S^JbSno*`9b-KejN+Y8uZ`i>6gvHiot)ZUtSB=uRN*$HUp89q<9^l=+_CesPlRH zH7G9Xv3~s&#QLRvK7yXa=OQUTML*H6;Ab9R16}{qub*{TzZPCw{}r&@B<1H%9VbqG z=J7Q^`#=5K=EwTg;ouP1n@I|ivMv0H{dGDZ>U^I2v7cOz-H*FeSifez`$+|>{eqDXfZ`MV3Vr7B)!QoeKkFBq@FLGcHP$=n6L~(860m=wUl#(R&gU6ly+k>F z{5lfB`ZcY4{(0c?la!w*L8SF_&mhh|Ah1xU&T&nNnI^)rvJ&f)***RSaL*P427C@V-( ze*M(>*R{_)zB<|dr(ar=YH%+L_KytUJqmaGL0Gc z3|L{3ay|Zue%%a+I-jRs?H!^X>(^}q)-UCh5%jI7A|&Ou9u{l)J%C^egh2$5%VK9@}3J(DScCzGh9KU&TnugHN4*-TlnttF7^W_SYY7 zY=0H&>D>ZMMNc=$Z~%M|;ce!W1C6X}|VMgdDBDK9>CoQQtr@zuil zKmB@b!S2UHN2hNErY0$`9iO-#|L}-9pJ#tHSBZLTe7!|qr#&D8_5qVf%G>BC`t?XY z-h7^ZHTC~bzuu$AiC~Avm4RtU%KJ|pCmw(1@x?zaPy0sqmogoCoanuAtpP*{xcyVd ziKm}=d^HZzKGA=yUzuS3@%v13n(oL0LQ9mHK6RY<%R_6>f1l@mG+J0O_>c9AII(^W z3Rj?SiIyZv;{C+(}N#uWkTViYRj^KG84uyk6qp=h zZ{c7j#Wdc!#DDy-<(XYQfvi?%-1$imDKoqd2*(;LTki#(KCm71B|x%bYUEvu3(y$q$Mkd3fjTaiX8gJ^}U z6hmR5={OdA!HA2lzktuZaU(JvH@?9T;{T_`135zsx+3`zuoC(A6`l%GX7&%&^vDAMo{zsqtBuF~bxet+$vQ~a@T5xD zjs?d|$B2R88=i8}b$G&>!#cd_ukIR`p zLsxl?DqqW6oMN4J5ctaLUGh~>$>;GVUnNa^KFZg*%_?0-Px-wsh7AVac|I3i?LF?V zqv8%-BV#IETekk$6~m(78<}v?)gi&>@g`r^`Pf1E8kJV*dN(p>4+aeZ->60xT^&8{ zui{#Vu1l2rueHTvtV?Kyg6|TS{g>IvoM$P@QshU=<+A{Jl^OsqI^EeSG-!KYxuTve!;L) zz!$G`(G~ExzqG7F*Huj_T@&9v0xxvR8wS3K1unXZJnk=cw=+u{?Z3Lj_&na|>X_s6 zk*=Ab(v{u$=^Yq$2KZ){xa6y=c)amOSBENxuDdE#x?XE)VSWC1Ciw2EanV)caep1r z@4ujYIf0ew8#C`)~W0Ms7lwq>YClCs~mjy$6R!Ek8wUv>UiMJ ziPoIdUk@txU*@v+U&e^D!S|rs{;P+#{nh1fj>&XAQmV>V(>%I~>^b0jq}(N6Ji zmBO$K!1tWn{!6}J!&MvMYqeZ7k={Qal{hc~*|U0AItN!McK{_Bf3Zdr~I7lCiF+x}~S z$Nlwl{Q*p->&=8JU+qS`F%QEo2H%@WmwcTV<@0!xFLsAnYfj47vPPAzilOhGh!LZ~ z_ZGP58su?*{g|>eSqJG_QLfUpv{hH@dGr$St*CU-6)mMn@E>pT^+N@pk94hUQ0Y4D zpv4bj*ckAw%)00rBAz$A(e-_kL)ZIJm995;O-x}}41Djq?Y~Yk_&na|`mUPKNBK(E zsdP;pR5u&LE(KpY?UJuy9@p_(!AZK-7pQdApELd))HN1->q}j9o$B%9#MiZse0^A@ z(lxE}5UUL@1K)?WF1jv^@p-(d;|`I3%GaixO4k!b&smQX9CvG2yVON0f+mws0u^#u=r%8vdAC&vTy~(C77s489pEN{V&a`I?hki54BAMUz5+JjuSlY zuaCB*S1*uV=?R+@a=7M(RGE#{k5se zq3bW@zOZ9#_E{J<34DLK?F-pm4y?Jn>93Cp9J>Bd?h9|(b$=4WD#7=U+rDsO1E0qm zUF^>H)|^(~`|}M|9S44M>`;uj7XKb~spB;s_t!=PPe=#pI;dKuYtJQ1&&Qa_;6JF& zMb{*c`)j?(Kj}K8Nu{gboCj`3UDtsh3S4wu8zngW$D2B?6Zt1yt(E)2iyz8gf@i!Q z{H@*gg_8xJH@es_7FevLt8Gq|uWO5{9>9njz~3&*Rk|M7bf@+C_Kn~_GUKA_#wef1n|!@r!{?)X z;m2!=eRQAfv({;=!0(T^=&JI#zgCqvbQL94y2khGeiMe>1pXqo{nu2F`|I75Lze+6 zT@Q_W_d*Pt3Vx%+C0{q!@p-(dqrA@s)iGSD($#Ci@jdahH-kT1o$-3>#bTYjOy5{RF$vBiL+k8uv@|3tK21DGYmeDH+{cM z=o+Nlf4%eB08C`w4Db(j+kf3{ z@Oiw^wYZYcNBJ6Bp~~0pXz3pqHWU0qt6cImtCr8>jjq>$&qumWNvU+bzWVPUG3*ZT zpOSOYb+5<$^=iVQYj}xD*Acg$GzY`(1pn|d7hU&x++X!RhprJdDqS;H470A=z6<;# z>Rog_VDNdospBj4d_JmUxpM#Y?Pra@V^}r#%iZ>0H6HiZ%ViE-=O$G7x^_!d6vOTY z|G7z*e6io0vF7q7UoYjXxvYcobwQ&_*Gp$UHvl7Mfqx{p=z7@W{#sB$qPVV6A=z7%S{$js?WoaW_ zmqt~(ZY-&rg%S6G|5CU8S8ahchjn<9ulWW|hX0VRadj$Pe{39M-M8R=@Q+KoTj zK94uL<~8v7NLRc-rR%uJaT_u00r1C5U35KR@Oiw^#ePf7nv-;0Ri)B3^Shs|>lA9h ze^srEt|vY2uV>PnlXP8^Q|TJl^RoLe>_PBP%5%{**W><5#vHmPEB9YtEG|A2!yW?v zWVij-(;oNN+-8Ta8#1bV&0Y1O^|{r<;J=~CC12L(ZS3%-zn-e$^HCjdil}s*pLfo^ z7&aUHH&wXkde-CqdJ-JErX^Ln)^DFM1H&Ex|Fo2gu6Z8!*PNt7R{~VJ9_?EG6ox$t z{zQq3uID}Oug4<}T{D#XuZ7#ESy7LHe}>!s>jgfIN00Z9W%z{DUw1aE@^$<}+Upor z3;w%&F8Qjf;`4aZ_m9T;e57kuOr>j2^qa3R>~ZkVO1S7+;BkM=&N+15msaUox$F5w z7&Zs|_cglcddcJddRXM2^7UY;O4lJfFIkGZo&f)Yw($fO&#U_mvqfm?!TIf zZaorD`Xu;gyY0VT5q#e0s;T3gq^s6Y=4{;-?7iNcqzm6hQM`}YQ2A^RjF<=h`iP6JWghp}9VLwNfUegQDqUkHpJ}~Ldmj9+ zCtY;C<#B(_NI7)9soa0FR#aicj#gb>Ls#?4m2>aev(^@=v-}Mpe3w7`W4VJ@g{@ zSH@g)trUFT1ZU432 z+2eot{d9EV?9p14*sv}U36t~d>(J|b&XTkcg-qYy}sFU8=iJC_`mnL z=-T9Qe@(3CoK(jj6DnP8tBbAc0hWOON4NdgW{>;psxpVJpBq)Wa+^NYG3*WS?*f;6 z$?J2yspAznhpu1CRl3eTto5fD_9pm$t#r|~Rm|g!uDIw6s^gvpm9EG3jy)B1HGqFl z)P^1J84g|l7O3)dw$Z^_wr_#|-%^)+;S=8~A)ye+61psdPPd<$c!s zZg1n?Yh840_qe|acL(5dUzTGpvGls2z zz@c#$U0-?JUzfxjy4ooBU!VTCB7|Y@K%kA={%c2y&*M#hUEIv)qy8$0sPffn@$B<4 zECqpr3YUC+6XElCqwAs?J|F4okW}e9VNlz?7`74u9a1j3zV*1jMu9_DXHe-XZoB9V z40{&>ol9JFeeZF9RU{p{0+lLV8@rzW8-~3Hfk2ImuErFf$D2Bi6n#N;3@Z0uGd6Cs z_BpE{ptwO4>5-$1r+2cB%7w7pWUBzjYt|jZ& zEyS?Z5GZbR(X}hb=kX?A=ZN`8S4pW#SLM_*R^e&aK%k`DMORaWx4O=*;`5QN?zJji z$LzksDpMK)-5XqV{VMvwn|zfQICPaZsC1nceQ_LyeE@;dtc$MSJnpYE>m0iJDEEag zzx%|c7`7Gyecbkids2KJZ}N3Ul+Q|d?Q*Yb|1^u(}r5a?g$lCQlU_t)tS4qYcS zsdOFP_EhWh+Vv0^P~f8L50Crnv~q{8K@}=pSGH=0+05Gjfk9O+y8iUIzsedNx`rtC zg$q}oWW5it5duTq_Jx0?_&nb9*Qp6UANAKM%6;L6;@7R$9UnsA6t{ih-w{5KH@b%T z_|kl$}%o>{Kw<|>Qm{^HNvOTwepp}&%>~fATT20qU&Fe`|CJx z=sGK*()C9D16wg{69mpms&$3)QhXk7>ewsE=c78FtK1i!GwcNG^M}n4IM-!g7;fQl zf0c^)NY@3*ec{BJ>wiF9TOe?O%f2w&vYzvKldqnlUrE=6SydgMHcabtzKbuF+AIuG-n{oQ?2@HBPxNtlF_`B!*=nFwSLP7(UeF{yMtAq3iNmRlX+e>^dLA zK83*L4KDd=UBc(_CSOO@@%gB~uF6yCI=|tVd<^>x0#_L>y4s}pJl^Q)YVi3;*EMmK zuB*1(vKqrahrl(}F1p%!++W2F4qew~RJyLO|M)Wu+XjJan_P6Y^SHml(E3qSpI4J0NhU+y2X!w3J(iH~9*r zXfphVblu&k%GbHKJhTrZzJ|aoaLHG|$LH}zm%oC~N4oASSLr(Z(cMpD*f$WkuhKyy0mX0P?L4h6%_s8O};wC9lB;4DqSs3=wiJd`VIoKqb|C% zB%j9{T}SfiSbsgH+<#46e6xme-$URrxBZvlaesBF<-(}Ho+wb|>&s=^tjDiL2s}~h zlCO|>yzwSq?MofH=2oe6J+rFsWDNTO0&{C!bcH?cuYx*~4%pU0bgwTtrksE*H4u*Cl5u{c{?Fc z=eGYk%H#fOQ|ZvPFrv!W(`)}3gke8JU}1$zzK#Yyk2iH}E#{*-E=sC&J-O@pxAC;Q zAh0OqqN`idTV01H_^xajKPaeslBk956JsnXT@;xFDn zT}=>pqsB$oF&_6I#%?9H~l5w@1T4wkE!ydjk{_& z>e>x~~{#PX>ifi*W3Oo{kv; zHVoSffpu>CuYL(Wk0*63-f!^vsJ}K=tMc{v;#&t`*dGwsSm%^+IZ*=|Lz~>`f zA2q3T6;7Le6NWWIU{isMuHoYG#v5JxN*%gBu2AV(ys(RbVShs4<0=?ud}>;{3`xk%tyMu_NjDTl{)nk)b$SpzK*!) zI@{y^+5?U{ewR?`dh@S~j=-?}5cn?XqU)R_pU0d2+AZdzeEra<(sgR5_eSDr|AoMh z;G*k1kNfM_25ZDe&u;s#^F=>+ldoSg4qZ)IRla`jHWJ^T$j^sB zQ?pCHMv8v$M%S*mL)V_DO4qvfOL3o*-vR=AVlKMm^;+KO+L?3c!k^bs?C)ok96bqj zwS>SQX%}6iJnpZbsvNrZ6{vLe@tuDb>N*Gl`$}DO$?E~V$=8ns4qf||`>$E8HrJxA zgCVfrZT~ge~7=VLS3z(u!Z50uS*hq9&hsXeU#55QabY13gf9+^==xV3je^pMXIuUgp28He1_Fv-?d>(K5>nkxI^;d@yRlc^R z3o)(vt)Z|(nM=OLH+!oqC;F9ib*fS6dTUzQEY#Ho3Om)i=(^nF{@O0)BVGPxm9ERW zUN;4G9S(&7pNp<5JnpYAN_hTBS1_j1_1u#SaKD=077Bw27hPA1e(^r?_tz(Jhpz61O4ql0-e^Ew?V+%H)J0cig3sekzO3ub z*g^T~S*_Bwzf+(M>goW6J?mU_UF&gwZK-wW>aE;=wSnp))YTCRd%NwwuJgFRHkUed z^{rCn>*smN<51U;P}sNDC12M!@_D?e<40*eAJs9EQ|ih_t58=bC_FyTMc0%BpT`?r znJAx+bPX(1={jrMM^=AzhQfhy7hN}c++Q1l2uw-ttK(eyQ|`aM>eON$>e8U_Jh%PV?J+)&H~D(6 zjL%2?H8QQr*EjQiT!6ZCC>+`7lCK$JU3;TzWzM1NqEeNvo=^Jvp)LaoFDiG@b%)3O zm8x*)x};X6>z(qB523CQ6kgKcqU%nN`)fs$L)X|mm9CAumQO%kCKQe}Ty#~(_&na! zad|bLkNOM0X0CYOr03kv_M)yZ6pnY>f8FhIf4yxubj6!gx=y*h=p@ut424$|xa8}e zaz2kY`C8V%=c9a0tWfE?x!Z9Up{_1aII+q_*S#M1*V0mlu1P7Cu8ZGZ*9vuYg~CZW z7hU(q_&na^>&-NukMeb0iAvW&6Xq>JT}MITb!9HP9`Lxo-VmImYl?FJ^~=JOmZGi_ zD4gQ9|9a5l{#xAZ$k$Y#Dqo{J-CKjYj)uai5tn?;7JS~+@pU{QJ1Ae%6DnO}wv?_x zUEQE?deTMLBZAKxU9W*d7j6p_k6+*HT7}G6KkGgt5;mk@GU9}!RPArNzblqL4(zSkB*&C?q7%05E#zohh7@x#+iruD!Ljcc89bQ21D>i>_ph&*M#h)fMph zsK4eY_l5PHy7Wg~y`gZ9+rID_kNazWokQ2$JXOA~oA&!0)O8#b&UM=tK3C4?@g`r- zNBMk|uV>;aT|=hsvfiKQ1BK62yVP->$NlwOgG1N6j7nF@p1D>X`$FNoCKp}vV|*TO z^7X99Kjo_~qSCc=;W498S3fAMt8mfvg2(-p6!|AzFE?5rV_Wy3EL@Zuy7R>gQBHp- zeC7Y17V&>Km*D4>!3|=#m8Q*@GYD>Mwx@0r3I_do$HUvEddoN8fs$@OU)LM!9Am4| z7haI&z7}|nOvduPXiF#hC{Ct^Q0l8}DA#sMwnUT&6xP=|Gs{u*z9sxL0!8nKLfK*Y z2qkp5I5qh&0zz$3yo@81@WPngw}~XaERY3?X*BaV@>y}FF2)iHUR5ls(zh}56QUds zh5vssF-Ot96T=0H_I;Y4MxYog;trpMV!YF2_c4@3PGmx<7xPJ!83rFKQREN)5z3NU z8%kzv027jb0u(O!zsFO7l8EssCCY8$)Dk6*qS!$`Lb)c4QMx%Zi$cJVm#|6{yg%82!}2kdCC;&! z00_S!QX{Go?%&ME3Y2iag!JKM2g|ZHly!5*8i+Cw-OXwgy>|s4E>QI2Qg$C(D~BZ< zzIv1xYVAk^LurUQ;s`~qAAw?q#aMx2nw5MkRb_eHhH{&6tF`eu5ek=At5LKcO8Ibs zqWxHF_YsP*(t%8mV8**CdmKZN>w>CBC`%i7oJ2{8^GcLkY;jnXcbaV|9TJOgLzF>K znDV)x%n(ybl$i>YtE#vhl2~sw-Nc;T$57n(b3y6ez=uneV+^~GRi$Ol;UkoT%j`aeBG-jPc{|PH1WH(5_AROsKCVW_ zAkJuaafhL6*iP<+kXfk%20GyxuD$1N83>D zQlMN@#sekFBm`oIM3L)4qP&~taS}z|Csm?+EY3kyS>I?w8S%}EQHXL96m9?)6#Puw zCWlp}w7~9TYejzbMxw~C2}u;WE+opTD4$QDgymOC1WH(b{e@6Itg@kelDgqDL^&A> zKde=w1m)Ec)~VTc^0O*_YLY{1r9R{EVLd>9En@ev29xVTqP(wIEArL1M3L_l5XzWpdK)V<>W6NR)IPkCQ0! z9?YUD<|c7os>&y2Hk1=qbvy%6PKClx;w~t?s`zQFQ?sh{&e?seDu*T=K0=XSLA1s) z6uB-W%GxL&D^SAn>uLfed`yju!>W9mwV@17RO0hNei^!()hNNwb9}f!34T##_YsQz zddlImQ1m4wb{|8L>q4TeYv6GbMZU8qQRKUjRF!RU8_Ktlg3}RYI23NHR-mW`|awpo;#;Lg(#-nQZcyh<#81iCBKD8cOx+3a~GCyFmn^fzkwX#|S?X0zSL zP~^IxI6|>sdBxwRke?bz6!{4Ut(EW6Hk7SBng%1v8Bq9LqZ&oq^IsHg?|)H@jpcUP ztie9a+IpI_jWa?QG#D3?Q+;!`5Np#LeZDT96k$0U)E^%F%-EjB+6%XJWf<4JX_2sQRJtm zgz{^N4Q1Mv)+-U^Y$*J-OpT)bk>ID1RcUreWL5bnYL8i^h>Ca$QK2 zFBEHKZH}K;qI?jSK1A7DWWH3Cmk}2$XPfQpO=lbF&R)@Ize}BFcGC_@_^e68y#?o2`{^vwTXDgZ~Hm z+vN^lz2#fpVE3^Glj}mFpu{r#G!kWO#O`A#k!FXl9;;%U5VQLj%Gb4aAA5@YR-{3q{9DH3B+5TRi-l5@ zS7$@{qtn3)5M?B~(=I3jvwTX4GAL&EF_a^@i{8#)Rp}JxPHQYfk?TTM<-2MgCs4xj z_CNw99IBCVh|)4*Ly6XJD@T+HbXTZRg5O8^aDftROxt~gqQ7G}eD&5^NePJ(MXn2p z(kRAC6nQ0;M3Gm0QB@9Zw4ofiXMKM}xe$t4ff_~I|KFk?y^-StEh@x z7ZT+M(R2dEyh@xypqN*P6cP$l*-$RndC5zNG75^I)&=D;F{P-ARwt$;IfQbnqXMkK z5>1@XienA-Q-R&b*2+#XR-&xR@i>VhfBTP6@b$Lbyj>aJNPP|Al36zwIEMUq1(w^!KXScA<-*?kN} zt_z8>Td`JFHu13%B~>MT*kDJ-Z7A!!J25IaaB zjsoM&sNKg<_HY+_q@%U+yG`POwPM~YQYcYo)$+kqmCp7C>k}D{s`6t{W6NR(y-VuwI6$44DL z3)#FZEq#a*^x06_H$5@~QO2S>qDIkPHu!LXqP-$cO>zk3juLwuTPt_g+kFg0t_z9s z7Y~yU#^#C~cZ#Z*_>u5|gBnav+fc^&&Y6iQmqC%<=z?;JLpFO}8P>$7lqkU(hYumZ z(0z6vL)lkl_pztQzr}o_D&c?_D^S9|Bp*vCW`zyq?b1KbN0f0;WLBwBg1?B9A%6nzbfX9xK#6#avU-N#Vmx}Z2r6omJSbV(HX?GlM{dyLOVD8-F7l)h))J_=FB zLs1t{qv(f-q6!op?^1B!5Gcl%H4dMJV&t0bK87OKg+M9hQFzfEf3`QrmUFK_F=JWj z!?ki$l?~;C3wlgIlnLmrRikK&n)q;mqP_axsuaS}!T z#<)aTW{X3VZeT;HKIkw&l*`dw;(}7W0@Dx9_tcsCv_^2xK7TZ=FLy_x3qO=g{ z5-8!$C44@C5J=^byIeb)=uhVuPRmHY0B#L~V5-8>vF`uZ4IaJS3yyqY8RB#OZae66>Ws*S(1~r9<9O-*=*U%+xJ^>3`MRBi2_ah9HJ^= zd8>C(m2mr{jKgK$ui1w3Tk)GGAj(82>hDvd1b?sL!v#w451-vfRna$8I(+qrr*A|^ zc1RStE+oofwrum4UelZTScxLP!An&+zRrfSJ}>+OqFfC{$EVdO`r-erir&_N#~SS0 za(-%(XrUP2HQ0TuDso*&l-4;OC#qszEanp^<|vUGLKzsbq0~*Q9fv5_K+(VoHHx+b zMX|#=HCroh`s_Z2a-TSjM0p@;k7FouT}YI}t9YD5S<>Y2Rad9CBK$J=-8d9Z32{tGAaO>3UdF9VWyN|7vOw8f4P;_}01#2urk?TUD z6vX*hQI)X##=S(5cLyMplNxO(1NZN_A5pG_qLV?5qPJ`2rx7Un5l-1umH&JD!9p>9 zz_wtAM3L)4q8yRqaRSA>Fy`>#OkkdxmOgB-VYN1tlczp|{gXc#-3@9Kts%jO3lwc> zqus~WN===^M<@>!*nO-ja$QK24i!93qP)&sw&#^s5r`dBmEk2elvCU1S?_~g2Svln zTu{m#ve{ZWr<_koa;PdtJ7lxxm2Oq`IEEtEg+%Gt#Nz}?xNXGYLkI}BNl718<@5#{ z%AASQE=82<(VbPJ1ot^)v$Z1c3@cFd|ND%w-dZbLYWb{dh;z_dIk(z|a`pOGrz6UZP;_pc3(C0;*$n0UDA!1G zFanHY#A(P!RXLW2*-+%VkSKu+4-_cj)+G)fHQ1pzD?13~0-p`##TF;GL6j;ex*(!P z3GR>b;nu0yTKTum?qkm@Te*w9p=6=x&g+p`Rph#mC`EBTSfX6t=VTU&`!0hSJ#?XGts$3ZFnRhoCTa z$Oem+N*|(J6tSV4ST}DHqD)11g&IX$5#_@LiuR5;4P}-Z?9sSAj;)o)GIk$Bk?TTM zMX%s-66Iy?vOTZ7gy8I;2E$ik^7ECo8%sAJ%FR$Ty3qyY0*7q2Rw@ekloF*>fznHX zBG-jPF+`j|2}6XRLsTW)DkXhbl~|Px<)XSrKSY#i=&p4^$#=+RD9*3gu(jg69+|45 zeq4TKWl|!4y>e}{!-w^NaAiXJ5alwkp`7=|LDs9t>F6#|qv$@IgdNtY z2}KV$@Yq^us<+3n2HWkk`xuH`7ZN3$<8h)Y=Af*@XQ7xUMx_r?#@E_Vj_n;8hA6k7 zyFrbj4Xx$F1&VeuciGh6}(ODfrI2^u>$(%DTmLhivESjtQE&lFM41E*Up3AbzPeKSu)(g5+fWX^xO)Sl+=lLIHHuzX#fJ+Ny(nk*v8w!*boeY3 z<98uPqR4e2QA*1ASb<^=NIQHMig`l0^dZWmW*f?i-6Ie*|8^*<^r=y_ReUt93)W!o z$GMZ_SXD8eEOGb<<*6FGk5#36h22LVN)-2K;y#Ij-*!51hz2vCM<904TA5sJL+LU0 zLTi&h1Bxcsxu9IaN83=wC{X$-Q2HxSTjomqsc z@@GQP4G|ZVRvFG>otjleK7EO*=-cb;^=+3yP+L3(86{rFCl7VDE}4CCcLw zej4%-%ABO#$EqT?juJ&a6iAc>;=Hmdbya*mYOq_YY$(_4@6#7is-fuCS{IZ<9da0o z^D8!N5B61ppGKhQI~wgih9cL6MCqO3aRMcL1vq?GRl=9oNFP?^cCeuwsx7QTl)KSg zqDIj}j%*W(ZYKGZBqwV%)1Og?kE-%l+U{d0$L8!l_F&v6&V2&K>?_8~s`M$BafmXr z)`pUuxA|v8nT75KHH!8@iVwGBv#P8svHRFlFxIq|b=4JC5@XNLXzOeEaDk$25E&ymcv3LtHQ3|WQ{;TZ?qeu&T}YGxIUXlb<`y`7xJtl$vR3*K z<-uwj%7PVVFG7?D&|T+(GC_fIxdLU70wrqjQ(Lkbid+{G<-`geCsF=%R*F#m$jCTE znH{mA^zTt$geW!Wu5dwV7vsaNQ?o~~g0$Vo*2?!$hp!&9s5jQxeGEme3xN`rUoaFX zVSM3!;1CTKzEq@@mVIr^hB7_A*Fcm9p{O>YM$x-w`IG`hFNxWGY_0suUGgoxP+pun zt+5P6t_y)uJjj-9{+{u%jeM*?F?*IvA68{flMUtXdtY3KC=Wr=69sA%?ZX%!E>N_L zI1R}`STJ6ww#TuxQrBenF%-EjBucc5$BC+#PZ$m#&JO0|;v7_!rxG@lvl8!*MwEx4 z=&7U&$`vs_r9`>1(e7ha86r+Y66-Czp$ZhaE+op36rWF`>~*dmLfK=B!>S|;Y$zA@ zX@jrU@@J#_|L&p&xGqXijy78qRiZrNXgY>6t(MD?D7SDIH62wY{Dm{lk{JG}fCoyH zH6jhN!B*Sw5arpF4W-|n4)YP^5p?I&Rnd=5^V0|vy?d$MM<}6uacY4QYAH@_`B;O= zbwP0!O7Te|PNMY4@^eU(?lI{@l;_KBDE;S*It)=BMR%ndMcY))hYJ*KbA#Q-sX{o6|=qzuJ%yWkID4<^Dm5;}NA6-8C*K zM;iPzvMQZ$Vs?<6EM`o{9k$(9Z~1n`?LM|vga7|Hx(zjo-a`~spy)mMjO;nYLJ1v|;!cuip@dqM*nO?6uB-W%4r!MCs7_T96myMxK8>I<+Z2{<%!-ab|A_V=#IIdOcGN{lu8B4sS1=b z1&Ul35@m!KD^Z#%q-@*);2FW(m6JY1S)8$!@Edq46~Rl3Av9HK03vZ3s3 zZix!==R(o40yT=3E#SiiiuP%h-N&9+>K(G#9_-bmJ&sjHt_y)ud{%_VNfdc~j6|ua zm2rsjcG8BTA5?68>h(0bQ!Xfz6)4v!P)<{zoUTBT>q4T$GEySn8UI}7@KIHMv>_wP zJEb<1*B3r{HKHWZUG9Ps$nhynJWe*)4Qc7as;nxvp$v;$fq%_^7TuLDD4*r{aEY?5%4}K)92Bj= zM@!`%?D`xZE>Wf^P|i@GTvB5n%TVOH5Gci$iF3%RG^Y4iiSoTTFE!W)H8zwfl?!Jf z$~-9gpxy-~i1}rQL~(w_hN_}FuSaHUWpA^6EJKm&LZXbX;Bf*ae4fwYtG3q4IZ5fm zs;oC`D6hAF#oFXQkM5`%CAhhq4;LuGEe&=bLwTvd;ll)gzOdHrV<;0cb{|_SE27*d zQRJJnqAKBMvN8@)HrCrvTFvg(6H(@)JL7_qiSgkQ<)gIS$585`4j-YsSZDVUitUEK zvMLf!qRfx+u@Yroqx2!lM^PKfdGluD+d=s+pgX2U(QZUh><}p0O%c0~P>eCn4xfc$ zTpF|cSXJb@kSOso9w$)DZ$ZmM66J~QG=j%>5F z(xJc}M<}6=j%H#ga$QK2YZYrH(9Gu(D5gIleOQ&RD{UzLO-F4*lvmJQqejs%{=gwn zv~RL@A8W9;Y8}3MtHG9Ymwb29wk`xpc#%krY_K~^`Cy4MvqAb0#d`1+_sPHcwGH@Y zX#OH}8!jl*6)3kTP{xbXkVHbc+~B9Se5@*RT}YJIqC8Hbe3^0hXsv9okUm6dtg)f2 zDtqKFM5#x2y$ed0W^`Q1I zK87+h>F^QC$t89lL%AVk_p#@d8zbB&QT_slk5HOxqz_S=Vm6c)cTMSyD6gYC;ev8@ znh%#K=a$=j4CRCZhmTMOIMTpSsxpo^OJecVGVT*7X3PIp#mrC0I7HdqWJ7s+%V_*# z{$eQlt-uAv`DPET75%g%pOTs>YZX5fbNC3Qccb0MP;O4yeXJ_e|63Ka4e&UzR?Nd{ zqz_SkPuNh32hP6&QI?=P>4I`13T20^%HXKo$EtE<&fz1J&T+esp~&YDN<+0(m0K{H z9kME&MH(bZr%D-zD9r^nl)HLXeT67*pu5xsWpo)IE>SKKr*a-u)mTvlmP>KJ&GuALeXC-7nJiF_;87GfnoQts+`DO zwoix$#ktcO%TVOHkSMpMc$`2n^T6S&wwidqNEe~}Q*J{s(*5w=j{F8F`lr$bWkd;| zQlgw8rX)Gof)J7yIFYa3^7VBzCqt3zLZZxw@N-BMXmy-1}lp>d{mX;X}gc1$aNu657y_q$YlKgw;*`1;es*}^T7^@Qqg4hF_gg>hmTN(MC?9>BG-jP zkx!cvdJJP^Vo^rO&u$u0fQQ5bT(ALAeD_#tw;+D6sojRW1;xAw2v)2vzv(aSWx#8Am7& zIb~<8vEMrJthmtENj@K;bS|}_T-m+*hYjXW*-$zs_x+71@1Z;Ag7Q!;A1+bwY4yNC zaGD3Lg*Yv8W>8gkSI|ePx7%6Xe154T;FJqWAC_3DYyF=irfWDlqY;VPNJ--aQHAO5PCl)eb`_prEOI? z?#vf@BFYAIH@Z~iX^{!*)C}bracWtW8?iR*ARkrbrl{S=P^4^$@?;HqP>jc3cn#k7~f99mj#zf$8f5TE`su`hwP} zjI4g3b*?9?KWKg*SrO0zNwSUytq90E0kmKxSpz`RvSbYe?Z9j86G00l$TtWyvyrU9 zpcONvQP8?Dr9<#TA%p%p6tt2$vQ7f6TLD=ogVvoXJq5HLIr0qyttV4@Drm=M$X5nh zuLxPgLF=6)>om~%Fr}x1)|V+A0b0Li`s*2>MPg)~3EJ^#vd#i+Kq*<}pbe}g>uk^l z8DyOU+Td!k&IK*nMAmtr4Xq&Se9%rxk#zxRr!ajZK^s<2z6#LFd}Lh++VBKfqd+^Y zk*teAv%bfV$HkzXktJ(1XlF&qx&*ZHIvGV>l#mq%EmlL;6`)<(OxBg4U6vs0D$vF;r4vD$ zP)@$9LA$(xtZP8K!XRrBXjj&eRSDWeru16SuC5~AWYDh3k#!wtm1SgI58Aa%=?$P= z7a`vi(5_FCbt7m~fUGLeZmcBhCeW&wzNw&1jgjwW&~8qXH4U`srDRP9?Uq`yZUHS} zkaa6)w^fss0PXfBvTg%yW(8TdgLX%XtQnx)#q`Ytt-79kcYrp_N7kL7-IE~eF3|36 zB&!;<`7$xf-&>pHI>t6gSO#xZ=f%XW~cRy&4kt^>3(CV1J8qi*3 z`W^)BC8qBo&=%$>@L|wiVfto+wutF_1hiL~zDGfOEkSXQfwmaPss(Kc)Au-NZ!mpx zKs#_f@e`meW%`~3?X6N8@f2upGktSG!?zi&<7v>|iIbHCEtMhb8PMKk`kn>ty%hPL z1MU41vgU!dx`wRhL0i*I)_l-DNRagcXlonEssn9(Iax1)wxNNn1)zOsko6L18K!R` zXqyVi_cCaktH^o6>EsU>R}Xx|xRy#?C$)nvU5T4NJg%R&3Gf~*yw z{gfi>9ngMe`ck0nswdw{(3*T?y$jl}39{Y;ZFeJCt3cbs^t}(-?^*J#2JMe1S!+OR zt|KcA+Fu1^eE`}&rDUxIZ9h}G4s`P5<*f%jKTh@r&|754+6ekVOzDT9ADkjz2J}Np z$odF$s3B_;=!Z6wwHfr*39`0;-i9gt81%N~xpm%E`>qpRgRFL%(=*OhU+6nrx zOyAF-m)4VS7wElxWc>pAaS5`TK=0E?)~}%VWBPW3-akve-#|Y;O4c6GPpBj7chCnG zkhK@|6Pdn0Kp#x5yk^j&aWek|eMp9^zd%1JLe@UePfn5bH|WDk$odELQ)|fD4|-WM zS^t85TFkO=2dSS<`ttKZKck#{EkHlBfvlFGmm6dq1p3+4WE~9pxuh?@73k+xk?#=D z&(DzsppPsg>rl`u>d86`^iiZQzcuI=CCS$Y^wB`p;h#`m`KbKG1Jr`uw2Z znjv2R^xK%eLeOtdlCKE#nM_|0^gEb74fH#k>90EI)iJUR(C=pYLZIKn^qHXF%k+go zzu%y^V$dI8`nrH#!}N6p{UN6BD9|5HQCtb=k1%~lgU((R=XV3W)<=Ks4*KH>vU-3% zr;)5>gr4i6yPLc0;{IT&8vQ7ZKzJ{y;pugHo)&^MHlbr#-ax|XbR z(An!A{MkVLqiXV<1Nx>Wvd+buhE|Yu9_SyZ$T}Zyj>z;~06Kf!gFo1%f99jVR^V-~ z5@cNn`nE>0MuE;=_u!8e>0f5acQNQ+Madcs`i?rXE&=_U0mIy0xxTl7{yGsa12)LI8uUM_$+`w~_PPge%&fE5J$PSZ{hu8D^;*1`tBkD4 zVC2=4bsZS&br0Ut)nKoC@Rq2?!9ahV0!FJ!vTg+95SEuJFxcxJyd9)*SepJi6@O8- zl&qWacVuhHng&KY%dl>RXB04fw}8Q3_u!4#j1Cp_*8~_HQ)Jx+MyC?8ZU=+C?!lW- z8Gax6W`Yq&kaY(bg^gt02}ZD-th>O_n7(Q-j41i;1|w8Q)-1dudjVPZfKgmU*1dS= zY0I!~ePJ9GC+mJNN-|_U07kb6Sv6pEPm=W@7(G*DJp@K+30V(=(W{26*<@qGsv0)#(-+Fo&e)Sru0cL1~H{ifiXBof1L}) zkTSBK#_y%qla&PHtl0^^DdS@mFC z#q_-j#>6D~UIXJAAnSE7CNX`B!KiE|-x4q;$H;mEjO&=bH^I1}lza_fOsOSnDHv4- zSNA?rgh9;+cM14eB#Ss#HhCq~vLFrHxgHiPk0Ir+ALF}H!N zkMR~*23cFdc&3`HPr!JN>C58HO{&QEDHzY^$odR#;!sA`=U~*;leGl-kZ)ROfr{vMTOo+jg6_B+DjP+Gy{SL;5wPfuD<0H$+%l`w6O>wfC z!PuN3>rXH~j*#^i7+X_h?E@prl>Uvsk5)szf57;xnXLWzJ5VvQ{srR;Qi|^k8ef)M zz83lTD>n^fwE$y>K~_sJzOE+gATYiyAnRcK)q*OrT7mI>j;urQ?(Ah`0T@5llXWQG zg_`uWI1G%RljLiSciRQB+JMniN!Hj*IZs3ogC z-WSU<@>+BNu0IuIbpm65imc8M$}1tu2ci6WviuNY*Kf86;P=)O zEKrIvPU$X0p0Ls4zxWcL)`w$?AdEx0I80 z421LsvU=iWp$1vULZ~;>SBjUv6_BqNUi4N=R&NOPw~V|N$3ZB<^!0(z@fq^2n}NTA`lwP^c@eOXfyrw1PBd{ku?B9CpD5a5JIOgeJ4U_7}GZhLS+X1 zbufg6SCbWm(CJLy5WGUVihM&MbViP>lOS|f8CfSosJx!6Q}827rf(R8&P|fk~IoK*D|FSLFl?D`7Vag^>t*8hR~D(vMzzpjZEnn2;F44@>;|oG&N4vr4YI~ zL)KUbu}c|STn3?cn#nf~LhSLX#drw4TSLAH5LyLfU5+1eB*=)eq3ta0CJ5zN+*AmC#o}(pt4v}vVj6_LVR6$T z^c{=41w!AmxLYCg1B**Q=*KLLxD7%(S={Xq`kBSez^m+8+)M~HvA8=Rw7Z-}+zBDJ zLvC>wgnnmn)ezdt;_ik}GmD!Ap+D0!;vNX?V{!LF=x-KxA6^H`;_ipgzbx(nF!Q4{ zq6W+sEbc)t4`Oi-fq5{Cdl)Y~WpT5?ga#V%2$+YlxJSWk&Eg&d^Kced3uapu_c)jZ zr8Hs=m`AX~i>&5`vsm?u||wH$wGgq>{#m=_x4 zdk4%>Y?c(57qhdi1amZtdl$?xEbcupV=QhJm}6Po`}j+XEN(TJ3a#eE9qZ7l9HFmKP%h|j^C z$>O$wc?XO80>5_1;9*b)Q<|-C<2$-vVGy=d}!{QDF^8*%l z7?^8WTx&4bv$!^3Zm6LVhlBYci)#yJhQ+l5a}$dz0CO{oI|9s)fkw0kb1RGM0A`lO zbp-QM7I!3=pR>45U~Ws$h|XYcXK_9-zhrTK{0=CK3xK(U#TA12bu*190`prI7X#P$l`P`e_(M2m_Jq0h!EZbCrOqGCVMBpWf;s~*(}9i{>EnM0_GkzOII-WGF3-` z`3H+D0rO85cQlxPvAAwv?qg@`4(2~Bt_PU^vbbX)oX6sNLO7qr9Sh->m87K&h#2`Ufbbb? zzLEcH>D=RUF5fu5@+_ZpnutYe+}Cwmh>@~VdOBdqVG)hQa%wqFq7k(mYI2&0Mf5n2 z9OgU`b8ID>tOr7TJk_5^SZ!wG_PyP1HH^kgzIeHYj9nH+_xKCSM$2Vy=Gny zxNhe4gzI5mFSwrBoOr$DfyU+~!6ljZ23&9Rdc*ZGuTRMX^8)RNGoc$hKW+2=U^WKDe+q^+=L(O{&ZdfK)9t<};iZldngn4h5ywK9T6u4CL zhQf_BZy4OD3{JcQH^#i-C9hjHZvMVctH-P3Ch+0`yNuxydNO9g*b5#a))_8Lhdy05G2C9d`Nloeu7kpW0^}X@Dnf>vcMs&+(@05Tzw6H$E_jhd}>}a zWQKVULOzSP5 z;#ktdkR>5fL&(x-(j$;%>7+*?%Zo{kAX$l|Sjfs;(qoX-@ubHgYqCj=A?u<@Pe9hE zk)DKP7m=DkzO;T%K{ggJ3qrn%BRvh-oJD#Dk`qaK7P2)&dJeK3q^6J^$)skGo%y8Z zkgtQJI7qJbdmgeohFJ^9o($3pkbR{P7HA2vJ4v7w+O1sRQJAJn3b~32T}FIT>Wu5%O~;sT1UM1nCvX zFDazXkTaza7I+m>m_+IVIh#l73bAwDKqBOPh}mlpJJ$_#gIq{w)*Vt*OzHvoE0NR_ zaxs_G3v$W&y$-pY%`6F097TEqawUz_8*;UX)Ccmf_3I0{Ucjs$=q<^lLC~`Kq_?2A21$dV<*eTj=-P?{LIShl(26;v5m39Q1m1;KPG|NW)b1&PRA`k{X759*7LrCntHqN>LGRBd zjfO@ANn@bZGf5vnT?FYvsHBk6pjtp03$1DWK7!i0ZeSd=RxGcMht>{}CO{toX(F_) z^_v8(SIjIOT0fCA8QLJ1^f9zy3~36qX+CKxw0V&92{g|7O@p?ue$$~ZSicNtt5Pj2 z@F}#l^_u~0lgDf(^hN9U8MJMP*(~Tw(WKeX_SWxnXb0;Tg4(B(z#M2t>o*r_pH2ev zpq;ZhJ0IF5inIXQHI1|onpi|y1np-1GNIiIm@S6(j3X_9_R1oC0Zob|ErtI7jOvBvY-Qkq?OP&6G^L}gRJRl=-?P;YoJ3iNNb_25*Ano9coS2Lx)+@ zZ0PU=dK;i4a!6l7--{+~gr-{4O;9`64SWS1mCCD|p`!~)Tc97rlX9RRTGOr2u|a0r zpmwes*bW^Z!E6U~0&4|!LMN3*VS!!H^d!>PQ2XmvAQw6%mf1JZsUgyC=rrrM2Rc2S z*Fk_b`H9| zkn|gLXFTaVbXPX%cW7>q^au2tOwtADo(NJAbZ-jjPw2h^(qGX1*6$)TFOS*Z(C=bN zm!RK=NSC1pLHY;!qxCC>9x7&b1^QDW=_>SaF6kQdXbkCJ=rQYe9eN^)*?-W2G|~;| z$)ZvU4}+dcAl(E#T|l}S`fD7i4D?JEDF8hiNeYLaOC{X`Jvs=)g;-v#1Ya>kstjMrnnuD`wx;*ON9OZt75FNNq^j^$b4mBXSF@(o z;P201c0YVnDTIYT0AD?g6a`)esV01# zLQ*t*-FVW2@b#=;E%^FDX0_oPWRmK@+i6DlL-3EJFslpSs1(A&>%qq+kz(K<%Oll? zZyZZ%0RKdY^e}uA>(>zesdQ$Kzz2&-kHSBbNNNQCY%VDlzNz(l48B=5v&Z4%qDYP5 zpHCw_0pFsC^dx*s>(>OnRROc7;M>HJg7EQKq^IHAMv|U^Zx7-!VvP4&TZ8#ld%uVfH-ys~Myg@LfwGEc^xd#3WKncsth(Zw22yfmv(#9yz2o z@V%l*@$j#wlU{^>!}_&_@14r59ekfc(o69D;z{k{`)89nz$XVuFT)SaBqhKPiXe4_ Xe=CL534U+^=@t05tzT#Ol)V1|!!bhZ literal 0 HcmV?d00001 diff --git a/tdc_releases/tdc_v1.4/Adder_304.vhd b/tdc_releases/tdc_v1.4/Adder_304.vhd new file mode 100644 index 0000000..d5b4914 --- /dev/null +++ b/tdc_releases/tdc_v1.4/Adder_304.vhd @@ -0,0 +1,1310 @@ +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + + +entity Adder_304 is + port (CLK : in std_logic; + RESET : in std_logic; + DataA : in std_logic_vector(303 downto 0); + DataB : in std_logic_vector(303 downto 0); + ClkEn : in std_logic; + Result : out std_logic_vector(303 downto 0) + ); +end Adder_304; + +architecture Structure of Adder_304 is + +-- internal signal declarations + signal r0_sum : std_logic_vector(303 downto 0); + signal tsum : std_logic_vector(303 downto 0); + signal co : std_logic_vector(151 downto 0); + signal scuba_vlo : std_logic; + +-- local component declarations + component FADD2B + port (A0 : in std_logic; + A1 : in std_logic; + B0 : in std_logic; + B1 : in std_logic; + CI : in std_logic; + COUT : out std_logic; + S0 : out std_logic; + S1 : out std_logic); + end component; + component FD1P3DX + port (D : in std_logic; + SP : in std_logic; + CK : in std_logic; + CD : in std_logic; + Q : out std_logic); + end component; + component VLO + port (Z : out std_logic); + end component; + + attribute GSR : string; + attribute GSR of FF_303 : label is "ENABLED"; + attribute GSR of FF_302 : label is "ENABLED"; + attribute GSR of FF_301 : label is "ENABLED"; + attribute GSR of FF_300 : label is "ENABLED"; + attribute GSR of FF_299 : label is "ENABLED"; + attribute GSR of FF_298 : label is "ENABLED"; + attribute GSR of FF_297 : label is "ENABLED"; + attribute GSR of FF_296 : label is "ENABLED"; + attribute GSR of FF_295 : label is "ENABLED"; + attribute GSR of FF_294 : label is "ENABLED"; + attribute GSR of FF_293 : label is "ENABLED"; + attribute GSR of FF_292 : label is "ENABLED"; + attribute GSR of FF_291 : label is "ENABLED"; + attribute GSR of FF_290 : label is "ENABLED"; + attribute GSR of FF_289 : label is "ENABLED"; + attribute GSR of FF_288 : label is "ENABLED"; + attribute GSR of FF_287 : label is "ENABLED"; + attribute GSR of FF_286 : label is "ENABLED"; + attribute GSR of FF_285 : label is "ENABLED"; + attribute GSR of FF_284 : label is "ENABLED"; + attribute GSR of FF_283 : label is "ENABLED"; + attribute GSR of FF_282 : label is "ENABLED"; + attribute GSR of FF_281 : label is "ENABLED"; + attribute GSR of FF_280 : label is "ENABLED"; + attribute GSR of FF_279 : label is "ENABLED"; + attribute GSR of FF_278 : label is "ENABLED"; + attribute GSR of FF_277 : label is "ENABLED"; + attribute GSR of FF_276 : label is "ENABLED"; + attribute GSR of FF_275 : label is "ENABLED"; + attribute GSR of FF_274 : label is "ENABLED"; + attribute GSR of FF_273 : label is "ENABLED"; + attribute GSR of FF_272 : label is "ENABLED"; + attribute GSR of FF_271 : label is "ENABLED"; + attribute GSR of FF_270 : label is "ENABLED"; + attribute GSR of FF_269 : label is "ENABLED"; + attribute GSR of FF_268 : label is "ENABLED"; + attribute GSR of FF_267 : label is "ENABLED"; + attribute GSR of FF_266 : label is "ENABLED"; + attribute GSR of FF_265 : label is "ENABLED"; + attribute GSR of FF_264 : label is "ENABLED"; + attribute GSR of FF_263 : label is "ENABLED"; + attribute GSR of FF_262 : label is "ENABLED"; + attribute GSR of FF_261 : label is "ENABLED"; + attribute GSR of FF_260 : label is "ENABLED"; + attribute GSR of FF_259 : label is "ENABLED"; + attribute GSR of FF_258 : label is "ENABLED"; + attribute GSR of FF_257 : label is "ENABLED"; + attribute GSR of FF_256 : label is "ENABLED"; + attribute GSR of FF_255 : label is "ENABLED"; + attribute GSR of FF_254 : label is "ENABLED"; + attribute GSR of FF_253 : label is "ENABLED"; + attribute GSR of FF_252 : label is "ENABLED"; + attribute GSR of FF_251 : label is "ENABLED"; + attribute GSR of FF_250 : label is "ENABLED"; + attribute GSR of FF_249 : label is "ENABLED"; + attribute GSR of FF_248 : label is "ENABLED"; + attribute GSR of FF_247 : label is "ENABLED"; + attribute GSR of FF_246 : label is "ENABLED"; + attribute GSR of FF_245 : label is "ENABLED"; + attribute GSR of FF_244 : label is "ENABLED"; + attribute GSR of FF_243 : label is "ENABLED"; + attribute GSR of FF_242 : label is "ENABLED"; + attribute GSR of FF_241 : label is "ENABLED"; + attribute GSR of FF_240 : label is "ENABLED"; + attribute GSR of FF_239 : label is "ENABLED"; + attribute GSR of FF_238 : label is "ENABLED"; + attribute GSR of FF_237 : label is "ENABLED"; + attribute GSR of FF_236 : label is "ENABLED"; + attribute GSR of FF_235 : label is "ENABLED"; + attribute GSR of FF_234 : label is "ENABLED"; + attribute GSR of FF_233 : label is "ENABLED"; + attribute GSR of FF_232 : label is "ENABLED"; + attribute GSR of FF_231 : label is "ENABLED"; + attribute GSR of FF_230 : label is "ENABLED"; + attribute GSR of FF_229 : label is "ENABLED"; + attribute GSR of FF_228 : label is "ENABLED"; + attribute GSR of FF_227 : label is "ENABLED"; + attribute GSR of FF_226 : label is "ENABLED"; + attribute GSR of FF_225 : label is "ENABLED"; + attribute GSR of FF_224 : label is "ENABLED"; + attribute GSR of FF_223 : label is "ENABLED"; + attribute GSR of FF_222 : label is "ENABLED"; + attribute GSR of FF_221 : label is "ENABLED"; + attribute GSR of FF_220 : label is "ENABLED"; + attribute GSR of FF_219 : label is "ENABLED"; + attribute GSR of FF_218 : label is "ENABLED"; + attribute GSR of FF_217 : label is "ENABLED"; + attribute GSR of FF_216 : label is "ENABLED"; + attribute GSR of FF_215 : label is "ENABLED"; + attribute GSR of FF_214 : label is "ENABLED"; + attribute GSR of FF_213 : label is "ENABLED"; + attribute GSR of FF_212 : label is "ENABLED"; + attribute GSR of FF_211 : label is "ENABLED"; + attribute GSR of FF_210 : label is "ENABLED"; + attribute GSR of FF_209 : label is "ENABLED"; + attribute GSR of FF_208 : label is "ENABLED"; + attribute GSR of FF_207 : label is "ENABLED"; + attribute GSR of FF_206 : label is "ENABLED"; + attribute GSR of FF_205 : label is "ENABLED"; + attribute GSR of FF_204 : label is "ENABLED"; + attribute GSR of FF_203 : label is "ENABLED"; + attribute GSR of FF_202 : label is "ENABLED"; + attribute GSR of FF_201 : label is "ENABLED"; + attribute GSR of FF_200 : label is "ENABLED"; + attribute GSR of FF_199 : label is "ENABLED"; + attribute GSR of FF_198 : label is "ENABLED"; + attribute GSR of FF_197 : label is "ENABLED"; + attribute GSR of FF_196 : label is "ENABLED"; + attribute GSR of FF_195 : label is "ENABLED"; + attribute GSR of FF_194 : label is "ENABLED"; + attribute GSR of FF_193 : label is "ENABLED"; + attribute GSR of FF_192 : label is "ENABLED"; + attribute GSR of FF_191 : label is "ENABLED"; + attribute GSR of FF_190 : label is "ENABLED"; + attribute GSR of FF_189 : label is "ENABLED"; + attribute GSR of FF_188 : label is "ENABLED"; + attribute GSR of FF_187 : label is "ENABLED"; + attribute GSR of FF_186 : label is "ENABLED"; + attribute GSR of FF_185 : label is "ENABLED"; + attribute GSR of FF_184 : label is "ENABLED"; + attribute GSR of FF_183 : label is "ENABLED"; + attribute GSR of FF_182 : label is "ENABLED"; + attribute GSR of FF_181 : label is "ENABLED"; + attribute GSR of FF_180 : label is "ENABLED"; + attribute GSR of FF_179 : label is "ENABLED"; + attribute GSR of FF_178 : label is "ENABLED"; + attribute GSR of FF_177 : label is "ENABLED"; + attribute GSR of FF_176 : label is "ENABLED"; + attribute GSR of FF_175 : label is "ENABLED"; + attribute GSR of FF_174 : label is "ENABLED"; + attribute GSR of FF_173 : label is "ENABLED"; + attribute GSR of FF_172 : label is "ENABLED"; + attribute GSR of FF_171 : label is "ENABLED"; + attribute GSR of FF_170 : label is "ENABLED"; + attribute GSR of FF_169 : label is "ENABLED"; + attribute GSR of FF_168 : label is "ENABLED"; + attribute GSR of FF_167 : label is "ENABLED"; + attribute GSR of FF_166 : label is "ENABLED"; + attribute GSR of FF_165 : label is "ENABLED"; + attribute GSR of FF_164 : label is "ENABLED"; + attribute GSR of FF_163 : label is "ENABLED"; + attribute GSR of FF_162 : label is "ENABLED"; + attribute GSR of FF_161 : label is "ENABLED"; + attribute GSR of FF_160 : label is "ENABLED"; + attribute GSR of FF_159 : label is "ENABLED"; + attribute GSR of FF_158 : label is "ENABLED"; + attribute GSR of FF_157 : label is "ENABLED"; + attribute GSR of FF_156 : label is "ENABLED"; + attribute GSR of FF_155 : label is "ENABLED"; + attribute GSR of FF_154 : label is "ENABLED"; + attribute GSR of FF_153 : label is "ENABLED"; + attribute GSR of FF_152 : label is "ENABLED"; + attribute GSR of FF_151 : label is "ENABLED"; + attribute GSR of FF_150 : label is "ENABLED"; + attribute GSR of FF_149 : label is "ENABLED"; + attribute GSR of FF_148 : label is "ENABLED"; + attribute GSR of FF_147 : label is "ENABLED"; + attribute GSR of FF_146 : label is "ENABLED"; + attribute GSR of FF_145 : label is "ENABLED"; + attribute GSR of FF_144 : label is "ENABLED"; + attribute GSR of FF_143 : label is "ENABLED"; + attribute GSR of FF_142 : label is "ENABLED"; + attribute GSR of FF_141 : label is "ENABLED"; + attribute GSR of FF_140 : label is "ENABLED"; + attribute GSR of FF_139 : label is "ENABLED"; + attribute GSR of FF_138 : label is "ENABLED"; + attribute GSR of FF_137 : label is "ENABLED"; + attribute GSR of FF_136 : label is "ENABLED"; + attribute GSR of FF_135 : label is "ENABLED"; + attribute GSR of FF_134 : label is "ENABLED"; + attribute GSR of FF_133 : label is "ENABLED"; + attribute GSR of FF_132 : label is "ENABLED"; + attribute GSR of FF_131 : label is "ENABLED"; + attribute GSR of FF_130 : label is "ENABLED"; + attribute GSR of FF_129 : label is "ENABLED"; + attribute GSR of FF_128 : label is "ENABLED"; + attribute GSR of FF_127 : label is "ENABLED"; + attribute GSR of FF_126 : label is "ENABLED"; + attribute GSR of FF_125 : label is "ENABLED"; + attribute GSR of FF_124 : label is "ENABLED"; + attribute GSR of FF_123 : label is "ENABLED"; + attribute GSR of FF_122 : label is "ENABLED"; + attribute GSR of FF_121 : label is "ENABLED"; + attribute GSR of FF_120 : label is "ENABLED"; + attribute GSR of FF_119 : label is "ENABLED"; + attribute GSR of FF_118 : label is "ENABLED"; + attribute GSR of FF_117 : label is "ENABLED"; + attribute GSR of FF_116 : label is "ENABLED"; + attribute GSR of FF_115 : label is "ENABLED"; + attribute GSR of FF_114 : label is "ENABLED"; + attribute GSR of FF_113 : label is "ENABLED"; + attribute GSR of FF_112 : label is "ENABLED"; + attribute GSR of FF_111 : label is "ENABLED"; + attribute GSR of FF_110 : label is "ENABLED"; + attribute GSR of FF_109 : label is "ENABLED"; + attribute GSR of FF_108 : label is "ENABLED"; + attribute GSR of FF_107 : label is "ENABLED"; + attribute GSR of FF_106 : label is "ENABLED"; + attribute GSR of FF_105 : label is "ENABLED"; + attribute GSR of FF_104 : label is "ENABLED"; + attribute GSR of FF_103 : label is "ENABLED"; + attribute GSR of FF_102 : label is "ENABLED"; + attribute GSR of FF_101 : label is "ENABLED"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + + FF_303 : FD1P3DX + port map (D => tsum(303), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(303)); + FF_302 : FD1P3DX + port map (D => tsum(302), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(302)); + FF_301 : FD1P3DX + port map (D => tsum(301), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(301)); + FF_300 : FD1P3DX + port map (D => tsum(300), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(300)); + FF_299 : FD1P3DX + port map (D => tsum(299), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(299)); + FF_298 : FD1P3DX + port map (D => tsum(298), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(298)); + FF_297 : FD1P3DX + port map (D => tsum(297), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(297)); + FF_296 : FD1P3DX + port map (D => tsum(296), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(296)); + FF_295 : FD1P3DX + port map (D => tsum(295), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(295)); + FF_294 : FD1P3DX + port map (D => tsum(294), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(294)); + FF_293 : FD1P3DX + port map (D => tsum(293), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(293)); + FF_292 : FD1P3DX + port map (D => tsum(292), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(292)); + FF_291 : FD1P3DX + port map (D => tsum(291), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(291)); + FF_290 : FD1P3DX + port map (D => tsum(290), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(290)); + FF_289 : FD1P3DX + port map (D => tsum(289), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(289)); + FF_288 : FD1P3DX + port map (D => tsum(288), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(288)); + FF_287 : FD1P3DX + port map (D => tsum(287), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(287)); + FF_286 : FD1P3DX + port map (D => tsum(286), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(286)); + FF_285 : FD1P3DX + port map (D => tsum(285), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(285)); + FF_284 : FD1P3DX + port map (D => tsum(284), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(284)); + FF_283 : FD1P3DX + port map (D => tsum(283), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(283)); + FF_282 : FD1P3DX + port map (D => tsum(282), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(282)); + FF_281 : FD1P3DX + port map (D => tsum(281), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(281)); + FF_280 : FD1P3DX + port map (D => tsum(280), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(280)); + FF_279 : FD1P3DX + port map (D => tsum(279), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(279)); + FF_278 : FD1P3DX + port map (D => tsum(278), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(278)); + FF_277 : FD1P3DX + port map (D => tsum(277), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(277)); + FF_276 : FD1P3DX + port map (D => tsum(276), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(276)); + FF_275 : FD1P3DX + port map (D => tsum(275), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(275)); + FF_274 : FD1P3DX + port map (D => tsum(274), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(274)); + FF_273 : FD1P3DX + port map (D => tsum(273), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(273)); + FF_272 : FD1P3DX + port map (D => tsum(272), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(272)); + FF_271 : FD1P3DX + port map (D => tsum(271), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(271)); + FF_270 : FD1P3DX + port map (D => tsum(270), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(270)); + FF_269 : FD1P3DX + port map (D => tsum(269), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(269)); + FF_268 : FD1P3DX + port map (D => tsum(268), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(268)); + FF_267 : FD1P3DX + port map (D => tsum(267), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(267)); + FF_266 : FD1P3DX + port map (D => tsum(266), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(266)); + FF_265 : FD1P3DX + port map (D => tsum(265), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(265)); + FF_264 : FD1P3DX + port map (D => tsum(264), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(264)); + FF_263 : FD1P3DX + port map (D => tsum(263), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(263)); + FF_262 : FD1P3DX + port map (D => tsum(262), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(262)); + FF_261 : FD1P3DX + port map (D => tsum(261), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(261)); + FF_260 : FD1P3DX + port map (D => tsum(260), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(260)); + FF_259 : FD1P3DX + port map (D => tsum(259), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(259)); + FF_258 : FD1P3DX + port map (D => tsum(258), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(258)); + FF_257 : FD1P3DX + port map (D => tsum(257), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(257)); + FF_256 : FD1P3DX + port map (D => tsum(256), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(256)); + FF_255 : FD1P3DX + port map (D => tsum(255), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(255)); + FF_254 : FD1P3DX + port map (D => tsum(254), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(254)); + FF_253 : FD1P3DX + port map (D => tsum(253), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(253)); + FF_252 : FD1P3DX + port map (D => tsum(252), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(252)); + FF_251 : FD1P3DX + port map (D => tsum(251), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(251)); + FF_250 : FD1P3DX + port map (D => tsum(250), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(250)); + FF_249 : FD1P3DX + port map (D => tsum(249), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(249)); + FF_248 : FD1P3DX + port map (D => tsum(248), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(248)); + FF_247 : FD1P3DX + port map (D => tsum(247), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(247)); + FF_246 : FD1P3DX + port map (D => tsum(246), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(246)); + FF_245 : FD1P3DX + port map (D => tsum(245), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(245)); + FF_244 : FD1P3DX + port map (D => tsum(244), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(244)); + FF_243 : FD1P3DX + port map (D => tsum(243), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(243)); + FF_242 : FD1P3DX + port map (D => tsum(242), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(242)); + FF_241 : FD1P3DX + port map (D => tsum(241), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(241)); + FF_240 : FD1P3DX + port map (D => tsum(240), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(240)); + FF_239 : FD1P3DX + port map (D => tsum(239), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(239)); + FF_238 : FD1P3DX + port map (D => tsum(238), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(238)); + FF_237 : FD1P3DX + port map (D => tsum(237), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(237)); + FF_236 : FD1P3DX + port map (D => tsum(236), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(236)); + FF_235 : FD1P3DX + port map (D => tsum(235), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(235)); + FF_234 : FD1P3DX + port map (D => tsum(234), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(234)); + FF_233 : FD1P3DX + port map (D => tsum(233), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(233)); + FF_232 : FD1P3DX + port map (D => tsum(232), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(232)); + FF_231 : FD1P3DX + port map (D => tsum(231), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(231)); + FF_230 : FD1P3DX + port map (D => tsum(230), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(230)); + FF_229 : FD1P3DX + port map (D => tsum(229), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(229)); + FF_228 : FD1P3DX + port map (D => tsum(228), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(228)); + FF_227 : FD1P3DX + port map (D => tsum(227), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(227)); + FF_226 : FD1P3DX + port map (D => tsum(226), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(226)); + FF_225 : FD1P3DX + port map (D => tsum(225), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(225)); + FF_224 : FD1P3DX + port map (D => tsum(224), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(224)); + FF_223 : FD1P3DX + port map (D => tsum(223), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(223)); + FF_222 : FD1P3DX + port map (D => tsum(222), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(222)); + FF_221 : FD1P3DX + port map (D => tsum(221), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(221)); + FF_220 : FD1P3DX + port map (D => tsum(220), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(220)); + FF_219 : FD1P3DX + port map (D => tsum(219), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(219)); + FF_218 : FD1P3DX + port map (D => tsum(218), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(218)); + FF_217 : FD1P3DX + port map (D => tsum(217), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(217)); + FF_216 : FD1P3DX + port map (D => tsum(216), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(216)); + FF_215 : FD1P3DX + port map (D => tsum(215), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(215)); + FF_214 : FD1P3DX + port map (D => tsum(214), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(214)); + FF_213 : FD1P3DX + port map (D => tsum(213), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(213)); + FF_212 : FD1P3DX + port map (D => tsum(212), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(212)); + FF_211 : FD1P3DX + port map (D => tsum(211), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(211)); + FF_210 : FD1P3DX + port map (D => tsum(210), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(210)); + FF_209 : FD1P3DX + port map (D => tsum(209), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(209)); + FF_208 : FD1P3DX + port map (D => tsum(208), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(208)); + FF_207 : FD1P3DX + port map (D => tsum(207), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(207)); + FF_206 : FD1P3DX + port map (D => tsum(206), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(206)); + FF_205 : FD1P3DX + port map (D => tsum(205), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(205)); + FF_204 : FD1P3DX + port map (D => tsum(204), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(204)); + FF_203 : FD1P3DX + port map (D => tsum(203), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(203)); + FF_202 : FD1P3DX + port map (D => tsum(202), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(202)); + FF_201 : FD1P3DX + port map (D => tsum(201), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(201)); + FF_200 : FD1P3DX + port map (D => tsum(200), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(200)); + FF_199 : FD1P3DX + port map (D => tsum(199), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(199)); + FF_198 : FD1P3DX + port map (D => tsum(198), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(198)); + FF_197 : FD1P3DX + port map (D => tsum(197), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(197)); + FF_196 : FD1P3DX + port map (D => tsum(196), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(196)); + FF_195 : FD1P3DX + port map (D => tsum(195), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(195)); + FF_194 : FD1P3DX + port map (D => tsum(194), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(194)); + FF_193 : FD1P3DX + port map (D => tsum(193), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(193)); + FF_192 : FD1P3DX + port map (D => tsum(192), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(192)); + FF_191 : FD1P3DX + port map (D => tsum(191), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(191)); + FF_190 : FD1P3DX + port map (D => tsum(190), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(190)); + FF_189 : FD1P3DX + port map (D => tsum(189), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(189)); + FF_188 : FD1P3DX + port map (D => tsum(188), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(188)); + FF_187 : FD1P3DX + port map (D => tsum(187), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(187)); + FF_186 : FD1P3DX + port map (D => tsum(186), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(186)); + FF_185 : FD1P3DX + port map (D => tsum(185), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(185)); + FF_184 : FD1P3DX + port map (D => tsum(184), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(184)); + FF_183 : FD1P3DX + port map (D => tsum(183), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(183)); + FF_182 : FD1P3DX + port map (D => tsum(182), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(182)); + FF_181 : FD1P3DX + port map (D => tsum(181), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(181)); + FF_180 : FD1P3DX + port map (D => tsum(180), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(180)); + FF_179 : FD1P3DX + port map (D => tsum(179), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(179)); + FF_178 : FD1P3DX + port map (D => tsum(178), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(178)); + FF_177 : FD1P3DX + port map (D => tsum(177), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(177)); + FF_176 : FD1P3DX + port map (D => tsum(176), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(176)); + FF_175 : FD1P3DX + port map (D => tsum(175), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(175)); + FF_174 : FD1P3DX + port map (D => tsum(174), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(174)); + FF_173 : FD1P3DX + port map (D => tsum(173), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(173)); + FF_172 : FD1P3DX + port map (D => tsum(172), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(172)); + FF_171 : FD1P3DX + port map (D => tsum(171), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(171)); + FF_170 : FD1P3DX + port map (D => tsum(170), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(170)); + FF_169 : FD1P3DX + port map (D => tsum(169), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(169)); + FF_168 : FD1P3DX + port map (D => tsum(168), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(168)); + FF_167 : FD1P3DX + port map (D => tsum(167), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(167)); + FF_166 : FD1P3DX + port map (D => tsum(166), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(166)); + FF_165 : FD1P3DX + port map (D => tsum(165), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(165)); + FF_164 : FD1P3DX + port map (D => tsum(164), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(164)); + FF_163 : FD1P3DX + port map (D => tsum(163), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(163)); + FF_162 : FD1P3DX + port map (D => tsum(162), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(162)); + FF_161 : FD1P3DX + port map (D => tsum(161), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(161)); + FF_160 : FD1P3DX + port map (D => tsum(160), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(160)); + FF_159 : FD1P3DX + port map (D => tsum(159), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(159)); + FF_158 : FD1P3DX + port map (D => tsum(158), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(158)); + FF_157 : FD1P3DX + port map (D => tsum(157), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(157)); + FF_156 : FD1P3DX + port map (D => tsum(156), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(156)); + FF_155 : FD1P3DX + port map (D => tsum(155), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(155)); + FF_154 : FD1P3DX + port map (D => tsum(154), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(154)); + FF_153 : FD1P3DX + port map (D => tsum(153), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(153)); + FF_152 : FD1P3DX + port map (D => tsum(152), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(152)); + FF_151 : FD1P3DX + port map (D => tsum(151), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(151)); + FF_150 : FD1P3DX + port map (D => tsum(150), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(150)); + FF_149 : FD1P3DX + port map (D => tsum(149), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(149)); + FF_148 : FD1P3DX + port map (D => tsum(148), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(148)); + FF_147 : FD1P3DX + port map (D => tsum(147), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(147)); + FF_146 : FD1P3DX + port map (D => tsum(146), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(146)); + FF_145 : FD1P3DX + port map (D => tsum(145), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(145)); + FF_144 : FD1P3DX + port map (D => tsum(144), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(144)); + FF_143 : FD1P3DX + port map (D => tsum(143), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(143)); + FF_142 : FD1P3DX + port map (D => tsum(142), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(142)); + FF_141 : FD1P3DX + port map (D => tsum(141), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(141)); + FF_140 : FD1P3DX + port map (D => tsum(140), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(140)); + FF_139 : FD1P3DX + port map (D => tsum(139), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(139)); + FF_138 : FD1P3DX + port map (D => tsum(138), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(138)); + FF_137 : FD1P3DX + port map (D => tsum(137), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(137)); + FF_136 : FD1P3DX + port map (D => tsum(136), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(136)); + FF_135 : FD1P3DX + port map (D => tsum(135), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(135)); + FF_134 : FD1P3DX + port map (D => tsum(134), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(134)); + FF_133 : FD1P3DX + port map (D => tsum(133), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(133)); + FF_132 : FD1P3DX + port map (D => tsum(132), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(132)); + FF_131 : FD1P3DX + port map (D => tsum(131), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(131)); + FF_130 : FD1P3DX + port map (D => tsum(130), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(130)); + FF_129 : FD1P3DX + port map (D => tsum(129), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(129)); + FF_128 : FD1P3DX + port map (D => tsum(128), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(128)); + FF_127 : FD1P3DX + port map (D => tsum(127), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(127)); + FF_126 : FD1P3DX + port map (D => tsum(126), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(126)); + FF_125 : FD1P3DX + port map (D => tsum(125), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(125)); + FF_124 : FD1P3DX + port map (D => tsum(124), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(124)); + FF_123 : FD1P3DX + port map (D => tsum(123), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(123)); + FF_122 : FD1P3DX + port map (D => tsum(122), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(122)); + FF_121 : FD1P3DX + port map (D => tsum(121), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(121)); + FF_120 : FD1P3DX + port map (D => tsum(120), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(120)); + FF_119 : FD1P3DX + port map (D => tsum(119), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(119)); + FF_118 : FD1P3DX + port map (D => tsum(118), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(118)); + FF_117 : FD1P3DX + port map (D => tsum(117), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(117)); + FF_116 : FD1P3DX + port map (D => tsum(116), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(116)); + FF_115 : FD1P3DX + port map (D => tsum(115), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(115)); + FF_114 : FD1P3DX + port map (D => tsum(114), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(114)); + FF_113 : FD1P3DX + port map (D => tsum(113), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(113)); + FF_112 : FD1P3DX + port map (D => tsum(112), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(112)); + FF_111 : FD1P3DX + port map (D => tsum(111), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(111)); + FF_110 : FD1P3DX + port map (D => tsum(110), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(110)); + FF_109 : FD1P3DX + port map (D => tsum(109), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(109)); + FF_108 : FD1P3DX + port map (D => tsum(108), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(108)); + FF_107 : FD1P3DX + port map (D => tsum(107), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(107)); + FF_106 : FD1P3DX + port map (D => tsum(106), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(106)); + FF_105 : FD1P3DX + port map (D => tsum(105), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(105)); + FF_104 : FD1P3DX + port map (D => tsum(104), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(104)); + FF_103 : FD1P3DX + port map (D => tsum(103), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(103)); + FF_102 : FD1P3DX + port map (D => tsum(102), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(102)); + FF_101 : FD1P3DX + port map (D => tsum(101), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(101)); + FF_100 : FD1P3DX + port map (D => tsum(100), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(100)); + FF_99 : FD1P3DX + port map (D => tsum(99), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(99)); + FF_98 : FD1P3DX + port map (D => tsum(98), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(98)); + FF_97 : FD1P3DX + port map (D => tsum(97), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(97)); + FF_96 : FD1P3DX + port map (D => tsum(96), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(96)); + FF_95 : FD1P3DX + port map (D => tsum(95), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(95)); + FF_94 : FD1P3DX + port map (D => tsum(94), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(94)); + FF_93 : FD1P3DX + port map (D => tsum(93), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(93)); + FF_92 : FD1P3DX + port map (D => tsum(92), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(92)); + FF_91 : FD1P3DX + port map (D => tsum(91), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(91)); + FF_90 : FD1P3DX + port map (D => tsum(90), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(90)); + FF_89 : FD1P3DX + port map (D => tsum(89), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(89)); + FF_88 : FD1P3DX + port map (D => tsum(88), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(88)); + FF_87 : FD1P3DX + port map (D => tsum(87), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(87)); + FF_86 : FD1P3DX + port map (D => tsum(86), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(86)); + FF_85 : FD1P3DX + port map (D => tsum(85), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(85)); + FF_84 : FD1P3DX + port map (D => tsum(84), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(84)); + FF_83 : FD1P3DX + port map (D => tsum(83), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(83)); + FF_82 : FD1P3DX + port map (D => tsum(82), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(82)); + FF_81 : FD1P3DX + port map (D => tsum(81), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(81)); + FF_80 : FD1P3DX + port map (D => tsum(80), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(80)); + FF_79 : FD1P3DX + port map (D => tsum(79), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(79)); + FF_78 : FD1P3DX + port map (D => tsum(78), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(78)); + FF_77 : FD1P3DX + port map (D => tsum(77), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(77)); + FF_76 : FD1P3DX + port map (D => tsum(76), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(76)); + FF_75 : FD1P3DX + port map (D => tsum(75), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(75)); + FF_74 : FD1P3DX + port map (D => tsum(74), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(74)); + FF_73 : FD1P3DX + port map (D => tsum(73), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(73)); + FF_72 : FD1P3DX + port map (D => tsum(72), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(72)); + FF_71 : FD1P3DX + port map (D => tsum(71), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(71)); + FF_70 : FD1P3DX + port map (D => tsum(70), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(70)); + FF_69 : FD1P3DX + port map (D => tsum(69), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(69)); + FF_68 : FD1P3DX + port map (D => tsum(68), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(68)); + FF_67 : FD1P3DX + port map (D => tsum(67), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(67)); + FF_66 : FD1P3DX + port map (D => tsum(66), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(66)); + FF_65 : FD1P3DX + port map (D => tsum(65), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(65)); + FF_64 : FD1P3DX + port map (D => tsum(64), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(64)); + FF_63 : FD1P3DX + port map (D => tsum(63), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(63)); + FF_62 : FD1P3DX + port map (D => tsum(62), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(62)); + FF_61 : FD1P3DX + port map (D => tsum(61), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(61)); + FF_60 : FD1P3DX + port map (D => tsum(60), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(60)); + FF_59 : FD1P3DX + port map (D => tsum(59), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(59)); + FF_58 : FD1P3DX + port map (D => tsum(58), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(58)); + FF_57 : FD1P3DX + port map (D => tsum(57), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(57)); + FF_56 : FD1P3DX + port map (D => tsum(56), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(56)); + FF_55 : FD1P3DX + port map (D => tsum(55), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(55)); + FF_54 : FD1P3DX + port map (D => tsum(54), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(54)); + FF_53 : FD1P3DX + port map (D => tsum(53), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(53)); + FF_52 : FD1P3DX + port map (D => tsum(52), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(52)); + FF_51 : FD1P3DX + port map (D => tsum(51), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(51)); + FF_50 : FD1P3DX + port map (D => tsum(50), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(50)); + FF_49 : FD1P3DX + port map (D => tsum(49), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(49)); + FF_48 : FD1P3DX + port map (D => tsum(48), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(48)); + FF_47 : FD1P3DX + port map (D => tsum(47), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(47)); + FF_46 : FD1P3DX + port map (D => tsum(46), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(46)); + FF_45 : FD1P3DX + port map (D => tsum(45), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(45)); + FF_44 : FD1P3DX + port map (D => tsum(44), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(44)); + FF_43 : FD1P3DX + port map (D => tsum(43), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(43)); + FF_42 : FD1P3DX + port map (D => tsum(42), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(42)); + FF_41 : FD1P3DX + port map (D => tsum(41), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(41)); + FF_40 : FD1P3DX + port map (D => tsum(40), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(40)); + FF_39 : FD1P3DX + port map (D => tsum(39), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(39)); + FF_38 : FD1P3DX + port map (D => tsum(38), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(38)); + FF_37 : FD1P3DX + port map (D => tsum(37), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(37)); + FF_36 : FD1P3DX + port map (D => tsum(36), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(36)); + FF_35 : FD1P3DX + port map (D => tsum(35), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(35)); + FF_34 : FD1P3DX + port map (D => tsum(34), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(34)); + FF_33 : FD1P3DX + port map (D => tsum(33), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(33)); + FF_32 : FD1P3DX + port map (D => tsum(32), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(32)); + FF_31 : FD1P3DX + port map (D => tsum(31), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(31)); + FF_30 : FD1P3DX + port map (D => tsum(30), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(30)); + FF_29 : FD1P3DX + port map (D => tsum(29), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(29)); + FF_28 : FD1P3DX + port map (D => tsum(28), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(28)); + FF_27 : FD1P3DX + port map (D => tsum(27), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(27)); + FF_26 : FD1P3DX + port map (D => tsum(26), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(26)); + FF_25 : FD1P3DX + port map (D => tsum(25), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(25)); + FF_24 : FD1P3DX + port map (D => tsum(24), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(24)); + FF_23 : FD1P3DX + port map (D => tsum(23), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(23)); + FF_22 : FD1P3DX + port map (D => tsum(22), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(22)); + FF_21 : FD1P3DX + port map (D => tsum(21), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(21)); + FF_20 : FD1P3DX + port map (D => tsum(20), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(20)); + FF_19 : FD1P3DX + port map (D => tsum(19), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(19)); + FF_18 : FD1P3DX + port map (D => tsum(18), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(18)); + FF_17 : FD1P3DX + port map (D => tsum(17), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(17)); + FF_16 : FD1P3DX + port map (D => tsum(16), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(16)); + FF_15 : FD1P3DX + port map (D => tsum(15), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(15)); + FF_14 : FD1P3DX + port map (D => tsum(14), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(14)); + FF_13 : FD1P3DX + port map (D => tsum(13), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(13)); + FF_12 : FD1P3DX + port map (D => tsum(12), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(12)); + FF_11 : FD1P3DX + port map (D => tsum(11), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(11)); + FF_10 : FD1P3DX + port map (D => tsum(10), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(10)); + FF_9 : FD1P3DX + port map (D => tsum(9), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(9)); + FF_8 : FD1P3DX + port map (D => tsum(8), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(8)); + FF_7 : FD1P3DX + port map (D => tsum(7), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(7)); + FF_6 : FD1P3DX + port map (D => tsum(6), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(6)); + FF_5 : FD1P3DX + port map (D => tsum(5), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(5)); + FF_4 : FD1P3DX + port map (D => tsum(4), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(4)); + FF_3 : FD1P3DX + port map (D => tsum(3), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(3)); + FF_2 : FD1P3DX + port map (D => tsum(2), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(2)); + FF_1 : FD1P3DX + port map (D => tsum(1), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(1)); + FF_0 : FD1P3DX + port map (D => tsum(0), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(0)); + + GEN_0_ADD : FADD2B + port map (A0 => DataA(0), + A1 => DataA(1), + B0 => DataB(0), + B1 => DataB(1), + CI => scuba_vlo, + COUT => co(0), + S0 => tsum(0), + S1 => tsum(1)); + + GEN : for i in 1 to 151 generate + ADD : FADD2B + port map (A0 => DataA(2*i), + A1 => DataA(2*i+1), + B0 => DataB(2*i), + B1 => DataB(2*i+1), + CI => co(i-1), + COUT => co(i), + S0 => tsum(2*i), + S1 => tsum(2*i+1)); + end generate GEN; + + scuba_vlo_inst : VLO + port map (Z => scuba_vlo); + + Result <= r0_sum; + +end Structure; + + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of adder_304 is + for Structure + for all : FADD2B use entity ecp3.FADD2B(V); end for; + for all : FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all : VLO use entity ecp3.VLO(V); end for; + end for; +end Structure_CON; +-- synopsys translate_on diff --git a/tdc_releases/tdc_v1.4/BusHandler.vhd b/tdc_releases/tdc_v1.4/BusHandler.vhd new file mode 100644 index 0000000..932cfe8 --- /dev/null +++ b/tdc_releases/tdc_v1.4/BusHandler.vhd @@ -0,0 +1,89 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.version.all; + +entity BusHandler is + generic ( + BUS_LENGTH : integer range 0 to 64 := 2); + port ( + RESET : in std_logic; + CLK : in std_logic; +-- + DATA_IN : in std_logic_vector_array_32(0 to BUS_LENGTH); + READ_EN_IN : in std_logic; + WRITE_EN_IN : in std_logic; + ADDR_IN : in std_logic_vector(6 downto 0); + DATA_OUT : out std_logic_vector(31 downto 0); + DATAREADY_OUT : out std_logic; + UNKNOWN_ADDR_OUT : out std_logic); +end BusHandler; + +architecture Behavioral of BusHandler is + + --Output signals + signal data_out_reg : std_logic_vector(31 downto 0); + signal data_ready_reg : std_logic; + signal unknown_addr_reg : std_logic; + signal read_en_i : std_logic; + signal write_en_i : std_logic; + signal addr_i : std_logic_vector(6 downto 0); + +begin + + read_en_i <= READ_EN_IN when rising_edge(CLK); + write_en_i <= WRITE_EN_IN when rising_edge(CLK); + addr_i <= ADDR_IN when rising_edge(CLK); + + READ_WRITE_RESPONSE : process (CLK, RESET) + begin + if rising_edge(CLK) then + if RESET = '1' then + data_out_reg <= (others => '0'); + data_ready_reg <= '0'; + unknown_addr_reg <= '0'; + elsif read_en_i = '1' then + if to_integer(unsigned(addr_i)) > BUS_LENGTH then -- if bigger than 64 + data_out_reg <= (others => '0'); + data_ready_reg <= '0'; + unknown_addr_reg <= '1'; + else + data_out_reg <= DATA_IN(to_integer(unsigned(addr_i))); + data_ready_reg <= '1'; + unknown_addr_reg <= '0'; + end if; + elsif write_en_i = '1' then + data_out_reg <= (others => '0'); + data_ready_reg <= '0'; + unknown_addr_reg <= '1'; + else + data_out_reg <= (others => '0'); + data_ready_reg <= '0'; + unknown_addr_reg <= '0'; + end if; + end if; + end process READ_WRITE_RESPONSE; + + + --FifoWriteSignal : process (CLK) + --begin + -- if rising_edge(CLK) then + -- if RESET = '1' then + -- unknown_addr_reg <= '0'; + -- else + -- unknown_addr_reg <= '1'; + -- end if; + -- end if; + --end process FifoWriteSignal; + + DATA_OUT <= data_out_reg; + DATAREADY_OUT <= data_ready_reg; + UNKNOWN_ADDR_OUT <= unknown_addr_reg; + +end Behavioral; + diff --git a/tdc_releases/tdc_v1.4/Channel.vhd b/tdc_releases/tdc_v1.4/Channel.vhd new file mode 100644 index 0000000..1f6d6df --- /dev/null +++ b/tdc_releases/tdc_v1.4/Channel.vhd @@ -0,0 +1,236 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.version.all; + +entity Channel is + + generic ( + CHANNEL_ID : integer range 0 to 64); + port ( + RESET_200 : in std_logic; + RESET_100 : in std_logic; + RESET_COUNTERS : in std_logic; + CLK_200 : in std_logic; + CLK_100 : in std_logic; +-- + HIT_IN : in std_logic; + TRIGGER_WIN_END_IN : in std_logic; + READ_EN_IN : in std_logic; + FIFO_DATA_OUT : out std_logic_vector(35 downto 0); + FIFO_WCNT_OUT : out unsigned(7 downto 0); + FIFO_EMPTY_OUT : out std_logic; + FIFO_FULL_OUT : out std_logic; + FIFO_ALMOST_FULL_OUT : out std_logic; + COARSE_COUNTER_IN : in std_logic_vector(10 downto 0); + EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0); +-- DATA_FINISHED_IN : in std_logic; +-- + LOST_HIT_NUMBER : out std_logic_vector(23 downto 0); + HIT_DETECT_NUMBER : out std_logic_vector(23 downto 0); + ENCODER_START_NUMBER : out std_logic_vector(23 downto 0); + ENCODER_FINISHED_NUMBER : out std_logic_vector(23 downto 0); +-- + Channel_DEBUG : out std_logic_vector(31 downto 0) + ); + +end Channel; + +architecture Channel of Channel is +------------------------------------------------------------------------------- +-- Signal Declarations +------------------------------------------------------------------------------- + + -- hit signals + signal hit_in_i : std_logic; + signal hit_buf : std_logic; + + -- time stamp + signal coarse_cntr_reg : std_logic_vector(10 downto 0); + signal trig_win_end_i : std_logic; + + -- debug + signal sync_q : std_logic_vector(2 downto 0); + signal hit_pulse : std_logic; + signal hit_pulse_100 : std_logic; + signal encoder_start_i : std_logic; + signal encoder_start_100 : std_logic; + signal encoder_finished_i : std_logic; + signal encoder_finished_100 : std_logic; + signal lost_hit_cntr : unsigned(23 downto 0) := (others => '0'); + signal hit_detect_cntr : unsigned(23 downto 0) := (others => '0'); + signal encoder_start_cntr : unsigned(23 downto 0) := (others => '0'); + signal encoder_finished_cntr : unsigned(23 downto 0) := (others => '0'); + + -- other +-- signal data_finished_i : std_logic; + +------------------------------------------------------------------------------- + + attribute syn_keep : boolean; + attribute syn_keep of hit_buf : signal is true; + attribute syn_preserve : boolean; + attribute syn_preserve of coarse_cntr_reg : signal is true; + attribute syn_preserve of hit_buf : signal is true; + attribute syn_preserve of trig_win_end_i : signal is true; + attribute nomerge : string; + attribute nomerge of hit_buf : signal is "true"; + +------------------------------------------------------------------------------- + +begin + + hit_in_i <= HIT_IN; + hit_buf <= not hit_in_i; + + Channel_200_1 : Channel_200 + generic map ( + CHANNEL_ID => CHANNEL_ID) + port map ( + CLK_200 => CLK_200, + RESET_200 => RESET_200, + CLK_100 => CLK_100, + RESET_100 => RESET_100, + HIT_IN => hit_buf, + TRIGGER_WIN_END_IN => trig_win_end_i, + EPOCH_COUNTER_IN => EPOCH_COUNTER_IN, +-- DATA_FINISHED_IN => data_finished_i, + COARSE_COUNTER_IN => coarse_cntr_reg, + READ_EN_IN => READ_EN_IN, + FIFO_DATA_OUT => FIFO_DATA_OUT, + FIFO_WCNT_OUT => FIFO_WCNT_OUT, + FIFO_EMPTY_OUT => FIFO_EMPTY_OUT, + FIFO_FULL_OUT => FIFO_FULL_OUT, + FIFO_ALMOST_FULL_OUT => FIFO_ALMOST_FULL_OUT, + ENCODER_START_OUT => encoder_start_i, + ENCODER_FINISHED_OUT => encoder_finished_i); + + trig_win_end_i <= TRIGGER_WIN_END_IN when rising_edge(CLK_200); +-- data_finished_i <= DATA_FINISHED_IN when rising_edge(CLK_100); + + pulse_sync_encoder_start : pulse_sync + port map ( + CLK_A_IN => CLK_200, + RESET_A_IN => RESET_200, + PULSE_A_IN => encoder_start_i, + CLK_B_IN => CLK_100, + RESET_B_IN => RESET_100, + PULSE_B_OUT => encoder_start_100); + + pulse_sync_encoder_finished : pulse_sync + port map ( + CLK_A_IN => CLK_200, + RESET_A_IN => RESET_200, + PULSE_A_IN => encoder_finished_i, + CLK_B_IN => CLK_100, + RESET_B_IN => RESET_100, + PULSE_B_OUT => encoder_finished_100); + + CoarseCounter : ShiftRegisterSISO + generic map ( + DEPTH => 1, + WIDTH => 11) + port map ( + CLK => CLK_200, + D_IN => COARSE_COUNTER_IN, + D_OUT => coarse_cntr_reg); + +------------------------------------------------------------------------------- +-- DEBUG Counters +------------------------------------------------------------------------------- + --purpose: Hit Signal Synchroniser + sync_q(0) <= HIT_IN when rising_edge(CLK_200); + sync_q(1) <= sync_q(0) when rising_edge(CLK_200); + sync_q(2) <= sync_q(1) when rising_edge(CLK_200); + + edge_to_pulse_1 : edge_to_pulse + port map ( + clock => CLK_200, + en_clk => '1', + signal_in => sync_q(2), + pulse => hit_pulse); + + pulse_sync_hit : pulse_sync + port map ( + CLK_A_IN => CLK_200, + RESET_A_IN => RESET_200, + PULSE_A_IN => hit_pulse, + CLK_B_IN => CLK_100, + RESET_B_IN => RESET_100, + PULSE_B_OUT => hit_pulse_100); + + --purpose: Counts the detected but unwritten hits + Lost_Hit_Counter : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + lost_hit_cntr <= (others => '0'); + elsif hit_pulse_100 = '1' then + lost_hit_cntr <= lost_hit_cntr + to_unsigned(1, 1); + elsif encoder_finished_100 = '1' then + lost_hit_cntr <= lost_hit_cntr - to_unsigned(1, 1); + end if; + end if; + end process Lost_Hit_Counter; + + LOST_HIT_NUMBER <= std_logic_vector(lost_hit_cntr) when rising_edge(CLK_100); + + --purpose: Counts the detected hits + Hit_Detect_Counter : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + hit_detect_cntr <= (others => '0'); + elsif hit_pulse_100 = '1' then + hit_detect_cntr <= hit_detect_cntr + to_unsigned(1, 1); + end if; + end if; + end process Hit_Detect_Counter; + + HIT_DETECT_NUMBER <= std_logic_vector(hit_detect_cntr) when rising_edge(CLK_100); + + --purpose: Counts the encoder start times + Encoder_Start_Counter : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + encoder_start_cntr <= (others => '0'); + elsif encoder_start_100 = '1' then + encoder_start_cntr <= encoder_start_cntr + to_unsigned(1, 1); + end if; + end if; + end process Encoder_Start_Counter; + + ENCODER_START_NUMBER <= std_logic_vector(encoder_start_cntr) when rising_edge(CLK_100); + + --purpose: Counts the written hits + Encoder_Finished_Counter : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + encoder_finished_cntr <= (others => '0'); + elsif encoder_finished_100 = '1' then + encoder_finished_cntr <= encoder_finished_cntr + to_unsigned(1, 1); + end if; + end if; + end process Encoder_Finished_Counter; + + ENCODER_FINISHED_NUMBER <= std_logic_vector(encoder_finished_cntr) when rising_edge(CLK_100); + + --Channel_DEBUG(0) <= HIT_IN; + --Channel_DEBUG(1) <= result_2_reg; + --Channel_DEBUG(2) <= hit_detect_i; + --Channel_DEBUG(3) <= hit_detect_reg; + --Channel_DEBUG(4) <= '0'; + --Channel_DEBUG(5) <= ff_array_en_i; + --Channel_DEBUG(6) <= encoder_start_i; + --Channel_DEBUG(7) <= encoder_finished_i; + --Channel_DEBUG(15 downto 8) <= result_i(7 downto 0); + --Channel_DEBUG(31 downto 16) <= (others => '0'); + +end Channel; diff --git a/tdc_releases/tdc_v1.4/Channel_200.vhd b/tdc_releases/tdc_v1.4/Channel_200.vhd new file mode 100644 index 0000000..23fe1d2 --- /dev/null +++ b/tdc_releases/tdc_v1.4/Channel_200.vhd @@ -0,0 +1,278 @@ +------------------------------------------------------------------------------- +-- Title : Channel 200 MHz Part +-- Project : +------------------------------------------------------------------------------- +-- File : Channel_200.vhd +-- Author : c.ugur@gsi.de +-- Created : 2012-08-28 +-- Last update: 2013-03-19 +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- + +library IEEE; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.version.all; + +entity Channel_200 is + + generic ( + CHANNEL_ID : integer range 0 to 64); + port ( + CLK_200 : in std_logic; -- 200 MHz clk + RESET_200 : in std_logic; -- reset sync with 200Mhz clk + CLK_100 : in std_logic; -- 100 MHz clk + RESET_100 : in std_logic; -- reset sync with 100Mhz clk +-- + HIT_IN : in std_logic; -- hit in + TRIGGER_WIN_END_IN : in std_logic; -- trigger in + EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0); -- system coarse counter +-- DATA_FINISHED_IN : in std_logic; + COARSE_COUNTER_IN : in std_logic_vector(10 downto 0); + READ_EN_IN : in std_logic; -- read en signal + FIFO_DATA_OUT : out std_logic_vector(35 downto 0); -- fifo data out + FIFO_WCNT_OUT : out unsigned(7 downto 0); -- fifo write counter out + FIFO_EMPTY_OUT : out std_logic; -- fifo empty signal + FIFO_FULL_OUT : out std_logic; -- fifo full signal + FIFO_ALMOST_FULL_OUT : out std_logic; +-- + ENCODER_START_OUT : out std_logic; + ENCODER_FINISHED_OUT : out std_logic); + + +end Channel_200; + +architecture Channel_200 of Channel_200 is + + -- carry chain + signal data_a_i : std_logic_vector(303 downto 0); + signal data_b_i : std_logic_vector(303 downto 0); + signal result_i : std_logic_vector(303 downto 0); + signal ff_array_en_i : std_logic; + + -- hit detection + signal result_2_reg : std_logic; + signal hit_detect_i : std_logic; + signal hit_detect_reg : std_logic; + signal hit_detect_2reg : std_logic; + + -- time stamp + signal time_stamp_i : std_logic_vector(10 downto 0); + signal coarse_cntr_reg : std_logic_vector(10 downto 0); + + -- encoder + signal encoder_start_i : std_logic; + signal encoder_finished_i : std_logic; + signal encoder_data_out_i : std_logic_vector(9 downto 0); + signal encoder_info_i : std_logic_vector(1 downto 0); + signal encoder_debug_i : std_logic_vector(31 downto 0); + + -- epoch counter + signal epoch_cntr : std_logic_vector(27 downto 0); + signal epoch_cntr_updated : std_logic := '0'; + signal epoch_capture_time : std_logic_vector(10 downto 0); + + -- fifo + signal fifo_data_out_i : std_logic_vector(35 downto 0); + signal fifo_data_in_i : std_logic_vector(35 downto 0); + signal fifo_wcnt_i : std_logic_vector(7 downto 0); + signal fifo_empty_i : std_logic; + signal fifo_full_i : std_logic; + signal fifo_almost_full_i : std_logic := '0'; + signal fifo_wr_en_i : std_logic; + signal fifo_rd_en_i : std_logic; + + -- fsm + type FSM is (WRITE_EPOCH, WRITE_DATA, WAIT_FOR_HIT); + signal FSM_CURRENT : FSM := WRITE_EPOCH; + signal FSM_NEXT : FSM; + signal write_epoch_fsm : std_logic; + signal write_epoch_i : std_logic; + signal write_data_fsm : std_logic; + signal write_data_i : std_logic; + signal fsm_debug_fsm : std_logic_vector(1 downto 0); + signal fsm_debug_i : std_logic_vector(1 downto 0); + + attribute syn_keep : boolean; + attribute syn_keep of ff_array_en_i : signal is true; + +begin -- Channel_200 + + --purpose: Tapped Delay Line 304 (Carry Chain) with wave launcher (21) double transition + FC : Adder_304 + port map ( + CLK => CLK_200, + RESET => RESET_200, + DataA => data_a_i, + DataB => data_b_i, + ClkEn => ff_array_en_i, + Result => result_i); + data_a_i <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" & x"7FFFFFF"; + data_b_i <= x"000000000000000000000000000000000000000000000000000000000000000000000" & not(HIT_IN) & x"000000" & "00" & HIT_IN; + ff_array_en_i <= not(hit_detect_i or hit_detect_reg); -- or hit_detect_2reg); + + result_2_reg <= result_i(2) when rising_edge(CLK_200); + hit_detect_i <= (not result_2_reg) and result_i(2); -- detects the hit by + -- comparing the + -- previous state of the + -- hit detection bit + hit_detect_reg <= hit_detect_i when rising_edge(CLK_200); + hit_detect_2reg <= hit_detect_reg when rising_edge(CLK_200); + coarse_cntr_reg <= COARSE_COUNTER_IN when rising_edge(CLK_200); + encoder_start_i <= hit_detect_i; + ENCODER_START_OUT <= encoder_start_i; + + TimeStampCapture : process (CLK_200) + begin + if rising_edge(CLK_200) then + if hit_detect_reg = '1' then + time_stamp_i <= coarse_cntr_reg; + end if; + end if; + end process TimeStampCapture; + + epoch_capture_time <= "00000000111"; + + EpochCounterCapture : process (CLK_200) + begin + if rising_edge(CLK_200) then + if coarse_cntr_reg = epoch_capture_time or TRIGGER_WIN_END_IN = '1' then --DATA_FINISHED_IN = '1' then + epoch_cntr <= EPOCH_COUNTER_IN; + epoch_cntr_updated <= '1'; + elsif write_epoch_i = '1' then + epoch_cntr_updated <= '0'; + end if; + end if; + end process EpochCounterCapture; + + --purpose: Encoder + Encoder : Encoder_304_Bit + port map ( + RESET => RESET_200, + CLK => CLK_200, + START_IN => encoder_start_i, + THERMOCODE_IN => result_i, + FINISHED_OUT => encoder_finished_i, + BINARY_CODE_OUT => encoder_data_out_i, + ENCODER_INFO_OUT => encoder_info_i, + ENCODER_DEBUG => encoder_debug_i); + + FIFO : FIFO_36x128_OutReg_Counter + port map ( + Data => fifo_data_in_i, + WrClock => CLK_200, + RdClock => CLK_100, + WrEn => fifo_wr_en_i, + RdEn => fifo_rd_en_i, + Reset => RESET_100, + RPReset => RESET_200, + Q => fifo_data_out_i, + WCNT => fifo_wcnt_i, + Empty => fifo_empty_i, + Full => fifo_full_i); + + fifo_rd_en_i <= READ_EN_IN or fifo_full_i; + + -- Readout fsm + FSM_CLK : process (CLK_200, RESET_200) + begin + if rising_edge(CLK_200) then + FSM_CURRENT <= FSM_NEXT; + write_epoch_i <= write_epoch_fsm; + write_data_i <= write_data_fsm; + fsm_debug_i <= fsm_debug_fsm; + end if; + end process FSM_CLK; + + FSM_PROC : process (FSM_CURRENT, encoder_finished_i, epoch_cntr_updated) --, TRIGGER_IN) + begin + + FSM_NEXT <= WAIT_FOR_HIT; + write_epoch_fsm <= '0'; + write_data_fsm <= '0'; + fsm_debug_fsm <= "00"; + + case (FSM_CURRENT) is + when WRITE_EPOCH => + if encoder_finished_i = '1' then + write_epoch_fsm <= '1'; + FSM_NEXT <= WRITE_DATA; + else + write_epoch_fsm <= '0'; + FSM_NEXT <= WRITE_EPOCH; + end if; + fsm_debug_fsm <= "01"; + + when WRITE_DATA => + write_data_fsm <= '1'; + FSM_NEXT <= WAIT_FOR_HIT; + fsm_debug_fsm <= "10"; + + when WAIT_FOR_HIT => + if epoch_cntr_updated = '1' then -- or TRIGGER_IN = '1' then + FSM_NEXT <= WRITE_EPOCH; + else + if encoder_finished_i = '1' and epoch_cntr_updated = '1' then + write_epoch_fsm <= '1'; + FSM_NEXT <= WRITE_DATA; + elsif encoder_finished_i = '1' and epoch_cntr_updated = '0' then + write_data_fsm <= '1'; + FSM_NEXT <= WAIT_FOR_HIT; + else + write_data_fsm <= '0'; + FSM_NEXT <= WAIT_FOR_HIT; + end if; + end if; + fsm_debug_fsm <= "11"; + + when others => + FSM_NEXT <= WRITE_EPOCH; + fsm_debug_fsm <= "00"; + end case; + end process FSM_PROC; + + -- purpose: Generate Fifo Wr Signal + FifoWriteSignal : process (CLK_200) + begin + if rising_edge(CLK_200) then + if write_epoch_i = '1' then + fifo_data_in_i(31 downto 29) <= "011"; + fifo_data_in_i(28) <= '0'; + fifo_data_in_i(27 downto 0) <= epoch_cntr; + fifo_wr_en_i <= '1'; + elsif write_data_i = '1' then + fifo_data_in_i(31) <= '1'; -- data marker + fifo_data_in_i(30) <= '0'; -- reserved bits + fifo_data_in_i(29) <= encoder_info_i(0); -- low resolution info bit + fifo_data_in_i(28 downto 22) <= std_logic_vector(to_unsigned(CHANNEL_ID, 7)); -- channel number + fifo_data_in_i(21 downto 12) <= encoder_data_out_i; -- fine time from the encoder + fifo_data_in_i(11) <= '1'; --edge_type_i; -- rising '1' or falling '0' edge + fifo_data_in_i(10 downto 0) <= time_stamp_i; -- hit time stamp + fifo_wr_en_i <= '1'; + else + fifo_data_in_i <= (others => '0'); + fifo_wr_en_i <= '0'; + end if; + end if; + end process FifoWriteSignal; + + ENCODER_FINISHED_OUT <= encoder_finished_i; + + RegisterOutputs : process (CLK_100) + begin + if rising_edge(CLK_100) then + FIFO_DATA_OUT <= fifo_data_out_i; + FIFO_WCNT_OUT <= unsigned(fifo_wcnt_i); + FIFO_EMPTY_OUT <= fifo_empty_i; + FIFO_FULL_OUT <= fifo_full_i; + FIFO_ALMOST_FULL_OUT <= fifo_almost_full_i; + end if; + end process RegisterOutputs; + +end Channel_200; diff --git a/tdc_releases/tdc_v1.4/Encoder_304_Bit.vhd b/tdc_releases/tdc_v1.4/Encoder_304_Bit.vhd new file mode 100644 index 0000000..1a403e0 --- /dev/null +++ b/tdc_releases/tdc_v1.4/Encoder_304_Bit.vhd @@ -0,0 +1,428 @@ +------------------------------------------------------------------------------- +-- Title : Encoder 304 bits +------------------------------------------------------------------------------- +-- File : Encoder_304_Bit.vhd +-- Author : Cahit Ugur +-- Created : 2011-11-28 +-- Last update: 2013-03-17 +------------------------------------------------------------------------------- +-- Description: Encoder for 304 bits +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2011-11-28 1.0 ugur Created +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb3_components.all; + +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity Encoder_304_Bit is + port ( + RESET : in std_logic; -- system reset + CLK : in std_logic; -- system clock + START_IN : in std_logic; + THERMOCODE_IN : in std_logic_vector(303 downto 0); + FINISHED_OUT : out std_logic; + BINARY_CODE_OUT : out std_logic_vector(9 downto 0); + ENCODER_INFO_OUT : out std_logic_vector(1 downto 0); + ENCODER_DEBUG : out std_logic_vector(31 downto 0) + ); +end Encoder_304_Bit; + +architecture behavioral of Encoder_304_Bit is + +------------------------------------------------------------------------------- +-- Component Declarations +------------------------------------------------------------------------------- + component LUT4 + generic ( + INIT : std_logic_vector); + port ( + A, B, C, D : in std_ulogic; + Z : out std_ulogic); + end component; + +------------------------------------------------------------------------------- +-- Signal Declarations +------------------------------------------------------------------------------- + signal P_lut : std_logic_vector(37 downto 0); + signal P_one : std_logic_vector(37 downto 0); + signal mux_control : std_logic_vector(5 downto 0); + signal mux_control_reg : std_logic_vector(5 downto 0); + signal mux_control_2reg : std_logic_vector(5 downto 0); + signal mux_control_3reg : std_logic_vector(5 downto 0); + signal interval_reg : std_logic_vector(8 downto 0); + signal interval_binary : std_logic_vector(2 downto 0); + signal binary_code_f : std_logic_vector(8 downto 0); + signal binary_code_r : std_logic_vector(8 downto 0); + signal start_reg : std_logic; + signal start_2reg : std_logic; + signal address_i : std_logic_vector(9 downto 0); + signal q_reg : std_logic_vector(7 downto 0); + signal info : std_logic_vector(1 downto 0); + signal info_reg : std_logic_vector(1 downto 0); + signal info_2reg : std_logic_vector(1 downto 0); + signal info_3reg : std_logic_vector(1 downto 0); + signal info_4reg : std_logic_vector(1 downto 0); + +-- FSM signals + type FSM is (IDLE, START_CNT_2, START_CNT_3, START_CNT_4); + signal FSM_CURRENT, FSM_NEXT : FSM; + + signal start_cnt_1_fsm : std_logic; + signal start_cnt_2_fsm : std_logic; + signal start_cnt_3_fsm : std_logic; + signal start_cnt_4_fsm : std_logic; + signal start_cnt_1_i : std_logic; + signal start_cnt_2_i : std_logic; + signal start_cnt_3_i : std_logic; + signal start_cnt_4_i : std_logic; +-- + signal proc_cnt_1 : std_logic_vector(3 downto 0) := x"6"; + signal proc_cnt_2 : std_logic_vector(3 downto 0) := x"6"; + signal proc_cnt_3 : std_logic_vector(3 downto 0) := x"6"; + signal proc_cnt_4 : std_logic_vector(3 downto 0); + signal proc_finished_1 : std_logic; + signal proc_finished_2 : std_logic; + signal proc_finished_3 : std_logic; + signal proc_finished_4 : std_logic; + signal conv_finished_i : std_logic; + signal thermocode_i : std_logic_vector(304 downto 0); + + attribute syn_keep : boolean; + attribute syn_keep of mux_control : signal is true; + attribute syn_keep of mux_control_reg : signal is true; + attribute syn_keep of mux_control_2reg : signal is true; + attribute syn_keep of mux_control_3reg : signal is true; +------------------------------------------------------------------------------- +begin + + + thermocode_i(304 downto 1) <= THERMOCODE_IN; + thermocode_i(0) <= '1'; + start_reg <= START_IN when rising_edge(CLK); + start_2reg <= start_reg when rising_edge(CLK); + mux_control_reg <= mux_control when rising_edge(CLK); + mux_control_2reg <= mux_control_reg when rising_edge(CLK); + mux_control_3reg <= mux_control_2reg when rising_edge(CLK); + + Interval_Determination_First : LUT4 + generic map (INIT => X"15A8") + port map (A => '1', B => '1', C => THERMOCODE_IN(0), D => START_IN, + Z => P_lut(0)); + + Interval_Determination : for i in 1 to 37 generate + U : LUT4 + generic map (INIT => X"15A8") + port map (A => THERMOCODE_IN(8*i-2), B => THERMOCODE_IN(8*i-1), C => THERMOCODE_IN(8*i), D => START_IN, + Z => P_lut(i)); + end generate Interval_Determination; +------------------------------------------------------------------------------- + + Gen_P_one : for i in 0 to 36 generate + P_one(i) <= P_lut(i) and (not P_lut(i+1)) when rising_edge(CLK); + end generate Gen_P_one; + + P_one_assign : process (CLK) + begin + if rising_edge(CLK) then + if START_IN = '0' then + P_one(37) <= '0'; + else + P_one(37) <= P_lut(37); + end if; + end if; + end process P_one_assign; + + Interval_Number_to_Binary : process (CLK) + begin -- The interval number with the 0-1 transition is converted from 1-of-N code to binary + -- code for the control of the MUX. + if rising_edge(CLK) then + if start_2reg = '1' or start_reg = '1' then + mux_control(0) <= P_one(0) or P_one(2) or P_one(4) or P_one(6) or P_one(8) or P_one(10) or + P_one(12) or P_one(14) or P_one(16) or P_one(18) or P_one(20) or P_one(22) or + P_one(24) or P_one(26) or P_one(28) or P_one(30) or P_one(32) or P_one(34) or + P_one(36); + mux_control(1) <= P_one(1) or P_one(2) or P_one(5) or P_one(6) or P_one(9) or P_one(10) or + P_one(13) or P_one(14) or P_one(17) or P_one(18) or P_one(21) or P_one(22) or + P_one(25) or P_one(26) or P_one(29) or P_one(30) or P_one(33) or P_one(34) or + P_one(37); + mux_control(2) <= P_one(3) or P_one(4) or P_one(5) or P_one(6) or P_one(11) or P_one(12) or + P_one(13) or P_one(14) or P_one(19) or P_one(20) or P_one(21) or P_one(22) or + P_one(27) or P_one(28) or P_one(29) or P_one(30) or P_one(35) or P_one(36) or + P_one(37); + mux_control(3) <= P_one(7) or P_one(8) or P_one(9) or P_one(10) or P_one(11) or P_one(12) or + P_one(13) or P_one(14) or P_one(23) or P_one(24) or P_one(25) or P_one(26) or + P_one(27) or P_one(28) or P_one(29) or P_one(30); + mux_control(4) <= P_one(15) or P_one(16) or P_one(17) or P_one(18) or P_one(19) or P_one(20) or + P_one(21) or P_one(22) or P_one(23) or P_one(24) or P_one(25) or P_one(26) or + P_one(27) or P_one(28) or P_one(29) or P_one(30); + mux_control(5) <= P_one(31) or P_one(32) or P_one(33) or P_one(34) or P_one(35) or P_one(36) or + P_one(37); + else + mux_control <= (others => '0'); + end if; + end if; + end process Interval_Number_to_Binary; + + Interval_Selection : process (CLK) + variable tmp : std_logic_vector(9 downto 1); + begin -- The interval with the 0-1 transition is selected. + if rising_edge(CLK) then + tmp := (others => '0'); + make_mux : for i in 0 to 37 loop + make_mux_2 : for j in 1 to 9 loop + tmp(j) := tmp(j) or (thermocode_i(i*8-1+j) and P_one(i)); + end loop; + end loop; + interval_reg <= tmp; + end if; + end process Interval_Selection; + + ROM_Encoder_1 : ROM_Encoder + port map ( + Address => address_i, + OutClock => CLK, + OutClockEn => '1', + Reset => RESET, + Q => q_reg); + + --ROM4_Encoder_1 : ROM4_Encoder + -- port map ( + -- Address => address_i, + -- OutClock => CLK, + -- OutClockEn => '1', + -- Reset => RESET, + -- Q => q_reg); + address_i <= start_2reg & interval_reg; + interval_binary <= q_reg(2 downto 0) when rising_edge(CLK); + info <= q_reg(7 downto 6) when rising_edge(CLK); + info_reg <= info when rising_edge(CLK); + info_2reg <= info_reg when rising_edge(CLK); + info_3reg <= info_2reg when rising_edge(CLK); + info_4reg <= info_3reg when rising_edge(CLK); + + Binary_Code_Calculation_rf : process (CLK) + begin + if rising_edge(CLK) then + binary_code_r <= (mux_control_3reg - 1) & interval_binary; + binary_code_f <= binary_code_r; + end if; + end process Binary_Code_Calculation_rf; + + --purpose: FSMs the encoder + FSM_CLK : process (CLK) + begin + if rising_edge(CLK) then + FSM_CURRENT <= FSM_NEXT; + start_cnt_1_i <= start_cnt_1_fsm; + start_cnt_2_i <= start_cnt_2_fsm; + start_cnt_3_i <= start_cnt_3_fsm; + start_cnt_4_i <= start_cnt_4_fsm; + end if; + end process FSM_CLK; + + FSM_PROC : process (FSM_CURRENT, START_IN) + begin + + FSM_NEXT <= IDLE; + start_cnt_1_fsm <= '0'; + start_cnt_2_fsm <= '0'; + start_cnt_3_fsm <= '0'; + start_cnt_4_fsm <= '0'; + + case (FSM_CURRENT) is + when IDLE => + if START_IN = '1' then + FSM_NEXT <= START_CNT_2; + start_cnt_1_fsm <= '1'; + end if; + + when START_CNT_2 => + if START_IN = '1' then + FSM_NEXT <= START_CNT_3; + start_cnt_2_fsm <= '1'; + else + FSM_NEXT <= START_CNT_2; + end if; + + when START_CNT_3 => + if START_IN = '1' then + FSM_NEXT <= START_CNT_4; + start_cnt_3_fsm <= '1'; + else + FSM_NEXT <= START_CNT_3; + end if; + + when START_CNT_4 => + if START_IN = '1' then + FSM_NEXT <= IDLE; + start_cnt_4_fsm <= '1'; + else + FSM_NEXT <= START_CNT_4; + end if; + + when others => + FSM_NEXT <= IDLE; + end case; + end process FSM_PROC; + + --purpose : Conversion number 1 + Conv_1 : process (CLK) + begin + if rising_edge(CLK) then + if start_cnt_1_i = '1' then + proc_cnt_1 <= x"1"; + proc_finished_1 <= '0'; + elsif proc_cnt_1 = x"5" then + proc_cnt_1 <= proc_cnt_1 + 1; + proc_finished_1 <= '1'; + elsif proc_cnt_1 = x"6" then + proc_cnt_1 <= x"6"; + proc_finished_1 <= '0'; + else + proc_cnt_1 <= proc_cnt_1 + 1; + proc_finished_1 <= '0'; + end if; + end if; + end process Conv_1; + + --purpose : Conversion number 2 + Conv_2 : process (CLK) + begin + if rising_edge(CLK) then + if start_cnt_2_i = '1' then + proc_cnt_2 <= x"1"; + proc_finished_2 <= '0'; + elsif proc_cnt_2 = x"5" then + proc_cnt_2 <= proc_cnt_2 + 1; + proc_finished_2 <= '1'; + elsif proc_cnt_2 = x"6" then + proc_cnt_2 <= x"6"; + proc_finished_2 <= '0'; + else + proc_cnt_2 <= proc_cnt_2 + 1; + proc_finished_2 <= '0'; + end if; + end if; + end process Conv_2; + + --purpose : Conversion number 3 + Conv_3 : process (CLK) + begin + if rising_edge(CLK) then + if start_cnt_3_i = '1' then + proc_cnt_3 <= x"1"; + proc_finished_3 <= '0'; + elsif proc_cnt_3 = x"5" then + proc_cnt_3 <= proc_cnt_3 + 1; + proc_finished_3 <= '1'; + elsif proc_cnt_3 = x"6" then + proc_cnt_3 <= x"6"; + proc_finished_3 <= '0'; + else + proc_cnt_3 <= proc_cnt_3 + 1; + proc_finished_3 <= '0'; + end if; + end if; + end process Conv_3; + + --purpose : Conversion number 4 + Conv_4 : process (CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + proc_cnt_4 <= x"6"; + proc_finished_4 <= '0'; + elsif start_cnt_4_i = '1' then + proc_cnt_4 <= x"1"; + proc_finished_4 <= '0'; + elsif proc_cnt_4 = x"5" then + proc_cnt_4 <= proc_cnt_4 + 1; + proc_finished_4 <= '1'; + elsif proc_cnt_4 = x"6" then + proc_cnt_4 <= x"6"; + proc_finished_4 <= '0'; + else + proc_cnt_4 <= proc_cnt_4 + 1; + proc_finished_4 <= '0'; + end if; + end if; + end process Conv_4; + + Binary_Code_Calculation : process (CLK) + begin + if rising_edge(CLK) then + if conv_finished_i = '1' then + if info_reg(1) = '1' and info_2reg(1) = '1' then + BINARY_CODE_OUT <= ('0' & binary_code_r) + ('0' & binary_code_f); + else + BINARY_CODE_OUT <= (others => '1'); + end if; + ENCODER_INFO_OUT <= (others => '0'); --info_reg or info_2reg; + FINISHED_OUT <= '1'; + else + FINISHED_OUT <= '0'; + end if; + end if; + end process Binary_Code_Calculation; + + conv_finished_i <= proc_finished_1 or proc_finished_2 or proc_finished_3 or proc_finished_4; + + +------------------------------------------------------------------------------- +-- DEBUG +------------------------------------------------------------------------------- + ----purpose : Conversion number 1 + --Conv_1 : process (CLK, RESET) + --begin + -- if rising_edge(CLK) then + -- if RESET = '1' then + -- proc_cnt_1 <= x"3"; + -- proc_finished_1 <= '0'; + -- elsif START_IN = '1' then + -- proc_cnt_1 <= x"1"; + -- proc_finished_1 <= '0'; + -- elsif proc_cnt_1 = x"1" or proc_cnt_1 = x"2" then + -- proc_cnt_1 <= proc_cnt_1 + 1; + -- proc_finished_1 <= '1'; + -- elsif proc_cnt_1 = x"3" then + -- proc_cnt_1 <= x"3"; + -- proc_finished_1 <= '0'; + -- else + -- proc_cnt_1 <= proc_cnt_1 + 1; + -- proc_finished_1 <= '0'; + -- end if; + -- end if; + --end process Conv_1; + + --Binary_Code_Calculation : process (CLK, RESET) + --begin + -- if rising_edge(CLK) then + -- if RESET = '1' then + -- BINARY_CODE_OUT <= (others => '0'); + -- FINISHED_OUT <= '0'; + -- elsif proc_finished_1 = '1' then + -- BINARY_CODE_OUT <= address_i; --'0' & interval_reg; + -- FINISHED_OUT <= '1'; + -- else + -- BINARY_CODE_OUT <= (others => '0'); + -- FINISHED_OUT <= '0'; + -- end if; + -- end if; + --end process Binary_Code_Calculation; + + --ENCODER_DEBUG(8 downto 0) <= interval_reg; + +end behavioral; diff --git a/tdc_releases/tdc_v1.4/FIFO_36x128_OutReg_Counter.vhd b/tdc_releases/tdc_v1.4/FIFO_36x128_OutReg_Counter.vhd new file mode 100644 index 0000000..14b4942 --- /dev/null +++ b/tdc_releases/tdc_v1.4/FIFO_36x128_OutReg_Counter.vhd @@ -0,0 +1,1094 @@ +-- VHDL netlist generated by SCUBA Diamond_2.0_Production (151) +-- Module Version: 5.4 +--/opt/lattice/diamond/2.01/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 128 -width 36 -depth 128 -rdata_width 36 -regout -no_enable -pe -1 -pf -1 -fill -e + +-- Wed Jan 30 11:50:36 2013 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity FIFO_36x128_OutReg_Counter is + port ( + Data : in std_logic_vector(35 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + RPReset : in std_logic; + Q : out std_logic_vector(35 downto 0); + WCNT : out std_logic_vector(7 downto 0); + Empty : out std_logic; + Full : out std_logic); +end FIFO_36x128_OutReg_Counter; + +architecture Structure of FIFO_36x128_OutReg_Counter is + + -- internal signal declarations + signal invout_1 : std_logic; + signal invout_0 : std_logic; + signal w_g2b_xor_cluster_1 : std_logic; + signal r_g2b_xor_cluster_1 : std_logic; + signal w_gdata_0 : std_logic; + signal w_gdata_1 : std_logic; + signal w_gdata_2 : std_logic; + signal w_gdata_3 : std_logic; + signal w_gdata_4 : std_logic; + signal w_gdata_5 : std_logic; + signal w_gdata_6 : std_logic; + signal wptr_7 : std_logic; + signal r_gdata_0 : std_logic; + signal r_gdata_1 : std_logic; + signal r_gdata_2 : std_logic; + signal r_gdata_3 : std_logic; + signal r_gdata_4 : std_logic; + signal r_gdata_5 : std_logic; + signal r_gdata_6 : std_logic; + signal rptr_0 : std_logic; + signal rptr_1 : std_logic; + signal rptr_2 : std_logic; + signal rptr_3 : std_logic; + signal rptr_4 : std_logic; + signal rptr_5 : std_logic; + signal rptr_6 : std_logic; + signal rptr_7 : std_logic; + signal w_gcount_0 : std_logic; + signal w_gcount_1 : std_logic; + signal w_gcount_2 : std_logic; + signal w_gcount_3 : std_logic; + signal w_gcount_4 : std_logic; + signal w_gcount_5 : std_logic; + signal w_gcount_6 : std_logic; + signal w_gcount_7 : std_logic; + signal r_gcount_0 : std_logic; + signal r_gcount_1 : std_logic; + signal r_gcount_2 : std_logic; + signal r_gcount_3 : std_logic; + signal r_gcount_4 : std_logic; + signal r_gcount_5 : std_logic; + signal r_gcount_6 : std_logic; + signal r_gcount_7 : std_logic; + signal w_gcount_r20 : std_logic; + signal w_gcount_r0 : std_logic; + signal w_gcount_r21 : std_logic; + signal w_gcount_r1 : std_logic; + signal w_gcount_r22 : std_logic; + signal w_gcount_r2 : std_logic; + signal w_gcount_r23 : std_logic; + signal w_gcount_r3 : std_logic; + signal w_gcount_r24 : std_logic; + signal w_gcount_r4 : std_logic; + signal w_gcount_r25 : std_logic; + signal w_gcount_r5 : std_logic; + signal w_gcount_r26 : std_logic; + signal w_gcount_r6 : std_logic; + signal w_gcount_r27 : std_logic; + signal w_gcount_r7 : std_logic; + signal r_gcount_w20 : std_logic; + signal r_gcount_w0 : std_logic; + signal r_gcount_w21 : std_logic; + signal r_gcount_w1 : std_logic; + signal r_gcount_w22 : std_logic; + signal r_gcount_w2 : std_logic; + signal r_gcount_w23 : std_logic; + signal r_gcount_w3 : std_logic; + signal r_gcount_w24 : std_logic; + signal r_gcount_w4 : std_logic; + signal r_gcount_w25 : std_logic; + signal r_gcount_w5 : std_logic; + signal r_gcount_w26 : std_logic; + signal r_gcount_w6 : std_logic; + signal r_gcount_w27 : std_logic; + signal r_gcount_w7 : std_logic; + signal empty_i : std_logic; + signal rRst : std_logic; + signal full_i : std_logic; + signal iwcount_0 : std_logic; + signal iwcount_1 : std_logic; + signal w_gctr_ci : std_logic; + signal iwcount_2 : std_logic; + signal iwcount_3 : std_logic; + signal co0 : std_logic; + signal iwcount_4 : std_logic; + signal iwcount_5 : std_logic; + signal co1 : std_logic; + signal iwcount_6 : std_logic; + signal iwcount_7 : std_logic; + signal co3 : std_logic; + signal wcount_7 : std_logic; + signal co2 : std_logic; + signal ircount_0 : std_logic; + signal ircount_1 : std_logic; + signal r_gctr_ci : std_logic; + signal ircount_2 : std_logic; + signal ircount_3 : std_logic; + signal co0_1 : std_logic; + signal ircount_4 : std_logic; + signal ircount_5 : std_logic; + signal co1_1 : std_logic; + signal ircount_6 : std_logic; + signal ircount_7 : std_logic; + signal co3_1 : std_logic; + signal rcount_7 : std_logic; + signal co2_1 : std_logic; + signal wfill_sub_0 : std_logic; + signal scuba_vhi : std_logic; + signal wptr_0 : std_logic; + signal wfill_sub_1 : std_logic; + signal wfill_sub_2 : std_logic; + signal co0_2 : std_logic; + signal wptr_1 : std_logic; + signal wptr_2 : std_logic; + signal wfill_sub_3 : std_logic; + signal wfill_sub_4 : std_logic; + signal co1_2 : std_logic; + signal wptr_3 : std_logic; + signal wptr_4 : std_logic; + signal wfill_sub_5 : std_logic; + signal wfill_sub_6 : std_logic; + signal co2_2 : std_logic; + signal wptr_5 : std_logic; + signal wptr_6 : std_logic; + signal wfill_sub_7 : std_logic; + signal co3_2 : std_logic; + signal wfill_sub_msb : std_logic; + signal rden_i : std_logic; + signal cmp_ci : std_logic; + signal wcount_r0 : std_logic; + signal wcount_r1 : std_logic; + signal rcount_0 : std_logic; + signal rcount_1 : std_logic; + signal co0_3 : std_logic; + signal wcount_r2 : std_logic; + signal wcount_r3 : std_logic; + signal rcount_2 : std_logic; + signal rcount_3 : std_logic; + signal co1_3 : std_logic; + signal w_g2b_xor_cluster_0 : std_logic; + signal wcount_r5 : std_logic; + signal rcount_4 : std_logic; + signal rcount_5 : std_logic; + signal co2_3 : std_logic; + signal wcount_r6 : std_logic; + signal empty_cmp_clr : std_logic; + signal rcount_6 : std_logic; + signal empty_cmp_set : std_logic; + signal empty_d : std_logic; + signal empty_d_c : std_logic; + signal wren_i : std_logic; + signal cmp_ci_1 : std_logic; + signal rcount_w0 : std_logic; + signal rcount_w1 : std_logic; + signal wcount_0 : std_logic; + signal wcount_1 : std_logic; + signal co0_4 : std_logic; + signal rcount_w2 : std_logic; + signal rcount_w3 : std_logic; + signal wcount_2 : std_logic; + signal wcount_3 : std_logic; + signal co1_4 : std_logic; + signal r_g2b_xor_cluster_0 : std_logic; + signal rcount_w5 : std_logic; + signal wcount_4 : std_logic; + signal wcount_5 : std_logic; + signal co2_4 : std_logic; + signal rcount_w6 : std_logic; + signal full_cmp_clr : std_logic; + signal wcount_6 : std_logic; + signal full_cmp_set : std_logic; + signal full_d : std_logic; + signal full_d_c : std_logic; + signal scuba_vlo : std_logic; + + -- local component declarations + component AGEB2 + port (A0 : in std_logic; A1 : in std_logic; B0 : in std_logic; + B1 : in std_logic; CI : in std_logic; GE : out std_logic); + end component; + component AND2 + port (A : in std_logic; B : in std_logic; Z : out std_logic); + end component; + component CU2 + port (CI : in std_logic; PC0 : in std_logic; PC1 : in std_logic; + CO : out std_logic; NC0 : out std_logic; NC1 : out std_logic); + end component; + component FADD2B + port (A0 : in std_logic; A1 : in std_logic; B0 : in std_logic; + B1 : in std_logic; CI : in std_logic; COUT : out std_logic; + S0 : out std_logic; S1 : out std_logic); + end component; + component FSUB2B + port (A0 : in std_logic; A1 : in std_logic; B0 : in std_logic; + B1 : in std_logic; BI : in std_logic; BOUT : out std_logic; + S0 : out std_logic; S1 : out std_logic); + end component; + component FD1P3BX + port (D : in std_logic; SP : in std_logic; CK : in std_logic; + PD : in std_logic; Q : out std_logic); + end component; + component FD1P3DX + port (D : in std_logic; SP : in std_logic; CK : in std_logic; + CD : in std_logic; Q : out std_logic); + end component; + component FD1S3BX + port (D : in std_logic; CK : in std_logic; PD : in std_logic; + Q : out std_logic); + end component; + component FD1S3DX + port (D : in std_logic; CK : in std_logic; CD : in std_logic; + Q : out std_logic); + end component; + component INV + port (A : in std_logic; Z : out std_logic); + end component; + component OR2 + port (A : in std_logic; B : in std_logic; Z : out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3 : in std_logic; AD2 : in std_logic; AD1 : in std_logic; + AD0 : in std_logic; DO0 : out std_logic); + end component; + component VHI + port (Z : out std_logic); + end component; + component VLO + port (Z : out std_logic); + end component; + component XOR2 + port (A : in std_logic; B : in std_logic; Z : out std_logic); + end component; + component PDPW16KC + generic (GSR : in string; CSDECODE_R : in string; + CSDECODE_W : in string; REGMODE : in string; + DATA_WIDTH_R : in integer; DATA_WIDTH_W : in integer); + port (DI0 : in std_logic; DI1 : in std_logic; DI2 : in std_logic; + DI3 : in std_logic; DI4 : in std_logic; DI5 : in std_logic; + DI6 : in std_logic; DI7 : in std_logic; DI8 : in std_logic; + DI9 : in std_logic; DI10 : in std_logic; DI11 : in std_logic; + DI12 : in std_logic; DI13 : in std_logic; + DI14 : in std_logic; DI15 : in std_logic; + DI16 : in std_logic; DI17 : in std_logic; + DI18 : in std_logic; DI19 : in std_logic; + DI20 : in std_logic; DI21 : in std_logic; + DI22 : in std_logic; DI23 : in std_logic; + DI24 : in std_logic; DI25 : in std_logic; + DI26 : in std_logic; DI27 : in std_logic; + DI28 : in std_logic; DI29 : in std_logic; + DI30 : in std_logic; DI31 : in std_logic; + DI32 : in std_logic; DI33 : in std_logic; + DI34 : in std_logic; DI35 : in std_logic; + ADW0 : in std_logic; ADW1 : in std_logic; + ADW2 : in std_logic; ADW3 : in std_logic; + ADW4 : in std_logic; ADW5 : in std_logic; + ADW6 : in std_logic; ADW7 : in std_logic; + ADW8 : in std_logic; BE0 : in std_logic; BE1 : in std_logic; + BE2 : in std_logic; BE3 : in std_logic; CEW : in std_logic; + CLKW : in std_logic; CSW0 : in std_logic; + CSW1 : in std_logic; CSW2 : in std_logic; + ADR0 : in std_logic; ADR1 : in std_logic; + ADR2 : in std_logic; ADR3 : in std_logic; + ADR4 : in std_logic; ADR5 : in std_logic; + ADR6 : in std_logic; ADR7 : in std_logic; + ADR8 : in std_logic; ADR9 : in std_logic; + ADR10 : in std_logic; ADR11 : in std_logic; + ADR12 : in std_logic; ADR13 : in std_logic; + CER : in std_logic; CLKR : in std_logic; CSR0 : in std_logic; + CSR1 : in std_logic; CSR2 : in std_logic; RST : in std_logic; + DO0 : out std_logic; DO1 : out std_logic; + DO2 : out std_logic; DO3 : out std_logic; + DO4 : out std_logic; DO5 : out std_logic; + DO6 : out std_logic; DO7 : out std_logic; + DO8 : out std_logic; DO9 : out std_logic; + DO10 : out std_logic; DO11 : out std_logic; + DO12 : out std_logic; DO13 : out std_logic; + DO14 : out std_logic; DO15 : out std_logic; + DO16 : out std_logic; DO17 : out std_logic; + DO18 : out std_logic; DO19 : out std_logic; + DO20 : out std_logic; DO21 : out std_logic; + DO22 : out std_logic; DO23 : out std_logic; + DO24 : out std_logic; DO25 : out std_logic; + DO26 : out std_logic; DO27 : out std_logic; + DO28 : out std_logic; DO29 : out std_logic; + DO30 : out std_logic; DO31 : out std_logic; + DO32 : out std_logic; DO33 : out std_logic; + DO34 : out std_logic; DO35 : out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "FIFO_36x128_OutReg_Counter.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; + attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + AND2_t17 : AND2 + port map (A => WrEn, B => invout_1, Z => wren_i); + + INV_1 : INV + port map (A => full_i, Z => invout_1); + + AND2_t16 : AND2 + port map (A => RdEn, B => invout_0, Z => rden_i); + + INV_0 : INV + port map (A => empty_i, Z => invout_0); + + OR2_t15 : OR2 + port map (A => Reset, B => RPReset, Z => rRst); + + XOR2_t14 : XOR2 + port map (A => wcount_0, B => wcount_1, Z => w_gdata_0); + + XOR2_t13 : XOR2 + port map (A => wcount_1, B => wcount_2, Z => w_gdata_1); + + XOR2_t12 : XOR2 + port map (A => wcount_2, B => wcount_3, Z => w_gdata_2); + + XOR2_t11 : XOR2 + port map (A => wcount_3, B => wcount_4, Z => w_gdata_3); + + XOR2_t10 : XOR2 + port map (A => wcount_4, B => wcount_5, Z => w_gdata_4); + + XOR2_t9 : XOR2 + port map (A => wcount_5, B => wcount_6, Z => w_gdata_5); + + XOR2_t8 : XOR2 + port map (A => wcount_6, B => wcount_7, Z => w_gdata_6); + + XOR2_t7 : XOR2 + port map (A => rcount_0, B => rcount_1, Z => r_gdata_0); + + XOR2_t6 : XOR2 + port map (A => rcount_1, B => rcount_2, Z => r_gdata_1); + + XOR2_t5 : XOR2 + port map (A => rcount_2, B => rcount_3, Z => r_gdata_2); + + XOR2_t4 : XOR2 + port map (A => rcount_3, B => rcount_4, Z => r_gdata_3); + + XOR2_t3 : XOR2 + port map (A => rcount_4, B => rcount_5, Z => r_gdata_4); + + XOR2_t2 : XOR2 + port map (A => rcount_5, B => rcount_6, Z => r_gdata_5); + + XOR2_t1 : XOR2 + port map (A => rcount_6, B => rcount_7, Z => r_gdata_6); + + LUT4_19 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => w_gcount_r24, AD2 => w_gcount_r25, + AD1 => w_gcount_r26, AD0 => w_gcount_r27, + DO0 => w_g2b_xor_cluster_0); + + LUT4_18 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => w_gcount_r20, AD2 => w_gcount_r21, + AD1 => w_gcount_r22, AD0 => w_gcount_r23, + DO0 => w_g2b_xor_cluster_1); + + LUT4_17 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => w_gcount_r26, AD2 => w_gcount_r27, AD1 => scuba_vlo, + AD0 => scuba_vlo, DO0 => wcount_r6); + + LUT4_16 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => w_gcount_r25, AD2 => w_gcount_r26, + AD1 => w_gcount_r27, AD0 => scuba_vlo, DO0 => wcount_r5); + + LUT4_15 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => w_gcount_r23, AD2 => w_gcount_r24, + AD1 => w_gcount_r25, AD0 => wcount_r6, DO0 => wcount_r3); + + LUT4_14 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => w_gcount_r22, AD2 => w_gcount_r23, + AD1 => w_gcount_r24, AD0 => wcount_r5, DO0 => wcount_r2); + + LUT4_13 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => w_gcount_r21, AD2 => w_gcount_r22, + AD1 => w_gcount_r23, AD0 => w_g2b_xor_cluster_0, DO0 => wcount_r1); + + LUT4_12 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => w_g2b_xor_cluster_0, AD2 => w_g2b_xor_cluster_1, + AD1 => scuba_vlo, AD0 => scuba_vlo, DO0 => wcount_r0); + + LUT4_11 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => r_gcount_w24, AD2 => r_gcount_w25, + AD1 => r_gcount_w26, AD0 => r_gcount_w27, + DO0 => r_g2b_xor_cluster_0); + + LUT4_10 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => r_gcount_w20, AD2 => r_gcount_w21, + AD1 => r_gcount_w22, AD0 => r_gcount_w23, + DO0 => r_g2b_xor_cluster_1); + + LUT4_9 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => r_gcount_w26, AD2 => r_gcount_w27, AD1 => scuba_vlo, + AD0 => scuba_vlo, DO0 => rcount_w6); + + LUT4_8 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => r_gcount_w25, AD2 => r_gcount_w26, + AD1 => r_gcount_w27, AD0 => scuba_vlo, DO0 => rcount_w5); + + LUT4_7 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => r_gcount_w23, AD2 => r_gcount_w24, + AD1 => r_gcount_w25, AD0 => rcount_w6, DO0 => rcount_w3); + + LUT4_6 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => r_gcount_w22, AD2 => r_gcount_w23, + AD1 => r_gcount_w24, AD0 => rcount_w5, DO0 => rcount_w2); + + LUT4_5 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => r_gcount_w21, AD2 => r_gcount_w22, + AD1 => r_gcount_w23, AD0 => r_g2b_xor_cluster_0, DO0 => rcount_w1); + + LUT4_4 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => r_g2b_xor_cluster_0, AD2 => r_g2b_xor_cluster_1, + AD1 => scuba_vlo, AD0 => scuba_vlo, DO0 => rcount_w0); + + XOR2_t0 : XOR2 + port map (A => wptr_7, B => r_gcount_w27, Z => wfill_sub_msb); + + LUT4_3 : ROM16X1A + generic map (initval => X"0410") + port map (AD3 => rptr_7, AD2 => rcount_7, AD1 => w_gcount_r27, + AD0 => scuba_vlo, DO0 => empty_cmp_set); + + LUT4_2 : ROM16X1A + generic map (initval => X"1004") + port map (AD3 => rptr_7, AD2 => rcount_7, AD1 => w_gcount_r27, + AD0 => scuba_vlo, DO0 => empty_cmp_clr); + + LUT4_1 : ROM16X1A + generic map (initval => X"0140") + port map (AD3 => wptr_7, AD2 => wcount_7, AD1 => r_gcount_w27, + AD0 => scuba_vlo, DO0 => full_cmp_set); + + LUT4_0 : ROM16X1A + generic map (initval => X"4001") + port map (AD3 => wptr_7, AD2 => wcount_7, AD1 => r_gcount_w27, + AD0 => scuba_vlo, DO0 => full_cmp_clr); + + pdp_ram_0_0_0 : PDPW16KC + generic map (CSDECODE_R => "0b001", CSDECODE_W => "0b001", GSR => "DISABLED", + REGMODE => "OUTREG", DATA_WIDTH_R => 36, DATA_WIDTH_W => 36) + port map (DI0 => Data(0), DI1 => Data(1), DI2 => Data(2), DI3 => Data(3), + DI4 => Data(4), DI5 => Data(5), DI6 => Data(6), DI7 => Data(7), + DI8 => Data(8), DI9 => Data(9), DI10 => Data(10), DI11 => Data(11), + DI12 => Data(12), DI13 => Data(13), DI14 => Data(14), + DI15 => Data(15), DI16 => Data(16), DI17 => Data(17), + DI18 => Data(18), DI19 => Data(19), DI20 => Data(20), + DI21 => Data(21), DI22 => Data(22), DI23 => Data(23), + DI24 => Data(24), DI25 => Data(25), DI26 => Data(26), + DI27 => Data(27), DI28 => Data(28), DI29 => Data(29), + DI30 => Data(30), DI31 => Data(31), DI32 => Data(32), + DI33 => Data(33), DI34 => Data(34), DI35 => Data(35), ADW0 => wptr_0, + ADW1 => wptr_1, ADW2 => wptr_2, ADW3 => wptr_3, ADW4 => wptr_4, + ADW5 => wptr_5, ADW6 => wptr_6, ADW7 => scuba_vlo, ADW8 => scuba_vlo, + BE0 => scuba_vhi, BE1 => scuba_vhi, BE2 => scuba_vhi, + BE3 => scuba_vhi, CEW => wren_i, CLKW => WrClock, CSW0 => scuba_vhi, + CSW1 => scuba_vlo, CSW2 => scuba_vlo, ADR0 => scuba_vlo, + ADR1 => scuba_vlo, ADR2 => scuba_vlo, ADR3 => scuba_vlo, + ADR4 => scuba_vlo, ADR5 => rptr_0, ADR6 => rptr_1, ADR7 => rptr_2, + ADR8 => rptr_3, ADR9 => rptr_4, ADR10 => rptr_5, ADR11 => rptr_6, + ADR12 => scuba_vlo, ADR13 => scuba_vlo, CER => scuba_vhi, + CLKR => RdClock, CSR0 => rden_i, CSR1 => scuba_vlo, + CSR2 => scuba_vlo, RST => Reset, DO0 => Q(18), DO1 => Q(19), + DO2 => Q(20), DO3 => Q(21), DO4 => Q(22), DO5 => Q(23), DO6 => Q(24), + DO7 => Q(25), DO8 => Q(26), DO9 => Q(27), DO10 => Q(28), DO11 => Q(29), + DO12 => Q(30), DO13 => Q(31), DO14 => Q(32), DO15 => Q(33), + DO16 => Q(34), DO17 => Q(35), DO18 => Q(0), DO19 => Q(1), DO20 => Q(2), + DO21 => Q(3), DO22 => Q(4), DO23 => Q(5), DO24 => Q(6), DO25 => Q(7), + DO26 => Q(8), DO27 => Q(9), DO28 => Q(10), DO29 => Q(11), + DO30 => Q(12), DO31 => Q(13), DO32 => Q(14), DO33 => Q(15), + DO34 => Q(16), DO35 => Q(17)); + + FF_89 : FD1P3BX + port map (D => iwcount_0, SP => wren_i, CK => WrClock, PD => Reset, + Q => wcount_0); + + FF_88 : FD1P3DX + port map (D => iwcount_1, SP => wren_i, CK => WrClock, CD => Reset, + Q => wcount_1); + + FF_87 : FD1P3DX + port map (D => iwcount_2, SP => wren_i, CK => WrClock, CD => Reset, + Q => wcount_2); + + FF_86 : FD1P3DX + port map (D => iwcount_3, SP => wren_i, CK => WrClock, CD => Reset, + Q => wcount_3); + + FF_85 : FD1P3DX + port map (D => iwcount_4, SP => wren_i, CK => WrClock, CD => Reset, + Q => wcount_4); + + FF_84 : FD1P3DX + port map (D => iwcount_5, SP => wren_i, CK => WrClock, CD => Reset, + Q => wcount_5); + + FF_83 : FD1P3DX + port map (D => iwcount_6, SP => wren_i, CK => WrClock, CD => Reset, + Q => wcount_6); + + FF_82 : FD1P3DX + port map (D => iwcount_7, SP => wren_i, CK => WrClock, CD => Reset, + Q => wcount_7); + + FF_81 : FD1P3DX + port map (D => w_gdata_0, SP => wren_i, CK => WrClock, CD => Reset, + Q => w_gcount_0); + + FF_80 : FD1P3DX + port map (D => w_gdata_1, SP => wren_i, CK => WrClock, CD => Reset, + Q => w_gcount_1); + + FF_79 : FD1P3DX + port map (D => w_gdata_2, SP => wren_i, CK => WrClock, CD => Reset, + Q => w_gcount_2); + + FF_78 : FD1P3DX + port map (D => w_gdata_3, SP => wren_i, CK => WrClock, CD => Reset, + Q => w_gcount_3); + + FF_77 : FD1P3DX + port map (D => w_gdata_4, SP => wren_i, CK => WrClock, CD => Reset, + Q => w_gcount_4); + + FF_76 : FD1P3DX + port map (D => w_gdata_5, SP => wren_i, CK => WrClock, CD => Reset, + Q => w_gcount_5); + + FF_75 : FD1P3DX + port map (D => w_gdata_6, SP => wren_i, CK => WrClock, CD => Reset, + Q => w_gcount_6); + + FF_74 : FD1P3DX + port map (D => wcount_7, SP => wren_i, CK => WrClock, CD => Reset, + Q => w_gcount_7); + + FF_73 : FD1P3DX + port map (D => wcount_0, SP => wren_i, CK => WrClock, CD => Reset, + Q => wptr_0); + + FF_72 : FD1P3DX + port map (D => wcount_1, SP => wren_i, CK => WrClock, CD => Reset, + Q => wptr_1); + + FF_71 : FD1P3DX + port map (D => wcount_2, SP => wren_i, CK => WrClock, CD => Reset, + Q => wptr_2); + + FF_70 : FD1P3DX + port map (D => wcount_3, SP => wren_i, CK => WrClock, CD => Reset, + Q => wptr_3); + + FF_69 : FD1P3DX + port map (D => wcount_4, SP => wren_i, CK => WrClock, CD => Reset, + Q => wptr_4); + + FF_68 : FD1P3DX + port map (D => wcount_5, SP => wren_i, CK => WrClock, CD => Reset, + Q => wptr_5); + + FF_67 : FD1P3DX + port map (D => wcount_6, SP => wren_i, CK => WrClock, CD => Reset, + Q => wptr_6); + + FF_66 : FD1P3DX + port map (D => wcount_7, SP => wren_i, CK => WrClock, CD => Reset, + Q => wptr_7); + + FF_65 : FD1P3BX + port map (D => ircount_0, SP => rden_i, CK => RdClock, PD => rRst, + Q => rcount_0); + + FF_64 : FD1P3DX + port map (D => ircount_1, SP => rden_i, CK => RdClock, CD => rRst, + Q => rcount_1); + + FF_63 : FD1P3DX + port map (D => ircount_2, SP => rden_i, CK => RdClock, CD => rRst, + Q => rcount_2); + + FF_62 : FD1P3DX + port map (D => ircount_3, SP => rden_i, CK => RdClock, CD => rRst, + Q => rcount_3); + + FF_61 : FD1P3DX + port map (D => ircount_4, SP => rden_i, CK => RdClock, CD => rRst, + Q => rcount_4); + + FF_60 : FD1P3DX + port map (D => ircount_5, SP => rden_i, CK => RdClock, CD => rRst, + Q => rcount_5); + + FF_59 : FD1P3DX + port map (D => ircount_6, SP => rden_i, CK => RdClock, CD => rRst, + Q => rcount_6); + + FF_58 : FD1P3DX + port map (D => ircount_7, SP => rden_i, CK => RdClock, CD => rRst, + Q => rcount_7); + + FF_57 : FD1P3DX + port map (D => r_gdata_0, SP => rden_i, CK => RdClock, CD => rRst, + Q => r_gcount_0); + + FF_56 : FD1P3DX + port map (D => r_gdata_1, SP => rden_i, CK => RdClock, CD => rRst, + Q => r_gcount_1); + + FF_55 : FD1P3DX + port map (D => r_gdata_2, SP => rden_i, CK => RdClock, CD => rRst, + Q => r_gcount_2); + + FF_54 : FD1P3DX + port map (D => r_gdata_3, SP => rden_i, CK => RdClock, CD => rRst, + Q => r_gcount_3); + + FF_53 : FD1P3DX + port map (D => r_gdata_4, SP => rden_i, CK => RdClock, CD => rRst, + Q => r_gcount_4); + + FF_52 : FD1P3DX + port map (D => r_gdata_5, SP => rden_i, CK => RdClock, CD => rRst, + Q => r_gcount_5); + + FF_51 : FD1P3DX + port map (D => r_gdata_6, SP => rden_i, CK => RdClock, CD => rRst, + Q => r_gcount_6); + + FF_50 : FD1P3DX + port map (D => rcount_7, SP => rden_i, CK => RdClock, CD => rRst, + Q => r_gcount_7); + + FF_49 : FD1P3DX + port map (D => rcount_0, SP => rden_i, CK => RdClock, CD => rRst, + Q => rptr_0); + + FF_48 : FD1P3DX + port map (D => rcount_1, SP => rden_i, CK => RdClock, CD => rRst, + Q => rptr_1); + + FF_47 : FD1P3DX + port map (D => rcount_2, SP => rden_i, CK => RdClock, CD => rRst, + Q => rptr_2); + + FF_46 : FD1P3DX + port map (D => rcount_3, SP => rden_i, CK => RdClock, CD => rRst, + Q => rptr_3); + + FF_45 : FD1P3DX + port map (D => rcount_4, SP => rden_i, CK => RdClock, CD => rRst, + Q => rptr_4); + + FF_44 : FD1P3DX + port map (D => rcount_5, SP => rden_i, CK => RdClock, CD => rRst, + Q => rptr_5); + + FF_43 : FD1P3DX + port map (D => rcount_6, SP => rden_i, CK => RdClock, CD => rRst, + Q => rptr_6); + + FF_42 : FD1P3DX + port map (D => rcount_7, SP => rden_i, CK => RdClock, CD => rRst, + Q => rptr_7); + + FF_41 : FD1S3DX + port map (D => w_gcount_0, CK => RdClock, CD => Reset, Q => w_gcount_r0); + + FF_40 : FD1S3DX + port map (D => w_gcount_1, CK => RdClock, CD => Reset, Q => w_gcount_r1); + + FF_39 : FD1S3DX + port map (D => w_gcount_2, CK => RdClock, CD => Reset, Q => w_gcount_r2); + + FF_38 : FD1S3DX + port map (D => w_gcount_3, CK => RdClock, CD => Reset, Q => w_gcount_r3); + + FF_37 : FD1S3DX + port map (D => w_gcount_4, CK => RdClock, CD => Reset, Q => w_gcount_r4); + + FF_36 : FD1S3DX + port map (D => w_gcount_5, CK => RdClock, CD => Reset, Q => w_gcount_r5); + + FF_35 : FD1S3DX + port map (D => w_gcount_6, CK => RdClock, CD => Reset, Q => w_gcount_r6); + + FF_34 : FD1S3DX + port map (D => w_gcount_7, CK => RdClock, CD => Reset, Q => w_gcount_r7); + + FF_33 : FD1S3DX + port map (D => r_gcount_0, CK => WrClock, CD => rRst, Q => r_gcount_w0); + + FF_32 : FD1S3DX + port map (D => r_gcount_1, CK => WrClock, CD => rRst, Q => r_gcount_w1); + + FF_31 : FD1S3DX + port map (D => r_gcount_2, CK => WrClock, CD => rRst, Q => r_gcount_w2); + + FF_30 : FD1S3DX + port map (D => r_gcount_3, CK => WrClock, CD => rRst, Q => r_gcount_w3); + + FF_29 : FD1S3DX + port map (D => r_gcount_4, CK => WrClock, CD => rRst, Q => r_gcount_w4); + + FF_28 : FD1S3DX + port map (D => r_gcount_5, CK => WrClock, CD => rRst, Q => r_gcount_w5); + + FF_27 : FD1S3DX + port map (D => r_gcount_6, CK => WrClock, CD => rRst, Q => r_gcount_w6); + + FF_26 : FD1S3DX + port map (D => r_gcount_7, CK => WrClock, CD => rRst, Q => r_gcount_w7); + + FF_25 : FD1S3DX + port map (D => w_gcount_r0, CK => RdClock, CD => Reset, + Q => w_gcount_r20); + + FF_24 : FD1S3DX + port map (D => w_gcount_r1, CK => RdClock, CD => Reset, + Q => w_gcount_r21); + + FF_23 : FD1S3DX + port map (D => w_gcount_r2, CK => RdClock, CD => Reset, + Q => w_gcount_r22); + + FF_22 : FD1S3DX + port map (D => w_gcount_r3, CK => RdClock, CD => Reset, + Q => w_gcount_r23); + + FF_21 : FD1S3DX + port map (D => w_gcount_r4, CK => RdClock, CD => Reset, + Q => w_gcount_r24); + + FF_20 : FD1S3DX + port map (D => w_gcount_r5, CK => RdClock, CD => Reset, + Q => w_gcount_r25); + + FF_19 : FD1S3DX + port map (D => w_gcount_r6, CK => RdClock, CD => Reset, + Q => w_gcount_r26); + + FF_18 : FD1S3DX + port map (D => w_gcount_r7, CK => RdClock, CD => Reset, + Q => w_gcount_r27); + + FF_17 : FD1S3DX + port map (D => r_gcount_w0, CK => WrClock, CD => rRst, Q => r_gcount_w20); + + FF_16 : FD1S3DX + port map (D => r_gcount_w1, CK => WrClock, CD => rRst, Q => r_gcount_w21); + + FF_15 : FD1S3DX + port map (D => r_gcount_w2, CK => WrClock, CD => rRst, Q => r_gcount_w22); + + FF_14 : FD1S3DX + port map (D => r_gcount_w3, CK => WrClock, CD => rRst, Q => r_gcount_w23); + + FF_13 : FD1S3DX + port map (D => r_gcount_w4, CK => WrClock, CD => rRst, Q => r_gcount_w24); + + FF_12 : FD1S3DX + port map (D => r_gcount_w5, CK => WrClock, CD => rRst, Q => r_gcount_w25); + + FF_11 : FD1S3DX + port map (D => r_gcount_w6, CK => WrClock, CD => rRst, Q => r_gcount_w26); + + FF_10 : FD1S3DX + port map (D => r_gcount_w7, CK => WrClock, CD => rRst, Q => r_gcount_w27); + + FF_9 : FD1S3DX + port map (D => wfill_sub_0, CK => WrClock, CD => Reset, Q => WCNT(0)); + + FF_8 : FD1S3DX + port map (D => wfill_sub_1, CK => WrClock, CD => Reset, Q => WCNT(1)); + + FF_7 : FD1S3DX + port map (D => wfill_sub_2, CK => WrClock, CD => Reset, Q => WCNT(2)); + + FF_6 : FD1S3DX + port map (D => wfill_sub_3, CK => WrClock, CD => Reset, Q => WCNT(3)); + + FF_5 : FD1S3DX + port map (D => wfill_sub_4, CK => WrClock, CD => Reset, Q => WCNT(4)); + + FF_4 : FD1S3DX + port map (D => wfill_sub_5, CK => WrClock, CD => Reset, Q => WCNT(5)); + + FF_3 : FD1S3DX + port map (D => wfill_sub_6, CK => WrClock, CD => Reset, Q => WCNT(6)); + + FF_2 : FD1S3DX + port map (D => wfill_sub_7, CK => WrClock, CD => Reset, Q => WCNT(7)); + + FF_1 : FD1S3BX + port map (D => empty_d, CK => RdClock, PD => rRst, Q => empty_i); + + FF_0 : FD1S3DX + port map (D => full_d, CK => WrClock, CD => Reset, Q => full_i); + + w_gctr_cia : FADD2B + port map (A0 => scuba_vlo, A1 => scuba_vhi, B0 => scuba_vlo, + B1 => scuba_vhi, CI => scuba_vlo, COUT => w_gctr_ci, S0 => open, + S1 => open); + + w_gctr_0 : CU2 + port map (CI => w_gctr_ci, PC0 => wcount_0, PC1 => wcount_1, CO => co0, + NC0 => iwcount_0, NC1 => iwcount_1); + + w_gctr_1 : CU2 + port map (CI => co0, PC0 => wcount_2, PC1 => wcount_3, CO => co1, + NC0 => iwcount_2, NC1 => iwcount_3); + + w_gctr_2 : CU2 + port map (CI => co1, PC0 => wcount_4, PC1 => wcount_5, CO => co2, + NC0 => iwcount_4, NC1 => iwcount_5); + + w_gctr_3 : CU2 + port map (CI => co2, PC0 => wcount_6, PC1 => wcount_7, CO => co3, + NC0 => iwcount_6, NC1 => iwcount_7); + + r_gctr_cia : FADD2B + port map (A0 => scuba_vlo, A1 => scuba_vhi, B0 => scuba_vlo, + B1 => scuba_vhi, CI => scuba_vlo, COUT => r_gctr_ci, S0 => open, + S1 => open); + + r_gctr_0 : CU2 + port map (CI => r_gctr_ci, PC0 => rcount_0, PC1 => rcount_1, CO => co0_1, + NC0 => ircount_0, NC1 => ircount_1); + + r_gctr_1 : CU2 + port map (CI => co0_1, PC0 => rcount_2, PC1 => rcount_3, CO => co1_1, + NC0 => ircount_2, NC1 => ircount_3); + + r_gctr_2 : CU2 + port map (CI => co1_1, PC0 => rcount_4, PC1 => rcount_5, CO => co2_1, + NC0 => ircount_4, NC1 => ircount_5); + + r_gctr_3 : CU2 + port map (CI => co2_1, PC0 => rcount_6, PC1 => rcount_7, CO => co3_1, + NC0 => ircount_6, NC1 => ircount_7); + + scuba_vhi_inst : VHI + port map (Z => scuba_vhi); + + wfill_0 : FSUB2B + port map (A0 => scuba_vhi, A1 => wptr_0, B0 => scuba_vlo, + B1 => rcount_w0, BI => scuba_vlo, BOUT => co0_2, S0 => open, + S1 => wfill_sub_0); + + wfill_1 : FSUB2B + port map (A0 => wptr_1, A1 => wptr_2, B0 => rcount_w1, B1 => rcount_w2, + BI => co0_2, BOUT => co1_2, S0 => wfill_sub_1, S1 => wfill_sub_2); + + wfill_2 : FSUB2B + port map (A0 => wptr_3, A1 => wptr_4, B0 => rcount_w3, + B1 => r_g2b_xor_cluster_0, BI => co1_2, BOUT => co2_2, + S0 => wfill_sub_3, S1 => wfill_sub_4); + + wfill_3 : FSUB2B + port map (A0 => wptr_5, A1 => wptr_6, B0 => rcount_w5, B1 => rcount_w6, + BI => co2_2, BOUT => co3_2, S0 => wfill_sub_5, S1 => wfill_sub_6); + + wfill_4 : FSUB2B + port map (A0 => wfill_sub_msb, A1 => scuba_vlo, B0 => scuba_vlo, + B1 => scuba_vlo, BI => co3_2, BOUT => open, S0 => wfill_sub_7, + S1 => open); + + empty_cmp_ci_a : FADD2B + port map (A0 => scuba_vlo, A1 => rden_i, B0 => scuba_vlo, B1 => rden_i, + CI => scuba_vlo, COUT => cmp_ci, S0 => open, S1 => open); + + empty_cmp_0 : AGEB2 + port map (A0 => rcount_0, A1 => rcount_1, B0 => wcount_r0, + B1 => wcount_r1, CI => cmp_ci, GE => co0_3); + + empty_cmp_1 : AGEB2 + port map (A0 => rcount_2, A1 => rcount_3, B0 => wcount_r2, + B1 => wcount_r3, CI => co0_3, GE => co1_3); + + empty_cmp_2 : AGEB2 + port map (A0 => rcount_4, A1 => rcount_5, B0 => w_g2b_xor_cluster_0, + B1 => wcount_r5, CI => co1_3, GE => co2_3); + + empty_cmp_3 : AGEB2 + port map (A0 => rcount_6, A1 => empty_cmp_set, B0 => wcount_r6, + B1 => empty_cmp_clr, CI => co2_3, GE => empty_d_c); + + a0 : FADD2B + port map (A0 => scuba_vlo, A1 => scuba_vlo, B0 => scuba_vlo, + B1 => scuba_vlo, CI => empty_d_c, COUT => open, S0 => empty_d, + S1 => open); + + full_cmp_ci_a : FADD2B + port map (A0 => scuba_vlo, A1 => wren_i, B0 => scuba_vlo, B1 => wren_i, + CI => scuba_vlo, COUT => cmp_ci_1, S0 => open, S1 => open); + + full_cmp_0 : AGEB2 + port map (A0 => wcount_0, A1 => wcount_1, B0 => rcount_w0, + B1 => rcount_w1, CI => cmp_ci_1, GE => co0_4); + + full_cmp_1 : AGEB2 + port map (A0 => wcount_2, A1 => wcount_3, B0 => rcount_w2, + B1 => rcount_w3, CI => co0_4, GE => co1_4); + + full_cmp_2 : AGEB2 + port map (A0 => wcount_4, A1 => wcount_5, B0 => r_g2b_xor_cluster_0, + B1 => rcount_w5, CI => co1_4, GE => co2_4); + + full_cmp_3 : AGEB2 + port map (A0 => wcount_6, A1 => full_cmp_set, B0 => rcount_w6, + B1 => full_cmp_clr, CI => co2_4, GE => full_d_c); + + scuba_vlo_inst : VLO + port map (Z => scuba_vlo); + + a1 : FADD2B + port map (A0 => scuba_vlo, A1 => scuba_vlo, B0 => scuba_vlo, + B1 => scuba_vlo, CI => full_d_c, COUT => open, S0 => full_d, + S1 => open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of FIFO_36x128_OutReg_Counter is + for Structure + for all : AGEB2 use entity ecp3.AGEB2(V); end for; + for all : AND2 use entity ecp3.AND2(V); end for; + for all : CU2 use entity ecp3.CU2(V); end for; + for all : FADD2B use entity ecp3.FADD2B(V); end for; + for all : FSUB2B use entity ecp3.FSUB2B(V); end for; + for all : FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all : FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all : FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all : FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all : INV use entity ecp3.INV(V); end for; + for all : OR2 use entity ecp3.OR2(V); end for; + for all : ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all : VHI use entity ecp3.VHI(V); end for; + for all : VLO use entity ecp3.VLO(V); end for; + for all : XOR2 use entity ecp3.XOR2(V); end for; + for all : PDPW16KC use entity ecp3.PDPW16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/tdc_releases/tdc_v1.4/LogicAnalyser.vhd b/tdc_releases/tdc_v1.4/LogicAnalyser.vhd new file mode 100644 index 0000000..f06bfc4 --- /dev/null +++ b/tdc_releases/tdc_v1.4/LogicAnalyser.vhd @@ -0,0 +1,79 @@ +------------------------------------------------------------------------------- +-- Title : Logic Analyser Signals +-- Project : +------------------------------------------------------------------------------- +-- File : LogicAnalyser.vhd +-- Author : cugur@gsi.de +-- Created : 2012-10-26 +-- Last update: 2013-03-01 +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- + +library IEEE; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; + +entity LogicAnalyser is + generic ( + CHANNEL_NUMBER : integer range 2 to 65); + + port ( + CLK : in std_logic; + RESET : in std_logic; +-- + DATA_IN : in std_logic_vector(3*32-1 downto 0); + CONTROL_IN : in std_logic_vector(3 downto 0); + DATA_OUT : out std_logic_vector(15 downto 0) + ); + +end LogicAnalyser; + + +architecture behavioral of LogicAnalyser is + + signal mux_out : std_logic_vector(15 downto 0); + +begin -- behavioral + +------------------------------------------------------------------------------- +-- Logic Analyser Signals +------------------------------------------------------------------------------- + REG_LOGIC_ANALYSER_OUTPUT : process (CLK, RESET) + begin + if rising_edge(CLK) then + if RESET = '1' then + mux_out <= (others => '0'); + elsif CONTROL_IN = x"1" then -- TRBNET connections debugging + mux_out(7 downto 0) <= DATA_IN(7 downto 0); --fsm_debug; + mux_out(8) <= DATA_IN(8); --REFERENCE_TIME; + mux_out(9) <= DATA_IN(9); --VALID_TIMING_TRG_IN; + mux_out(10) <= DATA_IN(10); --VALID_NOTIMING_TRG_IN; + mux_out(11) <= DATA_IN(11); --INVALID_TRG_IN; + mux_out(12) <= DATA_IN(12); --TRG_DATA_VALID_IN; + mux_out(13) <= DATA_IN(13); --data_wr_reg; + mux_out(14) <= DATA_IN(14); --data_finished_reg; + mux_out(15) <= DATA_IN(15); --trg_release_reg; + elsif CONTROL_IN = x"2" then -- Reference channel debugging + mux_out <= DATA_IN(31 downto 16); --ref_debug_i(15 downto 0); + elsif CONTROL_IN = x"3" then -- Data out + mux_out(7 downto 0) <= DATA_IN(7 downto 0); --fsm_debug; + mux_out(8) <= DATA_IN(8); --REFERENCE_TIME; + mux_out(9) <= DATA_IN(13); --data_wr_reg; + mux_out(15 downto 10) <= DATA_IN(37 downto 32); --data_out_reg(27 downto 22); + + --elsif CONTROL_IN = x"4" then -- channel debugging + -- mux_out <= DATA_IN(); --ch_debug_i(1)(15 downto 0); + end if; + end if; + end process REG_LOGIC_ANALYSER_OUTPUT; + + DATA_OUT <= mux_out; + + +end behavioral; diff --git a/tdc_releases/tdc_v1.4/ROM4_Encoder.vhd b/tdc_releases/tdc_v1.4/ROM4_Encoder.vhd new file mode 100644 index 0000000..e39b95c --- /dev/null +++ b/tdc_releases/tdc_v1.4/ROM4_Encoder.vhd @@ -0,0 +1,262 @@ +-- VHDL netlist generated by SCUBA Diamond_2.0_Production (151) +-- Module Version: 5.0 +--/opt/lattice/diamond/2.01/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 00 -rp 1100 -addr_width 10 -data_width 8 -num_rows 1024 -outdata REGISTERED -memfile /home/cugur/Projects/encoder/encoder_304_ROM4/source/rom_encoder.mem -memformat orca -cascade -1 -e + +-- Mon Mar 4 14:23:33 2013 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity ROM4_Encoder is + port ( + Address : in std_logic_vector(9 downto 0); + OutClock : in std_logic; + OutClockEn : in std_logic; + Reset : in std_logic; + Q : out std_logic_vector(7 downto 0)); +end ROM4_Encoder; + +architecture Structure of ROM4_Encoder is + + -- internal signal declarations + signal scuba_vhi : std_logic; + signal scuba_vlo : std_logic; + + -- local component declarations + component VHI + port (Z : out std_logic); + end component; + component VLO + port (Z : out std_logic); + end component; + component DP16KC + generic (INITVAL_3F : in string; INITVAL_3E : in string; + INITVAL_3D : in string; INITVAL_3C : in string; + INITVAL_3B : in string; INITVAL_3A : in string; + INITVAL_39 : in string; INITVAL_38 : in string; + INITVAL_37 : in string; INITVAL_36 : in string; + INITVAL_35 : in string; INITVAL_34 : in string; + INITVAL_33 : in string; INITVAL_32 : in string; + INITVAL_31 : in string; INITVAL_30 : in string; + INITVAL_2F : in string; INITVAL_2E : in string; + INITVAL_2D : in string; INITVAL_2C : in string; + INITVAL_2B : in string; INITVAL_2A : in string; + INITVAL_29 : in string; INITVAL_28 : in string; + INITVAL_27 : in string; INITVAL_26 : in string; + INITVAL_25 : in string; INITVAL_24 : in string; + INITVAL_23 : in string; INITVAL_22 : in string; + INITVAL_21 : in string; INITVAL_20 : in string; + INITVAL_1F : in string; INITVAL_1E : in string; + INITVAL_1D : in string; INITVAL_1C : in string; + INITVAL_1B : in string; INITVAL_1A : in string; + INITVAL_19 : in string; INITVAL_18 : in string; + INITVAL_17 : in string; INITVAL_16 : in string; + INITVAL_15 : in string; INITVAL_14 : in string; + INITVAL_13 : in string; INITVAL_12 : in string; + INITVAL_11 : in string; INITVAL_10 : in string; + INITVAL_0F : in string; INITVAL_0E : in string; + INITVAL_0D : in string; INITVAL_0C : in string; + INITVAL_0B : in string; INITVAL_0A : in string; + INITVAL_09 : in string; INITVAL_08 : in string; + INITVAL_07 : in string; INITVAL_06 : in string; + INITVAL_05 : in string; INITVAL_04 : in string; + INITVAL_03 : in string; INITVAL_02 : in string; + INITVAL_01 : in string; INITVAL_00 : in string; + GSR : in string; WRITEMODE_B : in string; + WRITEMODE_A : in string; CSDECODE_B : in string; + CSDECODE_A : in string; REGMODE_B : in string; + REGMODE_A : in string; DATA_WIDTH_B : in integer; + DATA_WIDTH_A : in integer); + port (DIA0 : in std_logic; DIA1 : in std_logic; + DIA2 : in std_logic; DIA3 : in std_logic; + DIA4 : in std_logic; DIA5 : in std_logic; + DIA6 : in std_logic; DIA7 : in std_logic; + DIA8 : in std_logic; DIA9 : in std_logic; + DIA10 : in std_logic; DIA11 : in std_logic; + DIA12 : in std_logic; DIA13 : in std_logic; + DIA14 : in std_logic; DIA15 : in std_logic; + DIA16 : in std_logic; DIA17 : in std_logic; + ADA0 : in std_logic; ADA1 : in std_logic; + ADA2 : in std_logic; ADA3 : in std_logic; + ADA4 : in std_logic; ADA5 : in std_logic; + ADA6 : in std_logic; ADA7 : in std_logic; + ADA8 : in std_logic; ADA9 : in std_logic; + ADA10 : in std_logic; ADA11 : in std_logic; + ADA12 : in std_logic; ADA13 : in std_logic; + CEA : in std_logic; CLKA : in std_logic; OCEA : in std_logic; + WEA : in std_logic; CSA0 : in std_logic; CSA1 : in std_logic; + CSA2 : in std_logic; RSTA : in std_logic; + DIB0 : in std_logic; DIB1 : in std_logic; + DIB2 : in std_logic; DIB3 : in std_logic; + DIB4 : in std_logic; DIB5 : in std_logic; + DIB6 : in std_logic; DIB7 : in std_logic; + DIB8 : in std_logic; DIB9 : in std_logic; + DIB10 : in std_logic; DIB11 : in std_logic; + DIB12 : in std_logic; DIB13 : in std_logic; + DIB14 : in std_logic; DIB15 : in std_logic; + DIB16 : in std_logic; DIB17 : in std_logic; + ADB0 : in std_logic; ADB1 : in std_logic; + ADB2 : in std_logic; ADB3 : in std_logic; + ADB4 : in std_logic; ADB5 : in std_logic; + ADB6 : in std_logic; ADB7 : in std_logic; + ADB8 : in std_logic; ADB9 : in std_logic; + ADB10 : in std_logic; ADB11 : in std_logic; + ADB12 : in std_logic; ADB13 : in std_logic; + CEB : in std_logic; CLKB : in std_logic; OCEB : in std_logic; + WEB : in std_logic; CSB0 : in std_logic; CSB1 : in std_logic; + CSB2 : in std_logic; RSTB : in std_logic; + DOA0 : out std_logic; DOA1 : out std_logic; + DOA2 : out std_logic; DOA3 : out std_logic; + DOA4 : out std_logic; DOA5 : out std_logic; + DOA6 : out std_logic; DOA7 : out std_logic; + DOA8 : out std_logic; DOA9 : out std_logic; + DOA10 : out std_logic; DOA11 : out std_logic; + DOA12 : out std_logic; DOA13 : out std_logic; + DOA14 : out std_logic; DOA15 : out std_logic; + DOA16 : out std_logic; DOA17 : out std_logic; + DOB0 : out std_logic; DOB1 : out std_logic; + DOB2 : out std_logic; DOB3 : out std_logic; + DOB4 : out std_logic; DOB5 : out std_logic; + DOB6 : out std_logic; DOB7 : out std_logic; + DOB8 : out std_logic; DOB9 : out std_logic; + DOB10 : out std_logic; DOB11 : out std_logic; + DOB12 : out std_logic; DOB13 : out std_logic; + DOB14 : out std_logic; DOB15 : out std_logic; + DOB16 : out std_logic; DOB17 : out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute MEM_LPC_FILE of ROM4_Encoder_0_0_0 : label is "ROM4_Encoder.lpc"; + attribute MEM_INIT_FILE of ROM4_Encoder_0_0_0 : label is "rom_encoder.mem"; + attribute RESETMODE of ROM4_Encoder_0_0_0 : label is "SYNC"; + +begin + -- component instantiation statements + scuba_vhi_inst : VHI + port map (Z => scuba_vhi); + + scuba_vlo_inst : VLO + port map (Z => scuba_vlo); + + ROM4_Encoder_0_0_0 : DP16KC + generic map (INITVAL_3F => "0x00080000400000000001000800000100001000020008000002000800000200080000020008000003", + INITVAL_3E => "0x00080000800008000003000800008000080000030008000080000800000300080000800008000004", + INITVAL_3D => "0x00080000800008000080000800008000080000040008000080000800008000080000800008000004", + INITVAL_3C => "0x00080000800008000080000800008000080000040008000080000800008000080000800008000005", + INITVAL_3B => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000005", + INITVAL_3A => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000005", + INITVAL_39 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000005", + INITVAL_38 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000046", + INITVAL_37 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_36 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000006", + INITVAL_35 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_34 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000006", + INITVAL_33 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_32 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000006", + INITVAL_31 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_30 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000047", + INITVAL_2F => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_2E => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_2D => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_2C => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000007", + INITVAL_2B => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_2A => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_29 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_28 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000047", + INITVAL_27 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_26 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_25 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_24 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_23 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_22 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_21 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_20 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_1F => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_1E => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_1D => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_1C => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_1B => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_1A => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_19 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_18 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_17 => "0x00047000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_16 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_15 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_14 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_13 => "0x00007000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_12 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_11 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_10 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_0F => "0x00047000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_0E => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_0D => "0x00006000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_0C => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_0B => "0x00006000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_0A => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_09 => "0x00006000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_08 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_07 => "0x00046000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_06 => "0x00005000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_05 => "0x00005000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_04 => "0x00005000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_03 => "0x00005000800008000080000800008000080000800000400080000800008000080000800008000080", + INITVAL_02 => "0x00004000800008000080000800008000080000800000400080000800008000080000800008000080", + INITVAL_01 => "0x00004000800008000080000030008000080000800000300080000800008000003000800008000080", + INITVAL_00 => "0x00003000800000200080000020008000002000800000200001000010008000001000800004000080", + CSDECODE_B => "0b111", CSDECODE_A => "0b000", WRITEMODE_B => "NORMAL", + WRITEMODE_A => "NORMAL", GSR => "DISABLED", REGMODE_B => "NOREG", + REGMODE_A => "OUTREG", DATA_WIDTH_B => 18, DATA_WIDTH_A => 18) + port map (DIA0 => scuba_vlo, DIA1 => scuba_vlo, DIA2 => scuba_vlo, + DIA3 => scuba_vlo, DIA4 => scuba_vlo, DIA5 => scuba_vlo, + DIA6 => scuba_vlo, DIA7 => scuba_vlo, DIA8 => scuba_vlo, + DIA9 => scuba_vlo, DIA10 => scuba_vlo, DIA11 => scuba_vlo, + DIA12 => scuba_vlo, DIA13 => scuba_vlo, DIA14 => scuba_vlo, + DIA15 => scuba_vlo, DIA16 => scuba_vlo, DIA17 => scuba_vlo, + ADA0 => scuba_vlo, ADA1 => scuba_vlo, ADA2 => scuba_vlo, + ADA3 => scuba_vlo, ADA4 => Address(0), ADA5 => Address(1), + ADA6 => Address(2), ADA7 => Address(3), ADA8 => Address(4), + ADA9 => Address(5), ADA10 => Address(6), ADA11 => Address(7), + ADA12 => Address(8), ADA13 => Address(9), CEA => OutClockEn, + CLKA => OutClock, OCEA => OutClockEn, WEA => scuba_vlo, + CSA0 => scuba_vlo, CSA1 => scuba_vlo, CSA2 => scuba_vlo, + RSTA => Reset, DIB0 => scuba_vlo, DIB1 => scuba_vlo, + DIB2 => scuba_vlo, DIB3 => scuba_vlo, DIB4 => scuba_vlo, + DIB5 => scuba_vlo, DIB6 => scuba_vlo, DIB7 => scuba_vlo, + DIB8 => scuba_vlo, DIB9 => scuba_vlo, DIB10 => scuba_vlo, + DIB11 => scuba_vlo, DIB12 => scuba_vlo, DIB13 => scuba_vlo, + DIB14 => scuba_vlo, DIB15 => scuba_vlo, DIB16 => scuba_vlo, + DIB17 => scuba_vlo, ADB0 => scuba_vhi, ADB1 => scuba_vlo, + ADB2 => scuba_vlo, ADB3 => scuba_vlo, ADB4 => scuba_vlo, + ADB5 => scuba_vlo, ADB6 => scuba_vlo, ADB7 => scuba_vlo, + ADB8 => scuba_vlo, ADB9 => scuba_vlo, ADB10 => scuba_vlo, + ADB11 => scuba_vlo, ADB12 => scuba_vlo, ADB13 => scuba_vlo, + CEB => scuba_vhi, CLKB => scuba_vlo, OCEB => scuba_vhi, + WEB => scuba_vlo, CSB0 => scuba_vlo, CSB1 => scuba_vlo, + CSB2 => scuba_vlo, RSTB => scuba_vlo, DOA0 => Q(0), DOA1 => Q(1), + DOA2 => Q(2), DOA3 => Q(3), DOA4 => Q(4), DOA5 => Q(5), DOA6 => Q(6), + DOA7 => Q(7), DOA8 => open, DOA9 => open, DOA10 => open, DOA11 => open, + DOA12 => open, DOA13 => open, DOA14 => open, DOA15 => open, + DOA16 => open, DOA17 => open, DOB0 => open, DOB1 => open, DOB2 => open, + DOB3 => open, DOB4 => open, DOB5 => open, DOB6 => open, DOB7 => open, + DOB8 => open, DOB9 => open, DOB10 => open, DOB11 => open, + DOB12 => open, DOB13 => open, DOB14 => open, DOB15 => open, + DOB16 => open, DOB17 => open); + +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of ROM4_Encoder is + for Structure + for all : VHI use entity ecp3.VHI(V); end for; + for all : VLO use entity ecp3.VLO(V); end for; + for all : DP16KC use entity ecp3.DP16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/tdc_releases/tdc_v1.4/ROM_encoder_3.vhd b/tdc_releases/tdc_v1.4/ROM_encoder_3.vhd new file mode 100644 index 0000000..765bf32 --- /dev/null +++ b/tdc_releases/tdc_v1.4/ROM_encoder_3.vhd @@ -0,0 +1,262 @@ +-- VHDL netlist generated by SCUBA Diamond_1.4_Production (87) +-- Module Version: 5.0 +--/opt/lattice/diamond/1.4/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 00 -rp 1100 -addr_width 10 -data_width 8 -num_rows 1024 -outdata REGISTERED -memfile /home/ugur/projects/encoder/encoder_304_with_more_bbl_errors/source/rom_encoder.mem -memformat orca -cascade -1 -e + +-- Mon Apr 16 15:10:22 2012 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity ROM_Encoder is + port ( + Address : in std_logic_vector(9 downto 0); + OutClock : in std_logic; + OutClockEn : in std_logic; + Reset : in std_logic; + Q : out std_logic_vector(7 downto 0)); +end ROM_Encoder; + +architecture Structure of ROM_Encoder is + + -- internal signal declarations + signal scuba_vhi : std_logic; + signal scuba_vlo : std_logic; + + -- local component declarations + component VHI + port (Z : out std_logic); + end component; + component VLO + port (Z : out std_logic); + end component; + component DP16KC + generic (INITVAL_3F : in string; INITVAL_3E : in string; + INITVAL_3D : in string; INITVAL_3C : in string; + INITVAL_3B : in string; INITVAL_3A : in string; + INITVAL_39 : in string; INITVAL_38 : in string; + INITVAL_37 : in string; INITVAL_36 : in string; + INITVAL_35 : in string; INITVAL_34 : in string; + INITVAL_33 : in string; INITVAL_32 : in string; + INITVAL_31 : in string; INITVAL_30 : in string; + INITVAL_2F : in string; INITVAL_2E : in string; + INITVAL_2D : in string; INITVAL_2C : in string; + INITVAL_2B : in string; INITVAL_2A : in string; + INITVAL_29 : in string; INITVAL_28 : in string; + INITVAL_27 : in string; INITVAL_26 : in string; + INITVAL_25 : in string; INITVAL_24 : in string; + INITVAL_23 : in string; INITVAL_22 : in string; + INITVAL_21 : in string; INITVAL_20 : in string; + INITVAL_1F : in string; INITVAL_1E : in string; + INITVAL_1D : in string; INITVAL_1C : in string; + INITVAL_1B : in string; INITVAL_1A : in string; + INITVAL_19 : in string; INITVAL_18 : in string; + INITVAL_17 : in string; INITVAL_16 : in string; + INITVAL_15 : in string; INITVAL_14 : in string; + INITVAL_13 : in string; INITVAL_12 : in string; + INITVAL_11 : in string; INITVAL_10 : in string; + INITVAL_0F : in string; INITVAL_0E : in string; + INITVAL_0D : in string; INITVAL_0C : in string; + INITVAL_0B : in string; INITVAL_0A : in string; + INITVAL_09 : in string; INITVAL_08 : in string; + INITVAL_07 : in string; INITVAL_06 : in string; + INITVAL_05 : in string; INITVAL_04 : in string; + INITVAL_03 : in string; INITVAL_02 : in string; + INITVAL_01 : in string; INITVAL_00 : in string; + GSR : in string; WRITEMODE_B : in string; + WRITEMODE_A : in string; CSDECODE_B : in string; + CSDECODE_A : in string; REGMODE_B : in string; + REGMODE_A : in string; DATA_WIDTH_B : in integer; + DATA_WIDTH_A : in integer); + port (DIA0 : in std_logic; DIA1 : in std_logic; + DIA2 : in std_logic; DIA3 : in std_logic; + DIA4 : in std_logic; DIA5 : in std_logic; + DIA6 : in std_logic; DIA7 : in std_logic; + DIA8 : in std_logic; DIA9 : in std_logic; + DIA10 : in std_logic; DIA11 : in std_logic; + DIA12 : in std_logic; DIA13 : in std_logic; + DIA14 : in std_logic; DIA15 : in std_logic; + DIA16 : in std_logic; DIA17 : in std_logic; + ADA0 : in std_logic; ADA1 : in std_logic; + ADA2 : in std_logic; ADA3 : in std_logic; + ADA4 : in std_logic; ADA5 : in std_logic; + ADA6 : in std_logic; ADA7 : in std_logic; + ADA8 : in std_logic; ADA9 : in std_logic; + ADA10 : in std_logic; ADA11 : in std_logic; + ADA12 : in std_logic; ADA13 : in std_logic; + CEA : in std_logic; CLKA : in std_logic; OCEA : in std_logic; + WEA : in std_logic; CSA0 : in std_logic; CSA1 : in std_logic; + CSA2 : in std_logic; RSTA : in std_logic; + DIB0 : in std_logic; DIB1 : in std_logic; + DIB2 : in std_logic; DIB3 : in std_logic; + DIB4 : in std_logic; DIB5 : in std_logic; + DIB6 : in std_logic; DIB7 : in std_logic; + DIB8 : in std_logic; DIB9 : in std_logic; + DIB10 : in std_logic; DIB11 : in std_logic; + DIB12 : in std_logic; DIB13 : in std_logic; + DIB14 : in std_logic; DIB15 : in std_logic; + DIB16 : in std_logic; DIB17 : in std_logic; + ADB0 : in std_logic; ADB1 : in std_logic; + ADB2 : in std_logic; ADB3 : in std_logic; + ADB4 : in std_logic; ADB5 : in std_logic; + ADB6 : in std_logic; ADB7 : in std_logic; + ADB8 : in std_logic; ADB9 : in std_logic; + ADB10 : in std_logic; ADB11 : in std_logic; + ADB12 : in std_logic; ADB13 : in std_logic; + CEB : in std_logic; CLKB : in std_logic; OCEB : in std_logic; + WEB : in std_logic; CSB0 : in std_logic; CSB1 : in std_logic; + CSB2 : in std_logic; RSTB : in std_logic; + DOA0 : out std_logic; DOA1 : out std_logic; + DOA2 : out std_logic; DOA3 : out std_logic; + DOA4 : out std_logic; DOA5 : out std_logic; + DOA6 : out std_logic; DOA7 : out std_logic; + DOA8 : out std_logic; DOA9 : out std_logic; + DOA10 : out std_logic; DOA11 : out std_logic; + DOA12 : out std_logic; DOA13 : out std_logic; + DOA14 : out std_logic; DOA15 : out std_logic; + DOA16 : out std_logic; DOA17 : out std_logic; + DOB0 : out std_logic; DOB1 : out std_logic; + DOB2 : out std_logic; DOB3 : out std_logic; + DOB4 : out std_logic; DOB5 : out std_logic; + DOB6 : out std_logic; DOB7 : out std_logic; + DOB8 : out std_logic; DOB9 : out std_logic; + DOB10 : out std_logic; DOB11 : out std_logic; + DOB12 : out std_logic; DOB13 : out std_logic; + DOB14 : out std_logic; DOB15 : out std_logic; + DOB16 : out std_logic; DOB17 : out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute MEM_LPC_FILE of ROM_Encoder_0_0_0 : label is "ROM_Encoder.lpc"; + attribute MEM_INIT_FILE of ROM_Encoder_0_0_0 : label is "rom_encoder.mem"; + attribute RESETMODE of ROM_Encoder_0_0_0 : label is "SYNC"; + +begin + -- component instantiation statements + scuba_vhi_inst : VHI + port map (Z => scuba_vhi); + + scuba_vlo_inst : VLO + port map (Z => scuba_vlo); + + ROM_Encoder_0_0_0 : DP16KC + generic map (INITVAL_3F => "0x00000000800008000081000000000000000000820000000081000820008200000000000008200083", + INITVAL_3E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000084", + INITVAL_3D => "0x00000000000000000000000000000000000000000000000083000830008300000000000008400084", + INITVAL_3C => "0x00000000000000000000000000000000000000000000000000000840008400000000000008500085", + INITVAL_3B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_39 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000085", + INITVAL_38 => "0x00000000000000000000000000000000000000000000000000000000008500000000000008600086", + INITVAL_37 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_36 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_35 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000085", + INITVAL_34 => "0x00000000000000000000000000000000000000000000000000000000008600000000000008600086", + INITVAL_33 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_32 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_31 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000086", + INITVAL_30 => "0x00000000000000000000000000000000000000000000000000000000008700000000000008700087", + INITVAL_2F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_29 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_28 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_27 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_26 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_25 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_24 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_23 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_22 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_21 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_20 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_19 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_18 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_17 => "0x00086000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_16 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_15 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_14 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_13 => "0x00085000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_12 => "0x00084000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_11 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_10 => "0x00083000000000000000000000000000000000000008200000000000000000081000800000000000", + INITVAL_0F => "0x00087000000000000000000870000000000000000000000000000000000000000000000000000000", + INITVAL_0E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0B => "0x00086000000000000000000860000000000000000000000000000000000000000000000000000000", + INITVAL_0A => "0x00085000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_09 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_08 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_07 => "0x00086000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_06 => "0x00085000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_05 => "0x00085000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_04 => "0x00084000000000000000000840000000000000000000000000000000000000083000830000000000", + INITVAL_03 => "0x00085000000000000000000840000000000000000000000000000000000000000000000000000000", + INITVAL_02 => "0x00084000000000000000000840008400000000000000000000000000000000000000000000000000", + INITVAL_01 => "0x00084000000000000000000830000000000000000000000000000000000000082000820000000000", + INITVAL_00 => "0x00083000000000000000000820008200081000000008200082000810000000081000800008000000", + CSDECODE_B => "0b111", CSDECODE_A => "0b000", WRITEMODE_B => "NORMAL", + WRITEMODE_A => "NORMAL", GSR => "DISABLED", REGMODE_B => "NOREG", + REGMODE_A => "OUTREG", DATA_WIDTH_B => 18, DATA_WIDTH_A => 18) + port map (DIA0 => scuba_vlo, DIA1 => scuba_vlo, DIA2 => scuba_vlo, + DIA3 => scuba_vlo, DIA4 => scuba_vlo, DIA5 => scuba_vlo, + DIA6 => scuba_vlo, DIA7 => scuba_vlo, DIA8 => scuba_vlo, + DIA9 => scuba_vlo, DIA10 => scuba_vlo, DIA11 => scuba_vlo, + DIA12 => scuba_vlo, DIA13 => scuba_vlo, DIA14 => scuba_vlo, + DIA15 => scuba_vlo, DIA16 => scuba_vlo, DIA17 => scuba_vlo, + ADA0 => scuba_vlo, ADA1 => scuba_vlo, ADA2 => scuba_vlo, + ADA3 => scuba_vlo, ADA4 => Address(0), ADA5 => Address(1), + ADA6 => Address(2), ADA7 => Address(3), ADA8 => Address(4), + ADA9 => Address(5), ADA10 => Address(6), ADA11 => Address(7), + ADA12 => Address(8), ADA13 => Address(9), CEA => OutClockEn, + CLKA => OutClock, OCEA => OutClockEn, WEA => scuba_vlo, + CSA0 => scuba_vlo, CSA1 => scuba_vlo, CSA2 => scuba_vlo, + RSTA => Reset, DIB0 => scuba_vlo, DIB1 => scuba_vlo, + DIB2 => scuba_vlo, DIB3 => scuba_vlo, DIB4 => scuba_vlo, + DIB5 => scuba_vlo, DIB6 => scuba_vlo, DIB7 => scuba_vlo, + DIB8 => scuba_vlo, DIB9 => scuba_vlo, DIB10 => scuba_vlo, + DIB11 => scuba_vlo, DIB12 => scuba_vlo, DIB13 => scuba_vlo, + DIB14 => scuba_vlo, DIB15 => scuba_vlo, DIB16 => scuba_vlo, + DIB17 => scuba_vlo, ADB0 => scuba_vlo, ADB1 => scuba_vlo, + ADB2 => scuba_vlo, ADB3 => scuba_vlo, ADB4 => scuba_vlo, + ADB5 => scuba_vlo, ADB6 => scuba_vlo, ADB7 => scuba_vlo, + ADB8 => scuba_vlo, ADB9 => scuba_vlo, ADB10 => scuba_vlo, + ADB11 => scuba_vlo, ADB12 => scuba_vlo, ADB13 => scuba_vlo, + CEB => scuba_vhi, CLKB => scuba_vlo, OCEB => scuba_vhi, + WEB => scuba_vlo, CSB0 => scuba_vlo, CSB1 => scuba_vlo, + CSB2 => scuba_vlo, RSTB => scuba_vlo, DOA0 => Q(0), DOA1 => Q(1), + DOA2 => Q(2), DOA3 => Q(3), DOA4 => Q(4), DOA5 => Q(5), DOA6 => Q(6), + DOA7 => Q(7), DOA8 => open, DOA9 => open, DOA10 => open, DOA11 => open, + DOA12 => open, DOA13 => open, DOA14 => open, DOA15 => open, + DOA16 => open, DOA17 => open, DOB0 => open, DOB1 => open, DOB2 => open, + DOB3 => open, DOB4 => open, DOB5 => open, DOB6 => open, DOB7 => open, + DOB8 => open, DOB9 => open, DOB10 => open, DOB11 => open, + DOB12 => open, DOB13 => open, DOB14 => open, DOB15 => open, + DOB16 => open, DOB17 => open); + +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of ROM_Encoder is + for Structure + for all : VHI use entity ecp3.VHI(V); end for; + for all : VLO use entity ecp3.VLO(V); end for; + for all : DP16KC use entity ecp3.DP16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/tdc_releases/tdc_v1.4/Readout.vhd b/tdc_releases/tdc_v1.4/Readout.vhd new file mode 100644 index 0000000..477ece9 --- /dev/null +++ b/tdc_releases/tdc_v1.4/Readout.vhd @@ -0,0 +1,947 @@ +------------------------------------------------------------------------------- +-- Title : Readout Entity +-- Project : +------------------------------------------------------------------------------- +-- File : Readout.vhd +-- Author : cugur@gsi.de +-- Created : 2012-10-25 +-- Last update: 2013-03-20 +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- +-- Copyright (c) 2012 +------------------------------------------------------------------------------- + +library IEEE; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; + +entity Readout is + generic ( + CHANNEL_NUMBER : integer range 2 to 65); + + port ( + CLK_200 : in std_logic; + RESET_200 : in std_logic; + CLK_100 : in std_logic; + RESET_100 : in std_logic; + RESET_COUNTERS : in std_logic; +-- + REFERENCE_TIME : in std_logic; + TRIGGER_TIME_IN : in std_logic_vector(38 downto 0); + TRG_WIN_PRE : in std_logic_vector(10 downto 0); + TRG_WIN_POST : in std_logic_vector(10 downto 0); +-- slow control + DEBUG_MODE_EN_IN : in std_logic; + TRIGGER_WIN_EN_IN : in std_logic; + +-- from the channels + CH_DATA_IN : in std_logic_vector_array_36(0 to CHANNEL_NUMBER); + CH_WCNT_IN : in unsigned_array_8(0 to CHANNEL_NUMBER-1); + CH_EMPTY_IN : in std_logic_vector(CHANNEL_NUMBER downto 0); + CH_FULL_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); + CH_ALMOST_FULL_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); +-- from the endpoint + TRG_DATA_VALID_IN : in std_logic; + VALID_TIMING_TRG_IN : in std_logic; + VALID_NOTIMING_TRG_IN : in std_logic; + INVALID_TRG_IN : in std_logic; + TMGTRG_TIMEOUT_IN : in std_logic; + SPIKE_DETECTED_IN : in std_logic; + MULTI_TMG_TRG_IN : in std_logic; + SPURIOUS_TRG_IN : in std_logic; + TRG_NUMBER_IN : in std_logic_vector(15 downto 0); + TRG_CODE_IN : in std_logic_vector(7 downto 0); + TRG_INFORMATION_IN : in std_logic_vector(23 downto 0); + TRG_TYPE_IN : in std_logic_vector(3 downto 0); +-- to the endpoint + TRG_RELEASE_OUT : out std_logic; + TRG_STATUSBIT_OUT : out std_logic_vector(31 downto 0); + DATA_OUT : out std_logic_vector(31 downto 0); + DATA_WRITE_OUT : out std_logic; + DATA_FINISHED_OUT : out std_logic; +-- to the channels + READ_EN_OUT : out std_logic_vector(CHANNEL_NUMBER-1 downto 0); + TRIGGER_WIN_END_OUT : out std_logic; +-- + STATUS_REGISTERS_BUS_OUT : out std_logic_vector_array_32(0 to 18); + READOUT_DEBUG : out std_logic_vector(31 downto 0) + ); + +end Readout; + +architecture behavioral of Readout is + +------------------------------------------------------------------------------- +-- Signal Declarations +------------------------------------------------------------------------------- + + -- slow control + signal slow_control_ch_empty_i : std_logic_vector(63 downto 0); + + -- trigger window + signal start_trg_win_cnt : std_logic := '0'; + signal start_trg_win_cnt_200_p : std_logic; + signal trg_win_post_200 : std_logic_vector(10 downto 0); + signal trg_win_cnt : std_logic_vector(11 downto 0); + signal trg_win_end_200 : std_logic := '0'; + signal trg_win_end_200_p : std_logic; + signal trg_win_end_100_p : std_logic; + signal trg_win_end_100_reg : std_logic; + signal trg_win_end_100_2reg : std_logic; + signal trg_win_end_100_3reg : std_logic; + signal trg_win_end_100_4reg : std_logic; + signal TW_pre : std_logic_vector(38 downto 0); +-- signal TW_post : std_logic_vector(38 downto 0); + signal trg_win_l : std_logic; +-- signal trg_win_r : std_logic; + -- channel signals + signal ch_data_reg : std_logic_vector_array_36(0 to CHANNEL_NUMBER); + signal ch_data_2reg : std_logic_vector_array_36(0 to CHANNEL_NUMBER); + --signal ch_data_3reg : std_logic_vector_array_36(0 to CHANNEL_NUMBER); + signal ch_wcnt_reg : unsigned_array_8(0 to CHANNEL_NUMBER-1) := (others => (others => '1')); + signal ch_wcnt_2reg : unsigned_array_8(0 to CHANNEL_NUMBER-1) := (others => (others => '1')); + signal ch_empty_reg : std_logic_vector(CHANNEL_NUMBER downto 0); + signal ch_empty_2reg : std_logic_vector(CHANNEL_NUMBER downto 0); + signal ch_empty_3reg : std_logic_vector(CHANNEL_NUMBER downto 0); + signal ch_empty_4reg : std_logic_vector(CHANNEL_NUMBER downto 0); + signal ch_hit_time : std_logic_vector(38 downto 0); + signal ch_epoch_cntr_i : std_logic_vector(27 downto 0); + -- readout fsm + type FSM_READ is (IDLE, WAIT_FOR_TRG_WIND_END, RD_CH, WAIT_FOR_LVL1_TRG_A, WAIT_FOR_LVL1_TRG_B, + WAIT_FOR_LVL1_TRG_C, SEND_STATUS, SEND_TRG_RELEASE_A, SEND_TRG_RELEASE_B); + signal RD_CURRENT : FSM_READ := IDLE; + signal RD_NEXT : FSM_READ; + type FSM_WRITE is (IDLE, WR_CH); + signal WR_CURRENT : FSM_WRITE := IDLE; + signal WR_NEXT : FSM_WRITE; + + signal start_trg_win_cnt_fsm : std_logic; + signal rd_fsm_debug_fsm : std_logic_vector(3 downto 0); + signal wr_fsm_debug_fsm : std_logic_vector(3 downto 0); + signal rd_en_fsm : std_logic_vector(CHANNEL_NUMBER-1 downto 0); + signal data_finished_fsm : std_logic; + signal wr_finished_fsm : std_logic; + signal trg_release_fsm : std_logic; + signal wr_header_fsm : std_logic; + signal wr_ch_data_fsm : std_logic; + signal wr_status_fsm : std_logic; + signal wrong_readout_fsm : std_logic; + signal rd_number_fsm : unsigned(7 downto 0); + signal rd_number : unsigned(7 downto 0); + signal wr_number_fsm : unsigned(7 downto 0); + signal wr_number : unsigned(7 downto 0); + signal fifo_nr_rd_fsm : integer range 0 to CHANNEL_NUMBER := 0; + signal fifo_nr_wr_fsm : integer range 0 to CHANNEL_NUMBER := 0; + +-- signal wr_trailer_fsm : std_logic; + signal idle_fsm : std_logic; + signal readout_fsm : std_logic; + signal wait_fsm : std_logic; + -- fifo number + type Std_Logic_8_array is array (0 to 8) of std_logic_vector(3 downto 0); + signal empty_channels : std_logic_vector(CHANNEL_NUMBER-1 downto 0); + signal fifo_nr_rd : integer range 0 to CHANNEL_NUMBER := 0; + signal fifo_nr_wr : integer range 0 to CHANNEL_NUMBER := 0; + signal fifo_nr_wr_reg : integer range 0 to CHANNEL_NUMBER := 0; + signal fifo_nr_wr_2reg : integer range 0 to CHANNEL_NUMBER := 0; + signal fifo_nr_wr_3reg : integer range 0 to CHANNEL_NUMBER := 0; + -- fifo read + signal rd_en : std_logic_vector(CHANNEL_NUMBER-1 downto 0); + -- data mux + signal wr_header : std_logic; + signal wr_ch_data_i : std_logic; + signal wr_ch_data_reg : std_logic; + signal wr_ch_data_2reg : std_logic; + signal wr_status : std_logic; + signal wr_trailer : std_logic; + signal stop_status_i : std_logic; + -- to endpoint + signal data_out_reg : std_logic_vector(31 downto 0); + signal data_wr_reg : std_logic; + signal data_finished : std_logic; + signal wr_finished : std_logic; + signal wr_finished_reg : std_logic; + signal wr_finished_2reg : std_logic; + signal trg_release_reg : std_logic; + -- statistics + signal trig_number : unsigned(23 downto 0) := (others => '0'); + signal release_number : unsigned(23 downto 0) := (others => '0'); + signal valid_tmg_trig_number : unsigned(23 downto 0) := (others => '0'); + signal valid_NOtmg_trig_number : unsigned(23 downto 0) := (others => '0'); + signal invalid_trig_number : unsigned(23 downto 0) := (others => '0'); + signal multi_tmg_trig_number : unsigned(23 downto 0) := (others => '0'); + signal spurious_trig_number : unsigned(23 downto 0) := (others => '0'); + signal wrong_readout_number : unsigned(23 downto 0) := (others => '0'); + signal spike_number : unsigned(23 downto 0) := (others => '0'); + signal timeout_number : unsigned(23 downto 0) := (others => '0'); + signal total_empty_channel : unsigned(23 downto 0) := (others => '0'); + signal idle_time : unsigned(23 downto 0) := (others => '0'); + signal readout_time : unsigned(23 downto 0) := (others => '0'); + signal wait_time : unsigned(23 downto 0) := (others => '0'); + signal finished_number : unsigned(23 downto 0) := (others => '0'); + signal valid_timing_trg_p : std_logic; + signal valid_notiming_trg_p : std_logic; + signal invalid_trg_p : std_logic; + signal multi_tmg_trg_p : std_logic; + signal spurious_trg_p : std_logic; + signal spike_detected_p : std_logic; + signal timeout_detected_p : std_logic; + signal idle_time_up : std_logic; + signal readout_time_up : std_logic; + signal wait_time_up : std_logic; + signal wrong_readout_up : std_logic; + signal finished_i : std_logic; + -- debug + signal header_error_bits : std_logic_vector(15 downto 0); + signal trailer_error_bits : std_logic_vector(15 downto 0); + signal ch_full_i : std_logic; + signal ch_almost_full_i : std_logic; + signal rd_fsm_debug : std_logic_vector(3 downto 0); + signal wr_fsm_debug : std_logic_vector(3 downto 0); + +begin -- behavioral +------------------------------------------------------------------------------- +-- Trigger window +------------------------------------------------------------------------------- +-- Trigger window start logic + StartTrgWinCntSync : pulse_sync + port map ( + CLK_A_IN => CLK_100, + RESET_A_IN => RESET_100, + PULSE_A_IN => start_trg_win_cnt, + CLK_B_IN => CLK_200, + RESET_B_IN => RESET_200, + PULSE_B_OUT => start_trg_win_cnt_200_p); + +-- Trigger window end logic + Check_Trg_Win_End_Conrollers : process (CLK_200) + begin + if rising_edge(CLK_200) then + if RESET_200 = '1' then + trg_win_cnt <= '1' & trg_win_post_200; + elsif start_trg_win_cnt_200_p = '1' then + trg_win_end_200 <= '0'; + trg_win_cnt <= "000000000001"; + elsif trg_win_cnt(10 downto 0) = trg_win_post_200 then + trg_win_end_200 <= '1'; + trg_win_cnt(11) <= '1'; + else + trg_win_end_200 <= '0'; + trg_win_cnt <= std_logic_vector(unsigned(trg_win_cnt) + to_unsigned(1, 1)); + end if; + end if; + end process Check_Trg_Win_End_Conrollers; + + TriggerWinEndPulse200 : edge_to_pulse + port map ( + clock => CLK_200, + en_clk => '1', + signal_in => trg_win_end_200, + pulse => trg_win_end_200_p); + TRIGGER_WIN_END_OUT <= trg_win_end_200_p; + + SyncTriggerWinEndPulse100 : pulse_sync + port map ( + CLK_A_IN => CLK_200, + RESET_A_IN => RESET_200, + PULSE_A_IN => trg_win_end_200_p, + CLK_B_IN => CLK_100, + RESET_B_IN => RESET_100, + PULSE_B_OUT => trg_win_end_100_p); + trg_win_end_100_reg <= trg_win_end_100_p when rising_edge(CLK_100); + trg_win_end_100_2reg <= trg_win_end_100_reg when rising_edge(CLK_100); + trg_win_end_100_3reg <= trg_win_end_100_2reg when rising_edge(CLK_100); + trg_win_end_100_4reg <= trg_win_end_100_3reg when rising_edge(CLK_100); + +-- Trigger window borders + Trg_Win_Calculation : process (CLK_100) + begin + if rising_edge(CLK_100) then + TW_pre <= std_logic_vector(to_unsigned(to_integer(unsigned(TRIGGER_TIME_IN))-to_integer(unsigned(TRG_WIN_PRE)), 39)); +-- TW_post <= std_logic_vector(to_unsigned(to_integer(unsigned(TRIGGER_TIME_IN))+to_integer(unsigned(TRG_WIN_POST)), 39)); + end if; + end process Trg_Win_Calculation; + + CaptureChannelWCount : process (CLK_200) + begin + if rising_edge(CLK_200) then + if trg_win_end_200_p = '1' then + ch_wcnt_reg <= CH_WCNT_IN after 10 ps; + end if; + end if; + end process CaptureChannelWCount; + ch_wcnt_2reg <= ch_wcnt_reg when rising_edge(CLK_100); + +-- Channel Hit Time Determination + ChannelEpochCounter : process (CLK_100) + begin + if rising_edge(CLK_100) then + if ch_data_reg(fifo_nr_wr_2reg)(31 downto 29) = "011" then + ch_epoch_cntr_i <= ch_data_reg(fifo_nr_wr_2reg)(27 downto 0); + end if; + end if; + end process ChannelEpochCounter; + + ChannelHitTime : process (CLK_100) + begin + if rising_edge(CLK_100) then + if ch_data_reg(fifo_nr_wr_2reg)(31) = '1' then + ch_hit_time <= ch_epoch_cntr_i & ch_data_reg(fifo_nr_wr_2reg)(10 downto 0); + elsif ch_data_reg(fifo_nr_wr_2reg)(31 downto 29) = "011" then + ch_hit_time <= (others => '0'); + end if; + end if; + end process ChannelHitTime; + +-- Controls if the data coming from the channel is greater than the trigger window pre-edge + Check_Trg_Win_Left : process (TW_pre, ch_hit_time) + begin + --if rising_edge(CLK_100) then + if to_integer(unsigned(TW_pre)) <= to_integer(unsigned(ch_hit_time)) then + trg_win_l <= '1'; + else + trg_win_l <= '0'; + end if; + --end if; + end process Check_Trg_Win_Left; + +-- Controls if the data coming from the channel is smaller than the trigger window post-edge + --Check_Trg_Win_Right : process (RESET_100, TW_post, ch_hit_time) + --begin + -- --if rising_edge(CLK_100) then + -- if RESET_100 = '1' then + -- trg_win_r <= '0'; + -- elsif to_integer(unsigned(ch_hit_time)) <= to_integer(unsigned(TW_post)) then + -- trg_win_r <= '1'; + -- else + -- trg_win_r <= '0'; + -- end if; + -- --end if; + --end process Check_Trg_Win_Right; + +------------------------------------------------------------------------------- +-- Readout +------------------------------------------------------------------------------- +-- Readout fsm + RD_FSM_CLK : process (CLK_100, RESET_100) + begin + if rising_edge(CLK_100) then + RD_CURRENT <= RD_NEXT; + start_trg_win_cnt <= start_trg_win_cnt_fsm; + rd_en <= rd_en_fsm; + wr_header <= wr_header_fsm; + wr_status <= wr_status_fsm; + data_finished <= data_finished_fsm; + trg_release_reg <= trg_release_fsm; + wrong_readout_up <= wrong_readout_fsm; + idle_time_up <= idle_fsm; + readout_time_up <= readout_fsm; + wait_time_up <= wait_fsm; + rd_number <= rd_number_fsm; + fifo_nr_rd <= fifo_nr_rd_fsm; + rd_fsm_debug <= rd_fsm_debug_fsm; + end if; + end process RD_FSM_CLK; + READ_EN_OUT <= rd_en; + + RD_FSM_PROC : process (RD_CURRENT, VALID_TIMING_TRG_IN, VALID_NOTIMING_TRG_IN, trg_win_end_100_p, + ch_empty_reg, TRG_DATA_VALID_IN, INVALID_TRG_IN, TMGTRG_TIMEOUT_IN, + TRG_TYPE_IN, SPURIOUS_TRG_IN, stop_status_i, DEBUG_MODE_EN_IN, rd_number, fifo_nr_rd) + begin + + start_trg_win_cnt_fsm <= '0'; + rd_en_fsm <= (others => '0'); + wr_header_fsm <= '0'; + data_finished_fsm <= '0'; + trg_release_fsm <= '0'; + wrong_readout_fsm <= '0'; + idle_fsm <= '0'; + readout_fsm <= '0'; + wait_fsm <= '0'; + wr_status_fsm <= '0'; + rd_number_fsm <= (others => '0'); + fifo_nr_rd_fsm <= fifo_nr_rd; + rd_fsm_debug_fsm <= x"0"; + RD_NEXT <= IDLE; + + case (RD_CURRENT) is + when IDLE => + if VALID_TIMING_TRG_IN = '1' then + RD_NEXT <= WAIT_FOR_TRG_WIND_END; --WR_HEADER_A; + start_trg_win_cnt_fsm <= '1'; + wr_header_fsm <= '1'; + readout_fsm <= '1'; + elsif VALID_NOTIMING_TRG_IN = '1' then + if TRG_TYPE_IN = x"E" then + wr_header_fsm <= '1'; + RD_NEXT <= SEND_STATUS; + else + data_finished_fsm <= '1'; + RD_NEXT <= SEND_TRG_RELEASE_A; + end if; + elsif INVALID_TRG_IN = '1' then + RD_NEXT <= SEND_TRG_RELEASE_A; + data_finished_fsm <= '1'; + else + RD_NEXT <= IDLE; + end if; + idle_fsm <= '1'; + rd_fsm_debug_fsm <= x"1"; + + --when WR_HEADER_A => + -- RD_NEXT <= WAIT_FOR_TRG_WIND_END; + -- wr_header_fsm <= '1'; + -- readout_fsm <= '1'; + -- rd_fsm_debug_fsm <= x"3"; + + when WAIT_FOR_TRG_WIND_END => + if trg_win_end_100_p = '1' then + RD_NEXT <= RD_CH; + else + RD_NEXT <= WAIT_FOR_TRG_WIND_END; + end if; + wait_fsm <= '1'; + rd_fsm_debug_fsm <= x"2"; + + when RD_CH => + if rd_number /= ch_wcnt_2reg(fifo_nr_rd) then + rd_en_fsm(fifo_nr_rd) <= '1'; + rd_number_fsm <= rd_number + to_unsigned(1, 8); + fifo_nr_rd_fsm <= fifo_nr_rd; + RD_NEXT <= RD_CH; + elsif fifo_nr_rd = CHANNEL_NUMBER-1 then + rd_en_fsm(fifo_nr_rd) <= '0'; + rd_number_fsm <= (others => '0'); + if DEBUG_MODE_EN_IN = '1' then + RD_NEXT <= SEND_STATUS; + else + RD_NEXT <= WAIT_FOR_LVL1_TRG_A; + end if; + else + rd_number_fsm <= (others => '0'); + fifo_nr_rd_fsm <= fifo_nr_rd + 1; + RD_NEXT <= RD_CH; + end if; + readout_fsm <= '1'; + rd_fsm_debug_fsm <= x"3"; + + when WAIT_FOR_LVL1_TRG_A => + if TRG_DATA_VALID_IN = '1' then + RD_NEXT <= WAIT_FOR_LVL1_TRG_B; + elsif TMGTRG_TIMEOUT_IN = '1' then + RD_NEXT <= IDLE; + else + RD_NEXT <= WAIT_FOR_LVL1_TRG_A; + end if; + wait_fsm <= '1'; + rd_fsm_debug_fsm <= x"4"; + + when WAIT_FOR_LVL1_TRG_B => + RD_NEXT <= WAIT_FOR_LVL1_TRG_C; + wait_fsm <= '1'; + rd_fsm_debug_fsm <= x"5"; + + when WAIT_FOR_LVL1_TRG_C => + if SPURIOUS_TRG_IN = '1' then + wrong_readout_fsm <= '1'; + end if; + RD_NEXT <= SEND_TRG_RELEASE_A; + wait_fsm <= '1'; + rd_fsm_debug_fsm <= x"6"; + + when SEND_STATUS => + if stop_status_i = '1' then + if DEBUG_MODE_EN_IN = '1' then + RD_NEXT <= WAIT_FOR_LVL1_TRG_A; + else + RD_NEXT <= SEND_TRG_RELEASE_A; + end if; + data_finished_fsm <= '1'; + else + RD_NEXT <= SEND_STATUS; + wr_status_fsm <= '1'; + end if; + readout_fsm <= '1'; + rd_fsm_debug_fsm <= x"7"; + + when SEND_TRG_RELEASE_A => + RD_NEXT <= SEND_TRG_RELEASE_B; + trg_release_fsm <= '1'; + fifo_nr_rd_fsm <= 0; + readout_fsm <= '1'; + rd_fsm_debug_fsm <= x"8"; + + when SEND_TRG_RELEASE_B => + RD_NEXT <= IDLE; + wait_fsm <= '1'; + rd_fsm_debug_fsm <= x"9"; + + when others => + RD_NEXT <= IDLE; + rd_fsm_debug_fsm <= x"F"; + end case; + end process RD_FSM_PROC; + + --purpose: FSM for writing data to buffer 0 + WR_FSM_CLK : process (CLK_100) + begin + if rising_edge(CLK_100) then + WR_CURRENT <= WR_NEXT; + wr_ch_data_i <= wr_ch_data_fsm; + wr_number <= wr_number_fsm; + fifo_nr_wr <= fifo_nr_wr_fsm; + wr_finished <= wr_finished_fsm; + wr_fsm_debug <= wr_fsm_debug_fsm; + end if; + end process WR_FSM_CLK; + + WR_FSM : process (WR_CURRENT, trg_win_end_100_3reg, TRG_TYPE_IN, wr_number, ch_wcnt_2reg, fifo_nr_wr) + + begin + + WR_NEXT <= WR_CURRENT; + wr_ch_data_fsm <= '0'; + wr_number_fsm <= (others => '0'); + fifo_nr_wr_fsm <= 0; + wr_finished_fsm <= '0'; + + case (WR_CURRENT) is + when IDLE => + if trg_win_end_100_3reg = '1' then + wr_number_fsm <= ch_wcnt_2reg(0); + WR_NEXT <= WR_CH; + else + WR_NEXT <= IDLE; + end if; + wr_fsm_debug_fsm <= x"1"; +-- + when WR_CH => + if wr_number /= x"00" then + wr_ch_data_fsm <= '1'; + wr_number_fsm <= wr_number - to_unsigned(1, 8); + fifo_nr_wr_fsm <= fifo_nr_wr; + wr_fsm_debug_fsm <= x"2"; + elsif fifo_nr_wr = CHANNEL_NUMBER-1 then + wr_ch_data_fsm <= '0'; + wr_number_fsm <= (others => '0'); + wr_finished_fsm <= '1'; + wr_fsm_debug_fsm <= x"3"; + WR_NEXT <= IDLE; + else + wr_number_fsm <= ch_wcnt_2reg(fifo_nr_wr+1); + fifo_nr_wr_fsm <= fifo_nr_wr + 1; + wr_fsm_debug_fsm <= x"4"; + end if; +-- + when others => + WR_NEXT <= IDLE; + wr_fsm_debug_fsm <= x"F"; + + end case; + end process WR_FSM; + + fifo_nr_wr_reg <= fifo_nr_wr when rising_edge(CLK_100); + fifo_nr_wr_2reg <= fifo_nr_wr_reg when rising_edge(CLK_100); + fifo_nr_wr_3reg <= fifo_nr_wr_2reg when rising_edge(CLK_100); + wr_ch_data_reg <= wr_ch_data_i when rising_edge(CLK_100); + wr_ch_data_2reg <= wr_ch_data_reg when rising_edge(CLK_100); + wr_finished_reg <= wr_finished when rising_edge(CLK_100); + wr_finished_2reg <= wr_finished_reg when rising_edge(CLK_100); + +------------------------------------------------------------------------------- +-- Data out mux +------------------------------------------------------------------------------- + Data_Out_MUX : process (CLK_100) + variable i : integer := 0; + begin + if rising_edge(CLK_100) then + if wr_header = '1' then + data_out_reg <= "001" & "0" & TRG_TYPE_IN & TRG_CODE_IN & header_error_bits; + data_wr_reg <= '1'; + stop_status_i <= '0'; + elsif wr_ch_data_2reg = '1' then + if TRIGGER_WIN_EN_IN = '1' then -- trigger window enabled + if ch_data_2reg(fifo_nr_wr_3reg)(31 downto 29) = "011" then + data_out_reg <= ch_data_2reg(fifo_nr_wr_3reg)(31 downto 0); + data_wr_reg <= '1'; + --elsif (TW_pre(10) = '1' and ref_time_coarse(10) = '0') or (TW_post(10) = '0' and ref_time_coarse(10) = '1') then -- if one of the trigger window edges has an overflow + -- if (trg_win_l = '0' and trg_win_r = '1') or (trg_win_l = '1' and trg_win_r = '0') then + -- data_out_reg <= ch_data_2reg(fifo_nr); + -- data_wr_reg <= '1'; + -- else + -- data_out_reg <= (others => '1'); + -- data_wr_reg <= '0'; + -- end if; + else -- if both of the trigger window edges are in the coarse counter boundries + if (trg_win_l = '1') then -- and trg_win_r = '1') then + data_out_reg <= ch_data_2reg(fifo_nr_wr_3reg)(31 downto 0); + data_wr_reg <= '1'; + else + data_out_reg <= (others => '1'); + data_wr_reg <= '0'; + end if; + end if; + stop_status_i <= '0'; + else -- trigger window disabled + data_out_reg <= ch_data_2reg(fifo_nr_wr_3reg)(31 downto 0); + data_wr_reg <= '1'; + stop_status_i <= '0'; + end if; + elsif wr_status = '1' then + case i is + when 0 => data_out_reg <= "010" & "00000" & std_logic_vector(trig_number); + when 1 => data_out_reg <= "010" & "00001" & std_logic_vector(release_number); + when 2 => data_out_reg <= "010" & "00010" & std_logic_vector(valid_tmg_trig_number); + when 3 => data_out_reg <= "010" & "00011" & std_logic_vector(valid_NOtmg_trig_number); + when 4 => data_out_reg <= "010" & "00100" & std_logic_vector(invalid_trig_number); + when 5 => data_out_reg <= "010" & "00101" & std_logic_vector(multi_tmg_trig_number); + when 6 => data_out_reg <= "010" & "00110" & std_logic_vector(spurious_trig_number); + when 7 => data_out_reg <= "010" & "00111" & std_logic_vector(wrong_readout_number); + when 8 => data_out_reg <= "010" & "01000" & std_logic_vector(spike_number); + when 9 => data_out_reg <= "010" & "01001" & std_logic_vector(idle_time); + when 10 => data_out_reg <= "010" & "01010" & std_logic_vector(wait_time); + when 11 => data_out_reg <= "010" & "01011" & std_logic_vector(total_empty_channel); + when 12 => data_out_reg <= "010" & "01100" & std_logic_vector(readout_time); + stop_status_i <= '1'; + when 13 => data_out_reg <= "010" & "01101" & std_logic_vector(timeout_number); + i := -1; + when others => null; + end case; + data_wr_reg <= '1'; + i := i+1; + elsif wr_trailer = '1' then + data_out_reg <= "011" & "0000000000000" & trailer_error_bits; + data_wr_reg <= '1'; + stop_status_i <= '0'; + else + data_out_reg <= (others => '1'); + data_wr_reg <= '0'; + stop_status_i <= '0'; + end if; + end if; + end process Data_Out_MUX; + + DATA_OUT <= data_out_reg; + DATA_WRITE_OUT <= data_wr_reg; + finished_i <= (data_finished or wr_finished_2reg) when rising_edge(CLK_100); + DATA_FINISHED_OUT <= finished_i; + TRG_RELEASE_OUT <= trg_release_reg; + TRG_STATUSBIT_OUT <= (others => '0'); + READOUT_DEBUG(3 downto 0) <= rd_fsm_debug; + READOUT_DEBUG(7 downto 4) <= wr_fsm_debug; + READOUT_DEBUG(8) <= data_wr_reg; + READOUT_DEBUG(9) <= finished_i; + READOUT_DEBUG(10) <= trg_release_reg; + READOUT_DEBUG(16 downto 11) <= data_out_reg(27 downto 22); + READOUT_DEBUG(31 downto 17) <= (others => '0'); + + -- Error, warning bits set in the header + header_error_bits(15 downto 3) <= (others => '0'); + header_error_bits(0) <= '0'; +--header_error_bits(0) <= lost_hit_i; -- if there is at least one lost hit (can be more if the FIFO is full). + header_error_bits(1) <= ch_full_i; + header_error_bits(2) <= '0'; --ch_almost_full_i; + + -- Error, warning bits set in the trailer + trailer_error_bits <= (others => '0'); + -- trailer_error_bits (0) <= wrong_readout_i; -- if there is a wrong readout because of a spurious timing trigger + + ch_full_i <= or_all(CH_FULL_IN); + ch_almost_full_i <= or_all(CH_ALMOST_FULL_IN); + + + +------------------------------------------------------------------------------- +-- Debug and statistics words +------------------------------------------------------------------------------- + + edge_to_pulse_1 : edge_to_pulse + port map ( + clock => CLK_100, + en_clk => '1', + signal_in => VALID_TIMING_TRG_IN, + pulse => valid_timing_trg_p); + + edge_to_pulse_2 : edge_to_pulse + port map ( + clock => CLK_100, + en_clk => '1', + signal_in => VALID_NOTIMING_TRG_IN, + pulse => valid_notiming_trg_p); + + edge_to_pulse_3 : edge_to_pulse + port map ( + clock => CLK_100, + en_clk => '1', + signal_in => INVALID_TRG_IN, + pulse => invalid_trg_p); + + edge_to_pulse_4 : edge_to_pulse + port map ( + clock => CLK_100, + en_clk => '1', + signal_in => MULTI_TMG_TRG_IN, + pulse => multi_tmg_trg_p); + + edge_to_pulse_5 : edge_to_pulse + port map ( + clock => CLK_100, + en_clk => '1', + signal_in => SPURIOUS_TRG_IN, + pulse => spurious_trg_p); + + edge_to_pulse_6 : edge_to_pulse + port map ( + clock => CLK_100, + en_clk => '1', + signal_in => SPIKE_DETECTED_IN, + pulse => spike_detected_p); + + edge_to_pulse_7 : edge_to_pulse + port map ( + clock => CLK_100, + en_clk => '1', + signal_in => TMGTRG_TIMEOUT_IN, + pulse => timeout_detected_p); + +-- Internal trigger number counter (only valid triggers) + Statistics_Trigger_Number : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + trig_number <= (others => '0'); + elsif valid_timing_trg_p = '1' or valid_notiming_trg_p = '1' then + trig_number <= trig_number + to_unsigned(1, 1); + end if; + end if; + end process Statistics_Trigger_Number; + +-- Internal release number counter + Statistics_Release_Number : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + release_number <= (others => '0'); + elsif trg_release_reg = '1' then + release_number <= release_number + to_unsigned(1, 1); + end if; + end if; + end process Statistics_Release_Number; + +-- Internal valid timing trigger number counter + Statistics_Valid_Timing_Trigger_Number : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + valid_tmg_trig_number <= (others => '0'); + elsif valid_timing_trg_p = '1' then + valid_tmg_trig_number <= valid_tmg_trig_number + to_unsigned(1, 1); + end if; + end if; + end process Statistics_Valid_Timing_Trigger_Number; + +-- Internal valid NOtiming trigger number counter + Statistics_Valid_NoTiming_Trigger_Number : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + valid_NOtmg_trig_number <= (others => '0'); + elsif valid_notiming_trg_p = '1' then + valid_NOtmg_trig_number <= valid_NOtmg_trig_number + to_unsigned(1, 1); + end if; + end if; + end process Statistics_Valid_NoTiming_Trigger_Number; + +-- Internal invalid trigger number counter + Statistics_Invalid_Trigger_Number : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + invalid_trig_number <= (others => '0'); + elsif invalid_trg_p = '1' then + invalid_trig_number <= invalid_trig_number + to_unsigned(1, 1); + end if; + end if; + end process Statistics_Invalid_Trigger_Number; + +-- Internal multi timing trigger number counter + Statistics_Multi_Timing_Trigger_Number : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + multi_tmg_trig_number <= (others => '0'); + elsif multi_tmg_trg_p = '1' then + multi_tmg_trig_number <= multi_tmg_trig_number + to_unsigned(1, 1); + end if; + end if; + end process Statistics_Multi_Timing_Trigger_Number; + +-- Internal spurious trigger number counter + Statistics_Spurious_Trigger_Number : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + spurious_trig_number <= (others => '0'); + elsif spurious_trg_p = '1' then + spurious_trig_number <= spurious_trig_number + to_unsigned(1, 1); + end if; + end if; + end process Statistics_Spurious_Trigger_Number; + +-- Number of wrong readout becasue of spurious trigger + Statistics_Wrong_Readout_Number : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + wrong_readout_number <= (others => '0'); + elsif wrong_readout_up = '1' then + wrong_readout_number <= wrong_readout_number + to_unsigned(1, 1); + end if; + end if; + end process Statistics_Wrong_Readout_Number; + +-- Internal spike number counter + Statistics_Spike_Number : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + spike_number <= (others => '0'); + elsif spike_detected_p = '1' then + spike_number <= spike_number + to_unsigned(1, 1); + end if; + end if; + end process Statistics_Spike_Number; + +-- Internal timeout number counter + Statistics_Timeout_Number : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + timeout_number <= (others => '0'); + elsif timeout_detected_p = '1' then + timeout_number <= timeout_number + to_unsigned(1, 1); + end if; + end if; + end process Statistics_Timeout_Number; + +-- IDLE time of the TDC readout + Statistics_Idle_Time : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + idle_time <= (others => '0'); + elsif idle_time_up = '1' then + idle_time <= idle_time + to_unsigned(1, 1); + end if; + end if; + end process Statistics_Idle_Time; + +-- Readout and Wait time of the TDC readout + Statistics_Readout_Wait_Time : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + readout_time <= (others => '0'); + wait_time <= (others => '0'); + elsif readout_time_up = '1' then + readout_time <= readout_time + to_unsigned(1, 1); + elsif wait_time_up = '1' then + wait_time <= wait_time + to_unsigned(1, 1); + end if; + end if; + end process Statistics_Readout_Wait_Time; + +-- Empty channel number + Statistics_Empty_Channel_Number : process (CLK_100) + variable i : integer := CHANNEL_NUMBER; + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + total_empty_channel <= (others => '0'); + i := CHANNEL_NUMBER; + elsif trg_win_end_100_p = '1' then + empty_channels(CHANNEL_NUMBER-1 downto 0) <= CH_EMPTY_IN(CHANNEL_NUMBER-1 downto 0); + i := 0; + elsif i = CHANNEL_NUMBER then + i := i; + elsif empty_channels(i) = '1' then + total_empty_channel <= total_empty_channel + to_unsigned(1, 1); + i := i + 1; + else + i := i + 1; + end if; + end if; + end process Statistics_Empty_Channel_Number; + + -- Number of sent data finished + Statistics_Finished_Number : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + finished_number <= (others => '0'); + elsif finished_i = '1' then + finished_number <= finished_number + to_unsigned(1, 1); + end if; + end if; + end process Statistics_Finished_Number; + + +------------------------------------------------------------------------------- +-- STATUS REGISTERS BUS +------------------------------------------------------------------------------- + STATUS_REGISTERS_BUS_OUT(0)(3 downto 0) <= rd_fsm_debug; + STATUS_REGISTERS_BUS_OUT(0)(7 downto 4) <= wr_fsm_debug; + STATUS_REGISTERS_BUS_OUT(0)(15 downto 8) <= std_logic_vector(to_unsigned(CHANNEL_NUMBER-1, 8)); + STATUS_REGISTERS_BUS_OUT(0)(16) <= REFERENCE_TIME when rising_edge(CLK_100); + STATUS_REGISTERS_BUS_OUT(0)(27 downto 17) <= (others => '0'); + STATUS_REGISTERS_BUS_OUT(0)(31 downto 28) <= TRG_TYPE_IN when rising_edge(CLK_100); + STATUS_REGISTERS_BUS_OUT(1) <= slow_control_ch_empty_i(31 downto 0); + STATUS_REGISTERS_BUS_OUT(2) <= slow_control_ch_empty_i(63 downto 32); + STATUS_REGISTERS_BUS_OUT(3)(10 downto 0) <= TRG_WIN_PRE; + STATUS_REGISTERS_BUS_OUT(3)(15 downto 11) <= (others => '0'); + STATUS_REGISTERS_BUS_OUT(3)(26 downto 16) <= TRG_WIN_POST; + STATUS_REGISTERS_BUS_OUT(3)(30 downto 27) <= (others => '0'); + STATUS_REGISTERS_BUS_OUT(3)(31) <= TRIGGER_WIN_EN_IN; + STATUS_REGISTERS_BUS_OUT(4)(23 downto 0) <= std_logic_vector(trig_number); + STATUS_REGISTERS_BUS_OUT(5)(23 downto 0) <= std_logic_vector(valid_tmg_trig_number); + STATUS_REGISTERS_BUS_OUT(6)(23 downto 0) <= std_logic_vector(valid_NOtmg_trig_number); + STATUS_REGISTERS_BUS_OUT(7)(23 downto 0) <= std_logic_vector(invalid_trig_number); + STATUS_REGISTERS_BUS_OUT(8)(23 downto 0) <= std_logic_vector(multi_tmg_trig_number); + STATUS_REGISTERS_BUS_OUT(9)(23 downto 0) <= std_logic_vector(spurious_trig_number); + STATUS_REGISTERS_BUS_OUT(10)(23 downto 0) <= std_logic_vector(wrong_readout_number); + STATUS_REGISTERS_BUS_OUT(11)(23 downto 0) <= std_logic_vector(spike_number); + STATUS_REGISTERS_BUS_OUT(12)(23 downto 0) <= std_logic_vector(idle_time); + STATUS_REGISTERS_BUS_OUT(13)(23 downto 0) <= std_logic_vector(wait_time); + STATUS_REGISTERS_BUS_OUT(14)(23 downto 0) <= std_logic_vector(total_empty_channel); + STATUS_REGISTERS_BUS_OUT(15)(23 downto 0) <= std_logic_vector(release_number); + STATUS_REGISTERS_BUS_OUT(16)(23 downto 0) <= std_logic_vector(readout_time); + STATUS_REGISTERS_BUS_OUT(17)(23 downto 0) <= std_logic_vector(timeout_number); + STATUS_REGISTERS_BUS_OUT(18)(23 downto 0) <= std_logic_vector(finished_number); + STATUS_REGISTERS_BUS_OUT(18)(31 downto 24) <= std_logic_vector(wr_number); + + FILL_BUS1 : for i in 4 to 17 generate + STATUS_REGISTERS_BUS_OUT(i)(31 downto 24) <= (others => '0'); + end generate FILL_BUS1; + + slow_control_ch_empty_i(63 downto CHANNEL_NUMBER-1) <= (others => '1'); + slow_control_ch_empty_i(CHANNEL_NUMBER-2 downto 0) <= ch_empty_2reg(CHANNEL_NUMBER-1 downto 1); + +------------------------------------------------------------------------------- +-- Registering +------------------------------------------------------------------------------- + ch_data_reg <= CH_DATA_IN when rising_edge(CLK_100); + ch_data_2reg <= ch_data_reg when rising_edge(CLK_100); + ch_empty_reg <= CH_EMPTY_IN when rising_edge(CLK_100); + ch_empty_2reg <= ch_empty_reg when rising_edge(CLK_100); + ch_empty_3reg <= ch_empty_2reg when rising_edge(CLK_100); + ch_empty_4reg <= ch_empty_3reg when rising_edge(CLK_100); + + trg_win_post_200 <= std_logic_vector(unsigned(TRG_WIN_POST)-8) when rising_edge(CLK_200); + +end behavioral; diff --git a/tdc_releases/tdc_v1.4/Reference_Channel.vhd b/tdc_releases/tdc_v1.4/Reference_Channel.vhd new file mode 100644 index 0000000..b9bb314 --- /dev/null +++ b/tdc_releases/tdc_v1.4/Reference_Channel.vhd @@ -0,0 +1,129 @@ +library IEEE; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.version.all; + +entity Reference_Channel is + + generic ( + CHANNEL_ID : integer range 0 to 0); + port ( + RESET_200 : in std_logic; + RESET_100 : in std_logic; + CLK_200 : in std_logic; + CLK_100 : in std_logic; +-- + HIT_IN : in std_logic; + READ_EN_IN : in std_logic; + VALID_TMG_TRG_IN : in std_logic; + SPIKE_DETECTED_IN : in std_logic; + MULTI_TMG_TRG_IN : in std_logic; + FIFO_DATA_OUT : out std_logic_vector(35 downto 0); + FIFO_WCNT_OUT : out unsigned(7 downto 0); + FIFO_EMPTY_OUT : out std_logic; + FIFO_FULL_OUT : out std_logic; + FIFO_ALMOST_FULL_OUT : out std_logic; + COARSE_COUNTER_IN : in std_logic_vector(10 downto 0); + EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0); + TRIGGER_WINDOW_END_IN : in std_logic; + DATA_FINISHED_IN : in std_logic; -- end of the readout process + RUN_MODE : in std_logic; + TRIGGER_TIME_STAMP_OUT : out std_logic_vector(38 downto 0); -- coarse time of the timing trigger + REF_DEBUG_OUT : out std_logic_vector(31 downto 0) + ); + +end Reference_Channel; + +architecture Reference_Channel of Reference_Channel is +------------------------------------------------------------------------------- +-- Signal Declarations +------------------------------------------------------------------------------- + + --hit detection + signal hit_in_i : std_logic; + signal hit_buf : std_logic; + + -- time stamp + signal coarse_cntr_reg : std_logic_vector(10 downto 0); + + -- other + signal trg_win_end_i : std_logic; + signal data_finished_i : std_logic; + signal run_mode_i : std_logic; + + attribute syn_keep : boolean; + attribute syn_keep of hit_buf : signal is true; + attribute NOMERGE : string; + attribute NOMERGE of hit_buf : signal is "true"; + attribute syn_preserve : boolean; + attribute syn_preserve of coarse_cntr_reg : signal is true; +------------------------------------------------------------------------------- + +begin + + hit_in_i <= HIT_IN; + hit_buf <= not hit_in_i; + + Reference_Channel_200_1 : Reference_Channel_200 + generic map ( + CHANNEL_ID => CHANNEL_ID) + port map ( + CLK_200 => CLK_200, + RESET_200 => RESET_200, + CLK_100 => CLK_100, + RESET_100 => RESET_100, + VALID_TMG_TRG_IN => VALID_TMG_TRG_IN, + SPIKE_DETECTED_IN => SPIKE_DETECTED_IN, + MULTI_TMG_TRG_IN => MULTI_TMG_TRG_IN, + HIT_IN => hit_buf, + READ_EN_IN => READ_EN_IN, + FIFO_DATA_OUT => FIFO_DATA_OUT, + FIFO_WCNT_OUT => FIFO_WCNT_OUT, + FIFO_EMPTY_OUT => FIFO_EMPTY_OUT, + FIFO_FULL_OUT => FIFO_FULL_OUT, + FIFO_ALMOST_FULL_OUT => FIFO_ALMOST_FULL_OUT, + EPOCH_COUNTER_IN => EPOCH_COUNTER_IN, + TRIGGER_WINDOW_END_IN => trg_win_end_i, + TRIGGER_TIME_STAMP_OUT => TRIGGER_TIME_STAMP_OUT, + DATA_FINISHED_IN => data_finished_i, + RUN_MODE => run_mode_i, + COARSE_COUNTER_IN => coarse_cntr_reg); + + trg_win_end_i <= TRIGGER_WINDOW_END_IN when rising_edge(CLK_200); + data_finished_i <= DATA_FINISHED_IN when rising_edge(CLK_100); + run_mode_i <= RUN_MODE when rising_edge(CLK_100); + + CoarseCounter : ShiftRegisterSISO + generic map ( + DEPTH => 1, + WIDTH => 11) + port map ( + CLK => CLK_200, + D_IN => COARSE_COUNTER_IN, + D_OUT => coarse_cntr_reg); + +------------------------------------------------------------------------------- +-- Debug signals +------------------------------------------------------------------------------- + --REF_DEBUG_OUT(3 downto 0) <= fsm_debug_i; + --REF_DEBUG_OUT(4) <= HIT_IN; + --REF_DEBUG_OUT(5) <= result_i(2); + --REF_DEBUG_OUT(6) <= result_2_reg; + --REF_DEBUG_OUT(7) <= '0'; --hit_detect_i; + --REF_DEBUG_OUT(8) <= '0'; --hit_detect_reg; + --REF_DEBUG_OUT(9) <= '0'; + --REF_DEBUG_OUT(10) <= '0'; + --REF_DEBUG_OUT(11) <= ff_array_en_i; + --REF_DEBUG_OUT(12) <= encoder_start_i; + --REF_DEBUG_OUT(13) <= encoder_finished_i; + --REF_DEBUG_OUT(14) <= fifo_wr_en_i; + + --REF_DEBUG_OUT(15) <= CLK_200; + + REF_DEBUG_OUT(31 downto 0) <= (others => '0'); +end Reference_Channel; diff --git a/tdc_releases/tdc_v1.4/Reference_Channel_200.vhd b/tdc_releases/tdc_v1.4/Reference_Channel_200.vhd new file mode 100644 index 0000000..ee8ec10 --- /dev/null +++ b/tdc_releases/tdc_v1.4/Reference_Channel_200.vhd @@ -0,0 +1,393 @@ +------------------------------------------------------------------------------- +-- Title : Reference Channel 200 MHz Part +-- Project : +------------------------------------------------------------------------------- +-- File : Reference_channel_200.vhd +-- Author : c.ugur@gsi.de +-- Created : 2012-09-04 +-- Last update: 2013-03-18 +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- + +library IEEE; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.version.all; + +entity Reference_Channel_200 is + + generic ( + CHANNEL_ID : integer range 0 to 0); + port ( + CLK_200 : in std_logic; -- 200 MHz clk + RESET_200 : in std_logic; -- reset sync with 200Mhz clk + CLK_100 : in std_logic; -- 100 MHz clk + RESET_100 : in std_logic; -- reset sync with 100Mhz clk +-- + VALID_TMG_TRG_IN : in std_logic; + SPIKE_DETECTED_IN : in std_logic; + MULTI_TMG_TRG_IN : in std_logic; +-- + HIT_IN : in std_logic; -- hit in + READ_EN_IN : in std_logic; -- read en signal + FIFO_DATA_OUT : out std_logic_vector(35 downto 0); -- fifo data out + FIFO_WCNT_OUT : out unsigned(7 downto 0); + FIFO_EMPTY_OUT : out std_logic; -- fifo empty signal + FIFO_FULL_OUT : out std_logic; -- fifo full signal + FIFO_ALMOST_FULL_OUT : out std_logic; -- fifo almost full signal + EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0); + TRIGGER_WINDOW_END_IN : in std_logic; + TRIGGER_TIME_STAMP_OUT : out std_logic_vector(38 downto 0); -- TRIGGER time stamp + DATA_FINISHED_IN : in std_logic; -- end of the readout process + RUN_MODE : in std_logic; + COARSE_COUNTER_IN : in std_logic_vector(10 downto 0)); + +end Reference_Channel_200; + +architecture Reference_Channel_200 of Reference_Channel_200 is + + -- carry chain + signal data_a_i : std_logic_vector(303 downto 0); + signal data_b_i : std_logic_vector(303 downto 0); + signal result_i : std_logic_vector(303 downto 0) := (others => '1'); + signal ff_array_en_i : std_logic := '0'; + + -- hit detection + signal result_2_reg : std_logic; + signal hit_detect_i : std_logic; + signal hit_detect_reg : std_logic; + signal hit_detect_2reg : std_logic; + + -- time stamp + signal time_stamp_i : std_logic_vector(10 downto 0); + signal coarse_cntr_reg : std_logic_vector(10 downto 0); + signal time_stamp_epoch_bits : std_logic_vector(27 downto 0); + + -- encoder + signal encoder_start_i : std_logic; + signal encoder_finished_i : std_logic; + signal encoder_data_out_i : std_logic_vector(9 downto 0); + signal encoder_info_i : std_logic_vector(1 downto 0); + signal encoder_debug_i : std_logic_vector(31 downto 0); + + -- fifo + signal fifo_data_in_i : std_logic_vector(35 downto 0); + signal fifo_data_out_i : std_logic_vector(35 downto 0); + signal fifo_wcnt_i : std_logic_vector(7 downto 0); + signal fifo_empty_i : std_logic; + signal fifo_full_i : std_logic; + signal fifo_was_full_i : std_logic := '0'; + signal fifo_almost_full_i : std_logic; + signal fifo_wr_en_i : std_logic := '0'; + signal fifo_rd_en_i : std_logic; + + -- timing trigger + signal valid_tmg_trg_i : std_logic; + signal multi_tmg_trg_i : std_logic; + signal spike_detected_i : std_logic; + + -- coarse counter overflow + signal coarse_cntr_overflow_release : std_logic := '0'; + signal coarse_cntr_overflow_flag : std_logic := '0'; + + -- epoch counter + signal epoch_cntr : std_logic_vector(27 downto 0); + signal epoch_time : std_logic_vector(27 downto 0); + signal epoch_word_first : std_logic_vector(35 downto 0); + signal epoch_cntr_up : std_logic := '0'; + signal epoch_capture_time : std_logic_vector(10 downto 0); + + -- other + signal read_en_reg : std_logic; + signal read_en_2reg : std_logic; + signal first_read_i : std_logic; + signal trg_win_end_i : std_logic; + + -- fsm + type FSM is (IDLE, LOOK_FOR_VALIDITY, ENCODER_FINISHED, WAIT_FOR_FALLING_EDGE); + signal FSM_CURRENT : FSM := IDLE; + signal FSM_NEXT : FSM; + signal valid_trigger_i : std_logic; + signal valid_trigger_fsm : std_logic; + signal fsm_debug_i : std_logic_vector(3 downto 0); + signal fsm_debug_fsm : std_logic_vector(3 downto 0); + + attribute syn_keep : boolean; + attribute syn_keep of ff_array_en_i : signal is true; + attribute syn_keep of trg_win_end_i : signal is true; + attribute syn_preserve : boolean; + attribute syn_preserve of trg_win_end_i : signal is true; + + +begin -- Reference_Channel_200 + + trg_win_end_i <= TRIGGER_WINDOW_END_IN when rising_edge(CLK_200); + + --purpose: Tapped Delay Line 304 (Carry Chain) with wave launcher (21) double transition + FC : Adder_304 + port map ( + CLK => CLK_200, + RESET => RESET_200, + DataA => data_a_i, + DataB => data_b_i, + ClkEn => ff_array_en_i, + Result => result_i); + data_a_i <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" & x"7FFFFFF"; + data_b_i <= x"000000000000000000000000000000000000000000000000000000000000000000000" & not(HIT_IN) & x"000000" & "00" & HIT_IN; + ff_array_en_i <= not(hit_detect_i or hit_detect_reg or hit_detect_2reg); + + result_2_reg <= result_i(2) when rising_edge(CLK_200); + hit_detect_i <= (not result_2_reg) and result_i(2); -- detects the hit by + -- comparing the + -- previous state of the + -- hit detection bit + hit_detect_reg <= hit_detect_i when rising_edge(CLK_200); + hit_detect_2reg <= hit_detect_reg when rising_edge(CLK_200); + coarse_cntr_reg <= COARSE_COUNTER_IN when rising_edge(CLK_200); + encoder_start_i <= hit_detect_i; + + TimeStampCapture : process (CLK_200) + begin + if rising_edge(CLK_200) then + if hit_detect_reg = '1' then + time_stamp_i <= coarse_cntr_reg; + end if; + end if; + end process TimeStampCapture; + + epoch_capture_time <= "00000000111"; + + EpochCounterUpdate : process (CLK_200) + begin + if rising_edge(CLK_200) then + if coarse_cntr_reg = epoch_capture_time then + epoch_cntr <= EPOCH_COUNTER_IN; + epoch_cntr_up <= '1'; + end if; + end if; + end process EpochCounterUpdate; + + EpochCounterCapture : process (CLK_200) + begin + if rising_edge(CLK_200) then + if encoder_finished_i = '1' then + epoch_time <= epoch_cntr; + end if; + end if; + end process EpochCounterCapture; + + --purpose: Encoder + Encoder : Encoder_304_Bit + port map ( + RESET => RESET_200, + CLK => CLK_200, + START_IN => encoder_start_i, + THERMOCODE_IN => result_i, + FINISHED_OUT => encoder_finished_i, + BINARY_CODE_OUT => encoder_data_out_i, + ENCODER_INFO_OUT => encoder_info_i, + ENCODER_DEBUG => encoder_debug_i); + + FIFO : FIFO_36x128_OutReg_Counter + port map ( + Data => fifo_data_in_i, + WrClock => CLK_200, + RdClock => CLK_100, + WrEn => fifo_wr_en_i, + RdEn => fifo_rd_en_i, + Reset => RESET_100, + RPReset => RESET_200, + Q => fifo_data_out_i, + WCNT => fifo_wcnt_i, + Empty => fifo_empty_i, + Full => fifo_full_i); + + fifo_rd_en_i <= READ_EN_IN or fifo_full_i; + + -- purpose: Sets the Overflow Flag + CoarseCounterOverflowFlag : process (CLK_200) + begin + if rising_edge(CLK_200) then + if epoch_cntr_up = '1' or trg_win_end_i = '1' then + coarse_cntr_overflow_flag <= '1'; + elsif coarse_cntr_overflow_release = '1' then + coarse_cntr_overflow_flag <= '0'; + end if; + end if; + end process CoarseCounterOverflowFlag; + + -- purpose: Generate Fifo Wr Signal + FifoWriteSignal : process (CLK_200) + begin + if rising_edge(CLK_200) then + if valid_trigger_i = '1' then + fifo_data_in_i(31 downto 29) <= "011"; + fifo_data_in_i(28) <= '0'; + fifo_data_in_i(27 downto 0) <= epoch_time; + coarse_cntr_overflow_release <= '1'; + fifo_wr_en_i <= '1'; + time_stamp_epoch_bits <= epoch_time; + elsif coarse_cntr_overflow_release = '1' then + fifo_data_in_i(31) <= '1'; -- data marker + fifo_data_in_i(30) <= '0'; -- reserved bits + fifo_data_in_i(29) <= encoder_info_i(0); -- low resolution info bit + fifo_data_in_i(28 downto 22) <= std_logic_vector(to_unsigned(CHANNEL_ID, 7)); -- channel number + if encoder_info_i(1) = '1' then + fifo_data_in_i(21 downto 12) <= (others => '1'); -- encoder didn't work + else + fifo_data_in_i(21 downto 12) <= encoder_data_out_i; -- fine time from the encoder + end if; + fifo_data_in_i(11) <= '1'; --edge_type_i; -- rising '1' or falling '0' edge + fifo_data_in_i(10 downto 0) <= time_stamp_i; -- hit time stamp + coarse_cntr_overflow_release <= '0'; + fifo_wr_en_i <= '1'; + elsif DATA_FINISHED_IN = '1' then + time_stamp_epoch_bits <= (others => '0'); + else + fifo_data_in_i <= (others => '0'); + coarse_cntr_overflow_release <= '0'; + fifo_wr_en_i <= '0'; + end if; + end if; + end process FifoWriteSignal; + + TRIGGER_TIME_STAMP_OUT <= time_stamp_epoch_bits & time_stamp_i; + + EpochCounterCaptureFirstWord : process (CLK_100) + begin + if rising_edge(CLK_100) then + if DATA_FINISHED_IN = '1' and RUN_MODE = '0' then + epoch_word_first <= x"060000000"; + elsif fifo_data_out_i(31 downto 29) = "011" then + epoch_word_first <= fifo_data_out_i; + end if; + end if; + end process EpochCounterCaptureFirstWord; + + read_en_reg <= READ_EN_IN when rising_edge(CLK_100); + read_en_2reg <= read_en_reg when rising_edge(CLK_100); + first_read_i <= read_en_reg and not(read_en_2reg) when rising_edge(CLK_100); + + FifoWasFull : process (CLK_100) + begin + if rising_edge(CLK_100) then + if fifo_full_i = '1' then + fifo_was_full_i <= '1'; + elsif fifo_empty_i = '1' then + fifo_was_full_i <= '0'; + end if; + end if; + end process FifoWasFull; + + RegisterOutputs : process (CLK_100) + begin + if rising_edge(CLK_100) then + if first_read_i = '1' and fifo_was_full_i = '1' then + FIFO_DATA_OUT <= epoch_word_first; + else + FIFO_DATA_OUT <= fifo_data_out_i; + end if; + FIFO_WCNT_OUT <= unsigned(fifo_wcnt_i); + FIFO_EMPTY_OUT <= fifo_empty_i; + FIFO_FULL_OUT <= fifo_full_i; + FIFO_ALMOST_FULL_OUT <= fifo_almost_full_i; + end if; + end process RegisterOutputs; + + --purpose: FSM for controlling the validity of the timing signal + FSM_CLK : process (CLK_200) + begin + if rising_edge(CLK_200) then + FSM_CURRENT <= FSM_NEXT; + valid_trigger_i <= valid_trigger_fsm; + fsm_debug_i <= fsm_debug_fsm; + end if; + end process FSM_CLK; + + FSM_PROC : process (FSM_CURRENT, hit_detect_i, encoder_finished_i, valid_tmg_trg_i, multi_tmg_trg_i, + spike_detected_i) + begin + valid_trigger_fsm <= '0'; + fsm_debug_fsm <= (others => '0'); + + case (FSM_CURRENT) is + when IDLE => + if hit_detect_i = '1' then + FSM_NEXT <= ENCODER_FINISHED; + else + FSM_NEXT <= IDLE; + end if; + fsm_debug_fsm <= x"1"; + + when ENCODER_FINISHED => + if encoder_finished_i = '1' then + FSM_NEXT <= LOOK_FOR_VALIDITY; + elsif valid_tmg_trg_i = '1' then + FSM_NEXT <= IDLE; + else + FSM_NEXT <= ENCODER_FINISHED; + end if; + fsm_debug_fsm <= x"2"; + + when LOOK_FOR_VALIDITY => + if valid_tmg_trg_i = '1' then + FSM_NEXT <= IDLE; + valid_trigger_fsm <= '1'; + elsif multi_tmg_trg_i = '1' or spike_detected_i = '1' then + FSM_NEXT <= IDLE; + else + FSM_NEXT <= LOOK_FOR_VALIDITY; + end if; + fsm_debug_fsm <= x"3"; + + --when WAIT_FOR_FALLING_EDGE => + -- if encoder_finished_i = '1' then + -- FSM_NEXT <= IDLE; + -- valid_trigger_fsm <= '1'; + -- fsm_debug_fsm <= x"C"; + -- else + -- FSM_NEXT <= WAIT_FOR_FALLING_EDGE; + -- valid_trigger_fsm <= '0'; + -- fsm_debug_fsm <= x"D"; + -- end if; + + when others => + FSM_NEXT <= IDLE; + end case; + end process FSM_PROC; + + bit_sync_1 : bit_sync + generic map ( + DEPTH => 3) + port map ( + RESET => RESET_200, + CLK0 => CLK_100, + CLK1 => CLK_200, + D_IN => VALID_TMG_TRG_IN, + D_OUT => valid_tmg_trg_i); + bit_sync_2 : bit_sync + generic map ( + DEPTH => 3) + port map ( + RESET => RESET_200, + CLK0 => CLK_100, + CLK1 => CLK_200, + D_IN => SPIKE_DETECTED_IN, + D_OUT => spike_detected_i); + bit_sync_3 : bit_sync + generic map ( + DEPTH => 3) + port map ( + RESET => RESET_200, + CLK0 => CLK_100, + CLK1 => CLK_200, + D_IN => MULTI_TMG_TRG_IN, + D_OUT => multi_tmg_trg_i); + +end Reference_Channel_200; diff --git a/tdc_releases/tdc_v1.4/ShiftRegisterSISO.vhd b/tdc_releases/tdc_v1.4/ShiftRegisterSISO.vhd new file mode 100644 index 0000000..a82160b --- /dev/null +++ b/tdc_releases/tdc_v1.4/ShiftRegisterSISO.vhd @@ -0,0 +1,54 @@ +------------------------------------------------------------------------------- +-- Title : Register.vhd +-- Project : +------------------------------------------------------------------------------- +-- File : Register.vhd +-- Author : c.ugur@gsi.de +-- Created : 2012-10-02 +-- Last update: 2013-03-06 +------------------------------------------------------------------------------- +-- Description: Used to register signals n levels. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +entity ShiftRegisterSISO is + + generic ( + DEPTH : integer range 1 to 32 := 1; -- defines the number register level + WIDTH : integer range 1 to 32 := 1); -- defines the register size + + port ( + CLK : in std_logic; -- register clock + D_IN : in std_logic_vector(WIDTH-1 downto 0); -- register input + D_OUT : out std_logic_vector(WIDTH-1 downto 0)); -- register out + +end ShiftRegisterSISO; + +architecture Behavioral of ShiftRegisterSISO is + + type RegisterArray is array (0 to DEPTH) of std_logic_vector(WIDTH-1 downto 0); + signal reg : RegisterArray; + + attribute syn_preserve : boolean; + attribute syn_preserve of reg : signal is true; + +begin -- RTL + + reg(0) <= D_IN; + + GEN_Registers : for i in 1 to DEPTH generate + Registers : process (CLK) + begin + if rising_edge(CLK) then + reg(i) <= reg(i-1); + end if; + end process Registers; + end generate GEN_Registers; + + D_OUT <= reg(DEPTH); + +end Behavioral; diff --git a/tdc_releases/tdc_v1.4/TDC.vhd b/tdc_releases/tdc_v1.4/TDC.vhd new file mode 100644 index 0000000..1c3c070 --- /dev/null +++ b/tdc_releases/tdc_v1.4/TDC.vhd @@ -0,0 +1,429 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.version.all; + +entity TDC is + generic ( + CHANNEL_NUMBER : integer range 2 to 65; + CONTROL_REG_NR : integer range 0 to 6); + port ( + RESET : in std_logic; + CLK_TDC : in std_logic; + CLK_READOUT : in std_logic; + REFERENCE_TIME : in std_logic; + HIT_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 1); + TRG_WIN_PRE : in std_logic_vector(10 downto 0); + TRG_WIN_POST : in std_logic_vector(10 downto 0); +-- + -- Trigger signals from handler + TRG_DATA_VALID_IN : in std_logic := '0'; + VALID_TIMING_TRG_IN : in std_logic := '0'; + VALID_NOTIMING_TRG_IN : in std_logic := '0'; + INVALID_TRG_IN : in std_logic := '0'; + TMGTRG_TIMEOUT_IN : in std_logic := '0'; + SPIKE_DETECTED_IN : in std_logic := '0'; + MULTI_TMG_TRG_IN : in std_logic := '0'; + SPURIOUS_TRG_IN : in std_logic := '0'; +-- + TRG_NUMBER_IN : in std_logic_vector(15 downto 0) := (others => '0'); + TRG_CODE_IN : in std_logic_vector(7 downto 0) := (others => '0'); + TRG_INFORMATION_IN : in std_logic_vector(23 downto 0) := (others => '0'); + TRG_TYPE_IN : in std_logic_vector(3 downto 0) := (others => '0'); +-- + --Response to handler + TRG_RELEASE_OUT : out std_logic; + TRG_STATUSBIT_OUT : out std_logic_vector(31 downto 0); + DATA_OUT : out std_logic_vector(31 downto 0); + DATA_WRITE_OUT : out std_logic; + DATA_FINISHED_OUT : out std_logic; +-- + --To Bus Handler + HCB_READ_EN_IN : in std_logic; + HCB_WRITE_EN_IN : in std_logic; + HCB_ADDR_IN : in std_logic_vector(6 downto 0); + HCB_DATA_OUT : out std_logic_vector(31 downto 0); + HCB_DATAREADY_OUT : out std_logic; + HCB_UNKNOWN_ADDR_OUT : out std_logic; + SRB_READ_EN_IN : in std_logic; + SRB_WRITE_EN_IN : in std_logic; + SRB_ADDR_IN : in std_logic_vector(6 downto 0); + SRB_DATA_OUT : out std_logic_vector(31 downto 0); + SRB_DATAREADY_OUT : out std_logic; + SRB_UNKNOWN_ADDR_OUT : out std_logic; + ESB_READ_EN_IN : in std_logic; + ESB_WRITE_EN_IN : in std_logic; + ESB_ADDR_IN : in std_logic_vector(6 downto 0); + ESB_DATA_OUT : out std_logic_vector(31 downto 0); + ESB_DATAREADY_OUT : out std_logic; + ESB_UNKNOWN_ADDR_OUT : out std_logic; + EFB_READ_EN_IN : in std_logic; + EFB_WRITE_EN_IN : in std_logic; + EFB_ADDR_IN : in std_logic_vector(6 downto 0); + EFB_DATA_OUT : out std_logic_vector(31 downto 0); + EFB_DATAREADY_OUT : out std_logic; + EFB_UNKNOWN_ADDR_OUT : out std_logic; + LHB_READ_EN_IN : in std_logic; + LHB_WRITE_EN_IN : in std_logic; + LHB_ADDR_IN : in std_logic_vector(6 downto 0); + LHB_DATA_OUT : out std_logic_vector(31 downto 0); + LHB_DATAREADY_OUT : out std_logic; + LHB_UNKNOWN_ADDR_OUT : out std_logic; +-- + LOGIC_ANALYSER_OUT : out std_logic_vector(15 downto 0); + CONTROL_REG_IN : in std_logic_vector(32*CONTROL_REG_NR-1 downto 0) + ); +end TDC; + +architecture TDC of TDC is + +------------------------------------------------------------------------------- +-- Signal Declarations +------------------------------------------------------------------------------- +-- Reset Signals + signal reset_tdc : std_logic; +-- Coarse counters + signal coarse_cntr : std_logic_vector_array_11(1 to 4); + signal coarse_cntr_reset : std_logic; + signal coarse_cntr_reset_r : std_logic_vector(4 downto 1); +-- Slow control + signal logic_anal_control : std_logic_vector(3 downto 0); + signal debug_mode_en_i : std_logic; + signal reset_counters_i : std_logic; + signal run_mode_i : std_logic; -- 1: cc reset every trigger + -- 0: free running mode + signal run_mode_200 : std_logic; + signal trigger_win_en_i : std_logic; + signal ch_en_i : std_logic_vector(64 downto 1); +-- Logic analyser + signal logic_anal_data_i : std_logic_vector(3*32-1 downto 0); +-- Hit signals + signal hit_in_i : std_logic_vector(CHANNEL_NUMBER-1 downto 1); +-- To the channels + signal rd_en_i : std_logic_vector(CHANNEL_NUMBER-1 downto 0); + signal trg_win_end_i : std_logic; +-- From the channels + signal ch_data_i : std_logic_vector_array_36(0 to CHANNEL_NUMBER); + signal ch_wcnt_i : unsigned_array_8(0 to CHANNEL_NUMBER-1); + signal ch_empty_i : std_logic_vector(CHANNEL_NUMBER downto 0); + signal ch_full_i : std_logic_vector(CHANNEL_NUMBER-1 downto 0); + signal ch_almost_full_i : std_logic_vector(CHANNEL_NUMBER-1 downto 0); + signal trg_time_i : std_logic_vector(38 downto 0); + signal ch_lost_hit_number_i : std_logic_vector_array_24(0 to CHANNEL_NUMBER-1); + signal ch_hit_detect_number_i : std_logic_vector_array_24(0 to CHANNEL_NUMBER-1); + signal ch_encoder_start_number_i : std_logic_vector_array_24(0 to CHANNEL_NUMBER-1); + signal ch_encoder_finished_number_i : std_logic_vector_array_24(0 to CHANNEL_NUMBER-1); + signal ch_level_hit_number : std_logic_vector_array_32(0 to CHANNEL_NUMBER-1); + signal ch_lost_hit_bus_i : std_logic_vector_array_32(0 to CHANNEL_NUMBER-1); + signal ch_encoder_start_bus_i : std_logic_vector_array_32(0 to CHANNEL_NUMBER-1); + signal ch_encoder_finished_bus_i : std_logic_vector_array_32(0 to CHANNEL_NUMBER-1); +-- To the endpoint + signal data_finished_i : std_logic; +-- Epoch counter + signal epoch_cntr : std_logic_vector(27 downto 0); + signal epoch_cntr_up_i : std_logic; + signal epoch_cntr_reset_i : std_logic; +-- Debug signals + signal ref_debug_i : std_logic_vector(31 downto 0); + signal ch_debug_i : std_logic_vector_array_32(0 to CHANNEL_NUMBER-1); + signal readout_debug_i : std_logic_vector(31 downto 0); +-- Bus signals + signal status_registers_bus_i : std_logic_vector_array_32(0 to 18); + + attribute syn_keep : boolean; + attribute syn_keep of reset_tdc : signal is true; + attribute syn_keep of coarse_cntr : signal is true; + attribute syn_preserve : boolean; + attribute syn_preserve of coarse_cntr : signal is true; + +begin + +-- Slow control signals + logic_anal_control <= CONTROL_REG_IN(3 downto 0) when rising_edge(CLK_READOUT); + debug_mode_en_i <= CONTROL_REG_IN(4); + reset_counters_i <= CONTROL_REG_IN(8); + run_mode_i <= CONTROL_REG_IN(12); + run_mode_200 <= run_mode_i when rising_edge(CLK_TDC); -- Run mode control register synchronised to the coarse counter clk + trigger_win_en_i <= CONTROL_REG_IN(1*32+31); + ch_en_i <= CONTROL_REG_IN(3*32+31 downto 2*32+0); + +-- Reset signal + reset_tdc <= RESET; + +-- Channel enable signals + GEN_Channel_Enable : for i in 1 to CHANNEL_NUMBER-1 generate + hit_in_i(i) <= HIT_IN(i) and ch_en_i(i); + end generate GEN_Channel_Enable; + +-- hit_in_i(1) <= REFERENCE_TIME; + +-- Reference channel + The_Reference_Time : Reference_Channel + generic map ( + CHANNEL_ID => 0) + port map ( + RESET_200 => reset_tdc, + RESET_100 => RESET, + CLK_200 => CLK_TDC, + CLK_100 => CLK_READOUT, + HIT_IN => REFERENCE_TIME, + READ_EN_IN => rd_en_i(0), + VALID_TMG_TRG_IN => VALID_TIMING_TRG_IN, + SPIKE_DETECTED_IN => SPIKE_DETECTED_IN, + MULTI_TMG_TRG_IN => MULTI_TMG_TRG_IN, + FIFO_DATA_OUT => ch_data_i(0), + FIFO_WCNT_OUT => ch_wcnt_i(0), + FIFO_EMPTY_OUT => ch_empty_i(0), + FIFO_FULL_OUT => ch_full_i(0), + FIFO_ALMOST_FULL_OUT => ch_almost_full_i(0), + COARSE_COUNTER_IN => coarse_cntr(1), + EPOCH_COUNTER_IN => epoch_cntr, + TRIGGER_WINDOW_END_IN => trg_win_end_i, + DATA_FINISHED_IN => data_finished_i, + RUN_MODE => run_mode_i, + TRIGGER_TIME_STAMP_OUT => trg_time_i, + REF_DEBUG_OUT => ref_debug_i); + +-- Channels + GEN_Channels : for i in 1 to CHANNEL_NUMBER - 1 generate + Channels : Channel + generic map ( + CHANNEL_ID => i) + port map ( + RESET_200 => reset_tdc, + RESET_100 => RESET, + RESET_COUNTERS => reset_counters_i, + CLK_200 => CLK_TDC, + CLK_100 => CLK_READOUT, + HIT_IN => hit_in_i(i), + TRIGGER_WIN_END_IN => trg_win_end_i, + READ_EN_IN => rd_en_i(i), + FIFO_DATA_OUT => ch_data_i(i), + FIFO_WCNT_OUT => ch_wcnt_i(i), + FIFO_EMPTY_OUT => ch_empty_i(i), + FIFO_FULL_OUT => ch_full_i(i), + FIFO_ALMOST_FULL_OUT => ch_almost_full_i(i), + COARSE_COUNTER_IN => coarse_cntr(integer(ceil(real(i)/real(16)))), + EPOCH_COUNTER_IN => epoch_cntr, +-- DATA_FINISHED_IN => data_finished_i, + LOST_HIT_NUMBER => ch_lost_hit_number_i(i), + HIT_DETECT_NUMBER => ch_hit_detect_number_i(i), + ENCODER_START_NUMBER => ch_encoder_start_number_i(i), + ENCODER_FINISHED_NUMBER => ch_encoder_finished_number_i(i), + Channel_DEBUG => ch_debug_i(i)); + end generate GEN_Channels; + ch_data_i(CHANNEL_NUMBER) <= (others => '1'); + + -- Readout + TheReadout : Readout + generic map ( + CHANNEL_NUMBER => CHANNEL_NUMBER) + port map ( + CLK_200 => CLK_TDC, + RESET_200 => reset_tdc, + CLK_100 => CLK_READOUT, + RESET_100 => RESET, + RESET_COUNTERS => reset_counters_i, + REFERENCE_TIME => REFERENCE_TIME, + TRIGGER_TIME_IN => trg_time_i, + TRG_WIN_PRE => TRG_WIN_PRE, + TRG_WIN_POST => TRG_WIN_POST, + DEBUG_MODE_EN_IN => debug_mode_en_i, + TRIGGER_WIN_EN_IN => trigger_win_en_i, + CH_DATA_IN => ch_data_i, + CH_WCNT_IN => ch_wcnt_i, + CH_EMPTY_IN => ch_empty_i, + CH_FULL_IN => ch_full_i, + CH_ALMOST_FULL_IN => ch_almost_full_i, + TRG_DATA_VALID_IN => TRG_DATA_VALID_IN, + VALID_TIMING_TRG_IN => VALID_TIMING_TRG_IN, + VALID_NOTIMING_TRG_IN => VALID_NOTIMING_TRG_IN, + INVALID_TRG_IN => INVALID_TRG_IN, + TMGTRG_TIMEOUT_IN => TMGTRG_TIMEOUT_IN, + SPIKE_DETECTED_IN => SPIKE_DETECTED_IN, + MULTI_TMG_TRG_IN => MULTI_TMG_TRG_IN, + SPURIOUS_TRG_IN => SPURIOUS_TRG_IN, + TRG_NUMBER_IN => TRG_NUMBER_IN, + TRG_CODE_IN => TRG_CODE_IN, + TRG_INFORMATION_IN => TRG_INFORMATION_IN, + TRG_TYPE_IN => TRG_TYPE_IN, + TRG_RELEASE_OUT => TRG_RELEASE_OUT, + TRG_STATUSBIT_OUT => TRG_STATUSBIT_OUT, + DATA_OUT => DATA_OUT, + DATA_WRITE_OUT => DATA_WRITE_OUT, + DATA_FINISHED_OUT => data_finished_i, + READ_EN_OUT => rd_en_i, + TRIGGER_WIN_END_OUT => trg_win_end_i, + STATUS_REGISTERS_BUS_OUT => status_registers_bus_i, + READOUT_DEBUG => readout_debug_i); + DATA_FINISHED_OUT <= data_finished_i; + +-- Coarse counter + GenCoarseCounter : for i in 1 to 4 generate + TheCoarseCounter : up_counter + generic map ( + NUMBER_OF_BITS => 11) + port map ( + CLK => CLK_TDC, + RESET => coarse_cntr_reset_r(i), + COUNT_OUT => coarse_cntr(i), + UP_IN => '1'); + end generate GenCoarseCounter; + + Coarse_Counter_Reset : process (CLK_TDC, reset_tdc) + begin + if rising_edge(CLK_TDC) then + if reset_tdc = '1' then + coarse_cntr_reset <= '1'; + elsif run_mode_200 = '1' then + coarse_cntr_reset <= '0'; + else + coarse_cntr_reset <= trg_win_end_i; + end if; + end if; + end process Coarse_Counter_Reset; + + GenCoarseCounterReset : for i in 1 to 4 generate + coarse_cntr_reset_r(i) <= coarse_cntr_reset when rising_edge(CLK_TDC); + end generate GenCoarseCounterReset; + +-- EPOCH counter + TheEpochCounter : up_counter + generic map ( + NUMBER_OF_BITS => 28) + port map ( + CLK => CLK_TDC, + RESET => epoch_cntr_reset_i, + COUNT_OUT => epoch_cntr, + UP_IN => epoch_cntr_up_i); + epoch_cntr_up_i <= and_all(coarse_cntr(1)); + epoch_cntr_reset_i <= reset_tdc or coarse_cntr_reset; + +-- Bus handler entities + TheHitCounterBus : BusHandler + generic map ( + BUS_LENGTH => CHANNEL_NUMBER-1) + port map ( + RESET => RESET, + CLK => CLK_READOUT, + DATA_IN => ch_level_hit_number, + READ_EN_IN => HCB_READ_EN_IN, + WRITE_EN_IN => HCB_WRITE_EN_IN, + ADDR_IN => HCB_ADDR_IN, + DATA_OUT => HCB_DATA_OUT, + DATAREADY_OUT => HCB_DATAREADY_OUT, + UNKNOWN_ADDR_OUT => HCB_UNKNOWN_ADDR_OUT); + + GenHitDetectNumber : for i in 1 to CHANNEL_NUMBER-1 generate + ch_level_hit_number(i) <= hit_in_i(i) & "0000000" & ch_hit_detect_number_i(i) when rising_edge(CLK_READOUT); + end generate GenHitDetectNumber; + + TheStatusRegistersBus : BusHandler + generic map ( + BUS_LENGTH => 18) + port map ( + RESET => RESET, + CLK => CLK_READOUT, + DATA_IN => status_registers_bus_i, + READ_EN_IN => SRB_READ_EN_IN, + WRITE_EN_IN => SRB_WRITE_EN_IN, + ADDR_IN => SRB_ADDR_IN, + DATA_OUT => SRB_DATA_OUT, + DATAREADY_OUT => SRB_DATAREADY_OUT, + UNKNOWN_ADDR_OUT => SRB_UNKNOWN_ADDR_OUT); + + TheLostHitBus : BusHandler + generic map ( + BUS_LENGTH => CHANNEL_NUMBER-1) + port map ( + RESET => RESET, + CLK => CLK_READOUT, + DATA_IN => ch_lost_hit_bus_i, + READ_EN_IN => LHB_READ_EN_IN, + WRITE_EN_IN => LHB_WRITE_EN_IN, + ADDR_IN => LHB_ADDR_IN, + DATA_OUT => LHB_DATA_OUT, + DATAREADY_OUT => LHB_DATAREADY_OUT, + UNKNOWN_ADDR_OUT => LHB_UNKNOWN_ADDR_OUT); + + GenLostHitNumber : for i in 1 to CHANNEL_NUMBER-1 generate + ch_lost_hit_bus_i(i) <= x"00" & ch_lost_hit_number_i(i) when rising_edge(CLK_READOUT); + end generate GenLostHitNumber; + + --TheEncoderStartBus : BusHandler + -- generic map ( + -- BUS_LENGTH => CHANNEL_NUMBER-1) + -- port map ( + -- RESET => RESET, + -- CLK => CLK_READOUT, + -- DATA_IN => ch_encoder_start_bus_i, + -- READ_EN_IN => ESB_READ_EN_IN, + -- WRITE_EN_IN => ESB_WRITE_EN_IN, + -- ADDR_IN => ESB_ADDR_IN, + -- DATA_OUT => ESB_DATA_OUT, + -- DATAREADY_OUT => ESB_DATAREADY_OUT, + -- UNKNOWN_ADDR_OUT => ESB_UNKNOWN_ADDR_OUT); + + --GenEncoderStartNumber : for i in 1 to CHANNEL_NUMBER-1 generate + -- ch_encoder_start_bus_i(i) <= x"00" & ch_encoder_start_number_i(i) when rising_edge(CLK_READOUT); + --end generate GenEncoderStartNumber; + + ESB_DATA_OUT <= (others => '0'); + ESB_DATAREADY_OUT <= '0'; + ESB_UNKNOWN_ADDR_OUT <= '0'; + + --TheEncoderFinishedBus : BusHandler + -- generic map ( + -- BUS_LENGTH => CHANNEL_NUMBER-1) + -- port map ( + -- RESET => RESET, + -- CLK => CLK_READOUT, + -- DATA_IN => ch_encoder_finished_bus_i, + -- READ_EN_IN => EFB_READ_EN_IN, + -- WRITE_EN_IN => EFB_WRITE_EN_IN, + -- ADDR_IN => EFB_ADDR_IN, + -- DATA_OUT => EFB_DATA_OUT, + -- DATAREADY_OUT => EFB_DATAREADY_OUT, + -- UNKNOWN_ADDR_OUT => EFB_UNKNOWN_ADDR_OUT); + + --GenFifoWriteNumber : for i in 1 to CHANNEL_NUMBER-1 generate + -- ch_encoder_finished_bus_i(i) <= x"00" & ch_encoder_finished_number_i(i) when rising_edge(CLK_READOUT); + --end generate GenFifoWriteNumber; + + EFB_DATA_OUT <= (others => '0'); + EFB_DATAREADY_OUT <= '0'; + EFB_UNKNOWN_ADDR_OUT <= '0'; + +-- Logic Analyser + TheLogicAnalyser : LogicAnalyser + generic map ( + CHANNEL_NUMBER => CHANNEL_NUMBER) + port map ( + CLK => CLK_READOUT, + RESET => RESET, + DATA_IN => logic_anal_data_i, + CONTROL_IN => logic_anal_control, + DATA_OUT => LOGIC_ANALYSER_OUT); + + logic_anal_data_i(7 downto 0) <= readout_debug_i(7 downto 0); + logic_anal_data_i(8) <= REFERENCE_TIME; + logic_anal_data_i(9) <= VALID_TIMING_TRG_IN; + logic_anal_data_i(10) <= VALID_NOTIMING_TRG_IN; + logic_anal_data_i(11) <= INVALID_TRG_IN; + logic_anal_data_i(12) <= TRG_DATA_VALID_IN; + logic_anal_data_i(13) <= readout_debug_i(8); --data_wr_reg; + logic_anal_data_i(14) <= readout_debug_i(9); --data_finished_reg; + logic_anal_data_i(15) <= readout_debug_i(10); --trg_release_reg; + logic_anal_data_i(31 downto 16) <= ref_debug_i(15 downto 0); + logic_anal_data_i(37 downto 32) <= readout_debug_i(16 downto 11); --data_out_reg(27 downto 22); + logic_anal_data_i(47 downto 38) <= (others => '0'); + logic_anal_data_i(63 downto 48) <= ch_debug_i(1)(15 downto 0); + logic_anal_data_i(95 downto 64) <= (others => '0'); + +end TDC; diff --git a/tdc_releases/tdc_v1.4/bit_sync.vhd b/tdc_releases/tdc_v1.4/bit_sync.vhd new file mode 100644 index 0000000..ba9adb2 --- /dev/null +++ b/tdc_releases/tdc_v1.4/bit_sync.vhd @@ -0,0 +1,60 @@ +--synchronizes a single bit to a different clock domain + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity bit_sync is + generic( + DEPTH : integer := 3 + ); + port( + RESET : in std_logic; --Reset is neceessary to avoid optimization to shift register + CLK0 : in std_logic; --clock for first FF + CLK1 : in std_logic; --Clock for other FF + D_IN : in std_logic; --Data input + D_OUT : out std_logic --Data output + ); +end entity; + +architecture behavioral of bit_sync is + + signal sync_q : std_logic_vector(DEPTH downto 0); + + attribute syn_preserve : boolean; + attribute syn_keep : boolean; + attribute syn_keep of sync_q : signal is true; + attribute syn_preserve of sync_q : signal is true; + + +begin + sync_q(0) <= D_IN; + D_OUT <= sync_q(DEPTH); + + process(CLK0) + begin + if rising_edge(CLK0) then + if RESET = '1' then + sync_q(1) <= '0'; + else + sync_q(1) <= sync_q(0); + end if; + end if; + end process; + + gen_others : if DEPTH > 1 generate + gen_flipflops : for i in 2 to DEPTH generate + process(CLK1) + begin + if rising_edge(CLK1) then + if RESET = '1' then + sync_q(i) <= '0'; + else + sync_q(i) <= sync_q(i-1); + end if; + end if; + end process; + end generate; + end generate; + +end architecture; diff --git a/tdc_releases/tdc_v1.4/fallingEdgeDetect.vhd b/tdc_releases/tdc_v1.4/fallingEdgeDetect.vhd new file mode 100644 index 0000000..f413d0b --- /dev/null +++ b/tdc_releases/tdc_v1.4/fallingEdgeDetect.vhd @@ -0,0 +1,17 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity fallingEdgeDetect is + port (CLK : in std_logic; + SIGNAL_IN : in std_logic; + PULSE_OUT : out std_logic); +end fallingEdgeDetect; + +architecture Behavioral of fallingEdgeDetect is + + signal signal_d : std_logic; + +begin + signal_d <= SIGNAL_IN when rising_edge(CLK); + PULSE_OUT <= (not SIGNAL_IN) and signal_d when rising_edge(CLK); +end Behavioral; diff --git a/tdc_releases/tdc_v1.4/risingEdgeDetect.vhd b/tdc_releases/tdc_v1.4/risingEdgeDetect.vhd new file mode 100644 index 0000000..fad9f7e --- /dev/null +++ b/tdc_releases/tdc_v1.4/risingEdgeDetect.vhd @@ -0,0 +1,17 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity risingEdgeDetect is + port (CLK : in std_logic; + SIGNAL_IN : in std_logic; + PULSE_OUT : out std_logic); +end risingEdgeDetect; + +architecture Behavioral of risingEdgeDetect is + + signal signal_d : std_logic; + +begin + signal_d <= SIGNAL_IN when rising_edge(CLK); + PULSE_OUT <= (not signal_d) and SIGNAL_IN when rising_edge(CLK); +end Behavioral; diff --git a/tdc_releases/tdc_v1.4/tdc_constraints.lpf b/tdc_releases/tdc_v1.4/tdc_constraints.lpf new file mode 100644 index 0000000..98242bb --- /dev/null +++ b/tdc_releases/tdc_v1.4/tdc_constraints.lpf @@ -0,0 +1,925 @@ +################################################################# +# TDC Constraints +################################################################# +############################################################################## +## REGION DECLERATION ## +############################################################################## +REGION "REGION_UR_CC" "R51C106D" 4 3 DEVSIZE; +REGION "REGION_LR_CC" "R85C106D" 3 3 DEVSIZE; +REGION "REGION_UL_CC" "R48C53D" 3 3 DEVSIZE; +REGION "REGION_LL_CC" "R90C53D" 3 3 DEVSIZE; + + +############################################################################## +## REFERENCE CHANNEL PLACEMENT ## +############################################################################## +UGROUP "Ref_Ch" BBOX 1 51 + BLKNAME THE_TDC/The_Reference_Time/Reference_Channel_200_1/FC; +LOCATE UGROUP "Ref_Ch" SITE "R8C131D" ; +UGROUP "ref_hit" BBOX 1 1 + BLKNAME THE_TDC/The_Reference_Time/hit_buf_RNO; +LOCATE UGROUP "ref_hit" SITE "R9C133D" ; +UGROUP "Ref_ff_en" BBOX 1 1 + BLKNAME THE_TDC/The_Reference_Time/Reference_Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "Ref_ff_en" SITE "R8C156D" ; + +############################################################################## +## DELAY LINE and HIT BUFFER PLACEMENTS ## +############################################################################## +UGROUP "FC_1" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.1.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_1" SITE "R10C131D" ; +UGROUP "hit_1" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.1.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_1" SITE "R11C133D" ; +UGROUP "ff_en_1" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.1.Channels/Channel_200_1/ff_array_en_i_RNO; +LOCATE UGROUP "ff_en_1" SITE "R10C156D" ; +# +UGROUP "FC_2" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.2.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_2" SITE "R21C131D" ; +UGROUP "hit_2" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.2.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_2" SITE "R22C133D" ; +UGROUP "ff_en_2" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.2.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_2" SITE "R21C156D" ; +# +UGROUP "FC_3" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.3.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_3" SITE "R23C131D" ; +UGROUP "hit_3" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.3.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_3" SITE "R24C133D" ; +UGROUP "ff_en_3" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.3.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_3" SITE "R23C156D" ; +# +UGROUP "FC_4" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.4.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_4" SITE "R30C131D" ; +UGROUP "hit_4" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.4.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_4" SITE "R31C133D" ; +UGROUP "ff_en_4" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.4.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_4" SITE "R30C156D" ; +# +UGROUP "FC_5" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.5.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_5" SITE "R32C131D" ; +UGROUP "hit_5" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.5.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_5" SITE "R33C133D" ; +UGROUP "ff_en_5" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.5.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_5" SITE "R32C156D" ; +# +UGROUP "FC_6" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.6.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_6" SITE "R35C131D" ; +UGROUP "hit_6" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.6.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_6" SITE "R36C133D" ; +UGROUP "ff_en_6" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.6.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_6" SITE "R35C156D" ; +# +UGROUP "FC_7" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.7.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_7" SITE "R37C131D" ; +UGROUP "hit_7" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.7.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_7" SITE "R38C133D" ; +UGROUP "ff_en_7" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.7.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_7" SITE "R37C156D" ; +# +UGROUP "FC_8" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.8.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_8" SITE "R48C131D" ; +UGROUP "hit_8" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.8.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_8" SITE "R49C133D" ; +UGROUP "ff_en_8" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.8.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_8" SITE "R48C156D" ; +# +UGROUP "FC_9" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.9.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_9" SITE "R50C131D" ; +UGROUP "hit_9" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.9.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_9" SITE "R51C133D" ; +UGROUP "ff_en_9" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.9.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_9" SITE "R50C156D" ; +# +UGROUP "FC_10" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.10.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_10" SITE "R53C131D" ; +UGROUP "hit_10" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.10.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_10" SITE "R54C133D" ; +UGROUP "ff_en_10" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.10.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_10" SITE "R53C156D" ; +# +UGROUP "FC_11" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.11.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_11" SITE "R55C131D" ; +UGROUP "hit_11" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.11.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_11" SITE "R56C133D" ; +UGROUP "ff_en_11" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.11.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_11" SITE "R55C156D" ; +# +UGROUP "FC_12" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.12.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_12" SITE "R10C58D" ; +UGROUP "hit_12" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.12.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_12" SITE "R11C60D" ; +UGROUP "ff_en_12" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.12.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_12" SITE "R10C83D" ; +# +UGROUP "FC_13" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.13.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_13" SITE "R23C58D" ; +UGROUP "hit_13" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.13.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_13" SITE "R24C60D" ; +UGROUP "ff_en_13" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.13.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_13" SITE "R23C83D" ; +# +UGROUP "FC_14" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.14.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_14" SITE "R32C58D" ; +UGROUP "hit_14" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.14.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_14" SITE "R33C60D" ; +UGROUP "ff_en_14" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.14.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_14" SITE "R32C83D" ; +# +UGROUP "FC_15" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.15.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_15" SITE "R37C58D" ; +UGROUP "hit_15" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.15.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_15" SITE "R38C60D" ; +UGROUP "ff_en_15" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.15.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_15" SITE "R37C83D" ; +# +UGROUP "FC_16" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.16.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_16" SITE "R50C58D" ; +UGROUP "hit_16" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.16.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_16" SITE "R51C60D" ; +UGROUP "ff_en_16" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.16.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_16" SITE "R50C83D" ; +# +UGROUP "FC_17" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.17.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_17" SITE "R66C131D" ; +UGROUP "hit_17" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.17.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_17" SITE "R67C133D" ; +UGROUP "ff_en_17" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.17.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_17" SITE "R66C156D" ; +# +UGROUP "FC_18" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.18.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_18" SITE "R68C131D" ; +UGROUP "hit_18" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.18.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_18" SITE "R69C133D" ; +UGROUP "ff_en_18" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.18.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_18" SITE "R68C156D" ; +# +UGROUP "FC_19" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.19.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_19" SITE "R71C131D" ; +UGROUP "hit_19" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.19.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_19" SITE "R72C133D" ; +UGROUP "ff_en_19" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.19.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_19" SITE "R71C156D" ; +# +UGROUP "FC_20" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.20.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_20" SITE "R73C131D" ; +UGROUP "hit_20" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.20.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_20" SITE "R74C133D" ; +UGROUP "ff_en_20" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.20.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_20" SITE "R73C156D" ; +# +UGROUP "FC_21" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.21.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_21" SITE "R84C131D" ; +UGROUP "hit_21" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.21.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_21" SITE "R85C133D" ; +UGROUP "ff_en_21" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.21.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_21" SITE "R84C156D" ; +# +UGROUP "FC_22" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.22.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_22" SITE "R86C131D" ; +UGROUP "hit_22" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.22.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_22" SITE "R87C133D" ; +UGROUP "ff_en_22" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.22.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_22" SITE "R86C156D" ; +# +UGROUP "FC_23" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.23.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_23" SITE "R89C131D" ; +UGROUP "hit_23" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.23.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_23" SITE "R90C133D" ; +UGROUP "ff_en_23" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.23.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_23" SITE "R89C156D" ; +# +UGROUP "FC_24" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.24.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_24" SITE "R91C131D" ; +UGROUP "hit_24" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.24.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_24" SITE "R92C133D" ; +UGROUP "ff_en_24" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.24.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_24" SITE "R91C156D" ; +# +UGROUP "FC_25" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.25.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_25" SITE "R102C131D" ; +UGROUP "hit_25" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.25.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_25" SITE "R103C133D" ; +UGROUP "ff_en_25" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.25.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_25" SITE "R102C156D" ; +# +UGROUP "FC_26" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.26.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_26" SITE "R104C131D" ; +UGROUP "hit_26" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.26.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_26" SITE "R105C133D" ; +UGROUP "ff_en_26" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.26.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_26" SITE "R104C156D" ; +# +UGROUP "FC_27" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.27.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_27" SITE "R111C131D" ; +UGROUP "hit_27" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.27.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_27" SITE "R112C133D" ; +UGROUP "ff_en_27" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.27.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_27" SITE "R111C156D" ; +# +UGROUP "FC_28" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.28.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_28" SITE "R113C131D" ; +UGROUP "hit_28" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.28.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_28" SITE "R114C133D" ; +UGROUP "ff_en_28" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.28.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_28" SITE "R113C156D" ; +# +UGROUP "FC_29" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.29.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_29" SITE "R91C58D" ; +UGROUP "hit_29" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.29.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_29" SITE "R92C60D" ; +UGROUP "ff_en_29" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.29.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_29" SITE "R91C83D" ; +# +UGROUP "FC_30" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.30.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_30" SITE "R104C58D" ; +UGROUP "hit_30" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.30.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_30" SITE "R105C60D" ; +UGROUP "ff_en_30" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.30.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_30" SITE "R104C83D" ; +# +UGROUP "FC_31" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.31.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_31" SITE "R113C58D" ; +UGROUP "hit_31" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.31.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_31" SITE "R114C60D" ; +UGROUP "ff_en_31" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.31.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_31" SITE "R113C83D" ; +# +UGROUP "FC_32" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.32.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_32" SITE "R84C58D" ; +UGROUP "hit_32" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.32.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_32" SITE "R85C60D" ; +UGROUP "ff_en_32" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.32.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_32" SITE "R84C83D" ; +# +UGROUP "FC_33" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.33.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_33" SITE "R8C58D" ; +UGROUP "hit_33" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.33.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_33" SITE "R9C60D" ; +UGROUP "ff_en_33" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.33.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_33" SITE "R8C83D" ; +# +UGROUP "FC_34" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.34.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_34" SITE "R21C58D" ; +UGROUP "hit_34" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.34.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_34" SITE "R22C60D" ; +UGROUP "ff_en_34" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.34.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_34" SITE "R21C83D" ; +# +UGROUP "FC_35" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.35.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_35" SITE "R30C58D" ; +UGROUP "hit_35" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.35.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_35" SITE "R31C60D" ; +UGROUP "ff_en_35" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.35.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_35" SITE "R30C83D" ; +# +UGROUP "FC_36" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.36.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_36" SITE "R35C58D" ; +UGROUP "hit_36" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.36.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_36" SITE "R36C60D" ; +UGROUP "ff_en_36" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.36.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_36" SITE "R35C83D" ; +# +UGROUP "FC_37" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.37.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_37" SITE "R48C58D" ; +UGROUP "hit_37" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.37.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_37" SITE "R49C60D" ; +UGROUP "ff_en_37" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.37.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_37" SITE "R48C83D" ; +# +UGROUP "FC_38" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.38.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_38" SITE "R8C2D" ; +UGROUP "hit_38" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.38.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_38" SITE "R9C4D" ; +UGROUP "ff_en_38" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.38.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_38" SITE "R8C27D" ; +# +UGROUP "FC_39" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.39.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_39" SITE "R10C2D" ; +UGROUP "hit_39" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.39.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_39" SITE "R11C4D" ; +UGROUP "ff_en_39" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.39.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_39" SITE "R10C27D" ; +# +UGROUP "FC_40" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.40.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_40" SITE "R21C2D" ; +UGROUP "hit_40" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.40.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_40" SITE "R22C4D" ; +UGROUP "ff_en_40" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.40.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_40" SITE "R21C27D" ; +# +UGROUP "FC_41" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.41.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_41" SITE "R23C2D" ; +UGROUP "hit_41" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.41.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_41" SITE "R24C4D" ; +UGROUP "ff_en_41" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.41.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_41" SITE "R23C27D" ; +# +UGROUP "FC_42" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.42.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_42" SITE "R30C2D" ; +UGROUP "hit_42" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.42.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_42" SITE "R31C4D" ; +UGROUP "ff_en_42" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.42.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_42" SITE "R30C27D" ; +# +UGROUP "FC_43" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.43.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_43" SITE "R32C2D" ; +UGROUP "hit_43" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.43.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_43" SITE "R33C4D" ; +UGROUP "ff_en_43" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.43.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_43" SITE "R32C27D" ; +# +UGROUP "FC_44" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.44.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_44" SITE "R35C2D" ; +UGROUP "hit_44" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.44.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_44" SITE "R36C4D" ; +UGROUP "ff_en_44" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.44.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_44" SITE "R35C27D" ; +# +UGROUP "FC_45" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.45.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_45" SITE "R37C2D" ; +UGROUP "hit_45" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.45.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_45" SITE "R38C4D" ; +UGROUP "ff_en_45" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.45.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_45" SITE "R37C27D" ; +# +UGROUP "FC_46" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.46.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_46" SITE "R48C2D" ; +UGROUP "hit_46" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.46.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_46" SITE "R49C4D" ; +UGROUP "ff_en_46" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.46.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_46" SITE "R48C27D" ; +# +UGROUP "FC_47" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.47.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_47" SITE "R50C2D" ; +UGROUP "hit_47" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.47.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_47" SITE "R51C4D" ; +UGROUP "ff_en_47" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.47.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_47" SITE "R50C27D" ; +# +UGROUP "FC_48" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.48.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_48" SITE "R53C2D" ; +UGROUP "hit_48" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.48.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_48" SITE "R54C4D" ; +UGROUP "ff_en_48" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.48.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_48" SITE "R53C27D" ; +# +UGROUP "FC_49" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.49.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_49" SITE "R55C2D" ; +UGROUP "hit_49" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.49.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_49" SITE "R56C4D" ; +UGROUP "ff_en_49" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.49.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_49" SITE "R55C27D" ; +# +UGROUP "FC_50" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.50.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_50" SITE "R89C58D" ; +UGROUP "hit_50" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.50.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_50" SITE "R90C60D" ; +UGROUP "ff_en_50" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.50.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_50" SITE "R89C83D" ; +# +UGROUP "FC_51" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.51.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_51" SITE "R102C58D" ; +UGROUP "hit_51" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.51.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_51" SITE "R103C60D" ; +UGROUP "ff_en_51" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.51.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_51" SITE "R102C83D" ; +# +UGROUP "FC_52" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.52.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_52" SITE "R111C58D" ; +UGROUP "hit_52" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.52.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_52" SITE "R112C60D" ; +UGROUP "ff_en_52" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.52.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_52" SITE "R111C83D" ; +# +UGROUP "FC_53" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.53.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_53" SITE "R66C2D" ; +UGROUP "hit_53" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.53.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_53" SITE "R67C4D" ; +UGROUP "ff_en_53" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.53.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_53" SITE "R66C27D" ; +# +UGROUP "FC_54" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.54.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_54" SITE "R68C2D" ; +UGROUP "hit_54" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.54.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_54" SITE "R69C4D" ; +UGROUP "ff_en_54" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.54.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_54" SITE "R68C27D" ; +# +UGROUP "FC_55" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.55.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_55" SITE "R71C2D" ; +UGROUP "hit_55" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.55.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_55" SITE "R72C4D" ; +UGROUP "ff_en_55" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.55.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_55" SITE "R71C27D" ; +# +UGROUP "FC_56" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.56.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_56" SITE "R73C2D" ; +UGROUP "hit_56" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.56.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_56" SITE "R74C4D" ; +UGROUP "ff_en_56" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.56.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_56" SITE "R73C27D" ; +# +UGROUP "FC_57" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.57.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_57" SITE "R84C2D" ; +UGROUP "hit_57" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.57.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_57" SITE "R85C4D" ; +UGROUP "ff_en_57" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.57.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_57" SITE "R84C27D" ; +# +UGROUP "FC_58" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.58.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_58" SITE "R86C2D" ; +UGROUP "hit_58" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.58.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_58" SITE "R87C4D" ; +UGROUP "ff_en_58" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.58.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_58" SITE "R86C27D" ; +# +UGROUP "FC_59" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.59.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_59" SITE "R89C2D" ; +UGROUP "hit_59" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.59.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_59" SITE "R90C4D" ; +UGROUP "ff_en_59" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.59.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_59" SITE "R89C27D" ; +# +UGROUP "FC_60" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.60.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_60" SITE "R91C2D" ; +UGROUP "hit_60" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.60.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_60" SITE "R92C4D" ; +UGROUP "ff_en_60" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.60.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_60" SITE "R91C27D" ; +# +UGROUP "FC_61" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.61.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_61" SITE "R102C2D" ; +UGROUP "hit_61" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.61.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_61" SITE "R103C4D" ; +UGROUP "ff_en_61" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.61.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_61" SITE "R102C27D" ; +# +UGROUP "FC_62" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.62.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_62" SITE "R104C2D" ; +UGROUP "hit_62" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.62.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_62" SITE "R105C4D" ; +UGROUP "ff_en_62" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.62.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_62" SITE "R104C27D" ; +# +UGROUP "FC_63" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.63.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_63" SITE "R111C2D" ; +UGROUP "hit_63" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.63.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_63" SITE "R112C4D" ; +UGROUP "ff_en_63" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.63.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_63" SITE "R111C27D" ; +# +UGROUP "FC_64" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels.64.Channels/Channel_200_1/FC; +LOCATE UGROUP "FC_64" SITE "R113C2D" ; +UGROUP "hit_64" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.64.Channels/hit_buf_RNO; +LOCATE UGROUP "hit_64" SITE "R114C4D" ; +UGROUP "ff_en_64" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels.64.Channels/Channel_200_1/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_64" SITE "R113C27D" ; + + +############################################################################## +## CHANNEL PLACEMENTS ## +############################################################################## +UGROUP "E&F_ref" BBOX 6 25 + BLKNAME THE_TDC/The_Reference_Time/Reference_Channel_200_1; +LOCATE UGROUP "E&F_ref" SITE "R11C131D" ; +UGROUP "E&F_1" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.1.Channels/Channel_200_1; +LOCATE UGROUP "E&F_1" SITE "R11C156D" ; +UGROUP "E&F_2" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.2.Channels/Channel_200_1; +LOCATE UGROUP "E&F_2" SITE "R15C131D" ; +UGROUP "E&F_3" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.3.Channels/Channel_200_1; +LOCATE UGROUP "E&F_3" SITE "R15C156D" ; +UGROUP "E&F_4" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.4.Channels/Channel_200_1; +LOCATE UGROUP "E&F_4" SITE "R24C131D" ; +UGROUP "E&F_5" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.5.Channels/Channel_200_1; +LOCATE UGROUP "E&F_5" SITE "R24C156D" ; +UGROUP "E&F_6" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.6.Channels/Channel_200_1; +LOCATE UGROUP "E&F_6" SITE "R38C131D" ; +UGROUP "E&F_7" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.7.Channels/Channel_200_1; +LOCATE UGROUP "E&F_7" SITE "R38C156D" ; +UGROUP "E&F_8" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.8.Channels/Channel_200_1; +LOCATE UGROUP "E&F_8" SITE "R42C131D" ; +UGROUP "E&F_9" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.9.Channels/Channel_200_1; +LOCATE UGROUP "E&F_9" SITE "R42C156D" ; +UGROUP "E&F_10" BBOX 6 24 + BLKNAME THE_TDC/GEN_Channels.10.Channels/Channel_200_1; +LOCATE UGROUP "E&F_10" SITE "R56C131D" ; +UGROUP "E&F_11" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.11.Channels/Channel_200_1; +LOCATE UGROUP "E&F_11" SITE "R56C155D" ; +UGROUP "E&F_12" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.12.Channels/Channel_200_1; +LOCATE UGROUP "E&F_12" SITE "R11C84D" ; +UGROUP "E&F_13" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.13.Channels/Channel_200_1; +LOCATE UGROUP "E&F_13" SITE "R15C84D" ; +UGROUP "E&F_14" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.14.Channels/Channel_200_1; +LOCATE UGROUP "E&F_14" SITE "R24C84D" ; +UGROUP "E&F_15" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.15.Channels/Channel_200_1; +LOCATE UGROUP "E&F_15" SITE "R38C84D" ; +UGROUP "E&F_16" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.16.Channels/Channel_200_1; +LOCATE UGROUP "E&F_16" SITE "R42C84D" ; +UGROUP "E&F_17" BBOX 6 24 + BLKNAME THE_TDC/GEN_Channels.17.Channels/Channel_200_1; +LOCATE UGROUP "E&F_17" SITE "R60C131D" ; +UGROUP "E&F_18" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.18.Channels/Channel_200_1; +LOCATE UGROUP "E&F_18" SITE "R60C155D" ; +UGROUP "E&F_19" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.19.Channels/Channel_200_1; +LOCATE UGROUP "E&F_19" SITE "R74C131D" ; +UGROUP "E&F_20" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.20.Channels/Channel_200_1; +LOCATE UGROUP "E&F_20" SITE "R74C156D" ; +UGROUP "E&F_21" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.21.Channels/Channel_200_1; +LOCATE UGROUP "E&F_21" SITE "R78C131D" ; +UGROUP "E&F_22" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.22.Channels/Channel_200_1; +LOCATE UGROUP "E&F_22" SITE "R78C156D" ; +UGROUP "E&F_23" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.23.Channels/Channel_200_1; +LOCATE UGROUP "E&F_23" SITE "R92C131D" ; +UGROUP "E&F_24" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.24.Channels/Channel_200_1; +LOCATE UGROUP "E&F_24" SITE "R92C156D" ; +UGROUP "E&F_25" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.25.Channels/Channel_200_1; +LOCATE UGROUP "E&F_25" SITE "R96C131D" ; +UGROUP "E&F_26" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.26.Channels/Channel_200_1; +LOCATE UGROUP "E&F_26" SITE "R96C156D" ; +UGROUP "E&F_27" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.27.Channels/Channel_200_1; +LOCATE UGROUP "E&F_27" SITE "R105C131D" ; +UGROUP "E&F_28" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.28.Channels/Channel_200_1; +LOCATE UGROUP "E&F_28" SITE "R105C156D" ; +UGROUP "E&F_29" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.29.Channels/Channel_200_1; +LOCATE UGROUP "E&F_29" SITE "R92C84D" ; +UGROUP "E&F_30" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.30.Channels/Channel_200_1; +LOCATE UGROUP "E&F_30" SITE "R96C84D" ; +UGROUP "E&F_31" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.31.Channels/Channel_200_1; +LOCATE UGROUP "E&F_31" SITE "R105C84D" ; +UGROUP "E&F_32" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.32.Channels/Channel_200_1; +LOCATE UGROUP "E&F_32" SITE "R78C72D" ; +UGROUP "E&F_33" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.33.Channels/Channel_200_1; +LOCATE UGROUP "E&F_33" SITE "R11C59D" ; +UGROUP "E&F_34" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.34.Channels/Channel_200_1; +LOCATE UGROUP "E&F_34" SITE "R15C59D" ; +UGROUP "E&F_35" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.35.Channels/Channel_200_1; +LOCATE UGROUP "E&F_35" SITE "R24C59D" ; +UGROUP "E&F_36" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.36.Channels/Channel_200_1; +LOCATE UGROUP "E&F_36" SITE "R38C59D" ; +UGROUP "E&F_37" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.37.Channels/Channel_200_1; +LOCATE UGROUP "E&F_37" SITE "R42C59D" ; +UGROUP "E&F_38" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.38.Channels/Channel_200_1; +LOCATE UGROUP "E&F_38" SITE "R11C3D" ; +UGROUP "E&F_39" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.39.Channels/Channel_200_1; +LOCATE UGROUP "E&F_39" SITE "R11C28D" ; +UGROUP "E&F_40" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.40.Channels/Channel_200_1; +LOCATE UGROUP "E&F_40" SITE "R15C3D" ; +UGROUP "E&F_41" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.41.Channels/Channel_200_1; +LOCATE UGROUP "E&F_41" SITE "R15C28D" ; +UGROUP "E&F_42" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.42.Channels/Channel_200_1; +LOCATE UGROUP "E&F_42" SITE "R24C3D" ; +UGROUP "E&F_43" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.43.Channels/Channel_200_1; +LOCATE UGROUP "E&F_43" SITE "R24C28D" ; +UGROUP "E&F_44" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.44.Channels/Channel_200_1; +LOCATE UGROUP "E&F_44" SITE "R38C3D" ; +UGROUP "E&F_45" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.45.Channels/Channel_200_1; +LOCATE UGROUP "E&F_45" SITE "R38C28D" ; +UGROUP "E&F_46" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.46.Channels/Channel_200_1; +LOCATE UGROUP "E&F_46" SITE "R42C3D" ; +UGROUP "E&F_47" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.47.Channels/Channel_200_1; +LOCATE UGROUP "E&F_47" SITE "R42C28D" ; +UGROUP "E&F_48" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.48.Channels/Channel_200_1; +LOCATE UGROUP "E&F_48" SITE "R56C3D" ; +UGROUP "E&F_49" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.49.Channels/Channel_200_1; +LOCATE UGROUP "E&F_49" SITE "R56C28D" ; +UGROUP "E&F_50" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.50.Channels/Channel_200_1; +LOCATE UGROUP "E&F_50" SITE "R92C59D" ; +UGROUP "E&F_51" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.51.Channels/Channel_200_1; +LOCATE UGROUP "E&F_51" SITE "R96C59D" ; +UGROUP "E&F_52" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.52.Channels/Channel_200_1; +LOCATE UGROUP "E&F_52" SITE "R105C59D" ; +UGROUP "E&F_53" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.53.Channels/Channel_200_1; +LOCATE UGROUP "E&F_53" SITE "R60C3D" ; +UGROUP "E&F_54" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.54.Channels/Channel_200_1; +LOCATE UGROUP "E&F_54" SITE "R60C28D" ; +UGROUP "E&F_55" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.55.Channels/Channel_200_1; +LOCATE UGROUP "E&F_55" SITE "R74C3D" ; +UGROUP "E&F_56" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.56.Channels/Channel_200_1; +LOCATE UGROUP "E&F_56" SITE "R74C28D" ; +UGROUP "E&F_57" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.57.Channels/Channel_200_1; +LOCATE UGROUP "E&F_57" SITE "R78C3D" ; +UGROUP "E&F_58" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.58.Channels/Channel_200_1; +LOCATE UGROUP "E&F_58" SITE "R78C28D" ; +UGROUP "E&F_59" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.59.Channels/Channel_200_1; +LOCATE UGROUP "E&F_59" SITE "R92C3D" ; +UGROUP "E&F_60" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.60.Channels/Channel_200_1; +LOCATE UGROUP "E&F_60" SITE "R92C28D" ; +UGROUP "E&F_61" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.61.Channels/Channel_200_1; +LOCATE UGROUP "E&F_61" SITE "R96C3D" ; +UGROUP "E&F_62" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.62.Channels/Channel_200_1; +LOCATE UGROUP "E&F_62" SITE "R96C28D" ; +UGROUP "E&F_63" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.63.Channels/Channel_200_1; +LOCATE UGROUP "E&F_63" SITE "R105C3D" ; +UGROUP "E&F_64" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels.64.Channels/Channel_200_1; +LOCATE UGROUP "E&F_64" SITE "R105C28D" ; + +############################################################################# +## Coarse counter register placement + +UGROUP "UR_Coarse_Counter" + BLKNAME THE_TDC/GenCoarseCounter.1.TheCoarseCounter; +LOCATE UGROUP "UR_Coarse_Counter" SITE R36C134D; #REGION "REGION_UR_CC" ; +UGROUP "LR_Coarse_Counter" + BLKNAME THE_TDC/GenCoarseCounter.2.TheCoarseCounter; +LOCATE UGROUP "LR_Coarse_Counter" SITE R85C134D; #REGION "REGION_LR_CC" ; +UGROUP "UL_Coarse_Counter" + BLKNAME THE_TDC/GenCoarseCounter.3.TheCoarseCounter; +LOCATE UGROUP "UL_Coarse_Counter" SITE R36C50D; #REGION "REGION_UL_CC" ; +UGROUP "LL_Coarse_Counter" + BLKNAME THE_TDC/GenCoarseCounter.4.TheCoarseCounter; +LOCATE UGROUP "LL_Coarse_Counter" SITE R85C50D; #REGION "REGION_LL_CC" ; +UGROUP "Epoch_Counter" + BLKNAME THE_TDC/TheEpochCounter; +LOCATE UGROUP "Epoch_Counter" SITE R36C138D; + +############################################################################# +## Bus Handler Placements + +UGROUP "BusHandlers" + BLKNAME THE_TDC/TheHitCounterBus + BLKNAME THE_TDC/TheStatusRegistersBus + BLKNAME THE_TDC/TheLostHitBus + BLKNAME THE_TDC/TheEncoderStartBus + BLKNAME THE_TDC/TheEncoderFinishedBus; +#LOCATE UGROUP "BusHandlers" REGION BUS + + + + +############################################################################# +## Unimportant Data Lines ## +############################################################################# + +#BLOCK NET "THE_TDC/reset_tdc*" ; +BLOCK NET "THE_TDC/hit_in_i_*" ; +#BLOCK PATH TO CELL "THE_TDC/GEN_Channels.*.Channels/Channel_200_1/FC/FF_*" ; +#BLOCK NET "THE_TDC/reset_counters_200*" ; +BLOCK PATH TO CELL "THE_TDC/GEN_Channels.*.Channels/sync_q_2[*]"; + +PROHIBIT SECONDARY NET "THE_TDC/The_Reference_Time/Reference_Channel_200_1/ff_array_en_i"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.*.Channels/Channel_200_1/ff_array_en_i"; + +MAXDELAY NET "THE_TDC/The_Reference_Time/hit_buf" 0.600000 nS DATAPATH_ONLY ; +MAXDELAY NET "THE_TDC/GEN_Channels.*.Channels/hit_buf" 0.600000 nS DATAPATH_ONLY ; + +MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset[1]" 50 ns; +MULTICYCLE FROM CELL "THE_TDC/TheEpochCounter/counter[*]" TO CELL "THE_TDC/GEN_Channels.*.Channels/Channel_200_1/epoch_cntr[*]" 5.000000 X; +MULTICYCLE FROM CELL "THE_TDC/TheEpochCounter/counter[*]" TO CELL "THE_TDC/The_Reference_Time/Reference_Channel_200_1/epoch_cntr[*]" 5.000000 X; +#MULTICYCLE FROM CELL "THE_TDC/The_Reference_Time/Reference_Channel_200_1/FIFO_ALMOST_FULL_OUT" TO CELL "THE_TDC/TheReadout/data_out_reg_*" 2.000000 X; +MULTICYCLE FROM CELL "THE_TDC/The_Reference_Time/Reference_Channel_200_1/FIFO_FULL_OUT" TO CELL "THE_TDC/TheReadout/data_out_reg_*" 2.000000 X; +MULTICYCLE FROM CELL "THE_TDC/GEN_Channels.*.Channels/Channel_200_1/FIFO_FULL_OUT" TO CELL "THE_TDC/TheReadout/data_out_reg*" 2.000000 X; +#MULTICYCLE FROM CELL "THE_TDC/GEN_Channels.*.Channels/Channel_200_1/FIFO_ALMOST_FULL_OUT" TO CELL "THE_TDC/TheReadout/data_out_reg*" 2.000000 X; + diff --git a/tdc_releases/tdc_v1.4/trb3_periph.vhd b/tdc_releases/tdc_v1.4/trb3_periph.vhd new file mode 100644 index 0000000..c4524c4 --- /dev/null +++ b/tdc_releases/tdc_v1.4/trb3_periph.vhd @@ -0,0 +1,795 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.version.all; + + +entity trb3_periph is + port( + --Clocks + CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz + CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA + CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right! + CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right! + --Trigger + TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out + TRIGGER_RIGHT : in std_logic; --right side trigger input from fan-out + --Serdes + CLK_SERDES_INT_LEFT : in std_logic; --Clock Manager 1/(1357), off, 125 MHz possible + CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 2/(1357), 200 MHz, only in case of problems + SERDES_INT_TX : out std_logic_vector(3 downto 0); + SERDES_INT_RX : in std_logic_vector(3 downto 0); + SERDES_ADDON_TX : out std_logic_vector(11 downto 0); + SERDES_ADDON_RX : in std_logic_vector(11 downto 0); + --Inter-FPGA Communication + FPGA5_COMM : inout std_logic_vector(11 downto 0); + --Bit 0/1 input, serial link RX active + --Bit 2/3 output, serial link TX active + --Connection to ADA AddOn + SPARE_LINE : inout std_logic_vector(3 downto 0); --inputs only + INP : in std_logic_vector(63 downto 0); + --DAC_SDO : in std_logic; + --DAC_SDI : out std_logic; + --DAC_SCK : out std_logic; + --DAC_CS : out std_logic_vector(3 downto 0); + --Flash ROM & Reboot + FLASH_CLK : out std_logic; + FLASH_CS : out std_logic; + FLASH_DIN : out std_logic; + FLASH_DOUT : in std_logic; + PROGRAMN : out std_logic; --reboot FPGA + --Misc + TEMPSENS : inout std_logic; --Temperature Sensor + CODE_LINE : in std_logic_vector(1 downto 0); + LED_GREEN : out std_logic; + LED_ORANGE : out std_logic; + LED_RED : out std_logic; + LED_YELLOW : out std_logic; + SUPPL : in std_logic; --terminated diff pair, PCLK, Pads + --Test Connectors + TEST_LINE : out std_logic_vector(15 downto 0) + ); + attribute syn_useioff : boolean; + --no IO-FF for LEDs relaxes timing constraints + attribute syn_useioff of LED_GREEN : signal is false; + attribute syn_useioff of LED_ORANGE : signal is false; + attribute syn_useioff of LED_RED : signal is false; + attribute syn_useioff of LED_YELLOW : signal is false; + attribute syn_useioff of TEMPSENS : signal is false; + attribute syn_useioff of PROGRAMN : signal is false; + attribute syn_useioff of CODE_LINE : signal is false; + attribute syn_useioff of TRIGGER_LEFT : signal is false; + attribute syn_useioff of TRIGGER_RIGHT : signal is false; + --important signals + attribute syn_useioff of FLASH_CLK : signal is true; + attribute syn_useioff of FLASH_CS : signal is true; + attribute syn_useioff of FLASH_DIN : signal is true; + attribute syn_useioff of FLASH_DOUT : signal is true; + attribute syn_useioff of FPGA5_COMM : signal is true; + attribute syn_useioff of TEST_LINE : signal is true; + attribute syn_useioff of INP : signal is false; + attribute syn_useioff of SPARE_LINE : signal is true; + --attribute syn_useioff of DAC_SDO : signal is true; + --attribute syn_useioff of DAC_SDI : signal is true; + --attribute syn_useioff of DAC_SCK : signal is true; + --attribute syn_useioff of DAC_CS : signal is true; + +end entity; + + +architecture trb3_periph_arch of trb3_periph is + --Constants + constant REGIO_NUM_STAT_REGS : integer := 3; + constant REGIO_NUM_CTRL_REGS : integer := 3; + + attribute syn_keep : boolean; + attribute syn_preserve : boolean; + + --Clock / Reset + signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL + signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL + signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic. + signal clear_i : std_logic; + signal reset_i : std_logic; + signal GSR_N : std_logic; + attribute syn_keep of GSR_N : signal is true; + attribute syn_preserve of GSR_N : signal is true; + + --Media Interface + signal med_stat_op : std_logic_vector (1*16-1 downto 0); + signal med_ctrl_op : std_logic_vector (1*16-1 downto 0); + signal med_stat_debug : std_logic_vector (1*64-1 downto 0); + signal med_data_out : std_logic_vector (1*16-1 downto 0); + signal med_packet_num_out : std_logic_vector (1*3-1 downto 0); + signal med_dataready_out : std_logic; + signal med_read_out : std_logic; + signal med_data_in : std_logic_vector (1*16-1 downto 0); + signal med_packet_num_in : std_logic_vector (1*3-1 downto 0); + signal med_dataready_in : std_logic; + signal med_read_in : std_logic; + + --LVL1 channel + signal timing_trg_received_i : std_logic; + signal trg_data_valid_i : std_logic; + signal trg_timing_valid_i : std_logic; + signal trg_notiming_valid_i : std_logic; + signal trg_invalid_i : std_logic; + signal trg_type_i : std_logic_vector(3 downto 0); + signal trg_number_i : std_logic_vector(15 downto 0); + signal trg_code_i : std_logic_vector(7 downto 0); + signal trg_information_i : std_logic_vector(23 downto 0); + signal trg_int_number_i : std_logic_vector(15 downto 0); + signal trg_multiple_trg_i : std_logic; + signal trg_timeout_detected_i : std_logic; + signal trg_spurious_trg_i : std_logic; + signal trg_missing_tmg_trg_i : std_logic; + signal trg_spike_detected_i : std_logic; + + --Data channel + signal fee_trg_release_i : std_logic; + signal fee_trg_statusbits_i : std_logic_vector(31 downto 0); + signal fee_data_i : std_logic_vector(31 downto 0); + signal fee_data_write_i : std_logic; + signal fee_data_finished_i : std_logic; + signal fee_almost_full_i : std_logic; + + --Slow Control channel + signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0); + signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); + signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0); + signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0); + signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0); + signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0); + signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0); + signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0); + + --RegIO + signal regio_addr_out : std_logic_vector (15 downto 0); + signal regio_read_enable_out : std_logic; + signal regio_write_enable_out : std_logic; + signal regio_data_out : std_logic_vector (31 downto 0); + signal regio_data_in : std_logic_vector (31 downto 0); + signal regio_dataready_in : std_logic; + signal regio_no_more_data_in : std_logic; + signal regio_write_ack_in : std_logic; + signal regio_unknown_addr_in : std_logic; + signal regio_timeout_out : std_logic; + + --Timer + signal global_time : std_logic_vector(31 downto 0); + signal local_time : std_logic_vector(7 downto 0); + signal time_since_last_trg : std_logic_vector(31 downto 0); + signal timer_ticks : std_logic_vector(1 downto 0); + + --Flash + signal spictrl_read_en : std_logic; + signal spictrl_write_en : std_logic; + signal spictrl_data_in : std_logic_vector(31 downto 0); + signal spictrl_addr : std_logic; + signal spictrl_data_out : std_logic_vector(31 downto 0); + signal spictrl_ack : std_logic; + signal spictrl_busy : std_logic; + signal spimem_read_en : std_logic; + signal spimem_write_en : std_logic; + signal spimem_data_in : std_logic_vector(31 downto 0); + signal spimem_addr : std_logic_vector(5 downto 0); + signal spimem_data_out : std_logic_vector(31 downto 0); + signal spimem_ack : std_logic; + signal spidac_read_en : std_logic; + signal spidac_write_en : std_logic; + signal spidac_data_in : std_logic_vector(31 downto 0); + signal spidac_addr : std_logic_vector(4 downto 0); + signal spidac_data_out : std_logic_vector(31 downto 0); + signal spidac_ack : std_logic; + signal spidac_busy : std_logic; + + signal dac_cs_i : std_logic_vector(3 downto 0); + signal dac_sck_i : std_logic; + signal dac_sdi_i : std_logic; + + signal hitreg_read_en : std_logic; + signal hitreg_write_en : std_logic; + signal hitreg_addr : std_logic_vector(6 downto 0); + signal hitreg_data_out : std_logic_vector(31 downto 0); + signal hitreg_data_ready : std_logic; + signal hitreg_invalid : std_logic; + + signal srb_read_en : std_logic; + signal srb_write_en : std_logic; + signal srb_addr : std_logic_vector(6 downto 0); + signal srb_data_out : std_logic_vector(31 downto 0); + signal srb_data_ready : std_logic; + signal srb_invalid : std_logic; + + signal lhb_read_en : std_logic; + signal lhb_write_en : std_logic; + signal lhb_addr : std_logic_vector(6 downto 0); + signal lhb_data_out : std_logic_vector(31 downto 0); + signal lhb_data_ready : std_logic; + signal lhb_invalid : std_logic; + + signal esb_read_en : std_logic; + signal esb_write_en : std_logic; + signal esb_addr : std_logic_vector(6 downto 0); + signal esb_data_out : std_logic_vector(31 downto 0); + signal esb_data_ready : std_logic; + signal esb_invalid : std_logic; + + signal efb_read_en : std_logic; + signal efb_write_en : std_logic; + signal efb_addr : std_logic_vector(6 downto 0); + signal efb_data_out : std_logic_vector(31 downto 0); + signal efb_data_ready : std_logic; + signal efb_invalid : std_logic; + + signal tdc_ctrl_read : std_logic; + signal last_tdc_ctrl_read : std_logic; + signal tdc_ctrl_write : std_logic; + signal tdc_ctrl_addr : std_logic_vector(1 downto 0); + signal tdc_ctrl_data_in : std_logic_vector(31 downto 0); + signal tdc_ctrl_data_out : std_logic_vector(31 downto 0); + signal tdc_ctrl_reg : std_logic_vector(5*32-1 downto 0); + + signal spi_bram_addr : std_logic_vector(7 downto 0); + signal spi_bram_wr_d : std_logic_vector(7 downto 0); + signal spi_bram_rd_d : std_logic_vector(7 downto 0); + signal spi_bram_we : std_logic; + + --TDC + signal hit_in_i : std_logic_vector(64 downto 1); + signal logic_analyser_i : std_logic_vector(15 downto 0); + +begin +--------------------------------------------------------------------------- +-- Reset Generation +--------------------------------------------------------------------------- + + GSR_N <= pll_lock; + + THE_RESET_HANDLER : trb_net_reset_handler + generic map( + RESET_DELAY => x"FEEE" + ) + port map( + CLEAR_IN => '0', -- reset input (high active, async) + CLEAR_N_IN => '1', -- reset input (low active, async) + CLK_IN => clk_200_i, -- raw master clock, NOT from PLL/DLL! + SYSCLK_IN => clk_100_i, -- PLL/DLL remastered clock + PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async) + RESET_IN => '0', -- general reset signal (SYSCLK) + TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK) + CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE! + RESET_OUT => reset_i, -- synchronous reset out (SYSCLK) + DEBUG_OUT => open + ); + + +--------------------------------------------------------------------------- +-- Clock Handling +--------------------------------------------------------------------------- + THE_MAIN_PLL : pll_in200_out100 + port map( + CLK => CLK_GPLL_RIGHT, + CLKOP => clk_100_i, + CLKOK => clk_200_i, + LOCK => pll_lock + ); + + +--------------------------------------------------------------------------- +-- The TrbNet media interface (to other FPGA) +--------------------------------------------------------------------------- + THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp + generic map( + SERDES_NUM => 1, --number of serdes in quad + EXT_CLOCK => c_NO, --use internal clock + USE_200_MHZ => c_YES, --run on 200 MHz clock + USE_125_MHZ => c_NO, + USE_CTC => c_NO + ) + port map( + CLK => clk_200_i, + SYSCLK => clk_100_i, + RESET => reset_i, + CLEAR => clear_i, + CLK_EN => '1', + --Internal Connection + MED_DATA_IN => med_data_out, + MED_PACKET_NUM_IN => med_packet_num_out, + MED_DATAREADY_IN => med_dataready_out, + MED_READ_OUT => med_read_in, + MED_DATA_OUT => med_data_in, + MED_PACKET_NUM_OUT => med_packet_num_in, + MED_DATAREADY_OUT => med_dataready_in, + MED_READ_IN => med_read_out, + REFCLK2CORE_OUT => open, + --SFP Connection + SD_RXD_P_IN => SERDES_INT_RX(2), + SD_RXD_N_IN => SERDES_INT_RX(3), + SD_TXD_P_OUT => SERDES_INT_TX(2), + SD_TXD_N_OUT => SERDES_INT_TX(3), + SD_REFCLK_P_IN => open, + SD_REFCLK_N_IN => open, + SD_PRSNT_N_IN => FPGA5_COMM(0), + SD_LOS_IN => FPGA5_COMM(0), + SD_TXDIS_OUT => FPGA5_COMM(2), + -- Status and control port + STAT_OP => med_stat_op, + CTRL_OP => med_ctrl_op, + STAT_DEBUG => med_stat_debug, + CTRL_DEBUG => (others => '0') + ); + +--------------------------------------------------------------------------- +-- Endpoint +--------------------------------------------------------------------------- + --regio_hardware_version_i <= x"9100" & addOn_type_i & edge_type_i & tdc_channel_no_i & x"0"; + + --addOn_type_i <= x"0"; -- x"0" - ADA AddOn version 1 + -- -- x"1" - ADA AddOn version 2 + -- -- x"2" - multi purpose test AddOn + -- -- x"3" - SFP hub AddOn + -- -- x"4" - Wasa AddOn + --edge_type_i <= x"0"; -- x"0" - single edge + -- -- x"1" - double edge + --tdc_channel_no_i <= x"6"; -- 2^n channels + + THE_ENDPOINT : trb_net16_endpoint_hades_full_handler + generic map( + REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS, --4, --16 stat reg + REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, --3, --8 cotrol reg + ADDRESS_MASK => x"FFFF", + BROADCAST_BITMASK => x"FF", + BROADCAST_SPECIAL_ADDR => x"48", + REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)), + REGIO_HARDWARE_VERSION => x"91000060", -- regio_hardware_version_i, + REGIO_INIT_ADDRESS => x"f305", + REGIO_USE_VAR_ENDPOINT_ID => c_YES, + CLOCK_FREQUENCY => 125, + TIMING_TRIGGER_RAW => c_YES, + --Configure data handler + DATA_INTERFACE_NUMBER => 1, + DATA_BUFFER_DEPTH => 13, --13 + DATA_BUFFER_WIDTH => 32, + DATA_BUFFER_FULL_THRESH => 2**13-800, --2**13-(maximal 2**12) + TRG_RELEASE_AFTER_DATA => c_YES, + HEADER_BUFFER_DEPTH => 9, + HEADER_BUFFER_FULL_THRESH => 2**9-16 + ) + port map( + CLK => clk_100_i, + RESET => reset_i, + CLK_EN => '1', + MED_DATAREADY_OUT => med_dataready_out, -- open, -- + MED_DATA_OUT => med_data_out, -- open, -- + MED_PACKET_NUM_OUT => med_packet_num_out, -- open, -- + MED_READ_IN => med_read_in, + MED_DATAREADY_IN => med_dataready_in, + MED_DATA_IN => med_data_in, + MED_PACKET_NUM_IN => med_packet_num_in, + MED_READ_OUT => med_read_out, -- open, -- + MED_STAT_OP_IN => med_stat_op, + MED_CTRL_OP_OUT => med_ctrl_op, + + --Timing trigger in + TRG_TIMING_TRG_RECEIVED_IN => timing_trg_received_i, + --LVL1 trigger to FEE + LVL1_TRG_DATA_VALID_OUT => trg_data_valid_i, + LVL1_VALID_TIMING_TRG_OUT => trg_timing_valid_i, + LVL1_VALID_NOTIMING_TRG_OUT => trg_notiming_valid_i, + LVL1_INVALID_TRG_OUT => trg_invalid_i, + + LVL1_TRG_TYPE_OUT => trg_type_i, + LVL1_TRG_NUMBER_OUT => trg_number_i, + LVL1_TRG_CODE_OUT => trg_code_i, + LVL1_TRG_INFORMATION_OUT => trg_information_i, + LVL1_INT_TRG_NUMBER_OUT => trg_int_number_i, + + --Information about trigger handler errors + TRG_MULTIPLE_TRG_OUT => trg_multiple_trg_i, + TRG_TIMEOUT_DETECTED_OUT => trg_timeout_detected_i, + TRG_SPURIOUS_TRG_OUT => trg_spurious_trg_i, + TRG_MISSING_TMG_TRG_OUT => trg_missing_tmg_trg_i, + TRG_SPIKE_DETECTED_OUT => trg_spike_detected_i, + + --Response from FEE + FEE_TRG_RELEASE_IN(0) => fee_trg_release_i, + FEE_TRG_STATUSBITS_IN => fee_trg_statusbits_i, + FEE_DATA_IN => fee_data_i, + FEE_DATA_WRITE_IN(0) => fee_data_write_i, + FEE_DATA_FINISHED_IN(0) => fee_data_finished_i, + FEE_DATA_ALMOST_FULL_OUT(0) => fee_almost_full_i, + + -- Slow Control Data Port + REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00 + REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 + REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe, + REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe, + REGIO_STAT_REG_IN => stat_reg, --start 0x80 + REGIO_CTRL_REG_OUT => ctrl_reg, --start 0xc0 + REGIO_STAT_STROBE_OUT => stat_reg_strobe, + REGIO_CTRL_STROBE_OUT => ctrl_reg_strobe, + REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE, + REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'), + + BUS_ADDR_OUT => regio_addr_out, + BUS_READ_ENABLE_OUT => regio_read_enable_out, + BUS_WRITE_ENABLE_OUT => regio_write_enable_out, + BUS_DATA_OUT => regio_data_out, + BUS_DATA_IN => regio_data_in, + BUS_DATAREADY_IN => regio_dataready_in, + BUS_NO_MORE_DATA_IN => regio_no_more_data_in, + BUS_WRITE_ACK_IN => regio_write_ack_in, + BUS_UNKNOWN_ADDR_IN => regio_unknown_addr_in, + BUS_TIMEOUT_OUT => regio_timeout_out, + ONEWIRE_INOUT => TEMPSENS, + ONEWIRE_MONITOR_OUT => open, + + TIME_GLOBAL_OUT => global_time, + TIME_LOCAL_OUT => local_time, + TIME_SINCE_LAST_TRG_OUT => time_since_last_trg, + TIME_TICKS_OUT => timer_ticks, + + STAT_DEBUG_IPU => open, + STAT_DEBUG_1 => open, + STAT_DEBUG_2 => open, + STAT_DEBUG_DATA_HANDLER_OUT => open, + STAT_DEBUG_IPU_HANDLER_OUT => open, + STAT_TRIGGER_OUT => open, + CTRL_MPLEX => (others => '0'), + IOBUF_CTRL_GEN => (others => '0'), + STAT_ONEWIRE => open, + STAT_ADDR_DEBUG => open, + DEBUG_LVL1_HANDLER_OUT => open + ); + + timing_trg_received_i <= TRIGGER_RIGHT; --TRIGGER_LEFT; + common_stat_reg <= (others => '0'); + stat_reg <= (others => '0'); + +--------------------------------------------------------------------------- +-- AddOn +--------------------------------------------------------------------------- + +--------------------------------------------------------------------------- +-- Bus Handler +--------------------------------------------------------------------------- + THE_BUS_HANDLER : trb_net16_regio_bus_handler + generic map( + PORT_NUMBER => 9, + PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"d400", 3 => x"c000", 4 => x"c100", 5 => x"c200", 6 => x"c300", 7 => x"c400", 8 => x"c800", others => x"0000"), + PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 5, 3 => 7, 4 => 5, 5 => 7, 6 => 7, 7 => 7, 8 => 2, others => 0) + ) + port map( + CLK => clk_100_i, + RESET => reset_i, + + DAT_ADDR_IN => regio_addr_out, + DAT_DATA_IN => regio_data_out, + DAT_DATA_OUT => regio_data_in, + DAT_READ_ENABLE_IN => regio_read_enable_out, + DAT_WRITE_ENABLE_IN => regio_write_enable_out, + DAT_TIMEOUT_IN => regio_timeout_out, + DAT_DATAREADY_OUT => regio_dataready_in, + DAT_WRITE_ACK_OUT => regio_write_ack_in, + DAT_NO_MORE_DATA_OUT => regio_no_more_data_in, + DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in, + + --Bus Handler (SPI CTRL) + BUS_READ_ENABLE_OUT(0) => spictrl_read_en, + BUS_WRITE_ENABLE_OUT(0) => spictrl_write_en, + BUS_DATA_OUT(0*32+31 downto 0*32) => spictrl_data_in, + BUS_ADDR_OUT(0*16) => spictrl_addr, + BUS_ADDR_OUT(0*16+15 downto 0*16+1) => open, + BUS_TIMEOUT_OUT(0) => open, + BUS_DATA_IN(0*32+31 downto 0*32) => spictrl_data_out, + BUS_DATAREADY_IN(0) => spictrl_ack, + BUS_WRITE_ACK_IN(0) => spictrl_ack, + BUS_NO_MORE_DATA_IN(0) => spictrl_busy, + BUS_UNKNOWN_ADDR_IN(0) => '0', + --Bus Handler (SPI Memory) + BUS_READ_ENABLE_OUT(1) => spimem_read_en, + BUS_WRITE_ENABLE_OUT(1) => spimem_write_en, + BUS_DATA_OUT(1*32+31 downto 1*32) => spimem_data_in, + BUS_ADDR_OUT(1*16+5 downto 1*16) => spimem_addr, + BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open, + BUS_TIMEOUT_OUT(1) => open, + BUS_DATA_IN(1*32+31 downto 1*32) => spimem_data_out, + BUS_DATAREADY_IN(1) => spimem_ack, + BUS_WRITE_ACK_IN(1) => spimem_ack, + BUS_NO_MORE_DATA_IN(1) => '0', + BUS_UNKNOWN_ADDR_IN(1) => '0', + --Bus Handler (SPI DAC) + BUS_READ_ENABLE_OUT(2) => spidac_read_en, + BUS_WRITE_ENABLE_OUT(2) => spidac_write_en, + BUS_DATA_OUT(2*32+31 downto 2*32) => spidac_data_in, + BUS_ADDR_OUT(2*16+4 downto 2*16) => spidac_addr, + BUS_ADDR_OUT(2*16+15 downto 2*16+5) => open, + BUS_TIMEOUT_OUT(2) => open, + BUS_DATA_IN(2*32+31 downto 2*32) => spidac_data_out, + BUS_DATAREADY_IN(2) => spidac_ack, + BUS_WRITE_ACK_IN(2) => spidac_ack, + BUS_NO_MORE_DATA_IN(2) => spidac_busy, + BUS_UNKNOWN_ADDR_IN(2) => '0', + --HitRegisters + BUS_READ_ENABLE_OUT(3) => hitreg_read_en, + BUS_WRITE_ENABLE_OUT(3) => hitreg_write_en, + BUS_DATA_OUT(3*32+31 downto 3*32) => open, + BUS_ADDR_OUT(3*16+6 downto 3*16) => hitreg_addr, + BUS_ADDR_OUT(3*16+15 downto 3*16+7) => open, + BUS_TIMEOUT_OUT(3) => open, + BUS_DATA_IN(3*32+31 downto 3*32) => hitreg_data_out, + BUS_DATAREADY_IN(3) => hitreg_data_ready, + BUS_WRITE_ACK_IN(3) => '0', + BUS_NO_MORE_DATA_IN(3) => '0', + BUS_UNKNOWN_ADDR_IN(3) => hitreg_invalid, + --Status Registers + BUS_READ_ENABLE_OUT(4) => srb_read_en, + BUS_WRITE_ENABLE_OUT(4) => srb_write_en, + BUS_DATA_OUT(4*32+31 downto 4*32) => open, + BUS_ADDR_OUT(4*16+6 downto 4*16) => srb_addr, + BUS_ADDR_OUT(4*16+15 downto 4*16+7) => open, + BUS_TIMEOUT_OUT(4) => open, + BUS_DATA_IN(4*32+31 downto 4*32) => srb_data_out, + BUS_DATAREADY_IN(4) => srb_data_ready, + BUS_WRITE_ACK_IN(4) => '0', + BUS_NO_MORE_DATA_IN(4) => '0', + BUS_UNKNOWN_ADDR_IN(4) => srb_invalid, + --Encoder Start Registers + BUS_READ_ENABLE_OUT(5) => esb_read_en, + BUS_WRITE_ENABLE_OUT(5) => esb_write_en, + BUS_DATA_OUT(5*32+31 downto 5*32) => open, + BUS_ADDR_OUT(5*16+6 downto 5*16) => esb_addr, + BUS_ADDR_OUT(5*16+15 downto 5*16+7) => open, + BUS_TIMEOUT_OUT(5) => open, + BUS_DATA_IN(5*32+31 downto 5*32) => esb_data_out, + BUS_DATAREADY_IN(5) => esb_data_ready, + BUS_WRITE_ACK_IN(5) => '0', + BUS_NO_MORE_DATA_IN(5) => '0', + BUS_UNKNOWN_ADDR_IN(5) => esb_invalid, + --Fifo Write Registers + BUS_READ_ENABLE_OUT(6) => efb_read_en, + BUS_WRITE_ENABLE_OUT(6) => efb_write_en, + BUS_DATA_OUT(6*32+31 downto 6*32) => open, + BUS_ADDR_OUT(6*16+6 downto 6*16) => efb_addr, + BUS_ADDR_OUT(6*16+15 downto 6*16+7) => open, + BUS_TIMEOUT_OUT(6) => open, + BUS_DATA_IN(6*32+31 downto 6*32) => efb_data_out, + BUS_DATAREADY_IN(6) => efb_data_ready, + BUS_WRITE_ACK_IN(6) => '0', + BUS_NO_MORE_DATA_IN(6) => '0', + BUS_UNKNOWN_ADDR_IN(6) => efb_invalid, + --Lost Hit Registers + BUS_READ_ENABLE_OUT(7) => lhb_read_en, + BUS_WRITE_ENABLE_OUT(7) => lhb_write_en, + BUS_DATA_OUT(7*32+31 downto 7*32) => open, + BUS_ADDR_OUT(7*16+6 downto 7*16) => lhb_addr, + BUS_ADDR_OUT(7*16+15 downto 7*16+7) => open, + BUS_TIMEOUT_OUT(7) => open, + BUS_DATA_IN(7*32+31 downto 7*32) => lhb_data_out, + BUS_DATAREADY_IN(7) => lhb_data_ready, + BUS_WRITE_ACK_IN(7) => '0', + BUS_NO_MORE_DATA_IN(7) => '0', + BUS_UNKNOWN_ADDR_IN(7) => lhb_invalid, + --TDC config registers + BUS_READ_ENABLE_OUT(8) => tdc_ctrl_read, + BUS_WRITE_ENABLE_OUT(8) => tdc_ctrl_write, + BUS_DATA_OUT(8*32+31 downto 8*32) => tdc_ctrl_data_in, + BUS_ADDR_OUT(8*16+1 downto 8*16) => tdc_ctrl_addr, + BUS_ADDR_OUT(8*16+15 downto 8*16+2) => open, + BUS_TIMEOUT_OUT(8) => open, + BUS_DATA_IN(8*32+31 downto 8*32) => tdc_ctrl_data_out, + BUS_DATAREADY_IN(8) => last_tdc_ctrl_read, + BUS_WRITE_ACK_IN(8) => tdc_ctrl_write, + BUS_NO_MORE_DATA_IN(8) => '0', + BUS_UNKNOWN_ADDR_IN(8) => '0', + + STAT_DEBUG => open + ); + + PROC_TDC_CTRL_REG : process + variable pos : integer; + begin + wait until rising_edge(clk_100_i); + pos := to_integer(unsigned(tdc_ctrl_addr))*32; + tdc_ctrl_data_out <= tdc_ctrl_reg(pos+31 downto pos); + last_tdc_ctrl_read <= tdc_ctrl_read; + if tdc_ctrl_write = '1' then + tdc_ctrl_reg(pos+31 downto pos) <= tdc_ctrl_data_in; + end if; + end process; + +--------------------------------------------------------------------------- +-- SPI / Flash +--------------------------------------------------------------------------- + + THE_SPI_MASTER : spi_master + port map( + CLK_IN => clk_100_i, + RESET_IN => reset_i, + -- Slave bus + BUS_READ_IN => spictrl_read_en, + BUS_WRITE_IN => spictrl_write_en, + BUS_BUSY_OUT => spictrl_busy, + BUS_ACK_OUT => spictrl_ack, + BUS_ADDR_IN(0) => spictrl_addr, + BUS_DATA_IN => spictrl_data_in, + BUS_DATA_OUT => spictrl_data_out, + -- SPI connections + SPI_CS_OUT => FLASH_CS, + SPI_SDI_IN => FLASH_DOUT, + SPI_SDO_OUT => FLASH_DIN, + SPI_SCK_OUT => FLASH_CLK, + -- BRAM for read/write data + BRAM_A_OUT => spi_bram_addr, + BRAM_WR_D_IN => spi_bram_wr_d, + BRAM_RD_D_OUT => spi_bram_rd_d, + BRAM_WE_OUT => spi_bram_we, + -- Status lines + STAT => open + ); + + -- data memory for SPI accesses + THE_SPI_MEMORY : spi_databus_memory + port map( + CLK_IN => clk_100_i, + RESET_IN => reset_i, + -- Slave bus + BUS_ADDR_IN => spimem_addr, + BUS_READ_IN => spimem_read_en, + BUS_WRITE_IN => spimem_write_en, + BUS_ACK_OUT => spimem_ack, + BUS_DATA_IN => spimem_data_in, + BUS_DATA_OUT => spimem_data_out, + -- state machine connections + BRAM_ADDR_IN => spi_bram_addr, + BRAM_WR_D_OUT => spi_bram_wr_d, + BRAM_RD_D_IN => spi_bram_rd_d, + BRAM_WE_IN => spi_bram_we, + -- Status lines + STAT => open + ); + + -- dac spi entity + DAC_SPI : spi_ltc2600 + port map ( + CLK_IN => clk_100_i, + RESET_IN => reset_i, + -- Slave bus + BUS_READ_IN => spidac_read_en, + BUS_WRITE_IN => spidac_write_en, + BUS_BUSY_OUT => spidac_busy, + BUS_ACK_OUT => spidac_ack, + BUS_ADDR_IN => spidac_addr, + BUS_DATA_IN => spidac_data_in, + BUS_DATA_OUT => spidac_data_out, + -- SPI connections + SPI_CS_OUT(15 downto 4) => open, + SPI_CS_OUT(3 downto 0) => dac_cs_i, + SPI_SDI_IN => open, + SPI_SDO_OUT => dac_sdi_i, + SPI_SCK_OUT => dac_sck_i); + + --DAC_CS <= open; --dac_cs_i; + --DAC_SDI <= open; --dac_sdi_i; + --DAC_SCK <= open; --dac_sck_i; + +--------------------------------------------------------------------------- +-- Reboot FPGA +--------------------------------------------------------------------------- + THE_FPGA_REBOOT : fpga_reboot + port map( + CLK => clk_100_i, + RESET => reset_i, + DO_REBOOT => common_ctrl_reg(15), + PROGRAMN => PROGRAMN + ); + +--------------------------------------------------------------------------- +-- LED +--------------------------------------------------------------------------- + LED_GREEN <= not med_stat_op(9); + LED_ORANGE <= not med_stat_op(10); + LED_RED <= not INP(0); + LED_YELLOW <= not med_stat_op(11); + +--------------------------------------------------------------------------- +-- Test Connector - Logic Analyser +--------------------------------------------------------------------------- + + TEST_LINE <= logic_analyser_i; + +------------------------------------------------------------------------------- +-- TDC +------------------------------------------------------------------------------- + + THE_TDC : TDC + generic map ( + CHANNEL_NUMBER => 65, -- Number of TDC channels + CONTROL_REG_NR => 5) -- Number of control regs + port map ( + RESET => reset_i, + CLK_TDC => CLK_PCLK_LEFT, -- Clock used for the time measurement + CLK_READOUT => clk_100_i, -- Clock for the readout + REFERENCE_TIME => timing_trg_received_i, -- Reference time input + HIT_IN => hit_in_i(64 downto 1), -- Channel start signals + TRG_WIN_PRE => tdc_ctrl_reg(42 downto 32), -- Pre-Trigger window width + TRG_WIN_POST => tdc_ctrl_reg(58 downto 48), -- Post-Trigger window width + -- + -- Trigger signals from handler + TRG_DATA_VALID_IN => trg_data_valid_i, -- trig data valid signal from trbnet + VALID_TIMING_TRG_IN => trg_timing_valid_i, -- valid timing trigger signal from trbnet + VALID_NOTIMING_TRG_IN => trg_notiming_valid_i, -- valid notiming signal from trbnet + INVALID_TRG_IN => trg_invalid_i, -- invalid trigger signal from trbnet + TMGTRG_TIMEOUT_IN => trg_timeout_detected_i, -- timing trigger timeout signal from trbnet + SPIKE_DETECTED_IN => trg_spike_detected_i, + MULTI_TMG_TRG_IN => trg_multiple_trg_i, + SPURIOUS_TRG_IN => trg_spurious_trg_i, + -- + TRG_NUMBER_IN => trg_number_i, -- LVL1 trigger information package + TRG_CODE_IN => trg_code_i, -- + TRG_INFORMATION_IN => trg_information_i, -- + TRG_TYPE_IN => trg_type_i, -- LVL1 trigger information package + -- + --Response to handler + TRG_RELEASE_OUT => fee_trg_release_i, -- trigger release signal + TRG_STATUSBIT_OUT => fee_trg_statusbits_i, -- status information of the tdc + DATA_OUT => fee_data_i, -- tdc data + DATA_WRITE_OUT => fee_data_write_i, -- data valid signal + DATA_FINISHED_OUT => fee_data_finished_i, -- readout finished signal + -- + --Hit Counter Bus + HCB_READ_EN_IN => hitreg_read_en, -- bus read en strobe + HCB_WRITE_EN_IN => hitreg_write_en, -- bus write en strobe + HCB_ADDR_IN => hitreg_addr, -- bus address + HCB_DATA_OUT => hitreg_data_out, -- bus data + HCB_DATAREADY_OUT => hitreg_data_ready, -- bus data ready strobe + HCB_UNKNOWN_ADDR_OUT => hitreg_invalid, -- bus invalid addr + --Status Registers Bus + SRB_READ_EN_IN => srb_read_en, -- bus read en strobe + SRB_WRITE_EN_IN => srb_write_en, -- bus write en strobe + SRB_ADDR_IN => srb_addr, -- bus address + SRB_DATA_OUT => srb_data_out, -- bus data + SRB_DATAREADY_OUT => srb_data_ready, -- bus data ready strobe + SRB_UNKNOWN_ADDR_OUT => srb_invalid, -- bus invalid addr + --Encoder Start Registers Bus + ESB_READ_EN_IN => esb_read_en, -- bus read en strobe + ESB_WRITE_EN_IN => esb_write_en, -- bus write en strobe + ESB_ADDR_IN => esb_addr, -- bus address + ESB_DATA_OUT => esb_data_out, -- bus data + ESB_DATAREADY_OUT => esb_data_ready, -- bus data ready strobe + ESB_UNKNOWN_ADDR_OUT => esb_invalid, -- bus invalid addr + --Fifo Write Registers Bus + EFB_READ_EN_IN => efb_read_en, -- bus read en strobe + EFB_WRITE_EN_IN => efb_write_en, -- bus write en strobe + EFB_ADDR_IN => efb_addr, -- bus address + EFB_DATA_OUT => efb_data_out, -- bus data + EFB_DATAREADY_OUT => efb_data_ready, -- bus data ready strobe + EFB_UNKNOWN_ADDR_OUT => efb_invalid, -- bus invalid addr + --Lost Hit Registers Bus + LHB_READ_EN_IN => lhb_read_en, -- bus read en strobe + LHB_WRITE_EN_IN => lhb_write_en, -- bus write en strobe + LHB_ADDR_IN => lhb_addr, -- bus address + LHB_DATA_OUT => lhb_data_out, -- bus data + LHB_DATAREADY_OUT => lhb_data_ready, -- bus data ready strobe + LHB_UNKNOWN_ADDR_OUT => lhb_invalid, -- bus invalid addr + -- + LOGIC_ANALYSER_OUT => logic_analyser_i, + CONTROL_REG_IN => tdc_ctrl_reg); + + -- For single edge measurements + -- hit_in_i <= INP; + + -- For ToT Measurements + Gen_Hit_In_Signals : for i in 1 to 32 generate + hit_in_i(i*2-1) <= INP(i-1); + hit_in_i(i*2) <= not INP(i-1); + end generate Gen_Hit_In_Signals; + + -- !!!!! IMPORTANT !!!!! Don't forget to set the REGIO_HARDWARE_VERSION !!!!! +end architecture; diff --git a/tdc_releases/tdc_v1.4/trbnet_constraints.lpf b/tdc_releases/tdc_v1.4/trbnet_constraints.lpf new file mode 100644 index 0000000..3d0a7a7 --- /dev/null +++ b/tdc_releases/tdc_v1.4/trbnet_constraints.lpf @@ -0,0 +1,46 @@ +################################################################# +# Reset Nets +################################################################# +GSR_NET NET "reset_i"; + +################################################################# +# Locate Serdes and media interfaces +################################################################# +LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ; + +REGION "MEDIA_UPLINK" "R105C109D" 10 22; +REGION "REGION_SPI" "R2C109D" 15 22 DEVSIZE; + +LOCATE UGROUP "THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ; +LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ; + +LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ; + +MULTICYCLE TO CELL "THE_MEDIA_DOWNLINK/SCI_DATA_OUT*" 50 ns; +MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns; +MULTICYCLE TO CELL "THE_RESET_HANDLER/final_reset*" 30 ns; + + +#Jan: Placement of TrbNet components (at least, most of them) +REGION "REGION_TRBNET" "R35C109D" 70 22 DEVSIZE; +#UGROUP "TrbNet" BBOX 77 27 +# BLKNAME THE_ENDPOINT +# BLKNAME THE_ENDPOINT/THE_ENDPOINT +#LOCATE UGROUP "TrbNet" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_BUS_HANDLER/Bus_handler_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers.0.geniobuf.IOBUF/genINITOBUF2.gen_INITOBUF3.INITOBUF/OBUF_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers.1.geniobuf.IOBUF/genINITOBUF2.gen_INITOBUF3.INITOBUF/OBUF_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers.2.gentermbuf.termbuf/TRMBUF_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers.3.geniobuf.IOBUF/genINITOBUF2.gen_INITOBUF3.INITOBUF/OBUF_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_INTERNAL_BUS_HANDLER/Bus_handler_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/MPLEX/MUX_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers.3.geniobuf.gen_regio.regIO/the_addresses/HUBLOGIC_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers.3.geniobuf.gen_regio.regIO/RegIO_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers.3.geniobuf.gen_api.DAT_PASSIVE_API/API_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API/API_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers.3.geniobuf.IOBUF/genREPLYOBUF1.REPLYOBUF/OBUF_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers.3.geniobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers.1.geniobuf.IOBUF/genREPLYOBUF1.REPLYOBUF/OBUF_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers.1.geniobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers.0.geniobuf.IOBUF/genREPLYOBUF1.REPLYOBUF/OBUF_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers.0.geniobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_TRBNET"; diff --git a/tdc_releases/tdc_v1.4/up_counter.vhd b/tdc_releases/tdc_v1.4/up_counter.vhd new file mode 100644 index 0000000..1d8a887 --- /dev/null +++ b/tdc_releases/tdc_v1.4/up_counter.vhd @@ -0,0 +1,41 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use IEEE.STD_LOGIC_UNSIGNED.all; + +entity up_counter is + + generic ( + NUMBER_OF_BITS : positive); + port ( + CLK : in std_logic; + RESET : in std_logic; + COUNT_OUT : out std_logic_vector(NUMBER_OF_BITS-1 downto 0); + UP_IN : in std_logic); + +end up_counter; + +architecture up_counter of up_counter is + + signal counter : std_logic_vector (NUMBER_OF_BITS-1 downto 0); + attribute syn_preserve : boolean; + attribute syn_preserve of counter : signal is true; + +begin + + COUNTER_PROC : process (CLK, RESET) + begin + if rising_edge(CLK) then + if RESET = '1' then + counter <= (others => '0'); + elsif UP_IN = '1' then + counter <= counter + 1; + else + counter <= counter; + end if; + end if; + end process COUNTER_PROC; + + COUNT_OUT <= counter; + +end up_counter; -- 2.43.0